diff -Naur binutils-2.13.orig/gas/config/tc-mips.c binutils-2.13/gas/config/tc-mips.c --- binutils-2.13.orig/gas/config/tc-mips.c 2002-08-02 04:03:09.000000000 +0200 +++ binutils-2.13/gas/config/tc-mips.c 2002-09-28 14:19:08.000000000 +0200 @@ -7604,6 +7604,8 @@ case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; case 'I': break; case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; + case 'K': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); + USE_BITS (OP_MASK_FT, OP_SH_FT); break; case 'L': break; case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; @@ -7628,6 +7630,10 @@ case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; case 'l': break; + case 'm': USE_BITS (OP_MASK_LOWVSEL, OP_SH_LOWVSEL); + USE_BITS (OP_MASK_FS, OP_SH_FS); break; + case 'n': USE_BITS (OP_MASK_LOWVSEL, OP_SH_LOWVSEL); + USE_BITS (OP_MASK_FT, OP_SH_FT); break; case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; @@ -8180,6 +8186,9 @@ continue; } /* Not MDMX Immediate. Fall through. */ + case 'K': /* MSP vector or element. */ + case 'm': /* MSP MFC2/MTC2 source register. */ + case 'n': /* MSP LWC2/SWC2 dest register. */ case 'X': /* MDMX destination register. */ case 'Y': /* MDMX source register. */ case 'Z': /* MDMX target register. */ @@ -8210,7 +8219,7 @@ if (regno > 31) as_bad (_("Invalid float register number (%d)"), regno); - if ((regno & 1) != 0 + if (((regno & 1) != 0 && !is_mdmx) && HAVE_32BIT_FPRS && ! (strcmp (str, "mtc1") == 0 || strcmp (str, "mfc1") == 0 @@ -8239,6 +8248,73 @@ case 'X': ip->insn_opcode |= regno << OP_SH_FD; break; + case 'm': + case 'n': + /* Need to fix the MSP low vector/scalar select bits. */ + if (*s == '[') + { + int max_el = 15; + s++; + my_getExpression(&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + imm_expr.X_op = O_absent; + s = expr_end; + if (imm_expr.X_add_number > max_el) + as_bad(_("Bad element selector %ld"), + (long) imm_expr.X_add_number); + imm_expr.X_add_number &= max_el; + ip->insn_opcode |= ((imm_expr.X_add_number) + << OP_SH_LOWVSEL); + if (*s != ']') + as_warn(_("Expecting ']' found '%s'"), s); + else + s++; + } + if(c == 'm') + ip->insn_opcode |= regno << OP_SH_FS; + if(c == 'n') + ip->insn_opcode |= regno << OP_SH_FT; + break; + case 'K': + /* Need to fix the MSP high vector/scalar select bits. */ + if (*s == '[') + { + int max_el; + s++; + my_getExpression(&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + imm_expr.X_op = O_absent; + s = expr_end; + if(*s == 'q') { + /* quarter select */ + max_el = 1; s++; + ip->insn_opcode |= 0x2 << OP_SH_VSEL; + } + else if(*s == 'h') { + /* half select */ + max_el = 3; s++; + ip->insn_opcode |= 0x4 << OP_SH_VSEL; + } else { + /* scalar select */ + max_el = 7; + ip->insn_opcode |= 0x8 << OP_SH_VSEL; + } + if (*s != ']') { + as_warn(_("Expecting ']' found '%s'"), s); + } + else { + s++; + } + + if (imm_expr.X_add_number > max_el) + as_bad(_("Bad element selector %ld"), + (long) imm_expr.X_add_number); + imm_expr.X_add_number &= max_el; + ip->insn_opcode |= imm_expr.X_add_number + << OP_SH_VSEL; + } + ip->insn_opcode |= regno << OP_SH_FT; + break; case 'V': case 'S': case 'Y': diff -Naur binutils-2.13.orig/include/opcode/mips.h binutils-2.13/include/opcode/mips.h --- binutils-2.13.orig/include/opcode/mips.h 2002-07-09 16:21:40.000000000 +0200 +++ binutils-2.13/include/opcode/mips.h 2002-09-28 14:19:39.000000000 +0200 @@ -137,6 +137,8 @@ #define OP_MASK_ALN 0x7 #define OP_SH_VSEL 21 #define OP_MASK_VSEL 0x1f +#define OP_SH_LOWVSEL 7 /* The vsel field of {mf/mt/lw/sw}c2 */ +#define OP_MASK_LOWVSEL 0xf /* Values in the 'VSEL' field. */ #define MDMX_FMTSEL_IMM_QH 0x1d @@ -238,14 +240,19 @@ "Y" MDMX source register (OP_*_FS) "Z" MDMX source register (OP_*_FT) + VICE MSP/Nintendo64 RCP instruction operands + "m" vector source for MFC2/MTC2 operations (OP_*_LOWVSEL and OP_*_FS) + "n" vector dest for LWC2/SWC2 operations (OP_*_LOWVSEL and OP_*_FT) + "K" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) + Other: "()" parens surrounding optional value "," separates operands Characters used so far, for quick reference when adding more: "<>()," - "ABCDEFGHIJLMNOPQRSTUVWXYZ" - "abcdfhijklopqrstuvwxz" + "ABCDEFGHIJKLMNOPQRSTUVWXYZ" + "abcdfhijklmnopqrstuvwxz" */ /* These are the bits which may be set in the pinfo field of an diff -Naur binutils-2.13.orig/opcodes/mips-dis.c binutils-2.13/opcodes/mips-dis.c --- binutils-2.13.orig/opcodes/mips-dis.c 2002-07-09 16:21:40.000000000 +0200 +++ binutils-2.13/opcodes/mips-dis.c 2002-09-27 22:28:38.000000000 +0200 @@ -93,7 +93,7 @@ /* Scalar register names. _print_insn_mips() decides which register name table to use. */ static const char * const *reg_names = NULL; - + /* Print insn arguments for 32/64-bit code. */ static void @@ -289,6 +289,45 @@ (l >> OP_SH_ALN) & OP_MASK_ALN); break; + case 'm': + case 'n': + { + unsigned int vsel = (l >> OP_SH_LOWVSEL) & OP_MASK_LOWVSEL; + + (*info->fprintf_func) (info->stream, "$v%d[%d]", + (l >> OP_SH_FS) & OP_MASK_FS, + vsel); + } + break; + + case 'K': + { + unsigned int vsel = (l >> OP_SH_LOWVSEL) & OP_MASK_LOWVSEL; + + if(vsel) + { + if(vsel & 8) + (*info->fprintf_func) (info->stream, "$v%d[%d]", + (l >> OP_SH_FS) & OP_MASK_FS, + vsel & 7); + else if(vsel & 4) + (*info->fprintf_func) (info->stream, "$v%d[%dh]", + (l >> OP_SH_FS) & OP_MASK_FS, + vsel & 3); + else if(vsel & 2) + (*info->fprintf_func) (info->stream, "$v%d[%dq]", + (l >> OP_SH_FS) & OP_MASK_FS, + vsel & 1); + else if(vsel & 1) + (*info->fprintf_func) (info->stream, "$v%d[?]", /* unknown code */ + (l >> OP_SH_FS) & OP_MASK_FS); + } else { + (*info->fprintf_func) (info->stream, "$v%d", + (l >> OP_SH_FS) & OP_MASK_FS); + } + } + break; + case 'Q': { unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; diff -Naur binutils-2.13.orig/opcodes/mips-opc.c binutils-2.13/opcodes/mips-opc.c --- binutils-2.13.orig/opcodes/mips-opc.c 2002-07-09 16:21:40.000000000 +0200 +++ binutils-2.13/opcodes/mips-opc.c 2002-09-28 14:06:49.000000000 +0200 @@ -95,6 +95,9 @@ /* MIPS64 MDMX ASE support. */ #define MX INSN_MDMX +/* SGI O2 VICE MSP and Nintendo 64 RCP support */ +#define MSP INSN_MDMX /* TEMP */ + #define P3 INSN_4650 #define L1 INSN_4010 #define V1 INSN_4100 @@ -420,6 +423,8 @@ {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, +{"cfc2c", "t", 0x48400000, 0xffe0ffff, LCD|WR_t|RD_C2, MSP }, +{"cfc2o", "t", 0x48400800, 0xffe0ffff, LCD|WR_t|RD_C2, MSP }, {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32 }, {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32 }, @@ -427,6 +432,8 @@ {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, +{"ctc2c", "t", 0x48c00000, 0xffe0ffff, COD|RD_t|WR_CC, MSP }, +{"ctc2o", "t", 0x48c00800, 0xffe0ffff, COD|RD_t|WR_CC, MSP }, {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 }, {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 }, @@ -622,6 +629,22 @@ {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */ {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, + /* TEMP new MSP load insn */ +{"lbv", "n,o(b)", 0xc8000000, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"lsv", "n,o(b)", 0xc8000800, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"llv", "n,o(b)", 0xc8001000, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"ldv", "n,o(b)", 0xc8001800, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"lqv", "n,o(b)", 0xc8002000, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"lrv", "Z,o(b)", 0xc8002800, 0xfc00ffc0, LDD|RD_b|WR_T, MSP }, +{"lpv", "n,o(b)", 0xc8003000, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"luv", "n,o(b)", 0xc8003800, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"lxv", "n,o(b)", 0xc8004000, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"lzv", "n,o(b)", 0xc8004800, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"lhv", "n,o(b)", 0xc8005000, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"lfv", "n,o(b)", 0xc8005800, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"lav", "n,o(b)", 0xc8006000, 0xfc00f800, LDD|RD_b|WR_T, MSP }, +{"ltv", "n,o(b)", 0xc8006800, 0xfc00f800, LDD|RD_b|WR_T, MSP }, + {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 }, {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, @@ -660,6 +683,7 @@ {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, +{"mfc2", "t,m", 0x48000000, 0xffe0007f, LCD|WR_t|RD_C2, MSP }, {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 }, {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 }, @@ -712,6 +736,7 @@ {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, +{"mtc2", "t,m", 0x48800000, 0xffe0007f, COD|RD_t|WR_C2|WR_CC, MSP }, {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 }, {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 }, @@ -934,6 +959,22 @@ {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */ {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, + /* TEMP new MSP store insn */ +{"sbv", "n,o(b)", 0xe8000000, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"ssv", "n,o(b)", 0xe8000800, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"slv", "n,o(b)", 0xe8001000, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"sdv", "n,o(b)", 0xe8001800, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"sqv", "n,o(b)", 0xe8002000, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"srv", "Z,o(b)", 0xe8002800, 0xfc00ffc0, SM|RD_b|RD_T, MSP }, +{"spv", "n,o(b)", 0xe8003000, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"suv", "n,o(b)", 0xe8003800, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"sxv", "n,o(b)", 0xe8004000, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"szv", "n,o(b)", 0xe8004800, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"shv", "n,o(b)", 0xe8005000, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"sfv", "n,o(b)", 0xe8005800, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"sav", "n,o(b)", 0xe8006000, 0xfc00f800, SM|RD_b|RD_T, MSP }, +{"stv", "n,o(b)", 0xe8006800, 0xfc00f800, SM|RD_b|RD_T, MSP }, + {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 }, {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 }, {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 }, @@ -1008,6 +1049,94 @@ {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 }, {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 }, {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 }, +/* TEMP: new MSP vector operations ( ! = illegal instruction ) */ +{"vmulf", "X,Y,K", 0x4a000000, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmulu", "X,Y,K", 0x4a000001, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vrndpl", "X,K", 0x4a000002, 0xfe00f83f, WR_D|RD_T, MSP }, +{"vrndph", "X,K", 0x4a000802, 0xfe00f83f, WR_D|RD_T, MSP }, +{"vmulq", "X,Y,K", 0x4a000003, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmudl", "X,Y,K", 0x4a000004, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmudm", "X,Y,K", 0x4a000005, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmudn", "X,Y,K", 0x4a000006, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmudh", "X,Y,K", 0x4a000007, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmacf", "X,Y,K", 0x4a000008, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmacu", "X,Y,K", 0x4a000009, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vrndnl", "X,K", 0x4a00000a, 0xfe00f83f, WR_D|RD_S|RD_T, MSP }, +{"vrndnh", "X,K", 0x4a00080a, 0xfe00f83f, WR_D|RD_S|RD_T, MSP }, +{"vmacq", "X,Y,K", 0x4a00000b, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmadl", "X,Y,K", 0x4a00000c, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmadm", "X,Y,K", 0x4a00000d, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmadn", "X,Y,K", 0x4a00000e, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmadh", "X,Y,K", 0x4a00000f, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vadd", "X,Y,K", 0x4a000010, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vsub", "X,Y,K", 0x4a000011, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vsut", "X,Y,K", 0x4a000012, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vabs", "X,Y,K", 0x4a000013, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vaddc", "X,Y,K", 0x4a000014, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vsubc", "X,Y,K", 0x4a000015, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vaddb", "X,Y,Z,O", 0x4a000016, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vaddb", "X,Y,Z", 0x4a000016, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vsubb", "X,Y,Z,O", 0x4a000017, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vsubb", "X,Y,Z", 0x4a000017, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vaccb", "X,Y,Z,O", 0x4a000018, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vaccb", "X,Y,Z", 0x4a000018, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vsucb", "X,Y,Z,O", 0x4a000019, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vsucb", "X,Y,Z", 0x4a000019, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vsad", "X,Y,Z", 0x4a00001a, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vsac", "X,Y,Z", 0x4a00001b, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vsumh", "X", 0x4a00001c, 0xfffff83f, WR_D, MSP }, +{"vsumm", "X", 0x4a20001c, 0xfffff83f, WR_D, MSP }, +{"vsuml", "X", 0x4a40001c, 0xfffff83f, WR_D, MSP }, +{"vsawh", "X,Y", 0x4a00001d, 0xffff003f, WR_D|RD_S, MSP }, +{"vsawm", "X,Y", 0x4a20001d, 0xffff003f, WR_D|RD_S, MSP }, +{"vsawl", "X,Y", 0x4a40001d, 0xffff003f, WR_D|RD_S, MSP }, +{"vacc", "X,Y,K", 0x4a00001e, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vsuc", "X,Y,K", 0x4a00001f, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vlt", "X,Y,K", 0x4a000020, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"veq", "X,Y,K", 0x4a000021, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vne", "X,Y,K", 0x4a000022, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vge", "X,Y,K", 0x4a000023, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vch"/*!*/, "X,Y,K", 0x4a000024, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vcl", "X,Y,K", 0x4a000025, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vmrg", "X,Y,K", 0x4a000026, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vcr", "X,Y,K", 0x4a000027, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, + +{"vand", "X,Y,K", 0x4a000028, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vnand", "X,Y,K", 0x4a000029, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vor", "X,Y,K", 0x4a00002a, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vnor", "X,Y,K", 0x4a00002b, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vxor", "X,Y,K", 0x4a00002c, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vnxor", "X,Y,K", 0x4a00002d, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vunk", "X,Y,K", 0x4a00002e, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, + /* ! */ + /* ! */ +{"vsumb", "X,Y,Z,O", 0x4a000030, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vsumb", "X,Y,Z", 0x4a000030, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vsacb", "X,Y,Z,O", 0x4a000031, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vsacb", "X,Y,Z", 0x4a000031, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vmulb", "X,Y,Z,O", 0x4a000032, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vmulb", "X,Y,Z", 0x4a000032, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vmulbn", "X,Y,Z,O", 0x4a000033, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vmulbn", "X,Y,Z", 0x4a000033, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vmacb", "X,Y,Z,O", 0x4a000034, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vmacb", "X,Y,Z", 0x4a000034, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vmsucb", "X,Y,Z,O", 0x4a000035, 0xff00003f, WR_D|RD_S|RD_T, MSP }, +{"vmsucb", "X,Y,Z", 0x4a000035, 0xffe0003f, WR_D|RD_S|RD_T, MSP }, +{"vrndl", "X,K", 0x4a000036, 0xfe00f83f, WR_D|RD_T, MSP }, +{"vrndh", "X,K", 0x4a000836, 0xfe00f83f, WR_D|RD_T, MSP }, +{"vrndbl", "X,O", 0x4a000037, 0xff1ff83f, WR_D, MSP }, +{"vrndbl", "X", 0x4a000837, 0xfffff83f, WR_D, MSP }, +{"vrndbh", "X,O", 0x4a000037, 0xff1ff83f, WR_D, MSP }, +{"vrndbh", "X", 0x4a000837, 0xfffff83f, WR_D, MSP }, +{"vextt"/*!*/, "X,Y,K", 0x4a000038, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vextq"/*!*/, "X,Y,K", 0x4a000039, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vextn"/*!*/, "X,Y,K", 0x4a00003a, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vinst"/*!*/, "X,Y,K", 0x4a00003b, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vinsq"/*!*/, "X,Y,K", 0x4a00003c, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, +{"vinsn"/*!*/, "X,Y,K", 0x4a00003d, 0xfe00003f, WR_D|RD_S|RD_T, MSP }, + /* ! */ + /* ! */ + {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX|SB1 }, {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX }, {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },