From owner-linux@cthulhu.engr.sgi.com  Tue Sep  2 14:50:10 1997
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Date: Tue, 2 Sep 1997 17:47:13 -0400 (EDT)
From: Alex deVries <adevries@engsoc.carleton.ca>
To: linux@cthulhu.engr.sgi.com
Subject: Booting off of sdb1...
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First off, thanks to input from Mike, I got my partition setup properly.
Here's how it's done:

In fx in IRIX, create an optional partition.  This will create one huge
partition at the beginning (sdb1), and a volume header (sdb2), which you
won't use.  It doesn't matter what type of partition you label sdb1, Linux
doesn't recognize either.  All this means is you may have to force the
type recognition when doing a mount.

>From within an nfs-rooted Linux, I mke2fs'd it, and copied all the files
over from my nfsroot (esentially Ralf's root .cpio.gz).

But, here's my problem:  I've take my old kernel that boots with NFS root,
and tried to boot it using:  
vmlinux root=/dev/sdb1

The kernel starts, and it finishes off with:

Partition check:
 sda: sad1 sda2 sda3 sda4
 sdb: sdb1 sdb2 sdb3
VFS: Mounted root (ext2 filesystem) readonly.
: Can't open

And then nothing.

What am I missing?

- Alex


      Alex deVries              Success is realizing 
  System Administrator          attainable dreams.
   The EngSoc Project     


From owner-linux@cthulhu.engr.sgi.com  Tue Sep  2 15:06:42 1997
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From: Mark Salter <marks@sun470.sun470.rd.qms.com>
To: adevries@engsoc.carleton.ca
Cc: linux@cthulhu.engr.sgi.com
In-Reply-To: 
	<Pine.LNX.3.95.970902173244.5212A-100000@lager.engsoc.carleton.ca>
	(message from Alex deVries on Tue, 2 Sep 1997 17:47:13 -0400 (EDT))
Subject: Re: Booting off of sdb1...
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> The kernel starts, and it finishes off with:

> Partition check:
>  sda: sad1 sda2 sda3 sda4
>  sdb: sdb1 sdb2 sdb3
> VFS: Mounted root (ext2 filesystem) readonly.
> : Can't open

> And then nothing.

> What am I missing?

> - Alex


>       Alex deVries              Success is realizing 
>   System Administrator          attainable dreams.
>    The EngSoc Project     


Try this patch to linux/arch/mips/sgi/prom/cmdline.c:

*** cmdline.c.orig      Tue Sep  2 16:59:26 1997
--- cmdline.c   Tue Sep  2 15:59:04 1997
***************
*** 52,57 ****
--- 52,59 ----
        pic_cont:
                actr++;
        }
+       if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
+               --cp;
        *cp = '\0';
  
  #ifdef DEBUG_CMDLINE


--Mark

From owner-linux@cthulhu.engr.sgi.com  Tue Sep  2 16:47:51 1997
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Date: Tue, 2 Sep 1997 19:45:59 -0400 (EDT)
From: Alex deVries <adevries@engsoc.carleton.ca>
Reply-To: Alex deVries <adevries@engsoc.carleton.ca>
To: Mark Salter <marks@sun470.sun470.rd.qms.com>
cc: linux@cthulhu.engr.sgi.com
Subject: Re: Booting off of sdb1...
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On Tue, 2 Sep 1997, Mark Salter wrote:
> > The kernel starts, and it finishes off with:
> > Partition check:
> >  sda: sad1 sda2 sda3 sda4
> >  sdb: sdb1 sdb2 sdb3
> > VFS: Mounted root (ext2 filesystem) readonly.
> > : Can't open
> 
> Try this patch to linux/arch/mips/sgi/prom/cmdline.c:

<snip>

Well, I would try that patch, but I am unable to compile kernels because I
_always_ get this:

make[1]: Entering directory `/usr/src/sgi/linux/arch/mips/kernel'
mips-linux-gcc -D__KERNEL__ -I/usr/src/sgi/linux/include -Wall
-Wstrict-prototypes -O2 -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic
-D__GOGOGO__ -mcpu=r4600 -mips2 -pipe -c entry.S -o entry.o
entry.S: Assembler messages:
entry.S:208: Error: .previous without corresponding .section; ignored
entry.S:208: Error: .previous without corresponding .section; ignored
entry.S:209: Error: .previous without corresponding .section; ignored
entry.S:209: Error: .previous without corresponding .section; ignored
entry.S:216: Error: .previous without corresponding .section; ignored
entry.S:216: Error: .previous without corresponding .section; ignored
entry.S:218: Error: .previous without corresponding .section; ignored
entry.S:218: Error: .previous without corresponding .section; ignored
entry.S:219: Error: .previous without corresponding .section; ignored
entry.S:219: Error: .previous without corresponding .section; ignored
entry.S:220: Error: .previous without corresponding .section; ignored
entry.S:220: Error: .previous without corresponding .section; ignored
make[1]: *** [entry.o] Error 1
make[1]: Leaving directory `/usr/src/sgi/linux/arch/mips/kernel'
make: *** [linuxsubdirs] Error 2

I'm using the gcc that's up on ftp.linux.sgi.com, and I'm using binutils
2.8.1, which is the latest I believe.

_PLEASE_ can someone who is able to succesfully cross compile kernels post
here what versions they are using, and where I can get them from. Not
sorting this out brings my development efforts to a complete stop. 

- Alex




From owner-linux@cthulhu.engr.sgi.com  Tue Sep  2 17:06:51 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: adevries@engsoc.carleton.ca
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	<Pine.LNX.3.95.970902180957.5212B-100000@lager.engsoc.carleton.ca>
	(message from Alex deVries on Tue, 2 Sep 1997 19:45:59 -0400 (EDT))
Subject: Re: Booting off of sdb1...
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> <snip>
> 
> Well, I would try that patch, but I am unable to compile kernels because I
> _always_ get this:

Probably you missed my post and Ralf's post on this issue. 

> I'm using the gcc that's up on ftp.linux.sgi.com, and I'm using binutils
> 2.8.1, which is the latest I believe.

You need to get the binutils tar file as it was made available on
ftp.linux.sgi.com, not the cross-compiler kit, nor the 2.8.1 release
from the FSF.  

> _PLEASE_ can someone who is able to succesfully cross compile kernels post
> here what versions they are using, and where I can get them from. Not
> sorting this out brings my development efforts to a complete stop. 

berenice-origin32$ mips-linux-as --version
GNU assembler version 2.7 (mips-linux), using BFD version 2.7

berenice-origin32$ mycc --version
2.7.2

But then, those versions are not really the stock GNU versions, they
are the ones available in ftp.linux.sgi.com

Cheers,
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Tue Sep  2 22:44:51 1997
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Date: Wed, 3 Sep 1997 01:44:34 -0400 (EDT)
From: Alex deVries <adevries@engsoc.carleton.ca>
Reply-To: Alex deVries <adevries@engsoc.carleton.ca>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
cc: linux@cthulhu.engr.sgi.com
Subject: Re: Booting off of sdb1...
In-Reply-To: <199709022358.SAA19505@athena.nuclecu.unam.mx>
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On Tue, 2 Sep 1997, Miguel de Icaza wrote:
> You need to get the binutils tar file as it was made available on
> ftp.linux.sgi.com, not the cross-compiler kit, nor the 2.8.1 release
> from the FSF.  

Okay, I'm getting closer.

I believe the correct version is binutils-2.7.tar.gz, patched with
ftp://ftp.linux.sgi.com/pub/src/binutils/binutils-2.7-4.diff.gz.  I'd have
used the patch for binutils-2.7.0.6, but I can't find the original
anywhere.

I did a ./configure --target=mips-big-linux (since mips-unknown-linux
produces a functional little endian binutils, which is useless for my
Indy).

I end up with this error when I compile binutils:

gcc -O2    -g  -DTARGET_BYTES_BIG_ENDIAN  -o as.new targ-cpu.o
obj-format.o atof-targ.o app.o as.o atof-generic.o bignum-copy.o cond.o
expr.o flonum-konst.o flonum-copy.o flonum-mult.o frags.o hash.o
input-file.o input-scrub.o literal.o messages.o output-file.o read.o
subsegs.o symbols.o write.o listing.o ecoff.o stabs.o sb.o macro.o
e-mipself.o  -L.../opcodes -lopcodes -L../bfd -lbfd
../libiberty/libiberty.a 
targ-cpu.o: In function `md_begin':
/home/binutils-2.7/gas/targ-cpu.c:826: undefined reference to
`bfd_mips_elf_swap_options_out'
targ-cpu.o: In function `mips_elf_final_processing':
/home/binutils-2.7/gas/targ-cpu.c:7863: undefined reference to
`bfd_mips_elf32_swap_reginfo_out'
/home/binutils-2.7/gas/targ-cpu.c:7879: undefined reference to
`bfd_mips_elf64_swap_reginfo_out'
make[1]: *** [as.new] Error 1
make[1]: Leaving directory `/home/binutils-2.7/gas'
make: *** [all-gas] Error 2

NB:  There's no problem with compiling with --target=mips-unknown-linux.

Ideas?  How have other people gotten around this?

Thanks for getting me started again, Miguel.

- Alex



From owner-linux@cthulhu.engr.sgi.com  Wed Sep  3 06:44:23 1997
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Date: Wed, 03 Sep 1997 09:43:34 -0400
From: Eric Kimminau <eak@cygnus.detroit.sgi.com>
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To: Mark Salter <marks@sun470.sun470.rd.qms.com>
CC: adevries@engsoc.carleton.ca, linux@cthulhu.engr.sgi.com
Subject: Re: Booting off of sdb1...
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Does anyone have a built kernel with this patch applied?

Thanks!
                  Eric.


Mark Salter wrote:
> 
> > The kernel starts, and it finishes off with:
> 
> > Partition check:
> >  sda: sad1 sda2 sda3 sda4
> >  sdb: sdb1 sdb2 sdb3
> > VFS: Mounted root (ext2 filesystem) readonly.
> > : Can't open
> 
> > And then nothing.
> 
> > What am I missing?
> 
> > - Alex
> 
> >       Alex deVries              Success is realizing
> >   System Administrator          attainable dreams.
> >    The EngSoc Project
> 
> Try this patch to linux/arch/mips/sgi/prom/cmdline.c:
> 
> *** cmdline.c.orig      Tue Sep  2 16:59:26 1997
> --- cmdline.c   Tue Sep  2 15:59:04 1997
> ***************
> *** 52,57 ****
> --- 52,59 ----
>         pic_cont:
>                 actr++;
>         }
> +       if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
> +               --cp;
>         *cp = '\0';
> 
>   #ifdef DEBUG_CMDLINE
> 
> --Mark

-- 
Eric Kimminau                           System Engineer/RSA
eak@detroit.sgi.com                     Silicon Graphics, Inc
Voice: (248) 848-4455                   39001 West 12 Mile Rd.
Fax:   (248) 848-5600                   Farmington, MI 48331-2903

                 VNet Extension - 6-327-4455
              "I speak my mind and no one else's."
       http://www.dcs.ex.ac.uk/~aba/rsa/perl-rsa-sig.html

    When confronted by a difficult problem, solve it by reducing 
    it to the question, "How would the Lone Ranger handle this?"

Windows 95: n.
    32 bit extensions and a graphical shell for a 16 bit patch to an
    8 bit operating system originally coded for a 4 bit microprocessor,
    written by a 2 bit company that can't stand 1 bit of competition.

    Author unknown.

From owner-linux@cthulhu.engr.sgi.com  Wed Sep  3 19:54:26 1997
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:
:Hi
:
:we don't have a spare Indy to play with, but have a
:spare Challenge S (single processor R5000) 
:
:I was wondering if you thing this machine is possible, it would be 
:used with a serial console (no X), for testing ;)
:-- 

If you feel up to the challenge, sure, please go ahead.

There may be a few assumptions in the current code which detects
the newport graphics console that this testing may uncover. If 
you can fix this so it won't be Indy dependent, we win one more
possible platform !

Moreover, since a challenge-S doesn't have graphics anyway
Linux which is fast and compact may even outperform IRIX
on some benchmarks.

I would suggest that:

1) You join the mailing list:
	To: majordomo@engr.sgi.com
	Body: subscribe linux your@preferred.email.address
   if you have questions, ask...

2) If you have Challenge-S patches, e-mail them to the list
   and we can check that they didn't break anything and
   merge them into the source tree.

-- 
Peace, Ariel

From owner-linux@cthulhu.engr.sgi.com  Wed Sep  3 20:41:46 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: linux@cthulhu.engr.sgi.com
Subject: Need help with with irix_elfmap.
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    I am trying to run the IRIX Xsgi server on top of Linux/SGI, and I
am running into some very strange problems.  If i let the program run
loose, the code crashes miserably inside a function called
_XSERVTransOpenCOTServer, just after the functions unlinks the file
/usr/tmp/.Xshmtrans%d, and just before making the sysmp system call
(this one I supposed is used as part of the usinit () libc routine).

    This is listing of the system calls done on IRIX for the X server
around this point:

mkdir("/tmp/.X11-unix", 0777)           = -1 EEXIST (File exists)
unlink("/tmp/.X11-unix/X0")             = 0
bind(5, {sun_family=AF_UNIX, sun_path="/tmp/.X11-unix/X0"}, 19) = 0
listen(5, 5)                            = 0
umask(022)                              = 0
unlink("/usr/tmp/.Xshmtrans0")          = 0
sysmp(0x420, 0x1, 0xe, 0x3d, 0)         = 1

    On Linux, this code is executed:

mkdir("/tmp/.X11-unix", 0777)		= -1 EEXIST (File exists)
unlink("/tmp/.X11-unix/X0")             = 0
bind(5, {sun_family=AF_UNIX, sun_path="/tmp/.X11-unix/X0"}, 19) = 0
listen(5, 5)                            = 0
umask(022)                              = 0
unlink("/usr/tmp/.Xshmtrans0")          = 0
segfault

   Segmentation fault address = somewhere inside libc, return address
suggests the usinit() libc routine was called (I guess this from an
IRIX 6.4 machine where stock FSF-gdb happens to understand the
symbolic information on the libc)

    Now, this *may* suggest that the problem is on the libc usinit()
routine and that I ought to be figuring what happens inside of it, but
if I run the program under gdb [1], and if I take extra care to single
step around the region that calls usinit() the program won't crash at
that point, it will just happen to crash at some point later at random
places (ie, stepi over the code, then let it continue).

    So, does this ring any bell to anyone?  I have the impression that
the elfmap() routine in the IRIX kernel may be poking some values in
the user address space and probably flushing the caches.  Which is
strange, since the Linux implementation uses do_mmap and that should
take care of flushing any thing that should be flushed.

Miguel.

[1] I have a couple of patches to the gdb.tar.gz file that we got from
the original DaveM-pack that I really need to commit.


    

   

From owner-linux@cthulhu.engr.sgi.com  Thu Sep  4 13:29:58 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709042025.QAA08151@neon.ingenia.ca>
Subject: Re: Booting off of sdb1...
In-Reply-To: <199709022201.RAA26782@speedy.rd.qms.com> from Mark Salter at "Sep 2, 97 05:01:43 pm"
To: marks@sun470.sun470.rd.qms.com (Mark Salter)
Date: Thu, 4 Sep 1997 16:25:44 -0400 (EDT)
Cc: linux@cthulhu.engr.sgi.com (Linux/SGI list)
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Thus spake Mark Salter:
> Try this patch to linux/arch/mips/sgi/prom/cmdline.c:

Fixed it for me.  Thanks.

I'll commit that to the tree and put a new kernel up on
ftp.linux.sgi.com.

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>      Chief System Architect -- will tame sendmail(8) for food       
#>                                                                     
#> "You are a very perverse individual, and I think I'd like to get to 
#>  know you better." --- eric@reference.com                           

From owner-linux@cthulhu.engr.sgi.com  Thu Sep  4 19:54:10 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: linux@fir.engr.sgi.com
Subject: [Q: Linux/SGI] IRIX executable memory map.
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Hello guys,

    Ok, it seems our irix_elfmap routine is just fine, I just found
out with a simple test case that the code is trying to access memory
from the location at 0x200000 which is making my IRIX executables
crash (this one is crashing inside usinit ()).

    Is there something magic about 0x20000 on IRIX that I should be
aware of? 

    This 0x20000 location is quite strange to me, since this is not a
region of memory that happens to be part of the executable according
to gdb (look at exhibit [1]).  So, if it does not come from here, the
obvious guess is that this memory region comes from mmaping something:
either /dev/zero, or from the sys_sgi (ELFMAP) system call, but
neither par nor strace show any trace of a virual mapping taking place
in this region (exhibit [2] shows this).

     The exact location of the crash is shown on my third dump [3].

Best wishes,
Miguel.

Exhibit [1]: Local exec file image, from gdb.
        Entry point: 0x400870
        0x00400134 - 0x00400147 is .interp
        0x004001c8 - 0x004001e0 is .reginfo
        0x004001e0 - 0x004002d8 is .dynamic
        0x004002d8 - 0x004002ec is .liblist
        0x0040050c - 0x0040070c is .dynsym
        0x004002ec - 0x00400401 is .dynstr
        0x00400404 - 0x0040050c is .hash
        0x0040072c - 0x0040082c is .msym
        0x0040082c - 0x00400870 is .MIPS.stubs
        0x00400870 - 0x00400a00 is .text
        0x00400a00 - 0x00400a20 is .init
        0x10001000 - 0x10001010 is .rodata
        0x10001010 - 0x10001048 is .got
        0x10001048 - 0x10001054 is .bss

Exhibit [2]: par output from running simple test program:
    2mS    usinit( 5349): execve(./usinit, 0x7fff2f64, 0x7fff2f6c) OK
    5mS    usinit( 5349): open(/lib/rld, O_RDONLY, 04) = 3
    5mS    usinit( 5349): read(3, <7f 45 4c 46 01 02 01 00 00 00 00>...,512) = 512 
    5mS    usinit( 5349): elfmap(3, 0x7fff2d58, 2) = 0xfb60000
    6mS    usinit( 5349): close(3) OK
    6mS    usinit( 5349): getpagesize() = 4096
    6mS    usinit( 5349): open(/dev/zero, O_RDONLY, 01757022324) = 3
    7mS    usinit( 5349): mmap(0xfbc4000, 16384, PROT_WRITE|PROT_READ,
			       MAP_PRIVATE, 3, 0) = 0xfbc4000
    7mS    usinit( 5349): close(3) OK
    9mS    usinit( 5349): syssgi(SGI_USE_FP_BCOPY, 0, 0x1dc,
				0xffffffff, 0x7fff2d70, 0xfb8eee8) = 0
    9mS    usinit( 5349): open(/dev/zero, O_RDONLY, 01757022324) = 3
    9mS    usinit( 5349): mmap(0xfbc8000, 32768, PROT_WRITE|PROT_READ,
				MAP_PRIVATE, 3, 0) = 0xfbc8000
    9mS    usinit( 5349): close(3) OK
    9mS    usinit( 5349): syssgi(SGI_TOSSTSAVE) OK
    9mS    usinit( 5349): write(2, "Test\n", 5) = 5
The IRIX program crashes here when running on Linux. 
   10mS    usinit( 5349): sysmp(MP_NPROCS) = 1
   10mS    usinit( 5349): open(tm, O_RDWR, 016) = 3
   10mS    usinit( 5349): fcntl(3, F_SETFD, 1) OK
   10mS    usinit( 5349): fcntl(3, F_SETLKW, type=F_WRLCK
				whence=SEEK_SET start=0 len=1) OK
   10mS    usinit( 5349): syssgi(SGI_USE_FP_BCOPY, 0x1000, 0x7fff1d5c,
				0xffffffff, 0x10001008, 0x7fff2fc0) = 0
   11mS    usinit( 5349): read(3, <de ad ba be 00 00 00 05 00 44 05 50
	00 44 05 a0>..., 4096) = 4096
[more system calls deleted]


Exhibit [3]:

The culprit piece of code, taken from the IRIX libc:

0xfa52a10 <_usinit+44>: lui $t6,0x20
0xfa52a14 <_usinit+48>: lw $t7,3584($t6)        <- This one is the culprit

This is loading something from 0x200e00

From owner-linux@cthulhu.engr.sgi.com  Thu Sep  4 20:58:28 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
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This is my next show stopper:

   There is a misterious fcntl call in the IRIX Xsgi server:
it is called with the F_ALLOCSP flag, what is this flag used for in
the X server setup code?  

Cheers,
Miguel.

[
   Unsolved misteries -- update

   The magical address at 0x200000 in the IRIX executables contains
   a one zeroed-page, for now I have mapped an empty page at this
   location on every IRIX program that is ran on the system.

   Both the usinit() test and the Xsgi server can continue execution
   under this scenario now, but it is still hackish. 

]

From owner-linux@cthulhu.engr.sgi.com  Thu Sep  4 22:01:47 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709050458.AAA16971@neon.ingenia.ca>
Subject: Kernel for local disk stuff
To: linux@cthulhu.engr.sgi.com (Linux/SGI list)
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ftp://ftp.linux.sgi.com/pub/test/vmlinux-950905.gz works for me for
mounting local disk as root.

Getting a local disk set up is still a minor nightmare, because
there's no simple boot image yet (though Alex is working on it), and
because heavy ethernet traffic occasionally generates bus errors that
lock up the box.  I'm going to take a look at what causes those
tomorrow, hopefully.

(I'm also going to reinstall IRIX on the primary disk.  mke2fs
can really wreck IRIX's day. =) )

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>              Linux: because every cycle counts.
#>
#> "I don't know what you do for a living[...]" -- perry@piermont.com
#>        "I change the world." -- davem@caip.rutgers.edu

From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 11:52:05 1997
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	Miguel de Icaza on Thu, 4 Sep 1997 21:45:31 -0500)
Subject: Re: [Q: Linux/SGI] IRIX executable memory map.
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IRIX unsolved misteries -- second update.

I said:

>     Ok, it seems our irix_elfmap routine is just fine, I just found
> out with a simple test case that the code is trying to access memory
> from the location at 0x200000 which is making my IRIX executables
> crash (this one is crashing inside usinit ()).

I was debatting this with my bed sheets this morning and I believe
that this page may be a special trick for IRIX sproc()ed binaries.
Probably I should also turn off the cache on this page.

Miguel.



From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 13:38:55 1997
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From: ariel@oz.engr.sgi.com (Ariel Faigon)
Message-Id: <199709052036.NAA29563@oz.engr.sgi.com>
Subject: 2.1.53 (from Linus)
To: linux@cthulhu.engr.sgi.com (SGI/Linux mailing list)
Date: Fri, 5 Sep 1997 13:36:12 -0700 (PDT)
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Just thought this would be of relevance to some:

Subject: Linux-2.1.53..
From: Linus Torvalds <torvalds@transmeta.com>
Date: Thu, 4 Sep 1997 17:10:27 -0700
Message-ID: <Pine.LNX.3.95.970904170831.428J-100000@penguin.transmeta.com>
Newsgroups: .mlist. linux-kernel linux-kernel@vger.rutgers.edu


I released a 2.1.53, which fixes two major bugs in the 2.1.x series. Ingo
Molnar found one (and hopefully _the_) reason for dcache corruption in
d_move(), and David Miller found and fixed a TCP-related crash-inducer. 

In short, I hope 2.1.53 will finally be stable for people,

                        Linus



-- 
Peace, Ariel

From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 15:33:37 1997
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Mike Shaver said:
> because heavy ethernet traffic occasionally generates bus errors that
> lock up the box.  I'm going to take a look at what causes those
> tomorrow, hopefully.

These finally annoyed me to the point I started looking at it today. I
was able to hack the buserr irq handler to set up a gdb frame so that
gdb gets control at the instruction that was interrupted. The problem
appears to be in sgiseeq.c which is no great surprise since it occurs
during times of heavy network traffic. The bus error irqs always occur
when interrupts are reenabled in the ret_from_sys_call after a sgiseeq
irq. The hpc_ethregs tx_ctrl value is 0x1 indicating that transmit was
inactive, but there was an underflow. The tx_ndptr value is 0xffffffff.
The latter I think leads to the bus error. Look at kick_tx() being
called from sgiseeq_tx() during the handling of the interrupt. With
that value of tx_ndptr, kick_tx would end up writing to 0xbffffff0
which is not we want to do. I don't have the HPC docs, so I'm probably
not going to be able to come up with a proper fix...

--Mark




From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 15:52:42 1997
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: [Q: Linux/SGI] IRIX executable memory map.
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Miguel de Icaza writes:
 > 
 > Hello guys,
 > 
 >     Ok, it seems our irix_elfmap routine is just fine, I just found
 > out with a simple test case that the code is trying to access memory
 > from the location at 0x200000 which is making my IRIX executables
 > crash (this one is crashing inside usinit ()).
 > 
 >     Is there something magic about 0x20000 on IRIX that I should be
 > aware of? 

     0x20000 (not 0x200000) is automatically mapped in a process
by the kernel when referenced.  See <sys/prctl.h> on IRIX for
the definitions.  Most of the fields you can probably ignore,
but you should set t_pid, t_rpid, and t_prid (where the latter is the value
of the $prid COP0 register).  Set t_pid and t_rpid to the pid of the process.
(They cannot really be different in IRIX.)

     The library is fetching the PID from t_pid instead of calling getpid()
for performance reasons.

     Simply automatically create the page in the page fault handler
when it is first referenced.  Treat as if it were an mmap() of /dev/zero
for 1 page.


From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 15:58:29 1997
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: [Q: Linux/SGI] IRIX executable memory map.
In-Reply-To: <199709051842.NAA07307@athena.nuclecu.unam.mx>
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Miguel de Icaza writes:
 > 
 > IRIX unsolved misteries -- second update.
 > 
 > I said:
 > 
 > >     Ok, it seems our irix_elfmap routine is just fine, I just found
 > > out with a simple test case that the code is trying to access memory
 > > from the location at 0x200000 which is making my IRIX executables
 > > crash (this one is crashing inside usinit ()).
 > 
 > I was debatting this with my bed sheets this morning and I believe
 > that this page may be a special trick for IRIX sproc()ed binaries.
 > Probably I should also turn off the cache on this page.

     No, I think this page should be private to a given thread (sproc
or process), and it can be cached.  

From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 16:13:30 1997
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From: alan@lxorguk.ukuu.org.uk (Alan Cox)
Subject: Re: [Q: Linux/SGI] IRIX executable memory map.
To: wje@fir.engr.sgi.com (William J. Earl)
Date: Sat, 6 Sep 1997 00:05:56 +0100 (BST)
Cc: miguel@nuclecu.unam.mx, linux@fir.engr.sgi.com
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>      Simply automatically create the page in the page fault handler
> when it is first referenced.  Treat as if it were an mmap() of /dev/zero
> for 1 page.

Better to map it first. page fault is a far more critical path to stick
conditionals into. Even better if possible is to stick it into the userspace
dynamic loader for irix binaries. That however means not using the irix one
or having a "preloader" before it

Alan


From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 16:56:35 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: wje@fir.engr.sgi.com
CC: linux@fir.engr.sgi.com
In-reply-to: <199709052251.PAA20078@fir.engr.sgi.com> (wje@fir.engr.sgi.com)
Subject: Re: [Q: Linux/SGI] IRIX executable memory map.
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>      0x20000 (not 0x200000) is automatically mapped in a process
> by the kernel when referenced.  See <sys/prctl.h> on IRIX for
> the definitions.  

Ok, thanks for the pointer.  btw, the code seems to indicate that the
address is indeed 0x200000 (it does a lui $reg,0x20).  Oops.  Hold
on.  The sys/prctl agrees with me, it is 0x200000.

That structure looks very promising, I will go and fill it.

> Most of the fields you can probably ignore, but you should set
> t_pid, t_rpid, and t_prid (where the latter is the value of the
> $prid COP0 register).  Set t_pid and t_rpid to the pid of the
> process.  (They cannot really be different in IRIX.)

Ok.  There is another bit that looks promising: the t_cpu field, which
is supposed to have the cpu number where the process is executing.
Does IRIX update this on every context switch? 

>      Simply automatically create the page in the page fault handler
> when it is first referenced.  Treat as if it were an mmap() of /dev/zero
> for 1 page.

Ok.  The code that I used last night to work around this was to map
a /dev/zero page at sys_irix_elfexec time, I think I will just poke
the right values there.

best wishes and thanks for this pointer!
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 16:59:44 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: alan@lxorguk.ukuu.org.uk
CC: wje@fir.engr.sgi.com, linux@fir.engr.sgi.com
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	(alan@lxorguk.ukuu.org.uk)
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> Better to map it first. page fault is a far more critical path to stick
> conditionals into. Even better if possible is to stick it into the userspace
> dynamic loader for irix binaries. That however means not using the irix one
> or having a "preloader" before it

Nah.  We already have an IRIX specific ELF loader, so I will just
modify my existing mmap in that place.  No need for extra hacks if a
10 line change to irixelf.c fixes it.

Cheers,
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 17:34:13 1997
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Received: by thoma (SMI-8.6/KO-2.0)
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Subject: Re: [Q: Linux/SGI] IRIX executable memory map.
To: wje@fir.engr.sgi.com (William J. Earl)
Date: Sat, 6 Sep 1997 02:33:05 +0200 (MET DST)
Cc: miguel@nuclecu.unam.mx, linux@fir.engr.sgi.com
In-Reply-To: <199709052251.PAA20078@fir.engr.sgi.com> from "William J. Earl" at Sep 5, 97 03:51:00 pm
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Hi,

>      The library is fetching the PID from t_pid instead of calling getpid()
> for performance reasons.

Byte Benchmarks ;-)

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 18:32:11 1997
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From: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
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Subject: Re: 2.1.53 (from Linus)
To: ariel@cthulhu.engr.sgi.com
Date: Sat, 6 Sep 1997 03:31:00 +0200 (MET DST)
Cc: linux@cthulhu.engr.sgi.com
In-Reply-To: <199709052036.NAA29563@oz.engr.sgi.com> from "Ariel Faigon" at Sep 5, 97 01:36:12 pm
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> Just thought this would be of relevance to some:
> 
> Subject: Linux-2.1.53..
> From: Linus Torvalds <torvalds@transmeta.com>
> Date: Thu, 4 Sep 1997 17:10:27 -0700
> Message-ID: <Pine.LNX.3.95.970904170831.428J-100000@penguin.transmeta.com>
> Newsgroups: .mlist. linux-kernel linux-kernel@vger.rutgers.edu
> 
> 
> I released a 2.1.53, which fixes two major bugs in the 2.1.x series. Ingo
> Molnar found one (and hopefully _the_) reason for dcache corruption in
> d_move(), and David Miller found and fixed a TCP-related crash-inducer. 
> 
> In short, I hope 2.1.53 will finally be stable for people,

I've fixed a couple more showstoppers in the MIPS part of the kernel.
In particular the kernel was misstreating all non-R4000/R4400 CPUs
with virtual indexed caches but without a second level caches or
a cachesize other than 16kbit.  For I/O this might result in old data
being written back to the disk.

I suspect this was the source of the Inode corruption I was observing
on my R5k Indy as well as the frequent crashes on my R4600 and R4300 box.
The big brother, an R5230 eval board I'm hacking right now has been stable
over days, same for the NCR driver.  The Z8530 driver however is still
as fragile as a snowflake.

I've fixed a couple of other showstoppers as well.  I'm currently
working on cleanly integrating yet another port into the source tree.
When this and some other important debugging (new init versions die)
is done, I'll merge back all the stuff.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 19:01:01 1997
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Date: Fri, 5 Sep 1997 19:00:26 -0700
Message-Id: <199709060200.TAA20744@fir.engr.sgi.com>
From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: [Q: Linux/SGI] IRIX executable memory map.
In-Reply-To: <199709052347.SAA09349@athena.nuclecu.unam.mx>
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Miguel de Icaza writes:
 > 
 > >      0x20000 (not 0x200000) is automatically mapped in a process
 > > by the kernel when referenced.  See <sys/prctl.h> on IRIX for
 > > the definitions.  
 > 
 > Ok, thanks for the pointer.  btw, the code seems to indicate that the
 > address is indeed 0x200000 (it does a lui $reg,0x20).  Oops.  Hold
 > on.  The sys/prctl agrees with me, it is 0x200000.

    Yes, you are correct.  

...
 > > Most of the fields you can probably ignore, but you should set
 > > t_pid, t_rpid, and t_prid (where the latter is the value of the
 > > $prid COP0 register).  Set t_pid and t_rpid to the pid of the
 > > process.  (They cannot really be different in IRIX.)
 > 
 > Ok.  There is another bit that looks promising: the t_cpu field, which
 > is supposed to have the cpu number where the process is executing.
 > Does IRIX update this on every context switch? 

     Yes, on a multiprocessor, but it is a constant on a uniprocessor.

 > >      Simply automatically create the page in the page fault handler
 > > when it is first referenced.  Treat as if it were an mmap() of /dev/zero
 > > for 1 page.
 > 
 > Ok.  The code that I used last night to work around this was to map
 > a /dev/zero page at sys_irix_elfexec time, I think I will just poke
 > the right values there.

      As someone else pointed out, mapping the page is sys_irix_elfexec
time is probably better, since it will avoid slowing down the page
fault handler.

From owner-linux@cthulhu.engr.sgi.com  Fri Sep  5 19:03:24 1997
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Date: Fri, 5 Sep 1997 19:03:01 -0700
Message-Id: <199709060203.TAA20799@fir.engr.sgi.com>
From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
Cc: miguel@nuclecu.unam.mx, linux@fir.engr.sgi.com
Subject: Re: [Q: Linux/SGI] IRIX executable memory map.
In-Reply-To: <199709060033.CAA11262@informatik.uni-koblenz.de>
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Ralf Baechle writes:
 > Hi,
 > 
 > >      The library is fetching the PID from t_pid instead of calling getpid()
 > > for performance reasons.
 > 
 > Byte Benchmarks ;-)

     Actually not, although we have thought about it.  getpid() itself is
a system call, even though it could just use the PRDA.  Note, however, that
IRIX processes which do not use the usema stuff generally do not have the
PRDA mapped, since we wanted to avoid allocating an extra page per process
for processes which do not use it.

From owner-linux@cthulhu.engr.sgi.com  Mon Sep  8 10:55:56 1997
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Message-Id: <199709081755.KAA27906@fir.engr.sgi.com>
From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: IRIX emulation, getting there.
In-Reply-To: <199709050350.WAA03387@athena.nuclecu.unam.mx>
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Miguel de Icaza writes:
 > 
 > This is my next show stopper:
 > 
 >    There is a misterious fcntl call in the IRIX Xsgi server:
 > it is called with the F_ALLOCSP flag, what is this flag used for in
 > the X server setup code?  
...

     This fcntl() sets the size of a file, and assures that
the underlying storage is really assigned.  From fcntl(2):

     F_FREESP  Alter storage space associated with a section of	the ordinary
	       file fildes.  The section is specified by a variable of data
	       type struct flock pointed to by the third argument arg.	The
	       data type struct	flock is defined in the	<fcntl.h> header file
	       [see fcntl(5)] and contains the following members:  l_whence is
	       0, 1, or	2 to indicate that the relative	offset l_start will be
	       measured	from the start of the file, the	current	position, or
	       the end of the file, respectively.  l_start is the offset from
	       the position specified in l_whence.  l_len is the size of the
	       section.	 An l_len of 0 frees up	to the end of the file;	in
	       this case, the end of file (i.e., file size) is set to the
	       beginning of the	section	freed.	Any data previously written
	       into this section is no longer accessible.  If the section
	       specified is beyond the current end of file, the	file is	grown
	       and filled with zeroes.	The l_len field	is currently ignored,
	       and should be set to 0.

     F_ALLOCSP This command is identical to F_FREESP.


From owner-linux@cthulhu.engr.sgi.com  Wed Sep 10 16:22:59 1997
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From: alan@lxorguk.ukuu.org.uk (Alan Cox)
To: linux@cthulhu.engr.sgi.com
Subject: Linux and SGI EFS
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I've been digging around the EFS stuff while I wait for my SGI to
materialise. It seems however thats another task we can do nice and fast

http://wwwcip.informatik.uni-erlangen.de/user/cnvogelg/proj.html

has a 2.0 read only EFS module for Linux

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 10 19:13:20 1997
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	Wed, 10 Sep 1997 21:04:06 -0500
Date: Wed, 10 Sep 1997 21:04:06 -0500
Message-Id: <199709110204.VAA25377@athena.nuclecu.unam.mx>
From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: linux@fir.engr.sgi.com
Subject: Linux/SGI: MAP_AUTOGROW, F_ALLOCSP
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Hello,

   I am running into a new problem: the X server is doing the
following:

	unlink ("/tmp/.Xshmtrans0");
	tfd = open ("/tmp/.Xshmtrans0", O_RDWR | O_CREAT);
	fcntl(tfd, F_SETFD, 1);
	fcntl(tfd, F_SETLKW, type=F_WRLCL, whence=SEEK_SET start=0 len=1)
	read(6, 0x7fff1b04, 4096) = 0;
	fstat(6, 0x7fff18e0) = 0;
	lseek(6, 0, SEEK_SET) = 0
	fcntl(6, F_ALLOCSP, whence=SEEK_SET, start=5224 len=0)
	mmap(0xe800000, 2149480, PROT_WRITE|PROT_READ, MAP_SHARED|MAP_AUTOGROW, 6, 0) = 0xe800000

   OK, my problem right now is that the code is using the MAP_AUTOGROW
flag for mmap.  And the second problem is that I do not understand
what the role for F_ALLOCSP is (thanks to all of you that sent me
information on this flag), but it still does not make sense.

   Regarding F_ALLOCSP: I am ignoring it.

   Regarding mmap (..., MAP_AUTOGROW,...) I have implemented two
solutions: 

	1. The "this does not have a chance of being accepted by the
	   Main Penguin" approach which implemented MAP_AUTOGROW:

		basically: new flag, and an extra if in mm/filemap.c:
	        filemap_nopage () routine.

	   This flag is not even on the opengroup web pages, so it has
           a very little chance of being accepted just for Xsgi's
           sake. 

	2. The "this sucks, but it will get into the main
           kernel real fast": on irix_mmap () if the MAP_AUTOGROW flag
           is set, it will check if the top limit for the mmap is
           bigger that the current file size, if it is it does:
	
		o = sys_lseek (fd, offset + len - 1, SEEK_SET);
		sys_write (fd, "", 1);
		sys_lseek (fd, o, SEEK_SET);

     Any ideas, comments?  I am ready to commit approach (2) ;-)

Cheers,
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 10 19:17:08 1997
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Date: Wed, 10 Sep 1997 19:16:48 -0700
Message-Id: <199709110216.TAA26791@fir.engr.sgi.com>
From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: Linux/SGI: MAP_AUTOGROW, F_ALLOCSP
In-Reply-To: <199709110204.VAA25377@athena.nuclecu.unam.mx>
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Miguel de Icaza writes:
...
 > 	2. The "this sucks, but it will get into the main
 >            kernel real fast": on irix_mmap () if the MAP_AUTOGROW flag
 >            is set, it will check if the top limit for the mmap is
 >            bigger that the current file size, if it is it does:
 > 	
 > 		o = sys_lseek (fd, offset + len - 1, SEEK_SET);
 > 		sys_write (fd, "", 1);
 > 		sys_lseek (fd, o, SEEK_SET);
 > 
 >      Any ideas, comments?  I am ready to commit approach (2) ;-)
...

     This seems reasonable enough.  This code supports the "shm" shared
memory transport of Xsgi; other process mmap() the file to communicate
with the server.  It is something of a hack (being not particularly secure).


From owner-linux@cthulhu.engr.sgi.com  Wed Sep 10 20:12:29 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: linux@fir.engr.sgi.com
Subject: Linux/SGI: Xsgi Shmiq/Qcntl
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Hello guys,

    Ok, 120 system calls after the last one, I need some more help.
If somebody can quickly look up the IRIX X sources, I would appreciate
if you could tell me how a little routine works.

    The source code should be in a directory called:
xc/programs/Xserver/hw/sgi 

    The code does an open on /dev/shmiq and then opens: sprintf (buf,
"/dev/qcntl%d", mistery_variable) I want to know how it computes
mistery_variable.  I am obviously screwing something in the shmiq
emulation code. 

Cheers,
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 10 20:53:06 1997
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Subject: R5000 caches
To: linux@cthulhu.engr.sgi.com
Date: Thu, 11 Sep 1997 05:51:07 +0200 (MET DST)
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Hi,

Can anybody give me a pointer to where the R5000 caches, especially
the cache instruction, are documented?  My two IDT R5000 manuals don't
contain the least bit of information regarding the cache instruction.
I'm primarily interested in how the indexed operations select the
cache set of the primary caches to operate on.  On the R4600 which has
16kb per cache bit 13 selects the set.  So I assume it's bit 14 on the
R5000 with it's 32kb per cache?  The code from David handles the
R5000 like a R4000 CPU but this doesn't look very credible to me as
this is a QED CPU and the other members of the R5k family like the
Nevada (which run Linux now also!) have two way primary caches.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 10 21:11:25 1997
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From: "David S. Miller" <davem@jenolan.rutgers.edu>
To: ralf@mailhost.uni-koblenz.de
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In-reply-to: <199709110351.FAA08065@informatik.uni-koblenz.de> (message from
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   From: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
   Date: Thu, 11 Sep 1997 05:51:07 +0200 (MET DST)

   Can anybody give me a pointer to where the R5000 caches, especially
   the cache instruction, are documented?  My two IDT R5000 manuals
   don't contain the least bit of information regarding the cache
   instruction.  I'm primarily interested in how the indexed
   operations select the cache set of the primary caches to operate
   on.  On the R4600 which has 16kb per cache bit 13 selects the set.
   So I assume it's bit 14 on the R5000 with it's 32kb per cache?  The
   code from David handles the R5000 like a R4000 CPU but this doesn't
   look very credible to me as this is a QED CPU and the other members
   of the R5k family like the Nevada (which run Linux now also!) have
   two way primary caches.

In SGI boxes, if my memory serves, the R5k's were the chips which
needed the special:

	cli();
	jump_into_64_bit_mode();
	{peek,poke}_magic_physaddr();
	leave_64_bit_mode();
	sti();

sequence, both to enable/disable the cache and to perform flush
operations.  Although this could have been for the R4600.  I do
remember that IRIX had special code to work the R5k caches, but this
might have been for the L2 cache operations only, not L1.

All of this was very SGI specific and was mostly for the L2 cache
operations.  I think the R5k had a special "flush command" which would
just pull a pin going to the cache and invalidate all the lines in one
cycle (earle told me this, he may be able to elaborate).

The R5k, by design at least in the SGI boxes, lacks a L2 cache, it was
added externally on the SGI motherboard's, and thus all the funcy
methods to access/enable/disable/flush it...  Again, I could be
confusing r4600 and r5k here, so who knows.

Later,
David "Sparc" Miller
davem@caip.rutgers.edu

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 10 21:29:21 1997
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Subject: Re: R5000 caches
To: davem@jenolan.rutgers.edu (David S. Miller)
Date: Thu, 11 Sep 1997 06:28:17 +0200 (MET DST)
Cc: ralf@mailhost.uni-koblenz.de, linux@cthulhu.engr.sgi.com
In-Reply-To: <199709110409.AAA14641@jenolan.rutgers.edu> from "David S. Miller" at Sep 11, 97 00:09:23 am
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> In SGI boxes, if my memory serves, the R5k's were the chips which
> needed the special:
> 
> 	cli();
> 	jump_into_64_bit_mode();
> 	{peek,poke}_magic_physaddr();
> 	leave_64_bit_mode();
> 	sti();
> 
> sequence, both to enable/disable the cache and to perform flush
> operations.  Although this could have been for the R4600.  I do

Afaik it's for both CPUs.

> remember that IRIX had special code to work the R5k caches, but this
> might have been for the L2 cache operations only, not L1.
> 
> All of this was very SGI specific and was mostly for the L2 cache
> operations.  I think the R5k had a special "flush command" which would
> just pull a pin going to the cache and invalidate all the lines in one
> cycle (earle told me this, he may be able to elaborate).

It's the L2 enable bit for the "true", means CPU controlled L2 cache
of the R5000.  The fact that we're dealing with two different types
of L2 caches for the R5000 complicates things slightly.  By design
the R5000 supports an external cache.  What SGI did was more or less
just ignoring that feature and using the R5000 as a R4600 replacement.
That's why they're using an external cache which is controlled by
the chipset.

> The R5k, by design at least in the SGI boxes, lacks a L2 cache, it was
> added externally on the SGI motherboard's, and thus all the funcy
> methods to access/enable/disable/flush it...  Again, I could be
> confusing r4600 and r5k here, so who knows.

Well, your memory serves right.  However my problem are especially
the primary caches (I've got not box with a "true" R5000 L2 cache), so
that doesn't solve my problem.  As far as I can tell your R4600 code seems
to work for the R5000 Indy with the "fake" cache.  I suspect that the
problem handling the L1 caches was causing the disk corruption I observed
on my Indy while on this Nevada box I'm using here SCSI works as realiable
as it is supposed to be.

Anyway, there is still enough fun to have.  I'm planning a little
lmbenchmania followed by a cycle-massacre and I'm just hacking
microsecond timers for that ...

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 10 23:55:29 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709110452.AAA03150@neon.ingenia.ca>
Subject: Re: Linux/SGI: Xsgi Shmiq/Qcntl
In-Reply-To: <199709110303.WAA25810@athena.nuclecu.unam.mx> from Miguel de Icaza at "Sep 10, 97 10:03:09 pm"
To: miguel@nuclecu.unam.mx (Miguel de Icaza)
Date: Thu, 11 Sep 1997 00:52:56 -0400 (EDT)
Cc: linux@fir.engr.sgi.com
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Thus spake Miguel de Icaza:
>     The code does an open on /dev/shmiq and then opens: sprintf (buf,
> "/dev/qcntl%d", mistery_variable) I want to know how it computes
> mistery_variable.  I am obviously screwing something in the shmiq
> emulation code. 

If it's like the rest of the shmiq stuff, it's probably the minor
number.   Remind me to test that stuff better now that I have an
Indy. =)

Mike

-- 
#> Mike Shaver (shaver@ingenia.com)      Information Warfare Division  
#> Chief Tactical and Strategic Officer         "Saepe fidelis"        
#>                                                                     
#> "I like your game, but we have to change the rules." -- Anon        
#>                                                                     

From owner-linux@cthulhu.engr.sgi.com  Thu Sep 11 00:36:34 1997
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From: alan@lxorguk.ukuu.org.uk (Alan Cox)
Subject: Re: Linux/SGI: MAP_AUTOGROW, F_ALLOCSP
To: wje@fir.engr.sgi.com (William J. Earl)
Date: Thu, 11 Sep 1997 08:26:10 +0100 (BST)
Cc: miguel@nuclecu.unam.mx, linux@fir.engr.sgi.com
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>      This seems reasonable enough.  This code supports the "shm" shared
> memory transport of Xsgi; other process mmap() the file to communicate
> with the server.  It is something of a hack (being not particularly secure).

So you use mmap() based XShm rather than the SYS5 ipc based shm Linux currently
uses. Makes some sense. As to secure well last time I looked nobody had yet
fixed the auth bug so X and security aren't related anyway



From owner-linux@cthulhu.engr.sgi.com  Thu Sep 11 17:55:55 1997
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: Linux/SGI: Xsgi Shmiq/Qcntl
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Miguel de Icaza writes:
 > 
 > Hello guys,
 > 
 >     Ok, 120 system calls after the last one, I need some more help.
 > If somebody can quickly look up the IRIX X sources, I would appreciate
 > if you could tell me how a little routine works.
 > 
 >     The source code should be in a directory called:
 > xc/programs/Xserver/hw/sgi 
 > 
 >     The code does an open on /dev/shmiq and then opens: sprintf (buf,
 > "/dev/qcntl%d", mistery_variable) I want to know how it computes
 > mistery_variable.  I am obviously screwing something in the shmiq
 > emulation code. 

	fd = open( SHMIQDEVNAME, O_EXCL | O_RDWR | O_NOCTTY ) ;
	if ( fd < 0 ) {
		perror( "Failed to open shmiq device." ) ;
		return 0 ;
	}

	/* Now open the control character device */
	if ( fstat ( fd, &sb ) < 0 ) {
		perror( "fstat failed -- shmiq not opened." ) ;
		(void) close( fd ) ;
		return 0 ;
	}

	(void) sprintf( cntldev, QCNTLDEVFORMAT, minor( sb.st_rdev ) ) ;

The /dev/qcntl2 device is the control device for minor device 2 as returned
by the clone open of /dev/shmiq.  A clone device returns a different
minor device for each open call; minor device numbers are reused only
after they have been closed.  Similary, /dev/ptc is a clone device for getting
PTYs.



From owner-linux@cthulhu.engr.sgi.com  Thu Sep 11 18:03:06 1997
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Date: Thu, 11 Sep 1997 18:02:20 -0700
Message-Id: <199709120102.SAA10756@fir.engr.sgi.com>
From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
Cc: davem@jenolan.rutgers.edu (David S. Miller), linux@cthulhu.engr.sgi.com
Subject: Re: R5000 caches
In-Reply-To: <199709110428.GAA12438@informatik.uni-koblenz.de>
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	<199709110428.GAA12438@informatik.uni-koblenz.de>
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Ralf Baechle writes:
 > > In SGI boxes, if my memory serves, the R5k's were the chips which
 > > needed the special:
 > > 
 > > 	cli();
 > > 	jump_into_64_bit_mode();
 > > 	{peek,poke}_magic_physaddr();
 > > 	leave_64_bit_mode();
 > > 	sti();
 > > 
 > > sequence, both to enable/disable the cache and to perform flush
 > > operations.  Although this could have been for the R4600.  I do
 > 
 > Afaik it's for both CPUs.

     It applies to the secondary cache on the Indy R4600SC and R5000SC
and the Indigo2 R4600SC, but not to any other systems or processors.

     For primary caches, the set is selected by the high order bit of
the cache index (virtual address bit 13 on the R4600, virtual
address bit 14 on the R5000).  (Note that the R10000 is different: it
uses the low order address bit to select the set.)  

 > > remember that IRIX had special code to work the R5k caches, but this
 > > might have been for the L2 cache operations only, not L1.
 > > 
 > > All of this was very SGI specific and was mostly for the L2 cache
 > > operations.  I think the R5k had a special "flush command" which would
 > > just pull a pin going to the cache and invalidate all the lines in one
 > > cycle (earle told me this, he may be able to elaborate).
 >
 > It's the L2 enable bit for the "true", means CPU controlled L2 cache
 > of the R5000.  The fact that we're dealing with two different types
 > of L2 caches for the R5000 complicates things slightly.  By design
 > the R5000 supports an external cache.  What SGI did was more or less
 > just ignoring that feature and using the R5000 as a R4600 replacement.
 > That's why they're using an external cache which is controlled by
 > the chipset.

       Yes, that is correct for hte Indy, but the O2 R5000SC does
use the real R5000 secondary cache.  The L2 enable bit is set on O2
R5000SC and is not set on the Indy.

 > > The R5k, by design at least in the SGI boxes, lacks a L2 cache, it was
 > > added externally on the SGI motherboard's, and thus all the funcy
 > > methods to access/enable/disable/flush it...  Again, I could be
 > > confusing r4600 and r5k here, so who knows.
 >
 > Well, your memory serves right.  However my problem are especially
 > the primary caches (I've got not box with a "true" R5000 L2 cache), so
 > that doesn't solve my problem.  As far as I can tell your R4600 code seems
 > to work for the R5000 Indy with the "fake" cache.  I suspect that the
 > problem handling the L1 caches was causing the disk corruption I observed
 > on my Indy while on this Nevada box I'm using here SCSI works as realiable
 > as it is supposed to be.
...

      If you were using the index bits incorrectly, that would cause
disk corruption, and, as noted above, the set selection bit differs,
due to the size of the cache.  Basically, if the size of the cache is
X, then (X >> 1) is the set selection bit.  The R4600SC secondary
cache code should apply equally to the Indy R5000SC, without change.


From owner-linux@cthulhu.engr.sgi.com  Thu Sep 11 18:23:18 1997
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From: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
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Subject: Re: R5000 caches
To: wje@fir.engr.sgi.com (William J. Earl)
Date: Fri, 12 Sep 1997 03:22:15 +0200 (MET DST)
Cc: ralf@mailhost.uni-koblenz.de, davem@jenolan.rutgers.edu,
        linux@cthulhu.engr.sgi.com
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Hi,

>      For primary caches, the set is selected by the high order bit of
> the cache index (virtual address bit 13 on the R4600, virtual
> address bit 14 on the R5000).  (Note that the R10000 is different: it
> uses the low order address bit to select the set.)  

Indeed, but currently our only R10k problem is that we don't support
that thing at all ...

>        Yes, that is correct for hte Indy, but the O2 R5000SC does
> use the real R5000 secondary cache.  The L2 enable bit is set on O2
> R5000SC and is not set on the Indy.

>       If you were using the index bits incorrectly, that would cause
> disk corruption, and, as noted above, the set selection bit differs,
> due to the size of the cache.  Basically, if the size of the cache is
> X, then (X >> 1) is the set selection bit.  The R4600SC secondary
> cache code should apply equally to the Indy R5000SC, without change.

Ok, thanks for the information.  It's what I was expecting.  In that
case the version which I'm just about to check in is still not R5000
safe.  I'm going to fix that rsn.

Quickfix for R5000 hackers: change the #define for waybit in
arch/mips/mm/r4xx0.c from 0x2000 to (dcache_size >> 1).

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Thu Sep 11 18:35:30 1997
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Date: Thu, 11 Sep 1997 18:34:54 -0700
Message-Id: <199709120134.SAA10912@fir.engr.sgi.com>
From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
Cc: davem@jenolan.rutgers.edu, linux@cthulhu.engr.sgi.com
Subject: Re: R5000 caches
In-Reply-To: <199709120122.DAA12959@informatik.uni-koblenz.de>
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Ralf Baechle writes:
...
 > >       If you were using the index bits incorrectly, that would cause
 > > disk corruption, and, as noted above, the set selection bit differs,
 > > due to the size of the cache.  Basically, if the size of the cache is
 > > X, then (X >> 1) is the set selection bit.  The R4600SC secondary
 > > cache code should apply equally to the Indy R5000SC, without change.
 > 
 > Ok, thanks for the information.  It's what I was expecting.  In that
 > case the version which I'm just about to check in is still not R5000
 > safe.  I'm going to fix that rsn.
 > 
 > Quickfix for R5000 hackers: change the #define for waybit in
 > arch/mips/mm/r4xx0.c from 0x2000 to (dcache_size >> 1).

      By the way, in case you are not familiar with the problem, watch
out for the R4600 errata in regard to index invalidate.  Basically,
you need to disable interrupts while using the index invalidate
and index writeback invalidate instructions on R4600 Rev. 1.7, so that
invalidating a given line in one set is atomic with invalidating
the corresponding line in the second set.  You can turn on interrupts
periodically, but it is important to do both sets for a given index
at the same time, without the possibility of an interrupt or exception.
The errata can result in the same line winding up in both sets,
leading to stale data.  The bug is not present in the R4600 Rev. 2.0
or the R5000.


From owner-linux@cthulhu.engr.sgi.com  Thu Sep 11 18:58:29 1997
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Subject: Re: R5000 caches
To: wje@fir.engr.sgi.com (William J. Earl)
Date: Fri, 12 Sep 1997 03:57:20 +0200 (MET DST)
Cc: ralf@mailhost.uni-koblenz.de, davem@jenolan.rutgers.edu,
        linux@cthulhu.engr.sgi.com
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>       By the way, in case you are not familiar with the problem, watch
> out for the R4600 errata in regard to index invalidate.  Basically,
> you need to disable interrupts while using the index invalidate
> and index writeback invalidate instructions on R4600 Rev. 1.7, so that
> invalidating a given line in one set is atomic with invalidating
> the corresponding line in the second set.  You can turn on interrupts
> periodically, but it is important to do both sets for a given index
> at the same time, without the possibility of an interrupt or exception.
> The errata can result in the same line winding up in both sets,
> leading to stale data.  The bug is not present in the R4600 Rev. 2.0
> or the R5000.

There is a more elegant solution for this bug.  Just leave the interrupts
as they are and invalidate set b before set a.  Anyway, Linux currently
still handles this erratum by disabling interrupts.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Thu Sep 11 22:02:13 1997
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Message-Id: <199709120348.WAA03611@athena.nuclecu.unam.mx>
From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: linux@fir.engr.sgi.com
Subject: Linux/SGI /dev/opengl magic ioctl 
X-Windows: You'd better sit down.
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Hello guys,

   Ok, 2 questions 2 for tonight :-).

   Ok, I am getting close, just out of curiosity, what does the ioctl
cmd=1 do on the /dev/opengl device?  

   If the ioctl does not return 3, the X server complains.  Right now
I have this nice piece of code in the graphics driver:

	switch (cmd){
		...

	case 1:
		return 3;
		...
	}
   
    which is not exactly what I would like to have, so any comments
are appreciated.

    Second question: what does the GFX_LABEL ioctl do on the
/dev/opengl device?  I am missing this one in my implementation.

    I am around 100 system calls far from getting a nice display on
Linux/SGI X. 

Cheers,
Miguel.



From owner-linux@cthulhu.engr.sgi.com  Thu Sep 11 21:59:40 1997
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From: rtray@b1mcast13.esd.sgi.com (Robert Tray)
Message-Id: <199709120459.VAA05184@b1mcast13.esd.sgi.com>
To: linux@fir.engr.sgi.com, Miguel de Icaza <miguel@nuclecu.unam.mx>
Subject: Re:  Linux/SGI /dev/opengl magic ioctl
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>    From: Miguel de Icaza <miguel@nuclecu.unam.mx>
>    
>    
>    Hello guys,
>    
>       Ok, 2 questions 2 for tonight :-).
>    
>       Ok, I am getting close, just out of curiosity, what does the ioctl
>    cmd=1 do on the /dev/opengl device?  
>    
>       If the ioctl does not return 3, the X server complains.  Right now
>    I have this nice piece of code in the graphics driver:
>    
>    	switch (cmd){
>    		...
>    
>    	case 1:
>    		return 3;
>    		...
>    	}

This is basically a version check.  1 == GFX_SYNC which is supposed
to return a number which the kernel gfx driver and the Xserver agree
is the current version.  (The version you have is 3)

>        Second question: what does the GFX_LABEL ioctl do on the
>    /dev/opengl device?  I am missing this one in my implementation.
>    

The X server sends down the ":display.screen_number".  I don't see
the kernel doing anything with it.

Robert Tray

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 12 09:51:57 1997
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Date: Fri, 12 Sep 1997 09:50:45 -0700
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: Linux/SGI /dev/opengl magic ioctl 
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Miguel de Icaza writes:
 > 
 > Hello guys,
 > 
 >    Ok, 2 questions 2 for tonight :-).
 > 
 >    Ok, I am getting close, just out of curiosity, what does the ioctl
 > cmd=1 do on the /dev/opengl device?  
 > 
 >    If the ioctl does not return 3, the X server complains.  Right now
 > I have this nice piece of code in the graphics driver:
 > 
 > 	switch (cmd){
 > 		...
 > 
 > 	case 1:
 > 		return 3;
 > 		...
 > 	}
 >    
 >     which is not exactly what I would like to have, so any comments
 > are appreciated.

      It turns out that is pretty much what the graphics driver is doing
in IRIX:

	        case GFX_SYNC :
		{
			*rvalp = GFX_SYNC_VALUE;
			goto out;
		}

For GL (not OpenGL), if the process is an sproc (a process sharing and
address space and file descriptors with a parent or siblings), the driver
acquires a semaphore before doing an ioctl and releases it afterwards.
For OpenGL, this ioctl does not really do anything at all.  

 >     Second question: what does the GFX_LABEL ioctl do on the
 > /dev/opengl device?  I am missing this one in my implementation.

It copies GFX_INFO_LABEL_SIZE (16) bytes from the argument (a char *) to
the label field of the gfx_info struct for the graphics device.  The label
field is the choice of the current owner of the device, so it is not really
significant.  The /usr/gfx/gfxinfo command can print the gfx_info structure
for the local device.

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 12 23:45:09 1997
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Subject: Modutils 2.1.55
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Hi all,

I've upgraded the modutils to 2.1.55.  Since I've seen no ill effects
so far with modutils under Linux/MIPS I've sent the patches to
rth for inclusion in the standard package.  Patches are in the CVS
archive on ftp.linux.sgi.com, as well as a source and little endian
binary package.  I could not connect to fnet, so for now these files
will only be available on ftp.linux.sgi.com.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 16 08:04:35 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709161458.KAA01510@neon.ingenia.ca>
Subject: EFS update
To: linux@cthulhu.engr.sgi.com (Linux/SGI list)
Date: Tue, 16 Sep 1997 10:58:41 -0400 (EDT)
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OK, I've managed to merge (read: rewrite) the EFS module code into the
2.1.55 tree from linus.  I can mount my root IRIX partition, ls -l
stuff, run simple binaries and the like.  I don't handle symlinks
correctly, but that's going to be easy enough to fix.

I'm checking in my changes now, and I'll put a kernel up on ftp.linux
for people to test with.  This should make the installation process
_much_ simpler.

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>           Resident Linux bigot and kernel hacker. (OOPS!)           
#> `If you get bitten by a bug, tough luck...the one thing I won't do  
#> is feel sorry for you.  In fact, I might ask you to do it all over  
#> again, just to get more information.  I'm a heartless bastard.'     
#>                       -- Linus Torvalds (on development kernels)    

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 16 08:58:38 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709161552.LAA02252@neon.ingenia.ca>
Subject: EFS update II
To: linux@cthulhu.engr.sgi.com (Linux/SGI list)
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OK, there's more that needs fixing than the symlink handling.
I still don't handle indirect extents properly either, and I've got
something a little wrong in the directory reading that gives bogus
filenames on occasion.

I'll let you know when I have something usable.

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>              Commando Developer - Whatever It Takes
#>                                                                     
#> "See, you not only have to be a good coder to create a system like
#>    Linux, you have to be a sneaky bastard too." - Linus Torvalds

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 16 14:07:12 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709162101.RAA05770@neon.ingenia.ca>
Subject: EFS test kernel
To: linux@cthulhu.engr.sgi.com (Linux/SGI list)
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ftp://ftp.linux.sgi.com/pub/test/vmlinux-970916-efs.gz has rudimentary
support for EFS partition mounting, and it lets me do some basic stuff
on my IRIX partition, like list small[*] directories and run binaries.

I've got my IRIX root mounted at /usr/gnemul/irix (the emulation code
requires that location), and have a symlink /lib/rld ->
/usr/gnemul/irix/lib/rld.  I sometimes get problems specifying
executables by explicit path (./ls or /usr/gnemul/irix/bin/ls), but if
I put the current directory in my path and chdir to there, things like
ls and date and wc and uname work just fine.

Please let me know if you get any problems.

[*] small == not requiring indirect extents

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>                 Ignore the man behind the curtain.                  
#>                                                                     
#> "And then I realized that it never should have worked in the first  
#>  place.  Thus, it would not work again until rewritten." --- Anon.  

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 16 18:05:01 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709170058.UAA07380@neon.ingenia.ca>
Subject: EFS question
To: linux@cthulhu.engr.sgi.com (Linux/SGI list)
Date: Tue, 16 Sep 1997 20:58:22 -0400 (EDT)
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Just to make sure I understand this correctly:
- when an inode has <= EFS_DIRECTEXTENTS extents, they're stored directly
in the inode.
- when an inode has > EFS_DIRECTEXTENTS extents, the extents in the
inode refer to contiguous block regions that contain extents referring
to the real data.

The EFS code that Alan posted, in addition to having a curious
aversion to structures, seemed to think that the first 4 bytes of
dinode->di_u were the block number of a block containing extents, and
thus doesn't work very well with files with numext >
EFS_DIRECTEXTENTS.  I just want to ensure that I make a sane fix.

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>                 UNIX medicine man -- dark magick, cheap!            
#>                                                                     
#>  When the going gets tough, the tough give cryptic error messages.  
#>          "We believe in rough consensus and running code."          

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 16 18:34:02 1997
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Date: Tue, 16 Sep 1997 18:33:19 -0700
Message-Id: <199709170133.SAA20782@fir.engr.sgi.com>
From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Mike Shaver <shaver@neon.ingenia.ca>
Cc: linux@cthulhu.engr.sgi.com (Linux/SGI list)
Subject: Re: EFS question
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Mike Shaver writes:
 > Just to make sure I understand this correctly:
 > - when an inode has <= EFS_DIRECTEXTENTS extents, they're stored directly
 > in the inode.
 > - when an inode has > EFS_DIRECTEXTENTS extents, the extents in the
 > inode refer to contiguous block regions that contain extents referring
 > to the real data.
 > 
 > The EFS code that Alan posted, in addition to having a curious
 > aversion to structures, seemed to think that the first 4 bytes of
 > dinode->di_u were the block number of a block containing extents, and
 > thus doesn't work very well with files with numext >
 > EFS_DIRECTEXTENTS.  I just want to ensure that I make a sane fix.
...

      The above is correct.  When there are indirect extents,
the offset field of the first indirect extent in the inode
contains the number of indirect extents, not a file offset.

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 16 18:47:24 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709170141.VAA07688@neon.ingenia.ca>
Subject: Re: EFS question
In-Reply-To: <199709170133.SAA20782@fir.engr.sgi.com> from "William J. Earl" at "Sep 16, 97 06:33:19 pm"
To: wje@fir.engr.sgi.com (William J. Earl)
Date: Tue, 16 Sep 1997 21:41:47 -0400 (EDT)
Cc: linux@cthulhu.engr.sgi.com
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Thus spake William J. Earl:
> When there are indirect extents,
> the offset field of the first indirect extent in the inode
> contains the number of indirect extents, not a file offset.

_Ah!_
That makes _much_ more sense, then.

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>              Commando Developer - Whatever It Takes
#>                                                                     
#> "See, you not only have to be a good coder to create a system like
#>    Linux, you have to be a sneaky bastard too." - Linus Torvalds

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 17 18:45:19 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: linux@fir.engr.sgi.com
Subject: Linux/SGI Xsgi server: /dev/opengl ioctl NG1_SETDISPLAYMODE
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Hello guys,

   IRIX Xsgi server is now clearing the screen -and crashing since I
do not have a mouse driver yet, I am quickly coding the iDev mouse
driver now-.

   But while I am doing this, I would like to ask the list about
another ioctl that the X server is issuing: the NG1_SETDISPLAYMODE, it
is being called like this:

	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 0, 0xda0080 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 1, 0xda0100 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 2, 0xda0488 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 3, 0xda0490 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 4, 0xda0498 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 5, 0xda04a0 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 6, 0xda0500 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 7, 0xda0800 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 8, 0xda0900 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 9, 0xda0d00 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 0xa, 0xda0e00 });
	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 0xb, 0x4ac });

    Where the structure is { int wid;  unsigned int mode }.

    Can someone tell me what the newport driver on the IRIX kernel is
doing with these calls?

    There is also another intersesting ioctl done later:
NG1_SETGAMMARAMP0, this one takes 256 reds, 256 greens and 256 blues
that I assume I have to load, do they go directly to the xmap9 lookup
table?

Thanks in advance,
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 17 19:03:57 1997
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: Linux/SGI Xsgi server: /dev/opengl ioctl NG1_SETDISPLAYMODE
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Miguel de Icaza writes:
 > 
 > Hello guys,
 > 
 >    IRIX Xsgi server is now clearing the screen -and crashing since I
 > do not have a mouse driver yet, I am quickly coding the iDev mouse
 > driver now-.
 > 
 >    But while I am doing this, I would like to ask the list about
 > another ioctl that the X server is issuing: the NG1_SETDISPLAYMODE, it
 > is being called like this:
 > 
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 0, 0xda0080 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 1, 0xda0100 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 2, 0xda0488 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 3, 0xda0490 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 4, 0xda0498 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 5, 0xda04a0 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 6, 0xda0500 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 7, 0xda0800 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 8, 0xda0900 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 9, 0xda0d00 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 0xa, 0xda0e00 });
 > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 0xb, 0x4ac });
 > 
 >     Where the structure is { int wid;  unsigned int mode }.
 >
 >     Can someone tell me what the newport driver on the IRIX kernel is
 > doing with these calls?

     After waiting for the rex3 FIFO to drain, and the the xmap9 FIFO
to not be full, it sets the xmap9 mode register for the given "wid":

 	xmap9SetModeReg( rex3, wid, displaymode, ng1_video_timing[bd->boardnum]->cfreq ); 
where

#define xmap9SetModeReg(rex,modereg,data24,cfreq) 			\
	if (cfreq > 119 )						\
	    rex->set.dcbmode =  DCB_XMAP_ALL |  XM9_CRS_MODE_REG_DATA | \
                        DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL;	    	\
	else if (cfreq > 59) \
	    rex->set.dcbmode =  DCB_XMAP_ALL |  XM9_CRS_MODE_REG_DATA | \
                        DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL;    	\
	else \
	    rex->set.dcbmode =  DCB_XMAP_ALL |  XM9_CRS_MODE_REG_DATA | \
                        DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL;  	\
        rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff)

 >     There is also another intersesting ioctl done later:
 > NG1_SETGAMMARAMP0, this one takes 256 reds, 256 greens and 256 blues
 > that I assume I have to load, do they go directly to the xmap9 lookup
 > table?

       It sets the address register for the BT445 RAMDAC to 0, and then
then, for each RGB triple, does 

#define Bt445SetRGB( rex3, r, g, b ) \
	rex3->set.dcbdata0.byword = ( (r) << 24 ) | ( (g) << 16 ) | ( (b) << 8 )

Before setting the address and before storing each RGB triple, it does

#define BFIFOWAIT(rex) 	while ((rex)->p1.set.configmode & BFIFO);

to avoid getting a FIFO overrun.  


From owner-linux@cthulhu.engr.sgi.com  Wed Sep 17 20:33:59 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
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Subject: Re: Linux/SGI Xsgi server: /dev/opengl ioctl NG1_SETDISPLAYMODE
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Another question regarding the Newport:

>      After waiting for the rex3 FIFO to drain, and the the xmap9 FIFO
> to not be full, it sets the xmap9 mode register for the given "wid":
> 
> 	  xmap9SetModeReg( rex3, wid, displaymode, ng1_video_timing[bd->boardnum]->cfreq ); 

If the newport registers are available to the userland application,
why the X server does not directly call those routines instead of
relying on the kernel to perform them?  Is it a convention that
applications should only touch the rex3 registers and not attempt to
program any of the other chips on the dcb?

It would make sense since the graphics context switching would not
involve the kernel peeking at the chips on the dcb what their context
is and then the pain of restoring this.  

Miguel.


From owner-linux@cthulhu.engr.sgi.com  Wed Sep 17 23:03:46 1997
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From: rtray@b1mcast13.esd.sgi.com (Robert Tray)
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To: wje@fir.engr.sgi.com, Miguel de Icaza <miguel@nuclecu.unam.mx>
Subject: Re: Linux/SGI Xsgi server: /dev/opengl ioctl NG1_SETDISPLAYMODE
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>    From: "William J. Earl" <wje@fir.engr.sgi.com>
>    
>    Miguel de Icaza writes:
>     > 
>     >    But while I am doing this, I would like to ask the list about
>     > another ioctl that the X server is issuing: the NG1_SETDISPLAYMODE, it
>     > is being called like this:
>     > 
>     > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 0, 0xda0080 });
...
>     > 	ioctl (/dev/opengl, NG1_SETDISPLAYMODE, { 0xb, 0x4ac });
>     > 
>     >     Where the structure is { int wid;  unsigned int mode }.
>     >
>     >     Can someone tell me what the newport driver on the IRIX kernel is
>     > doing with these calls?
>    
>         After waiting for the rex3 FIFO to drain, and the the xmap9 FIFO
>    to not be full, it sets the xmap9 mode register for the given "wid":
>    
>     	xmap9SetModeReg( rex3, wid, displaymode, ng1_video_timing[bd->boardnum]->cfreq ); 
>    where

The XMAP9 controls how the frame buffer pixels are interpreted and displayed
to the monitor.  That is the frame buffer may be 24 bits deep but a certain
window may only be rendering 8 bits of PseudoColor (Color Index) while another
window is rendering two buffers of TrueColor (RGB) split 12+12.  It's also
used to control which of the multiple colormaps is used to index the Pseudo-
Color pixels.  The X server is typically just running 8 bit PseudoColor while
most GL programs run 12+12 RGB Double Buffer.

The X server presets a certain number of Window IDs (wid) to be certain standard
display modes ( eg. 1==Single buffer color index, 2==double buffer color index,
3==single buffer RGB, etc...).  The other half of this setup involves a telling
the backend hardware (VC2) which pixels use which Window ID (actually it's more
frequently called Display ID (DID) in the last few years).  The X server talks
directly to VC2 to load a DID table which describes which XMAP9 DID/WID index
every single pixel is using.  (I hope that poorly worded sentence made sense.)

The good news is that if you don't care about running GL programs in a separate
display mode then you only have to set one DID entry in the XMAP and tell VC2
that the whole screen uses the same index into XMAP.




>     >     There is also another intersesting ioctl done later:
>     > NG1_SETGAMMARAMP0, this one takes 256 reds, 256 greens and 256 blues
>     > that I assume I have to load, do they go directly to the xmap9 lookup
>     > table?
>    
>           It sets the address register for the BT445 RAMDAC to 0, and then
>    then, for each RGB triple, does 
>    
>    #define Bt445SetRGB( rex3, r, g, b ) \
>    	rex3->set.dcbdata0.byword = ( (r) << 24 ) | ( (g) << 16 ) | ( (b) << 8 )
>    
>    Before setting the address and before storing each RGB triple, it does
>    
>    #define BFIFOWAIT(rex) 	while ((rex)->p1.set.configmode & BFIFO);
>    
>    to avoid getting a FIFO overrun.  

The BrookTree 445 RAMDAC is that last chip the pixels go through on their way
out to the monitor.  It contains the gamma ramp to adjust the pixels for the
monitors non-linearity.

For Newport graphics there are two FIFOs.  One FIFO paces access to the
REX3 chip.  All the "back end" chips are accessed via an 8 bit Display Control
Bus (DCB) which is accessed throught hte REX3 dcbdata & dcbmode.  You can
do 64 bit writes to dcbdata but they get sent 8 bits at a time across the DCB.
So you need a second FIFO (BFIFO) to pace access to the back end chips.
Anyway that's the explanation for the BFIFOWAIT.




>    Another question regarding the Newport:
>    
>    >      After waiting for the rex3 FIFO to drain, and the the xmap9 FIFO
>    > to not be full, it sets the xmap9 mode register for the given "wid":
>    > 
>    > 	  xmap9SetModeReg( rex3, wid, displaymode, ng1_video_timing[bd->boardnum]->cfreq ); 
>    
>    If the newport registers are available to the userland application,
>    why the X server does not directly call those routines instead of
>    relying on the kernel to perform them?  Is it a convention that
>    applications should only touch the rex3 registers and not attempt to
>    program any of the other chips on the dcb?

The less that user code touches the DCB the better.  But truthfully the
biggest reason that the X server calls the kernel to set the XMAP regs
is historical.  In previous architectures those types of registers couldn't
be set by the X server and required and ioctl.  So one piece of code tends
to look like the piece that it was copied from...  However those registers
are only preset at initialization and not touched again by the server.  They
are touched frequently after that by the kernel at the request of GL and
to do swapbuffers.  So as far as the X server is concerned performance is
not a problem for those registers and it's best to avoid touching the DCB
when you can.

>    It would make sense since the graphics context switching would not
>    involve the kernel peeking at the chips on the dcb what their context
>    is and then the pain of restoring this.  

Yeah, we actually strongly suspected that graphics context switches while
the X server was accessing the DCB was causing the graphics to hang.  We
narrowed down the times that the X server accesses the DCB and that helped.

Robert Tray

From owner-linux@cthulhu.engr.sgi.com  Thu Sep 18 09:21:36 1997
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Miguel de Icaza <miguel@nuclecu.unam.mx>
Cc: linux@fir.engr.sgi.com
Subject: Re: Linux/SGI Xsgi server: /dev/opengl ioctl NG1_SETDISPLAYMODE
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Miguel de Icaza writes:
 > 
 > Another question regarding the Newport:
 > 
 > >      After waiting for the rex3 FIFO to drain, and the the xmap9 FIFO
 > > to not be full, it sets the xmap9 mode register for the given "wid":
 > > 
 > > 	  xmap9SetModeReg( rex3, wid, displaymode, ng1_video_timing[bd->boardnum]->cfreq ); 
 > 
 > If the newport registers are available to the userland application,
 > why the X server does not directly call those routines instead of
 > relying on the kernel to perform them?  Is it a convention that
 > applications should only touch the rex3 registers and not attempt to
 > program any of the other chips on the dcb?
 > 
 > It would make sense since the graphics context switching would not
 > involve the kernel peeking at the chips on the dcb what their context
 > is and then the pain of restoring this.  

      I believe that making this work reasonably would require some way
of making a given user-mode primitive atomic.  This can be hacked by via various
schemes, but the current IRIX implementation does all sequences which must
be atomic in the kernel.  (For example, if I must BFIFOWAIT and then do
some stores, but I context switch after the BFIFOWAIT, there is no guarantee
that the FIFO is not full when I regain control.)  

From owner-linux@cthulhu.engr.sgi.com  Thu Sep 18 11:54:39 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
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Subject: indirect EFS extent question
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I just read the comment in fs/efs_fs.h properly for the first time,
and things are now much clearer.  I think.

So, is _this_ correct?
	/* 
	 * We're indirect, so we need to start looking in the 
	 * indirect extents.
	 *
	 * EFS indirect extents are really doubly indirect:
	 * inode->di_u.di_extents (1st level extents) refers to
	 * contiguous blocks of extents (2nd level extents).  The
	 * block of these 2nd level extents contain direct extents (or
	 * 3rd level extents).  So, for each indirect extent in
	 * di_u.di_extents, we need to get a block of 2nd-level
	 * extents, get a block from one of the 2nd-level extents, and
	 * then check the extents in that final block -- which, at
	 * long last, contains direct extents.
	 */

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>      Chief System Architect -- will tame sendmail(8) for food       
#>                                                                     
#> "You are a very perverse individual, and I think I'd like to get to 
#>  know you better." --- eric@reference.com                           

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Hello guys, 

   Well, my IRIX Xsgi server is running on Linux/SGI without aborting
now.  It displays the nice X cursor and a black background (ie, no
nice X background yet.

   This is caused -I believe- because I am not actually loading the
xmap9 modes as kindly described by Bill.  I have not yet debugged that
problem (for some reason the display control bus locks out most of the
kernel, I will look into fixing this on the afternoon).

   There are a couple of problems here and there, but at least it
seems to be working, here is my list of known bugs for the emulation
bits of IRIX Xsgi:

1. Keymaps are hossed, trivial to fix.

2. Remote clients can not connect (but then, I believe this is caused
   because of some faulty bit on query-net-devices-ioctl emulation).

3. /dev/mouse is hosed: the shmiq device is broken; trivial to fix as well.

4. psaux device is not working, I do not have any idea of how this
   works, so I have to sit down and read docs.

5. my xmap9 loading routine has problems talking to the display
   bus.  This ought to be pretty easy to fix.  Right now, I am using
   the DCB real slow protocol to talk to the xmap9, probably this is
   the culprit:

	relevant dcbmode bits: 
 	CSHOLD = 12;  CSSETUP = 12; CSWIDTH = 0

   On the xmap9.h include file, the macro that loads values into the 
   xmap9 (xmapSetModeRegs) chooses the values for CSHOLD, CSSETUP and
   CSWIDTH based on the cfreq argument.  On the sample code that Bill
   showed me, this value was passed like this (last parameter):

 xmap9SetModeReg( rex3, wid, displaymode, ng1_video_timing[bd->boardnum]->cfreq );

   I am passing a 0 there which forces the cs values I showed previously.	

6. The rrm code is not quite what an IRIX X server expects, so more
   work on this area is required.  Which brings up an interesting
   question:

	I have the impression that you need to get a rendering node
        before you get permission to do direct rendering.  My guess is
        that the context switch information should not be stored on
        the per-process task_struct but on the rendering node
        instead.  Is this the case on IRIX?  I have not really though
        very well about this.

Thanks to all of the kind people at SGI who have helped me with
explanations, documentation and helpful advise in the past for getting
the X server up and running.

best wishes and have a nice day,
Miguel

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 19 13:20:33 1997
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From: ariel@oz.engr.sgi.com (Ariel Faigon)
Message-Id: <199709192019.NAA02902@oz.engr.sgi.com>
Subject: Re: Linux/SGI: IRIX X server -- kind-of-works-now status.
To: miguel@nuclecu.unam.mx (Miguel de Icaza)
Date: Fri, 19 Sep 1997 13:19:27 -0700 (PDT)
Cc: linux@cthulhu.engr.sgi.com (SGI/Linux mailing list)
In-Reply-To: <199709191928.OAA30318@athena.nuclecu.unam.mx> from "Miguel de Icaza" at Sep 19, 97 02:28:38 pm
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Miguel,

Congtratulations on getting Xsgi on Linux to this stage.

To me it is pretty amazing that you were able to do all this
only by looking at the HW docs, lots of syscall tracing, and so
few hints from us.  Keep up the great work. 

Please continue to update us on further progress until you have
a fully functional Xsgi server working.  Hope the X guys on the
list would be able to help on the remaining questions.

--
Peace, Ariel

:
:
:Hello guys, 
:
:   Well, my IRIX Xsgi server is running on Linux/SGI without aborting
:now.  It displays the nice X cursor and a black background (ie, no
:nice X background yet.
:

From owner-linux@cthulhu.engr.sgi.com  Sun Sep 21 14:54:39 1997
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From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: linux@cthulhu.engr.sgi.com
Subject: Linux/SGI: IRIX X server -- more status.
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Hello guys,

    Thanks to Robert Tray for helping me finding the proper protocol
that has to be used with the xmap9 and 24 hours of rest, the X server
is now displaying correctly on my machine.  

    The reason the ioctl NG1_SETDISPLAYMODE was hanging my machine was
pretty easy: on the xmap9 documentation it says that the number of
entries available on the xmap9 fifo is a 3 bit number, but later on
the document, it explains that this number is actually mapped like
this:

	000	- no entries available
	001	- one entry available
	011	- two entries available
	010	- three entries available.
	
    Next time I will be more careful reading that.

    Now, I am off to test xterm and merge my code with the cvs
repository at linux.sgi.com.

Cheers,
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Mon Sep 22 19:43:58 1997
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Message-Id: <199709230232.VAA16659@athena.nuclecu.unam.mx>
From: Miguel de Icaza <miguel@nuclecu.unam.mx>
To: linux-mips@fnet.fr, linux@fir.engr.sgi.com
Subject: Task list --preliminary list
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Here is a preliminary task list of things that should be done for a
complete Linux/MIPS port, right now it includes by personal favorites
and I am working on some of those bits, but some of the other can be
done now, I have a copy of this at:

	http://www.nuclecu.unam.mx/~miguel/mips-task-list.txt

Priority: 

[9]  Get more userland programs compiled in RPM form

[9]  Merging the latest GNU libc releases.

[9]  Get the X libraries compiled.

[5]  Getting SGI mouse to work.

[5]  Test the STREAMS implementation of the mouse.

[6]  Figure why init is setting the sigprocmask to a value different
     from 0.  This disables the debugger (SIGTRAP is disabled for
     all child processes).

[7]  Getting IRIX X server to accept connections.

Please, send me additions to this list.
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Mon Sep 22 20:05:55 1997
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From: ariel@oz.engr.sgi.com (Ariel Faigon)
Message-Id: <199709230305.UAA09789@oz.engr.sgi.com>
Subject: Re: Task list --preliminary list
To: miguel@nuclecu.unam.mx (Miguel de Icaza)
Date: Mon, 22 Sep 1997 20:05:26 -0700 (PDT)
Cc: linux@cthulhu.engr.sgi.com (SGI/Linux mailing list)
In-Reply-To: <199709230232.VAA16659@athena.nuclecu.unam.mx> from "Miguel de Icaza" at Sep 22, 97 09:32:19 pm
Reply-To: ariel@cthulhu.engr.sgi.com (Ariel Faigon)
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My personal favorites are a drudgery to wizards but an essential
necessity for most mortals:

[5] Verify that the latest source tree on Llinus compiles and boots
    (maybe automate this with a daily build that gets tested)
[4] Utility to boot Linux from IRIX (both locally and over net)
[3] Stable precompiled Indy kernel + root-contents on linus
[3] A working HOWTO for booting Linux on Indy

All the above even without having X :-)


:
:
:Here is a preliminary task list of things that should be done for a
:complete Linux/MIPS port, right now it includes by personal favorites
:and I am working on some of those bits, but some of the other can be
:done now, I have a copy of this at:
:
:	http://www.nuclecu.unam.mx/~miguel/mips-task-list.txt
:
:Priority: 
:
:[9]  Get more userland programs compiled in RPM form
:
:[9]  Merging the latest GNU libc releases.
:
:[9]  Get the X libraries compiled.
:
:[5]  Getting SGI mouse to work.
:
:[5]  Test the STREAMS implementation of the mouse.
:
:[6]  Figure why init is setting the sigprocmask to a value different
:     from 0.  This disables the debugger (SIGTRAP is disabled for
:     all child processes).
:
:[7]  Getting IRIX X server to accept connections.
:
:Please, send me additions to this list.
:Miguel.
:


-- 
Peace, Ariel

From owner-linux@cthulhu.engr.sgi.com  Mon Sep 22 20:47:27 1997
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Subject: Re: Task list --preliminary list
X-Windows: It could be worse, but it'll take time.
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> [5] Verify that the latest source tree on Llinus compiles and boots
>     (maybe automate this with a daily build that gets tested)

I checked this yesterday when I commited my code to linus.

> [4] Utility to boot Linux from IRIX (both locally and over net)

Well, we do not need this, since sash can load the Linux kernel from
both an efs file system and from the network.  I thought this had been
covered in the HOWTO?

	Booting from local disk:

	1. Put your kernel on an EFS partition say, /linux/vmlinux.gz

	2. reset your Indy.

	3. Enter maintenance mode (click on the button before IRIX
	   boots).

	4. at the prompt type:  boot /linux/vmlinux.gz

	Note that I lack a manual on the ARC, so I am limited by what
	I figured would boot the kernel.  There are some very interesting
	variables that allow you to boot the kernel from any file
	system on any partition.
	
> [3] Stable precompiled Indy kernel + root-contents on linus

	I have my stable precompiled Indy kernel, I can setup a cron
	job to upload my latest kernel everyday :-).  They are always
	stable.

	My root contents are currently pretty hosed up, as I have a mixture
	of IRIX, Linux and gnemul + some rpms + some broken rpms + a libc
	that I am not sure it is ok. 

Cheers,
Miguel.

From owner-linux@cthulhu.engr.sgi.com  Mon Sep 22 20:52:52 1997
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Date: Mon, 22 Sep 1997 23:49:34 -0400
From: Eric Kimminau <eak@detroit.sgi.com>
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Organization: Silicon Graphics, Inc
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Subject: Re: Task list --preliminary list
References: <199709230232.VAA16659@athena.nuclecu.unam.mx>
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PRI 10
Howto updated so it show how to take a system currently running IRIX and
get it to a point where it is running Linux. I know it isn't truly
development work, but Ive been stuck with a non-functional Indy for most
of a month.My problems seem to be related to trying to NFS boot off of a
remote XFS file system but I could be wrong. I haven't grabbed the
latest kernel to try so that could resolve my issue.

Miguel de Icaza wrote:
> 
> Here is a preliminary task list of things that should be done for a
> complete Linux/MIPS port, right now it includes by personal favorites
> and I am working on some of those bits, but some of the other can be
> done now, I have a copy of this at:
> 
>         http://www.nuclecu.unam.mx/~miguel/mips-task-list.txt
> 
> Priority:
> 
> [9]  Get more userland programs compiled in RPM form
> 
> [9]  Merging the latest GNU libc releases.
> 
> [9]  Get the X libraries compiled.
> 
> [5]  Getting SGI mouse to work.
> 
> [5]  Test the STREAMS implementation of the mouse.
> 
> [6]  Figure why init is setting the sigprocmask to a value different
>      from 0.  This disables the debugger (SIGTRAP is disabled for
>      all child processes).
> 
> [7]  Getting IRIX X server to accept connections.
> 
> Please, send me additions to this list.
> Miguel.

-- 
Eric Kimminau                             System Engineer
eak@detroit.sgi.com                       Silicon Graphics, Inc
Vox:(810) 848-4455                        39001 West 12mile Road
Fax:(810)848-5600                         Farmington, MI 48331-2903
            "I speak my mind and no one else's."
    http://www.dcs.ex.ac.uk/~aba/rsa/perl-rsa-sig.html

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To: linux-mips@fnet.fr
Date: Mon, 22 Sep 1997 21:09:11 -0700 (PDT)
Cc: miguel@nuclecu.unam.mx, linux@fir.engr.sgi.com
In-Reply-To: <34273C4E.9AD0AB2F@detroit.sgi.com> from "Eric Kimminau" at Sep 22, 97 11:49:34 pm
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> PRI 10
> Howto updated so it show how to take a system currently running IRIX and
> get it to a point where it is running Linux. I know it isn't truly
> development work, but Ive been stuck with a non-functional Indy for most
> of a month.My problems seem to be related to trying to NFS boot off of a
> remote XFS file system but I could be wrong. I haven't grabbed the
> latest kernel to try so that could resolve my issue.

This issues might have been resolved by Miguel's latest CVS commit.
Your NFS problems might also have been cause by the VFS rewrite which
was essentially turning the filesystems into an inferno for a limited
time.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 23 03:49:00 1997
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From: Eric Kimminau <eak@cygnus.detroit.sgi.com>
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To: Ralf Baechle <ralf@cobaltmicro.com>
CC: linux-mips@fnet.fr, miguel@nuclecu.unam.mx, linux@fir.engr.sgi.com
Subject: Re: Task list --preliminary list
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Ralf Baechle wrote:
> 
> > PRI 10
> > Howto updated so it show how to take a system currently running IRIX and
> > get it to a point where it is running Linux. I know it isn't truly
> > development work, but Ive been stuck with a non-functional Indy for most
> > of a month.My problems seem to be related to trying to NFS boot off of a
> > remote XFS file system but I could be wrong. I haven't grabbed the
> > latest kernel to try so that could resolve my issue.
> 
> This issues might have been resolved by Miguel's latest CVS commit.
> Your NFS problems might also have been cause by the VFS rewrite which
> was essentially turning the filesystems into an inferno for a limited
> time.
> 
>   Ralf

Agreed. Im going to re-try boot later this afternoon with the new
kernel.

-- 
Eric Kimminau                           System Engineer/RSA
eak@detroit.sgi.com                     Silicon Graphics, Inc
Voice: (248) 848-4455                   39001 West 12 Mile Rd.
Fax:   (248) 848-5600                   Farmington, MI 48331-2903

                 VNet Extension - 6-327-4455
              "I speak my mind and no one else's."
       http://www.dcs.ex.ac.uk/~aba/rsa/perl-rsa-sig.html

    When confronted by a difficult problem, solve it by reducing 
    it to the question, "How would the Lone Ranger handle this?"

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 23 11:39:32 1997
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In-Reply-To: <199709230335.WAA17103@athena.nuclecu.unam.mx> (message from
	Miguel de Icaza on Mon, 22 Sep 1997 22:35:49 -0500)
Subject: Re: Task list --preliminary list
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>> [5] Verify that the latest source tree on Llinus compiles and boots
>> (maybe automate this with a daily build that gets tested)

> I checked this yesterday when I commited my code to linus.

Yes, but I bet you didn't check it on an Indy with no scache :-)
I have one of those beasts and the latest code in the cvs tree
crashes early in the boot process.

The code in arch/mips/mm/r4xx0.c which sets up the cache flush
procs now selects r4k_flush_page_to_ram_d32i32_r4600 where
earlier versions of r4xx0.c selected r4k_flush_page_to_ram_d32i32.
I think the current choice is correct in that my Indy has the
R4600 cache bug mentioned in IDT's errata. But the *_r4600 version
also has some inline assembler under an ifdef CONFIG_SGI which
appears to do something to the SGI scache. But since I have
no scache, I get a bus error irq instead.

It seems a bit strange that r4k_flush_page_to_ram_d32i32_r4600
has this bit of SGI specific code, but r4k_flush_page_to_ram_d32i32
does not. ???

--Mark


From owner-linux@cthulhu.engr.sgi.com  Tue Sep 23 15:41:08 1997
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From: Mike Shaver <shaver@neon.ingenia.ca>
Message-Id: <199709232232.SAA02473@neon.ingenia.ca>
Subject: Re: Task list --preliminary list
In-Reply-To: <199709230305.UAA09789@oz.engr.sgi.com> from Ariel Faigon at "Sep 22, 97 08:05:26 pm"
To: ariel@cthulhu.engr.sgi.com
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Thus spake Ariel Faigon:
> [5] Verify that the latest source tree on Llinus compiles and boots
>     (maybe automate this with a daily build that gets tested)

Boots on?
We'll need to define a set of known-tested/supported systems, at least
for now.

> [4] Utility to boot Linux from IRIX (both locally and over net)

Stay tuned.
I'm going to be incommunicado for about a week while I move to
Mountain View, but I only have one bug[*] keeping me from being able
to boot off of an EFS partition, etc.  That should make things a lot
easier.

[*] Yes, it's embarrassingly true: I still can't get indirect extents
right.  I'll check my code in tomorrow, in case someone smarter than
me wants to take a crack at it.

Mike

-- 
#> Mike Shaver (shaver@ingenia.com) Ingenia Communications Corporation 
#>           Resident Linux bigot and kernel hacker. (OOPS!)           
#> `If you get bitten by a bug, tough luck...the one thing I won't do  
#> is feel sorry for you.  In fact, I might ask you to do it all over  
#> again, just to get more information.  I'm a heartless bastard.'     
#>                       -- Linus Torvalds (on development kernels)    

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 23 15:41:07 1997
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Mark Salter <marks@sun470.sun470.rd.qms.com>
Cc: miguel@nuclecu.unam.mx, ariel@cthulhu.engr.sgi.com,
        linux@cthulhu.engr.sgi.com
Subject: Re: Task list --preliminary list
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Mark Salter writes:
 > 
 > >> [5] Verify that the latest source tree on Llinus compiles and boots
 > >> (maybe automate this with a daily build that gets tested)
 > 
 > > I checked this yesterday when I commited my code to linus.
 > 
 > Yes, but I bet you didn't check it on an Indy with no scache :-)
 > I have one of those beasts and the latest code in the cvs tree
 > crashes early in the boot process.
 > 
 > The code in arch/mips/mm/r4xx0.c which sets up the cache flush
 > procs now selects r4k_flush_page_to_ram_d32i32_r4600 where
 > earlier versions of r4xx0.c selected r4k_flush_page_to_ram_d32i32.
 > I think the current choice is correct in that my Indy has the
 > R4600 cache bug mentioned in IDT's errata. But the *_r4600 version
 > also has some inline assembler under an ifdef CONFIG_SGI which
 > appears to do something to the SGI scache. But since I have
 > no scache, I get a bus error irq instead.
 > 
 > It seems a bit strange that r4k_flush_page_to_ram_d32i32_r4600
 > has this bit of SGI specific code, but r4k_flush_page_to_ram_d32i32
 > does not. ???

     I have not looked at the source, but the problem is probably that
there needs to be two cases, one with and one without Indy R4600 scache.
This is determined by reading out the EEPROM on the CPU board, and looking
at the appropriate bits for "scache present" and "scache size".  The 
processor will get a bus error trying to reference the control registers
of the scache controller (via uncached memory references) if the secondary
cache is not present.

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 23 16:35:48 1997
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From: Ralf Baechle <ralf@mailhost.uni-koblenz.de>
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Subject: Re: Task list --preliminary list
To: marks@sun470.sun470.rd.qms.com (Mark Salter)
Date: Wed, 24 Sep 1997 01:34:50 +0200 (MET DST)
Cc: miguel@nuclecu.unam.mx, ariel@cthulhu.engr.sgi.com,
        linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr
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> Yes, but I bet you didn't check it on an Indy with no scache :-)
> I have one of those beasts and the latest code in the cvs tree
> crashes early in the boot process.
> 
> The code in arch/mips/mm/r4xx0.c which sets up the cache flush
> procs now selects r4k_flush_page_to_ram_d32i32_r4600 where
> earlier versions of r4xx0.c selected r4k_flush_page_to_ram_d32i32.
> I think the current choice is correct in that my Indy has the
> R4600 cache bug mentioned in IDT's errata. But the *_r4600 version
> also has some inline assembler under an ifdef CONFIG_SGI which
> appears to do something to the SGI scache. But since I have
> no scache, I get a bus error irq instead.
> 
> It seems a bit strange that r4k_flush_page_to_ram_d32i32_r4600
> has this bit of SGI specific code, but r4k_flush_page_to_ram_d32i32
> does not. ???

The R4400 versions of the Indy have the "real" second level cache and
use a SC CPU version.  Opposed to that the  L2 cache of the R4600 and
R5000 Indies is controlled by external circuitry which needs special code.

Actually since we have the same problem on a couple of other machines,
SNI RM family one of them,  what should be done is to break out all the
#ifugly'ed SGI bits and provide some hooks for them.  You L2 less
machine would simply plug an empty function into these hooks.

Using r4k_flush_page_to_ram_d32i32 was definately wrong, the R4600
cache is two way set associative and flush_page_to_ram needs to take
care of that for all the R4600 and R5000 relatives.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 24 01:53:59 1997
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From: Ralf Baechle <ralf@cobaltmicro.com>
Message-Id: <199709240715.AAA20896@dns.cobaltmicro.com>
Subject: glibc 2.0.4 bug ...
To: linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com, drepper@cygnus.com
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Hi all,

glibc 2.0.4 contains a fatal bug.  It does not declare a prototype for
the function llseek in unistd.h.  As result GCC will (correctly) truncate
the 64 bit file offset and build erroneous filesystems when building
filesystems of 2GB.  e2fsck will complain about read errors when trying
to read blocks from the 2GB border on.  Actually I wonder why I never saw
a report about that on other mailinglists.

Quickfix: add the following prototype for llseek(2):

  extern loff_t llseek (int fd, loff_t offset, int whence);

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 24 10:17:41 1997
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Subject: Re: glibc 2.0.4 bug ...
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From: Ralf Baechle <ralf@cobaltmicro.com>
Subject: glibc 2.0.4 bug ...
Date: Wed, 24 Sep 1997 00:15:10 -0700 (PDT)

> Quickfix: add the following prototype for llseek(2):
> 
>   extern loff_t llseek (int fd, loff_t offset, int whence);

I've mentioned this several times: llseek is an internal function.
What we need is the LFS interface which then defines lseek64.

-- Uli
---------------.      drepper@cygnus.com  ,-.   Rubensstrasse 5
Ulrich Drepper  \    ,-------------------'   \  76149 Karlsruhe/Germany
Cygnus Solutions `--' drepper@gnu.ai.mit.edu  `------------------------

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 24 14:38:48 1997
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Subject: Indy netboot problems
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Hello all,
Sorry to bother you if this is a routine question, but I read the FAQ, and 
therein lies my problem.

I'm trying to make an Indy netboot, but I'm not too familiar with the new 
monitor (let's just say that I knew sifex much better...Anyone remember the 
IRIS 3130s?). I need a way to correct the HW address, since it appears to be 
set to '0:0:FF:FF:0:0', and it is complaining about it.

Is there any other way to change nvram settings except through the 
setenv/printenv commands?

I hope to be contributing to this project soon, but I'm off to a fairly rocky 
start ;-)

Thanks in advance,

--Charles Lepple, <clepple@foo.org>
<clepple@ugrad.ee.vt.edu>
http://www.ee.vt.edu/solarcar/
http://www.mitre.org/research/nanotech/





From owner-linux@cthulhu.engr.sgi.com  Wed Sep 24 15:24:18 1997
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: clepple@foo.org
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: Indy netboot problems
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Charles Lepple writes:
 > Hello all,
 > Sorry to bother you if this is a routine question, but I read the FAQ, and 
 > therein lies my problem.
 > 
 > I'm trying to make an Indy netboot, but I'm not too familiar with the new 
 > monitor (let's just say that I knew sifex much better...Anyone remember the 
 > IRIS 3130s?). I need a way to correct the HW address, since it appears to be 
 > set to '0:0:FF:FF:0:0', and it is complaining about it.
 > 
 > Is there any other way to change nvram settings except through the 
 > setenv/printenv commands?
...

      "setenv -p xxx yyy" will set xxx permanently (in NVRAM) to yyy.  Without
the "-p", it just sets xxx in the environment in memory.  For the hardware
address ("eaddr"), however, you cannot readily change it, as it is the
system serial number as well as the MAC address.  I don't know any easy
way for it have been corrupted; it would normally be fixed by field service.

From owner-linux@cthulhu.engr.sgi.com  Wed Sep 24 17:51:46 1997
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Date: Thu, 25 Sep 1997 12:50:18 +1200
From: Alistair Lambie <alambie@sgi.com>
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Subject: Re: Indy netboot problems
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Charles Lepple wrote:
> 
> Hello all,
> Sorry to bother you if this is a routine question, but I read the FAQ, and
> therein lies my problem.
> 
> I'm trying to make an Indy netboot, but I'm not too familiar with the new
> monitor (let's just say that I knew sifex much better...Anyone remember the
> IRIS 3130s?). I need a way to correct the HW address, since it appears to be
> set to '0:0:FF:FF:0:0', and it is complaining about it.
> 
> Is there any other way to change nvram settings except through the
> setenv/printenv commands?
> 

You can not change this with setenv.  If it is '0:0:FF:FF:0:0' there is
a fault and you need to get the motherboard replaced.  It is probably
the 'Dallas Chip' that is the problem.  I have twice seen where a pin
gets bent on this and it returns funny MAC adresses....so if you have
some hardware knowledge it may be worth checking that it is seated
correctly and the pins are not bent.

Cheers, Alistair

-- 
Alistair Lambie					    alambie@wellington.sgi.com
Silicon Graphics New Zealand				  SGI Voicemail: 56791
Level 5, Walsh Wrightson Tower,				    Ph: +64-4-802 1455
94-96 Dixon St, Wellington, NZ			  	   Fax: +64-4-802 1459

From owner-linux@cthulhu.engr.sgi.com  Thu Sep 25 23:42:30 1997
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From: Ralf Baechle <ralf@cobaltmicro.com>
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Subject: R3000 SGI machines
To: linux@cthulhu.engr.sgi.com
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Hi all,

I receive an increasing number of emails asking for Linux as replacement
operating system for older R3000 SGI machines as well as Mips Inc.
machines.  Is there still documentation available for these systems
that would make a port possible?

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 04:24:26 1997
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You know I was just thinking about that this morning. I was more leaning
towards the personal iris, and the crimson with the video adapter that is not
supported in 6.2(the name isn't coming to me right now, GTX?). I was
wondering how we got the specs from the ethernet, bus, and serial controllers
from SGI. And the chip specs from mips. If I understand SGI history
correctly, there was a change in the CPU after revision 3, and we are going
to need to see if this is going to cause problems. another thing we need to
do(I'll do it) is call ID Software and get the code for DOOM so It can be
compiled for Linux.

Thanks,
Robbie Stone


From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 08:10:53 1997
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To: Ralf Baechle <ralf@cobaltmicro.com>
Subject: Re: R3000 SGI machines 
Cc: linux@cthulhu.engr.sgi.com
In-reply-to: Your message of "Thu, 25 Sep 1997 23:39:27 PDT."
		<199709260639.XAA09959@dull.cobaltmicro.com> 
References: <199709260639.XAA09959@dull.cobaltmicro.com>  
Date: Fri, 26 Sep 1997 09:10:24 -0600
From: Warner Losh <imp@village.org>
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In message <199709260639.XAA09959@dull.cobaltmicro.com> Ralf Baechle writes:
: I receive an increasing number of emails asking for Linux as replacement
: operating system for older R3000 SGI machines as well as Mips Inc.
: machines.  Is there still documentation available for these systems
: that would make a port possible?

I'll have to search my email archive (which would take some doing),
but someone at SGI offered to get me the sources to RISCos, or at
least the device drivers.  They were donated to berkeley, who didn't
integrate them into their 4.4 or 4.4lite release, was the story I was
told.  Might be worth looking into.  Wouldn't help with some of the
older SGI machines, but would help with the MIPS co boxes.

Warner

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 08:50:58 1997
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Date: Fri, 26 Sep 1997 08:50:34 -0700
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Ralf Baechle <ralf@cobaltmicro.com>
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: R3000 SGI machines
In-Reply-To: <199709260639.XAA09959@dull.cobaltmicro.com>
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Ralf Baechle writes:
 > Hi all,
 > 
 > I receive an increasing number of emails asking for Linux as replacement
 > operating system for older R3000 SGI machines as well as Mips Inc.
 > machines.  Is there still documentation available for these systems
 > that would make a port possible?

     There is some, which I could track down, on the same basis as the
Indy documentation.  I don't know how complete the files are, however.
There is a family resemblance in much of Indigo system, especially the I/O.
The Personal IRIS and Power Series machines, which were VME-based, are
fairly different (except for graphics), but are relatively similar to the 
MIPS VME systems, such as the M1000 and M2000.  The Power Series are
MP systems, and have some special purpose interprocessor synchronization
hardware.  The documentation for the VME systems will be harder to 
locate.



From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 08:56:23 1997
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Date: Fri, 26 Sep 1997 08:56:09 -0700
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: LetherGlov@aol.com
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: R3000 SGI machines
In-Reply-To: <970926072404_1332144893@emout08.mail.aol.com>
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LetherGlov@aol.com writes:
 > You know I was just thinking about that this morning. I was more leaning
 > towards the personal iris, and the crimson with the video adapter that is not
 > supported in 6.2(the name isn't coming to me right now, GTX?). I was
 > wondering how we got the specs from the ethernet, bus, and serial controllers
 > from SGI. And the chip specs from mips. If I understand SGI history
 > correctly, there was a change in the CPU after revision 3, and we are going
 > to need to see if this is going to cause problems. another thing we need to
 > do(I'll do it) is call ID Software and get the code for DOOM so It can be
 > compiled for Linux.

     The MIPS processor specifications are public, and available as printed
books.  Also, many of them are online at http://www.sgi.com/MIPS/.  

     With the approval of the appropriate division general manager, I 
supplied the people doing the Indy port of linux with copies of the
Indy hardware documentation.

     Since the Personal IRIX and Crimson use mostly VME controllers. those
drivers should carry over from other VME ports.  I don't know if I can
arrange to provide documentation for the graphics controllers.

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 08:58:32 1997
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Warner Losh <imp@village.org>
Cc: Ralf Baechle <ralf@cobaltmicro.com>, linux@cthulhu.engr.sgi.com
Subject: Re: R3000 SGI machines 
In-Reply-To: <199709261510.JAA22806@harmony.village.org>
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Warner Losh writes:
 > In message <199709260639.XAA09959@dull.cobaltmicro.com> Ralf Baechle writes:
 > : I receive an increasing number of emails asking for Linux as replacement
 > : operating system for older R3000 SGI machines as well as Mips Inc.
 > : machines.  Is there still documentation available for these systems
 > : that would make a port possible?
 > 
 > I'll have to search my email archive (which would take some doing),
 > but someone at SGI offered to get me the sources to RISCos, or at
 > least the device drivers.  They were donated to berkeley, who didn't
 > integrate them into their 4.4 or 4.4lite release, was the story I was
 > told.  Might be worth looking into.  Wouldn't help with some of the
 > older SGI machines, but would help with the MIPS co boxes.

     The RISCos driver source was supplied with every system, and we
did donate the source to Berkeley.  Most of the VME controllers were
common to MIPS and SGI VME systems, so most of the drivers, other than
graphics, would be covered.


From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 11:59:10 1997
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From: sr@dragon.engr.sgi.com (Steve Rikli)
Message-Id: <199709261858.LAA67409@dragon.engr.sgi.com>
Subject: Re: R3000 SGI machines
To: linux@cthulhu.engr.sgi.com
Date: Fri, 26 Sep 1997 11:58:50 -0700 (PDT)
In-Reply-To: <199709261556.IAA10936@fir.engr.sgi.com> from "William J. Earl" at Sep 26, 97 08:56:09 am
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William J. Earl wrote:
> LetherGlov@aol.com writes:
>>
>> You know I was just thinking about that this morning. I was more leaning
>> towards the personal iris, and the crimson with the video adapter that is not
>> supported in 6.2(the name isn't coming to me right now, GTX?). I was
>> wondering how we got the specs from the ethernet, bus, and serial controllers
>> from SGI. And the chip specs from mips. If I understand SGI history
>> correctly, there was a change in the CPU after revision 3, and we are going
>> to need to see if this is going to cause problems. another thing we need to
>> do(I'll do it) is call ID Software and get the code for DOOM so It can be
>> compiled for Linux.
> 
>      The MIPS processor specifications are public, and available as printed
> books.  Also, many of them are online at http://www.sgi.com/MIPS/.  
> 
>      With the approval of the appropriate division general manager, I 
> supplied the people doing the Indy port of linux with copies of the
> Indy hardware documentation.
> 
>      Since the Personal IRIX and Crimson use mostly VME controllers. those
> drivers should carry over from other VME ports.  I don't know if I can
> arrange to provide documentation for the graphics controllers.

This may not be exactly the kind of thing some of y'all are looking
for, but since we're talking about doc & info sources for old SGI
hardware I felt I should point this one out:

	http://www.geocities.com/SiliconValley/Pines/2258/4dfaq.html

Several handfulls of general notes about the 4D and/or other R3K 
platforms.

Hope someone finds it useful.

cheers,
sr.
-- 
|| Steve Rikli <sr@sgi.com> ||| Any sufficiently advanced technology is ||
|| Systems Administrator    ||| indistinguishable from a rigged demo.   ||
|| NSD, EIS Infrastructure  |||                                         ||
|| Silicon Graphics, Inc.   |||               - Andy Finkel             ||

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 12:11:53 1997
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Date: Fri, 26 Sep 1997 12:11:29 -0700
From: Ariel Faigon <ariel@sgi.com>
Organization: Silicon Graphics, Inc.
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Subject: Muchos thankyous (4D FAQ)!
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Dear AJC,

Your 4D-IRIS / old SGI hardware documentation is a treasure.
Thank you for puting it online.

I linked to it from the www.linux.sgi.com web site
with the hope that one day someone would port SGI/Linux
to these old machines.

Thanks to Steve Rikli for pointing this site to teh linux list.
--
Peace, Ariel

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 17:36:55 1997
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From: Ralf Baechle <ralf@cobaltmicro.com>
Message-Id: <199709270036.RAA02682@dns.cobaltmicro.com>
Subject: Re: R3000 SGI machines
To: wje@fir.engr.sgi.com (William J. Earl)
Date: Fri, 26 Sep 1997 17:36:25 -0700 (PDT)
Cc: imp@village.org, ralf@cobaltmicro.com, linux@cthulhu.engr.sgi.com,
        ab@ivm.net
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> Warner Losh writes:
>  > In message <199709260639.XAA09959@dull.cobaltmicro.com> Ralf Baechle writes:
>  > : I receive an increasing number of emails asking for Linux as replacement
>  > : operating system for older R3000 SGI machines as well as Mips Inc.
>  > : machines.  Is there still documentation available for these systems
>  > : that would make a port possible?
>  > 
>  > I'll have to search my email archive (which would take some doing),
>  > but someone at SGI offered to get me the sources to RISCos, or at
>  > least the device drivers.  They were donated to berkeley, who didn't
>  > integrate them into their 4.4 or 4.4lite release, was the story I was
>  > told.  Might be worth looking into.  Wouldn't help with some of the
>  > older SGI machines, but would help with the MIPS co boxes.
> 
>      The RISCos driver source was supplied with every system, and we
> did donate the source to Berkeley.  Most of the VME controllers were
> common to MIPS and SGI VME systems, so most of the drivers, other than
> graphics, would be covered.

I think I can still get access to RISC/os 5.x system, maybe also old
RISC/os 4.51 tapes.  What files should I try to look for?

Andy, I think you still have Resi in use, don't you?  Any driver sources
included?

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Fri Sep 26 19:24:51 1997
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From: Ralf Baechle <ralf@cobaltmicro.com>
Message-Id: <199709270224.TAA03105@dns.cobaltmicro.com>
Subject: Re: MIPS R2k/3k machines....
To: linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com
Date: Fri, 26 Sep 1997 19:24:35 -0700 (PDT)
In-Reply-To: <Pine.GSO.3.96.970927024945.6430C-100000@tardis.tardis.ed.ac.uk> from "Lucien Murray-Pitts" at Sep 27, 97 02:55:42 am
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Hi,

> 	I too, like the several other people, want to help port Linux to
> the older 2k and 3k systems BUT like all the others I am hindered by a
> total LACK of documentation.  I did manage to find one nice chap who gave
> me some docco. but unfortuantely it was for the R4Ks, however...

I assume you only refer to the system documentation.  The CPU documentation
is available for free from {sgigate,www}.sgi.com and a couple of
Mips silicon manufacturers like {ftp,www}.idt.com and others more.

> 	Does ANYONE have ANY technical INFORMATION which might be of use
> to all of us port of linux.
> 
> 	No matter how small, silly or whatever I'd like to hear about it.

I asked some people at SGI and they'll try to dig out what still
exists.  Somebody came up with a quite nice link for owners of
historic SGI machines.  Check out the site, there is a link to it
on www.linux.sgi.com.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sun Sep 28 17:15:38 1997
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From: Regan Russell <Regan@bde.com.au>
To: linux-mips <linux-mips@fnet.fr>, linux <linux@cthulhu.engr.sgi.com>,
        linux-mips-request <linux-mips-request@fnet.fr>
Subject: RE: MIPS R2k/3k machines....
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Look for "The mips programmers refenence manual".  (Faquar and Bunce ?) (   
R2000 / R3000 )
"The MIPS RISC architecture". (Kane ?) ( mentions R4000 but contrates on   
the R2000 / R3000 )
Both books were availible recently.
I have both books at home, (I do complete crap in windoze for a living),   
also look at xspim and spim the
simulator for the R2000, R3000. Think it was on sunsite...

Hope this helps..

PS. Anyone got a spare motherboard for a DS3100 ?

 ----------
From:  linux-mips-request
Sent:  Friday, September 26, 1997 7:24 PM
To:  linux-mips; linux
Subject:  Re: MIPS R2k/3k machines....

Hi,

>       I too, like the several other people, want to help port Linux to
> the older 2k and 3k systems BUT like all the others I am hindered by a
> total LACK of documentation.  I did manage to find one nice chap who   
gave
> me some docco. but unfortuantely it was for the R4Ks, however...

I assume you only refer to the system documentation.  The CPU   
documentation
is available for free from {sgigate,www}.sgi.com and a couple of
Mips silicon manufacturers like {ftp,www}.idt.com and others more.

>       Does ANYONE have ANY technical INFORMATION which might be of use
> to all of us port of linux.
>
>       No matter how small, silly or whatever I'd like to hear about it.

I asked some people at SGI and they'll try to dig out what still
exists.  Somebody came up with a quite nice link for owners of
historic SGI machines.  Check out the site, there is a link to it
on www.linux.sgi.com.

  Ralf



From owner-linux@cthulhu.engr.sgi.com  Tue Sep 30 16:38:42 1997
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From: Ralf Baechle <ralf@cobaltmicro.com>
Message-Id: <199709302336.QAA22417@dns.cobaltmicro.com>
Subject: IRIX ELF docs
To: linux@cthulhu.engr.sgi.com
Date: Tue, 30 Sep 1997 16:36:24 -0700 (PDT)
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Hi all,

our current linker is producing IRIX flavored ELF binaries, not MIPS
ABI.  We still seem to have some bugs in the dynamic linker and these
are now pretty close to the top on my to do list.  However I've got
not documentation about the IRIX binary format, so I'm pretty much
relying on reverse engineering for fixing them.  Does anybody have
a pointer to documentation or documentation about IRIX ELF flavoured
o32 bit object file format?

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 30 16:42:52 1997
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Message-Id: <199709302342.QAA14355@fir.engr.sgi.com>
From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Ralf Baechle <ralf@cobaltmicro.com>
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: IRIX ELF docs
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Ralf Baechle writes:
 > Hi all,
 > 
 > our current linker is producing IRIX flavored ELF binaries, not MIPS
 > ABI.  We still seem to have some bugs in the dynamic linker and these
 > are now pretty close to the top on my to do list.  However I've got
 > not documentation about the IRIX binary format, so I'm pretty much
 > relying on reverse engineering for fixing them.  Does anybody have
 > a pointer to documentation or documentation about IRIX ELF flavoured
 > o32 bit object file format?

      IRIX ELF O32 (dynamic) object files are MIPS ABI object files.
There are optional extra sections, to support features such as "quickstart"
(which allows RLD to skip some of the fixups at startup time), but the
required parts are as defined by the MIPS ABI.

From owner-linux@cthulhu.engr.sgi.com  Tue Sep 30 18:07:11 1997
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From: Ralf Baechle <ralf@cobaltmicro.com>
Message-Id: <199710010102.SAA22736@dns.cobaltmicro.com>
Subject: For stability freaks ...
To: linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com
Date: Tue, 30 Sep 1997 18:02:51 -3100 (PDT)
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Ok, I said I'd touch 2.0.x for MIPS again when hell freezes.  It was
damn cold weather the last days and hell has froozen ...

[root@(none) /]# uname -a
Linux (none) 2.0.30 #389 Tue Sep 30 17:47:39 PDT 1997 mips unknown
[root@(none) /]# cat /proc/cpuinfo
cpu                     : MIPS
cpu model               : Nevada V1.0
system type             : Cray YMP  [just kidding ...]
BogoMIPS                : 131.89
byteorder               : little endian
unaligned accesses      : 0
wait instruction        : yes
microsecond timers      : yes
extra interrupt vector  : yes

  Ralf

