Subject: mozilla on the Indy

From: Mike Shaver <[email-masked]>
Date: Wed, 01 Jul 1998 10:15:23 -0400

It builds.
It links (now that Alex made lesstif go, and I fixed up xpm).
It crashes very early in the startup.

I think it's probably something in the NSPR thread initialization, but
I'll have to build some test stuff to be sure.  The files I've changed
that matter (not Makefiles and link lines, but actual source) are
attached, and are the likely source of my problems.  Since the final
mostly-static link takes about 40 minutes, experimentation is expensive.

I'm also taking donations of gdb.

Mike

-- 
73275.46 64180.31

/* -*- Mode: C++; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 2 -*- */
/*
 * The contents of this file are subject to the Netscape Public License
 * Version 1.0 (the "NPL"); you may not use this file except in
 * compliance with the NPL.  You may obtain a copy of the NPL at
 * http://www.mozilla.org/NPL/
 * 
 * Software distributed under the NPL is distributed on an "AS IS" basis,
 * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the NPL
 * for the specific language governing rights and limitations under the
 * NPL.
 * 
 * The Initial Developer of this code under the NPL is Netscape
 * Communications Corporation.  Portions created by Netscape are
 * Copyright (C) 1998 Netscape Communications Corporation.  All Rights
 * Reserved.
 */

#ifndef nspr_cpucfg___
#define nspr_cpucfg___

#ifndef XP_UNIX
#define XP_UNIX
#endif

#ifndef LINUX
#define LINUX
#endif

#ifdef __powerpc__

#undef  IS_LITTLE_ENDIAN
#define IS_BIG_ENDIAN    1

#define PR_BYTES_PER_BYTE   1
#define PR_BYTES_PER_SHORT  2
#define PR_BYTES_PER_INT    4
#define PR_BYTES_PER_INT64  8
#define PR_BYTES_PER_LONG   4
#define PR_BYTES_PER_FLOAT  4
#define PR_BYTES_PER_DOUBLE 8
#define PR_BYTES_PER_WORD   4
#define PR_BYTES_PER_DWORD  8

#define PR_BITS_PER_BYTE    8
#define PR_BITS_PER_SHORT   16
#define PR_BITS_PER_INT     32
#define PR_BITS_PER_INT64   64
#define PR_BITS_PER_LONG    32
#define PR_BITS_PER_FLOAT   32
#define PR_BITS_PER_DOUBLE  64
#define PR_BITS_PER_WORD    32

#define PR_BITS_PER_BYTE_LOG2   3
#define PR_BITS_PER_SHORT_LOG2  4
#define PR_BITS_PER_INT_LOG2    5
#define PR_BITS_PER_INT64_LOG2  6
#define PR_BITS_PER_LONG_LOG2   5
#define PR_BITS_PER_FLOAT_LOG2  5
#define PR_BITS_PER_DOUBLE_LOG2 6
#define PR_BITS_PER_WORD_LOG2   5

#define PR_ALIGN_OF_SHORT   2
#define PR_ALIGN_OF_INT     4
#define PR_ALIGN_OF_LONG    4
#define PR_ALIGN_OF_INT64   4
#define PR_ALIGN_OF_FLOAT   4
#define PR_ALIGN_OF_DOUBLE  4
#define PR_ALIGN_OF_POINTER 4

#define PR_BYTES_PER_WORD_LOG2   2
#define PR_BYTES_PER_DWORD_LOG2  3

#elif defined(__alpha)

#define IS_LITTLE_ENDIAN 1
#undef  IS_BIG_ENDIAN
#define IS_64

#define PR_BYTES_PER_BYTE   1
#define PR_BYTES_PER_SHORT  2
#define PR_BYTES_PER_INT    4
#define PR_BYTES_PER_INT64  8
#define PR_BYTES_PER_LONG   8
#define PR_BYTES_PER_FLOAT  4
#define PR_BYTES_PER_DOUBLE 8
#define PR_BYTES_PER_WORD   8
#define PR_BYTES_PER_DWORD  8

#define PR_BITS_PER_BYTE    8
#define PR_BITS_PER_SHORT   16
#define PR_BITS_PER_INT     32
#define PR_BITS_PER_INT64   64
#define PR_BITS_PER_LONG    64
#define PR_BITS_PER_FLOAT   32
#define PR_BITS_PER_DOUBLE  64
#define PR_BITS_PER_WORD    64

#define PR_BITS_PER_BYTE_LOG2   3
#define PR_BITS_PER_SHORT_LOG2  4
#define PR_BITS_PER_INT_LOG2    5
#define PR_BITS_PER_INT64_LOG2  6
#define PR_BITS_PER_LONG_LOG2   6
#define PR_BITS_PER_FLOAT_LOG2  5
#define PR_BITS_PER_DOUBLE_LOG2 6
#define PR_BITS_PER_WORD_LOG2   6

#define PR_ALIGN_OF_SHORT   2
#define PR_ALIGN_OF_INT     4
#define PR_ALIGN_OF_LONG    8
#define PR_ALIGN_OF_INT64   8
#define PR_ALIGN_OF_FLOAT   4
#define PR_ALIGN_OF_DOUBLE  8
#define PR_ALIGN_OF_POINTER 8

#define PR_BYTES_PER_WORD_LOG2  3
#define PR_BYTES_PER_DWORD_LOG2 3

#elif defined(__mc68000__)

#undef  IS_LITTLE_ENDIAN
#define IS_BIG_ENDIAN 1

#define PR_BYTES_PER_BYTE   1
#define PR_BYTES_PER_SHORT  2
#define PR_BYTES_PER_INT    4
#define PR_BYTES_PER_INT64  8
#define PR_BYTES_PER_LONG   4
#define PR_BYTES_PER_FLOAT  4
#define PR_BYTES_PER_DOUBLE 8
#define PR_BYTES_PER_WORD   4
#define PR_BYTES_PER_DWORD  8

#define PR_BITS_PER_BYTE    8
#define PR_BITS_PER_SHORT   16
#define PR_BITS_PER_INT     32
#define PR_BITS_PER_INT64   64
#define PR_BITS_PER_LONG    32
#define PR_BITS_PER_FLOAT   32
#define PR_BITS_PER_DOUBLE  64
#define PR_BITS_PER_WORD    32

#define PR_BITS_PER_BYTE_LOG2   3
#define PR_BITS_PER_SHORT_LOG2  4
#define PR_BITS_PER_INT_LOG2    5
#define PR_BITS_PER_INT64_LOG2  6
#define PR_BITS_PER_LONG_LOG2   5
#define PR_BITS_PER_FLOAT_LOG2  5
#define PR_BITS_PER_DOUBLE_LOG2 6
#define PR_BITS_PER_WORD_LOG2   5

#define PR_ALIGN_OF_SHORT   2
#define PR_ALIGN_OF_INT     2
#define PR_ALIGN_OF_LONG    2
#define PR_ALIGN_OF_INT64   2
#define PR_ALIGN_OF_FLOAT   2
#define PR_ALIGN_OF_DOUBLE  2
#define PR_ALIGN_OF_POINTER 2

#define PR_BYTES_PER_WORD_LOG2   2
#define PR_BYTES_PER_DWORD_LOG2  3

#elif defined(__sparc__)

#undef	IS_LITTLE_ENDIAN
#define	IS_BIG_ENDIAN 1

#define PR_BYTES_PER_BYTE   1
#define PR_BYTES_PER_SHORT  2
#define PR_BYTES_PER_INT    4
#define PR_BYTES_PER_INT64  8
#define PR_BYTES_PER_LONG   4
#define PR_BYTES_PER_FLOAT  4
#define PR_BYTES_PER_DOUBLE 8
#define PR_BYTES_PER_WORD   4
#define PR_BYTES_PER_DWORD  8

#define PR_BITS_PER_BYTE    8
#define PR_BITS_PER_SHORT   16
#define PR_BITS_PER_INT     32
#define PR_BITS_PER_INT64   64
#define PR_BITS_PER_LONG    32
#define PR_BITS_PER_FLOAT   32
#define PR_BITS_PER_DOUBLE  64
#define PR_BITS_PER_WORD    32

#define PR_BITS_PER_BYTE_LOG2   3
#define PR_BITS_PER_SHORT_LOG2  4
#define PR_BITS_PER_INT_LOG2    5
#define PR_BITS_PER_INT64_LOG2  6
#define PR_BITS_PER_LONG_LOG2   5
#define PR_BITS_PER_FLOAT_LOG2  5
#define PR_BITS_PER_DOUBLE_LOG2 6
#define PR_BITS_PER_WORD_LOG2   5

#define PR_ALIGN_OF_SHORT   2
#define PR_ALIGN_OF_INT     4
#define PR_ALIGN_OF_LONG    4
#define PR_ALIGN_OF_INT64   8
#define PR_ALIGN_OF_FLOAT   4
#define PR_ALIGN_OF_DOUBLE  8
#define PR_ALIGN_OF_POINTER 4

#define PR_BYTES_PER_WORD_LOG2   2
#define PR_BYTES_PER_DWORD_LOG2  3

#elif defined(__i386__)

#define IS_LITTLE_ENDIAN 1
#undef  IS_BIG_ENDIAN

#define PR_BYTES_PER_BYTE   1
#define PR_BYTES_PER_SHORT  2
#define PR_BYTES_PER_INT    4
#define PR_BYTES_PER_INT64  8
#define PR_BYTES_PER_LONG   4
#define PR_BYTES_PER_FLOAT  4
#define PR_BYTES_PER_DOUBLE 8
#define PR_BYTES_PER_WORD   4
#define PR_BYTES_PER_DWORD  8

#define PR_BITS_PER_BYTE    8
#define PR_BITS_PER_SHORT   16
#define PR_BITS_PER_INT     32
#define PR_BITS_PER_INT64   64
#define PR_BITS_PER_LONG    32
#define PR_BITS_PER_FLOAT   32
#define PR_BITS_PER_DOUBLE  64
#define PR_BITS_PER_WORD    32

#define PR_BITS_PER_BYTE_LOG2   3
#define PR_BITS_PER_SHORT_LOG2  4
#define PR_BITS_PER_INT_LOG2    5
#define PR_BITS_PER_INT64_LOG2  6
#define PR_BITS_PER_LONG_LOG2   5
#define PR_BITS_PER_FLOAT_LOG2  5
#define PR_BITS_PER_DOUBLE_LOG2 6
#define PR_BITS_PER_WORD_LOG2   5

#define PR_ALIGN_OF_SHORT   2
#define PR_ALIGN_OF_INT     4
#define PR_ALIGN_OF_LONG    4
#define PR_ALIGN_OF_INT64   4
#define PR_ALIGN_OF_FLOAT   4
#define PR_ALIGN_OF_DOUBLE  4
#define PR_ALIGN_OF_POINTER 4

#define PR_BYTES_PER_WORD_LOG2   2
#define PR_BYTES_PER_DWORD_LOG2  3

#elif defined(__mips__)

#ifdef __MIPSEB__
#define IS_BIG_ENDIAN 1
#undef  IS_LITTLE_ENDIAN
#elif defined(__MIPSEL__
#define IS_LITTLE_ENDIAN 1
#undef  IS_BIG_ENDIAN
#else
#error "Unknown MIPS endianness."
#endif

#define PR_BYTES_PER_BYTE   1
#define PR_BYTES_PER_SHORT  2
#define PR_BYTES_PER_INT    4
#define PR_BYTES_PER_INT64  8
#define PR_BYTES_PER_LONG   4
#define PR_BYTES_PER_FLOAT  4
#define PR_BYTES_PER_DOUBLE 8
#define PR_BYTES_PER_WORD   4
#define PR_BYTES_PER_DWORD  8

#define PR_BITS_PER_BYTE    8
#define PR_BITS_PER_SHORT   16
#define PR_BITS_PER_INT     32
#define PR_BITS_PER_INT64   64
#define PR_BITS_PER_LONG    32
#define PR_BITS_PER_FLOAT   32
#define PR_BITS_PER_DOUBLE  64
#define PR_BITS_PER_WORD    32

#define PR_BITS_PER_BYTE_LOG2   3
#define PR_BITS_PER_SHORT_LOG2  4
#define PR_BITS_PER_INT_LOG2    5
#define PR_BITS_PER_INT64_LOG2  6
#define PR_BITS_PER_LONG_LOG2   5
#define PR_BITS_PER_FLOAT_LOG2  5
#define PR_BITS_PER_DOUBLE_LOG2 6
#define PR_BITS_PER_WORD_LOG2   5

#define PR_ALIGN_OF_SHORT   2
#define PR_ALIGN_OF_INT     4
#define PR_ALIGN_OF_LONG    4
#define PR_ALIGN_OF_INT64   4
#define PR_ALIGN_OF_FLOAT   4
#define PR_ALIGN_OF_DOUBLE  4
#define PR_ALIGN_OF_POINTER 4

#define PR_BYTES_PER_WORD_LOG2   2
#define PR_BYTES_PER_DWORD_LOG2  3

#else
#error "Unknown CPU architecture"

#endif

#define	HAVE_LONG_LONG
/*
 * XXX These two macros need to be investigated for different architectures.
 */
#undef	HAVE_ALIGNED_DOUBLES
#undef	HAVE_ALIGNED_LONGLONGS

#ifndef NO_NSPR_10_SUPPORT

#define BYTES_PER_BYTE		PR_BYTES_PER_BYTE
#define BYTES_PER_SHORT 	PR_BYTES_PER_SHORT
#define BYTES_PER_INT 		PR_BYTES_PER_INT
#define BYTES_PER_INT64		PR_BYTES_PER_INT64
#define BYTES_PER_LONG		PR_BYTES_PER_LONG
#define BYTES_PER_FLOAT		PR_BYTES_PER_FLOAT
#define BYTES_PER_DOUBLE	PR_BYTES_PER_DOUBLE
#define BYTES_PER_WORD		PR_BYTES_PER_WORD
#define BYTES_PER_DWORD		PR_BYTES_PER_DWORD

#define BITS_PER_BYTE		PR_BITS_PER_BYTE
#define BITS_PER_SHORT		PR_BITS_PER_SHORT
#define BITS_PER_INT		PR_BITS_PER_INT
#define BITS_PER_INT64		PR_BITS_PER_INT64
#define BITS_PER_LONG		PR_BITS_PER_LONG
#define BITS_PER_FLOAT		PR_BITS_PER_FLOAT
#define BITS_PER_DOUBLE		PR_BITS_PER_DOUBLE
#define BITS_PER_WORD		PR_BITS_PER_WORD

#define BITS_PER_BYTE_LOG2	PR_BITS_PER_BYTE_LOG2
#define BITS_PER_SHORT_LOG2	PR_BITS_PER_SHORT_LOG2
#define BITS_PER_INT_LOG2	PR_BITS_PER_INT_LOG2
#define BITS_PER_INT64_LOG2	PR_BITS_PER_INT64_LOG2
#define BITS_PER_LONG_LOG2	PR_BITS_PER_LONG_LOG2
#define BITS_PER_FLOAT_LOG2	PR_BITS_PER_FLOAT_LOG2
#define BITS_PER_DOUBLE_LOG2 	PR_BITS_PER_DOUBLE_LOG2
#define BITS_PER_WORD_LOG2	PR_BITS_PER_WORD_LOG2

#define ALIGN_OF_SHORT		PR_ALIGN_OF_SHORT
#define ALIGN_OF_INT		PR_ALIGN_OF_INT
#define ALIGN_OF_LONG		PR_ALIGN_OF_LONG
#define ALIGN_OF_INT64		PR_ALIGN_OF_INT64
#define ALIGN_OF_FLOAT		PR_ALIGN_OF_FLOAT
#define ALIGN_OF_DOUBLE		PR_ALIGN_OF_DOUBLE
#define ALIGN_OF_POINTER	PR_ALIGN_OF_POINTER
#define ALIGN_OF_WORD		PR_ALIGN_OF_WORD

#define BYTES_PER_WORD_LOG2	PR_BYTES_PER_WORD_LOG2
#define BYTES_PER_DWORD_LOG2	PR_BYTES_PER_DWORD_LOG2
#define WORDS_PER_DWORD_LOG2	PR_WORDS_PER_DWORD_LOG2

#endif /* NO_NSPR_10_SUPPORT */

#endif /* nspr_cpucfg___ */
/* -*- Mode: C++; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 2 -*- */
/*
 * The contents of this file are subject to the Netscape Public License
 * Version 1.0 (the "NPL"); you may not use this file except in
 * compliance with the NPL.  You may obtain a copy of the NPL at
 * http://www.mozilla.org/NPL/
 * 
 * Software distributed under the NPL is distributed on an "AS IS" basis,
 * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the NPL
 * for the specific language governing rights and limitations under the
 * NPL.
 * 
 * The Initial Developer of this code under the NPL is Netscape
 * Communications Corporation.  Portions created by Netscape are
 * Copyright (C) 1998 Netscape Communications Corporation.  All Rights
 * Reserved.
 */

#ifndef nspr_linux_defs_h___
#define nspr_linux_defs_h___

#include "prthread.h"

/*
 * Internal configuration macros
 */

#define PR_LINKER_ARCH	"linux"
#define _PR_SI_SYSNAME  "LINUX"
#ifdef __powerpc__
#define _PR_SI_ARCHITECTURE "ppc"
#elif defined(__alpha)
#define _PR_SI_ARCHITECTURE "alpha"
#elif defined(__mc68000__)
#define _PR_SI_ARCHITECTURE "m68k"
#elif defined(__sparc__)
#define _PR_SI_ARCHITECTURE "sparc"
#elif defined(__i386__)
#define _PR_SI_ARCHITECTURE "x86"
#elif defined(__mips__)
#define _PR_SI_ARCHITECTURE "mips"
#else
#error "Unknown CPU architecture"
#endif
#define PR_DLL_SUFFIX		".so"

#define _PR_VMBASE              0x30000000
#define _PR_STACK_VMBASE	0x50000000
#define _MD_DEFAULT_STACK_SIZE	65536L
#define _MD_MMAP_FLAGS          MAP_PRIVATE

#undef	HAVE_STACK_GROWING_UP

/*
 * Elf linux supports dl* functions
 */
#define HAVE_DLL
#define USE_DLFCN

#if !defined(MKLINUX) && !defined(NEED_TIME_R)
#define NEED_TIME_R
#endif

#define USE_SETJMP

#ifdef _PR_PTHREADS

extern void _MD_CleanupBeforeExit(void);
#define _MD_CLEANUP_BEFORE_EXIT _MD_CleanupBeforeExit

#else  /* ! _PR_PTHREADS */

#include <setjmp.h>

#define PR_CONTEXT_TYPE	sigjmp_buf

#define CONTEXT(_th) ((_th)->md.context)

#ifdef __powerpc__
/* PowerPC based MkLinux */
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[0].__misc[0]
#define _MD_SET_FP(_t, val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) ((void *) 0)
/* aix = 64, macos = 70 */
#define PR_NUM_GCREGS  64

#elif defined(__alpha)
/* Alpha based Linux */

#if defined(__GLIBC__) && __GLIBC__ >= 2
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[JB_SP]
#define _MD_SET_FP(_t, val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) ((void *) 0)
#define _MD_SP_TYPE long int
#else
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[0].__sp
#define _MD_SET_FP(_t, val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) ((void *) 0)
#define _MD_SP_TYPE __ptr_t
#endif /* defined(__GLIBC__) && __GLIBC__ >= 2 */

/* XXX not sure if this is correct, or maybe it should be 17? */
#define PR_NUM_GCREGS 9

#elif defined(__mc68000__)
/* m68k based Linux */

/*
 * On the m68k, glibc still uses the old style sigjmp_buf, even
 * in glibc 2.0.7.
 */
#if defined(__GLIBC__) && __GLIBC__ >= 2
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[0].__sp
#define _MD_SET_FP(_t, val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) ((void *) 0)
#else
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[0].__sp
#define _MD_SET_FP(_t, val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) ((void *) 0)
#endif /* defined(__GLIBC__) && __GLIBC__ >= 2 */

/* XXX not sure if this is correct, or maybe it should be 17? */
#define PR_NUM_GCREGS 9

#elif defined(__sparc__)
/* Sparc */
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[0].__fp
#define _MD_SET_FP(_t, val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) ((void *) 0)
#define _MD_SP_TYPE __ptr_t

#elif defined(__i386__)
/* Intel based Linux */
#if defined(__GLIBC__) && __GLIBC__ >= 2
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[JB_SP]
#define _MD_SET_FP(_t, val) ((_t)->md.context[0].__jmpbuf[JB_BP] = val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) (&(_t)->md.context[0].__jmpbuf[JB_BP])
#define _MD_SP_TYPE int
#else
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[0].__sp
#define _MD_SET_FP(_t, val) ((_t)->md.context[0].__jmpbuf[0].__bp = val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) &((_t)->md.context[0].__jmpbuf[0].__bp)
#define _MD_SP_TYPE __ptr_t
#endif /* defined(__GLIBC__) && __GLIBC__ >= 2 */
#define PR_NUM_GCREGS   6

#elif defined(__mips)
/* Linux/MIPS */
#if defined(__GLIBC__) && __GLIBC__ >= 2
#define _MD_GET_SP(_t) (_t)->md.context[0].__jmpbuf[0].__sp
#define _MD_SET_FP(_t, val) ((_t)->md.context[0].__jmpbuf[0].__fp = val)
#define _MD_GET_SP_PTR(_t) &(_MD_GET_SP(_t))
#define _MD_GET_FP_PTR(_t) (&(_t)->md.context[0].__jmpbuf[0].__fp)
#define _MD_SP_TYPE __ptr_t
#else
#error "Linux/MIPS pre glibc2 not supported yet (hack away!)"
#endif /* defined(__GLIBC__) && __GLIBC__ >= 2 */
#else

#error "Unknown CPU architecture"

#endif /*__powerpc__*/

/*
** Initialize a thread context to run "_main()" when started
*/
#ifdef __powerpc__

#define _MD_INIT_CONTEXT(_thread, _sp, _main, status)  \
{  \
    *status = PR_TRUE;  \
    if (sigsetjmp(CONTEXT(_thread), 1)) {  \
        _main();  \
    }  \
    _MD_GET_SP(_thread) = (unsigned char*) ((_sp) - 128); \
	_thread->md.sp = _MD_GET_SP_PTR(_thread); \
	_thread->md.fp = _MD_GET_FP_PTR(_thread); \
    _MD_SET_FP(_thread, 0); \
}

#else

#define _MD_INIT_CONTEXT(_thread, _sp, _main, status)  \
{  \
    *status = PR_TRUE;  \
    if (sigsetjmp(CONTEXT(_thread), 1)) {  \
        _main();  \
    }  \
    _MD_GET_SP(_thread) = (_MD_SP_TYPE) ((_sp) - 64); \
	_thread->md.sp = _MD_GET_SP_PTR(_thread); \
	_thread->md.fp = _MD_GET_FP_PTR(_thread); \
    _MD_SET_FP(_thread, 0); \
}

#endif /*__powerpc__*/

#define _MD_SWITCH_CONTEXT(_thread)  \
    if (!sigsetjmp(CONTEXT(_thread), 1)) {  \
	(_thread)->md.errcode = errno;  \
	_PR_Schedule();  \
    }

/*
** Restore a thread context, saved by _MD_SWITCH_CONTEXT
*/
#define _MD_RESTORE_CONTEXT(_thread) \
{   \
    errno = (_thread)->md.errcode;  \
    _MD_SET_CURRENT_THREAD(_thread);  \
    siglongjmp(CONTEXT(_thread), 1);  \
}

/* Machine-dependent (MD) data structures */

struct _MDThread {
    PR_CONTEXT_TYPE context;
	void *sp;
	void *fp;
    int id;
    int errcode;
};

struct _MDThreadStack {
    PRInt8 notused;
};

struct _MDLock {
    PRInt8 notused;
};

struct _MDSemaphore {
    PRInt8 notused;
};

struct _MDCVar {
    PRInt8 notused;
};

struct _MDSegment {
    PRInt8 notused;
};

struct _MDCPU {
	struct _MDCPU_Unix md_unix;
};

#define _MD_INIT_LOCKS()
#define _MD_NEW_LOCK(lock) PR_SUCCESS
#define _MD_FREE_LOCK(lock)
#define _MD_LOCK(lock)
#define _MD_UNLOCK(lock)
#define _MD_INIT_IO()
#define _MD_IOQ_LOCK()
#define _MD_IOQ_UNLOCK()

extern PRStatus _MD_InitializeThread(PRThread *thread);

#define _MD_INIT_RUNNING_CPU(cpu)       _MD_unix_init_running_cpu(cpu)
#define _MD_INIT_THREAD                 _MD_InitializeThread
#define _MD_EXIT_THREAD(thread)
#define _MD_SUSPEND_THREAD(thread)      _MD_suspend_thread
#define _MD_RESUME_THREAD(thread)       _MD_resume_thread
#define _MD_CLEAN_THREAD(_thread)

extern PRStatus _MD_CREATE_THREAD(
    PRThread *thread,
    void (*start) (void *),
    PRThreadPriority priority,
    PRThreadScope scope,
    PRThreadState state,
    PRUint32 stackSize);
extern void _MD_SET_PRIORITY(struct _MDThread *thread, PRUintn newPri);
extern PRStatus _MD_WAIT(PRThread *, PRIntervalTime timeout);
extern PRStatus _MD_WAKEUP_WAITER(PRThread *);
extern void _MD_YIELD(void);

#endif /* ! _PR_PTHREADS */

extern void _MD_EarlyInit(void);
extern PRIntervalTime _PR_UNIX_GetInterval(void);
extern PRIntervalTime _PR_UNIX_TicksPerSecond(void);

#define _MD_EARLY_INIT                  _MD_EarlyInit
#define _MD_FINAL_INIT					_PR_UnixInit
#define _MD_GET_INTERVAL                _PR_UNIX_GetInterval
#define _MD_INTERVAL_PER_SEC            _PR_UNIX_TicksPerSecond

/*
 * We wrapped the select() call.  _MD_SELECT refers to the built-in,
 * unwrapped version.
 */
#define _MD_SELECT __select

#ifdef _PR_POLL_AVAILABLE
#include <poll.h>
extern int __syscall_poll(struct pollfd *ufds, unsigned long int nfds,
	int timeout);
#define _MD_POLL __syscall_poll
#endif

/* For writev() */
#include <sys/uio.h>

#endif /* nspr_linux_defs_h___ */

---

From: [email-masked]
Date: Wed, 1 Jul 1998 17:54:25 +0200

> mostly-static link takes about 40 minutes, experimentation is expensive.

Threads are broken, the attempt to create one will crash the process.
On the to do list of things to be finished for Alex tomorrow.

  ralf

---

From: [email-masked]
Date: Thu, 2 Jul 1998 04:11:37 +0200

> mostly-static link takes about 40 minutes, experimentation is expensive.

Now that I've taken myself two minutes to browse your attached sources -
the patches to the NSPR thread routines look suspicious.  The are
playing games with the frame pointer which at least on the first look
don't make sense as gcc automatically enables -fomit-frame-pointer when
optimizing.

  Ralf

---

From: [email-masked]
Date: Sun, 5 Jul 1998 02:31:22 +0200

> I'm also taking donations of gdb.

Look what I've found on my harddisk, I think you must be talking about
this?

Current directory is /home/ralf
GNU gdb 4.17
Copyright 1998 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB.  Type "show warranty" for details.
This GDB was configured as "mips-unknown-linux-gnu"...
(gdb) break main
Breakpoint 1 at 0x40092c: file c.c, line 5.
(gdb) run
Starting program: /ext/gdb-mips/c
Cannot insert breakpoint -2:
Temporarily disabling shared library breakpoints:
-2

Program received signal SIGTRAP, Trace/breakpoint trap.
0x0 in ?? () from /lib/ld.so.1
(gdb) bt
#0  0x0 in ?? () from /lib/ld.so.1
#1  0x400924 in main () at c.c:4
(gdb)

A patch against the vanilla FSF gdb is appended.  Use it, test it, tell
me what's broken in it.  You'll also need to apply a patch to the
kernel include file <asm/ptrace.h>, it's also appended.  When testing
think of it, it's crude first cut.  Don't expect things to work to
well.

(Somebody interested in bringing the remote kernel debugging support
upto speed again?)

  Ralf
diff -urN gdb-4.17.orig/bfd/config.bfd gdb-4.17/bfd/config.bfd
--- gdb-4.17.orig/bfd/config.bfd	Tue Apr 21 00:01:31 1998
+++ gdb-4.17/bfd/config.bfd	Sun Jul  5 00:42:12 1998
@@ -427,11 +427,13 @@
     ;;
   mips*el*-*-linux* | mips*el*-*-openbsd*)
     targ_defvec=bfd_elf32_littlemips_vec
-    targ_selvecs="bfd_elf32_bigmips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec ecoff_little_vec ecoff_big_vec"
+    #targ_selvecs="bfd_elf32_bigmips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec ecoff_little_vec ecoff_big_vec"
+    targ_selvecs="bfd_elf32_bigmips_vec ecoff_little_vec ecoff_big_vec"
     ;;
   mips*-*-linux* | mips*-*-openbsd*)
     targ_defvec=bfd_elf32_bigmips_vec
-    targ_selvecs="bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec ecoff_big_vec ecoff_little_vec"
+    #targ_selvecs="bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec ecoff_big_vec ecoff_little_vec"
+    targ_selvecs="bfd_elf32_littlemips_vec ecoff_big_vec ecoff_little_vec"
     ;;
 
   mn10200-*-*)
Binary files gdb-4.17.orig/gdb/.mipslinux-nat.c.swp and gdb-4.17/gdb/.mipslinux-nat.c.swp differ
diff -urN gdb-4.17.orig/gdb/config/mips/mips-linux.mh gdb-4.17/gdb/config/mips/mips-linux.mh
--- gdb-4.17.orig/gdb/config/mips/mips-linux.mh	Thu Jan  1 01:00:00 1970
+++ gdb-4.17/gdb/config/mips/mips-linux.mh	Thu Jul  4 23:55:19 1996
@@ -0,0 +1,8 @@
+# Host: Big-endian MIPS running Linux
+XDEPFILES=
+XM_FILE= xm-linux.h
+NAT_FILE= nm-linux.h
+NATDEPFILES= infptrace.o inftarg.o mipslinux-nat.o corelow.o core-regset.o fork-child.o solib.o
+
+MMALLOC =
+MMALLOC_CFLAGS = -DNO_MMALLOC
diff -urN gdb-4.17.orig/gdb/config/mips/mips-linux.mt gdb-4.17/gdb/config/mips/mips-linux.mt
--- gdb-4.17.orig/gdb/config/mips/mips-linux.mt	Thu Jan  1 01:00:00 1970
+++ gdb-4.17/gdb/config/mips/mips-linux.mt	Thu Jul  4 23:55:19 1996
@@ -0,0 +1,3 @@
+# Target: Big-endian MIPS
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-linux.h
diff -urN gdb-4.17.orig/gdb/config/mips/nm-linux.h gdb-4.17/gdb/config/mips/nm-linux.h
--- gdb-4.17.orig/gdb/config/mips/nm-linux.h	Thu Jan  1 01:00:00 1970
+++ gdb-4.17/gdb/config/mips/nm-linux.h	Thu Jul  4 23:55:19 1996
@@ -0,0 +1,50 @@
+/* Definitions for native support of Linux/MIPS.
+
+Copyright (C) 1996 Free Software Foundation, Inc.
+
+Contributed by David S. Miller ([email-masked]) at
+Rutgers University CAIP Research Center.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR)
+extern int
+get_longjmp_target PARAMS ((CORE_ADDR *));
+
+/* Tell gdb that we can attach and detach other processes */
+#define ATTACH_DETACH
+
+/* ptrace register ``addresses'' are absolute.  */
+
+#define U_REGS_OFFSET 0
+
+#define PTRACE_ARG3_TYPE long
+
+/* ptrace transfers longs */
+
+#define PTRACE_XFER_TYPE long
+
+/* Linux has shared libraries.  */
+
+#define GDB_TARGET_HAS_SHARED_LIBS
+#define SVR4_SHARED_LIBS
+
+#include "solib.h"
+
+/* Wheee, really it is in stdio.h.  */
+
+#define PSIGNAL_IN_SIGNAL_H
diff -urN gdb-4.17.orig/gdb/config/mips/tm-linux.h gdb-4.17/gdb/config/mips/tm-linux.h
--- gdb-4.17.orig/gdb/config/mips/tm-linux.h	Thu Jan  1 01:00:00 1970
+++ gdb-4.17/gdb/config/mips/tm-linux.h	Thu Jul  4 23:55:19 1996
@@ -0,0 +1,93 @@
+/* Definitions to make GDB run on a MIPS box under Linux.  The
+   definitions here are used when the _target_ system is running Linux.
+   Copyright 1996 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef TM_MIPSLINUX_H
+#define TM_MIPSLINUX_H
+
+#include "mips/tm-bigmips.h"
+
+/* Redefine register numbers for Linux. */
+
+#undef NUM_REGS
+#undef REGISTER_NAMES
+#undef FP0_REGNUM
+#undef PC_REGNUM
+#undef PS_REGNUM
+#undef HI_REGNUM
+#undef LO_REGNUM
+#undef CAUSE_REGNUM
+#undef BADVADDR_REGNUM
+#undef FCRCS_REGNUM
+#undef FCRIR_REGNUM
+
+/* Number of machine registers */
+
+#define NUM_REGS 71
+
+/* Initializer for an array of names of registers.
+   There should be NUM_REGS strings in this initializer.  */
+
+#define REGISTER_NAMES 	\
+    {	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3", \
+	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7", \
+	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7", \
+	"t8",	"jp",	"k0",	"k1",	"gp",	"sp",	"fp",	"ra", \
+	"f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
+	"f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
+	"f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
+	"f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
+	"pc",	"cause", "badvaddr",	"lo",	"hi",	"fsr",  "fir" \
+    }
+
+/* Register numbers of various important registers.
+   Note that some of these values are "real" register numbers,
+   and correspond to the general registers of the machine,
+   and some are "phony" register numbers which are too large
+   to be actual register numbers as far as the user is concerned
+   but do serve to get the desired values when passed to read_register.  */
+
+#define FP0_REGNUM	32	/* Floating point register 0 (single float) */
+#define PC_REGNUM	64	/* Contains program counter */
+#define CAUSE_REGNUM	65	/* describes last exception */
+#define BADVADDR_REGNUM	66	/* bad vaddr for addressing exception */
+#define LO_REGNUM 	67	/* Multiple/divide temp */
+#define HI_REGNUM	68	/* ... */
+#define FCRCS_REGNUM	69	/* FP control/status */
+#define FCRIR_REGNUM	70	/* FP implementation/revision */
+
+#define CANNOT_FETCH_REGISTER(regno) \
+  ((regno) == FP_REGNUM || (regno) == ZERO_REGNUM)
+#define CANNOT_STORE_REGISTER(regno) \
+  ((regno) == FP_REGNUM || (regno) == ZERO_REGNUM)
+
+/* Must call functions within PIC code using $t9. */
+#undef  Dest_Reg
+#define Dest_Reg 25
+
+/* Just like the Sparc, we do single stepping in software, this
+   feature does _not_ belong in the kernel as far as I'm concerned.  */
+
+#define NO_SINGLE_STEP 1
+
+/* XXX TODO */
+#undef  IN_SIGTRAMP
+#define IN_SIGTRAMP(pc, name)	(0)
+
+#endif /* TM_MIPSLINUX_H */
diff -urN gdb-4.17.orig/gdb/config/mips/tm-mips.h gdb-4.17/gdb/config/mips/tm-mips.h
--- gdb-4.17.orig/gdb/config/mips/tm-mips.h	Thu Oct  9 22:26:08 1997
+++ gdb-4.17/gdb/config/mips/tm-mips.h	Thu Jul  4 23:56:58 1996
@@ -121,8 +121,6 @@
 
 #define INNER_THAN <
 
-#define BIG_ENDIAN 4321
-
 /* Old-style breakpoint macros.
    The IDT board uses an unusual breakpoint value, and sometimes gets
    confused when it sees the usual MIPS breakpoint instruction.  */
diff -urN gdb-4.17.orig/gdb/config/mips/xm-linux.h gdb-4.17/gdb/config/mips/xm-linux.h
--- gdb-4.17.orig/gdb/config/mips/xm-linux.h	Thu Jan  1 01:00:00 1970
+++ gdb-4.17/gdb/config/mips/xm-linux.h	Thu Jul  4 23:55:19 1996
@@ -0,0 +1,33 @@
+/* Definitions for Linux/MIPS hosting support.
+
+Copyright (C) 1996 Free Software Foundation, Inc.
+
+Contributed by David S. Miller ([email-masked]) at
+Rutgers University CAIP Research Center.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#if !defined (HOST_BYTE_ORDER)
+#define HOST_BYTE_ORDER BIG_ENDIAN
+#endif
+
+/* The mips has no siginterrupt routine. */
+#define NO_SIGINTERRUPT
+
+#define HAVE_TERMIOS
+#define HAVE_SIGSETMASK 1
+#define USG
diff -urN gdb-4.17.orig/gdb/configure.host gdb-4.17/gdb/configure.host
--- gdb-4.17.orig/gdb/configure.host	Thu Apr 16 23:29:58 1998
+++ gdb-4.17/gdb/configure.host	Sun Jul  5 00:21:40 1998
@@ -114,6 +114,7 @@
 # Close enough for now.
 mips-sgi-irix6*)	gdb_host=irix5 ;;
 mips-sony-*)		gdb_host=news-mips ;;
+mips-*-linux*)		gdb_host=mips-linux ;;
 mips-*-mach3*)		gdb_host=mipsm3 ;;
 mips-*-sysv4*)		gdb_host=mipsv4 ;;
 mips-*-sysv*)		gdb_host=riscos ;;
diff -urN gdb-4.17.orig/gdb/configure.tgt gdb-4.17/gdb/configure.tgt
--- gdb-4.17.orig/gdb/configure.tgt	Thu Apr 16 23:29:59 1998
+++ gdb-4.17/gdb/configure.tgt	Sun Jul  5 00:25:31 1998
@@ -187,6 +187,7 @@
 mips*-sgi-irix6*)	gdb_target=irix5 ;;
 mips*-sgi-*)		gdb_target=irix3 ;;
 mips*-sony-*)		gdb_target=bigmips ;;
+mips*-*-linux*)		gdb_target=mips-linux ;;
 mips*-*-mach3*)		gdb_target=mipsm3 ;;
 mips*-*-sysv4*)		gdb_target=mipsv4 ;;
 mips*-*-sysv*)		gdb_target=bigmips ;;
diff -urN gdb-4.17.orig/gdb/mips-nat.c gdb-4.17/gdb/mips-nat.c
--- gdb-4.17.orig/gdb/mips-nat.c	Mon Sep  9 05:01:42 1996
+++ gdb-4.17/gdb/mips-nat.c	Thu Jul  4 23:55:19 1996
@@ -1,4 +1,4 @@
-/* Low level DECstation interface to ptrace, for GDB when running native.
+/* Low level Linux & DECstation interface to ptrace, for GDB when running native.
    Copyright 1988, 1989, 1991, 1992, 1995 Free Software Foundation, Inc.
    Contributed by Alessandro Forin([email-masked]) at CMU
    and by Per Bothner([email-masked]) at U.Wisconsin.
@@ -23,6 +23,10 @@
 #include "inferior.h"
 #include "gdbcore.h"
 #include <sys/ptrace.h>
+#ifdef __linux__
+# include <asm/reg.h>
+# include <mips/ptrace.h>
+#endif
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/user.h>
diff -urN gdb-4.17.orig/gdb/mips-tdep.c gdb-4.17/gdb/mips-tdep.c
--- gdb-4.17.orig/gdb/mips-tdep.c	Wed Dec 17 20:46:10 1997
+++ gdb-4.17/gdb/mips-tdep.c	Thu Jul  4 23:55:19 1996
@@ -1500,6 +1500,148 @@
 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
 
+#ifdef NO_SINGLE_STEP
+
+static int isbranch PARAMS ((long, CORE_ADDR, CORE_ADDR *));
+
+#define INSN_BRANCH_BITS (INSN_UNCOND_BRANCH_DELAY | \
+			  INSN_COND_BRANCH_DELAY | \
+			  INSN_COND_BRANCH_LIKELY)
+
+static int
+isbranch(insn, pc, target)
+     long insn;
+     CORE_ADDR pc;
+     CORE_ADDR *target;
+{
+  long delta;
+  int i;
+
+  for (i = 0; i < NUMOPCODES; ++i)
+    if (mips_opcodes[i].pinfo != INSN_MACRO
+	&& (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
+      break;
+  if (i >= NUMOPCODES)
+    return 0;
+  if((mips_opcodes[i].pinfo & INSN_BRANCH_BITS) == 0)
+    return 0;
+
+  /* We've got one. */
+  if (mips_opcodes[i].name[0] != 'j')
+    {
+      /* The easy PC-relative branch case.  */
+      delta = (insn & 0xffff);
+      if(delta & 0x8000)
+	delta |= ~0xffff;
+      *target = (CORE_ADDR) (((long)pc) + ((delta << 2) + 4));
+    }
+  else
+    {
+      /* It's a jump, slightly more difficult.  */
+      if(mips_opcodes[i].pinfo & INSN_READ_GPR_S)
+	{
+	  int target_regno;
+
+	  /* Target is source register. */
+	  target_regno = (insn >> OP_SH_RS) & OP_MASK_RS;
+	  *target = (CORE_ADDR) read_register (target_regno);
+	}
+      else
+	{
+	  CORE_ADDR target_part;
+
+	  /* Target is low order 26 bits of insn, shifted left by 2, and
+	     or'd with the high order bits of pc.  */
+	  target_part = ((insn >> OP_SH_TARGET) & OP_MASK_TARGET) << 2;
+	  *target = ((pc & 0xf0000000) | target_part);
+	}
+    }
+  return 1;
+}
+
+static CORE_ADDR next_pc, target;
+typedef char binsn_quantum[BREAKPOINT_MAX];
+static binsn_quantum break_mem[2];
+
+/* Non-zero if we just simulated a single-step ptrace call.  This is
+   needed because we cannot remove the breakpoints in the inferior
+   process until after the `wait' in `wait_for_inferior'.  */
+
+int one_stepped;
+
+/* This is so that the code below knows whether we need to clear one,
+   or two breakpoints when the inferior resumes.  */
+
+static int doing_branch = 0;
+
+/* single_step() is called just before we want to resume the inferior,
+   if we want to single-step it but there is no hardware or kernel single-step
+   support (MIPS on Linux for example).  We find all the possible targets of
+   the coming instruction and breakpoint them.
+
+   single_step is also called just after the inferior stops.  If we had
+   set up a simulated single-step, we undo our damage.  */
+
+void
+single_step (ignore)
+     enum target_signal ignore; /* pid, but we don't need it */
+{
+  CORE_ADDR pc;
+  long pc_instruction;
+  int br;
+
+  if (!one_stepped)
+    {
+      pc = read_register (PC_REGNUM);
+      pc_instruction = read_memory_integer (pc, 4);
+      br = isbranch (pc_instruction, pc, &target);
+
+      if (br)
+	{
+	  /* Breakpoint at target of branch and 2 insns
+	     later as well.  If the branch is to itself
+	     the best we can do is wait for it to fall
+	     out on us.  */
+	  if(target != pc)
+	    {
+	      target_insert_breakpoint(target, break_mem[1]);
+	      doing_branch = 1;
+	    }
+	  else
+	    {
+	      doing_branch = 0;
+	    }
+	  next_pc = pc + 8;
+	  target_insert_breakpoint(next_pc, break_mem[0]);
+	}
+      else
+	{
+	  /* Just the very next instruction needs a break.  */
+	  doing_branch = 0;
+	  next_pc = pc + 4;
+	  target_insert_breakpoint(next_pc, break_mem[0]);
+	}
+
+      /* We are ready to let it go */
+      one_stepped = 1;
+      return;
+    }
+  else
+    {
+      /* Remove breakpoints */
+      target_remove_breakpoint (next_pc, break_mem[0]);
+
+      if (doing_branch)
+	{
+	  target_remove_breakpoint (target, break_mem[1]);
+	}
+
+      one_stepped = 0;
+    }
+}
+
+#endif /* NO_SINGLE_STEP */
+
 void
 mips_push_dummy_frame()
 {
diff -urN gdb-4.17.orig/gdb/mipslinux-nat.c gdb-4.17/gdb/mipslinux-nat.c
--- gdb-4.17.orig/gdb/mipslinux-nat.c	Thu Jan  1 01:00:00 1970
+++ gdb-4.17/gdb/mipslinux-nat.c	Sun Jul  5 01:42:13 1998
@@ -0,0 +1,193 @@
+/* Low level MIPS/Linux interface, for GDB when running native.
+   Copyright 1996 Free Software Foundation, Inc.
+   Contributed by David S. Miller ([email-masked]) at
+   Rutgers University CAIP Research Center.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define __timespec_defined /* Yuck ... */
+#include <linux/time.h>
+
+#include "defs.h"
+#include "inferior.h"
+#include "gdbcore.h"
+#include "target.h"
+#include "gdb_string.h"
+#include "symtab.h"
+#include "bfd.h"
+#include "symfile.h"
+#include "objfiles.h"
+#include "command.h"
+#include "frame.h"
+#include "gnu-regex.h"
+#include "inferior.h"
+#include "language.h"
+#include "gdbcmd.h"
+#include <sys/ptrace.h>
+//#include <sys/time.h>
+#include <asm/reg.h>
+#include <linux/elf.h>
+#include <linux/elfcore.h>
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/user.h>
+
+#include <setjmp.h>   /* For JB_PC and friends. */
+
+/* Size of elements in jmpbuf */
+
+#define JB_ELEMENT_SIZE 4
+
+/* Figure out where the longjmp will land.
+   We expect the first arg to be a pointer to the jmp_buf structure from which
+   we extract the pc (JB_PC) that we will land at.  The pc is copied into PC.
+   This routine returns true on success. */
+
+int
+get_longjmp_target(pc)
+     CORE_ADDR *pc;
+{
+  CORE_ADDR jb_addr;
+  char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
+
+  jb_addr = read_register (A0_REGNUM);
+
+  if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
+			  TARGET_PTR_BIT / TARGET_CHAR_BIT))
+    return 0;
+
+  *pc = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
+
+  return 1;
+}
+
+/*
+ * See the comment in m68k-tdep.c regarding the utility of these functions.
+ *
+ * These definitions are from the MIPS SVR4 ABI, so they may work for
+ * any MIPS SVR4 target.
+ */
+
+void 
+supply_gregset (gregsetp)
+     gregset_t *gregsetp;
+{
+  register int regi;
+  register unsigned int *regp = (unsigned int *) &(*gregsetp)[0];
+  static char zerobuf[MAX_REGISTER_RAW_SIZE] = {0};
+
+  for (regi = EF_REG0; regi <= EF_LO; regi++)
+    supply_register ((regi - EF_REG0), (char *)(regp + regi));
+
+  supply_register(PC_REGNUM, (char *)(regp + EF_CP0_EPC));
+  supply_register(CAUSE_REGNUM, (char *)(regp + EF_CP0_CAUSE));
+  supply_register(BADVADDR_REGNUM, (char *)(regp + EF_CP0_BADVADDR));
+  supply_register(LO_REGNUM, (char *)(regp + EF_LO));
+  supply_register(HI_REGNUM, (char *)(regp + EF_HI));
+
+  /* Fill inaccessible registers with zero.  */
+  supply_register (FP_REGNUM, zerobuf);
+  supply_register (UNUSED_REGNUM, zerobuf);
+}
+
+void
+fill_gregset (gregsetp, regno)
+     gregset_t *gregsetp;
+     int regno;
+{
+  int regi;
+  register unsigned int *regp = (unsigned int *) &(*gregsetp)[0];
+
+  for (regi = 0; regi <= (EF_SIZE / 4); regi++)
+    if ((regno == -1) || (regno == regi))
+      *(regp + regi) = *(unsigned int *) &registers[REGISTER_BYTE (regi)];
+}
+
+/* Now we do the same thing for floating-point registers.
+ * We don't bother to condition on FP0_REGNUM since any
+ * reasonable MIPS configuration has an R3010 in it.
+ *
+ * Again, see the comments in m68k-tdep.c.
+ */
+
+void
+supply_fpregset (fpregsetp)
+     fpregset_t *fpregsetp;
+{
+  register int regi;
+  static char zerobuf[MAX_REGISTER_RAW_SIZE] = {0};
+
+  for (regi = 0; regi < 32; regi++)
+    supply_register (FP0_REGNUM + regi,
+		     (char *)&fpregsetp[regi]);
+
+  supply_register (FCRCS_REGNUM, (char *)&fpregsetp[32]);
+
+  /* FIXME: how can we supply FCRIR_REGNUM?  The ABI doesn't tell us. */
+  supply_register (FCRIR_REGNUM, zerobuf);
+}
+
+void
+fill_fpregset (fpregsetp, regno)
+     fpregset_t *fpregsetp;
+     int regno;
+{
+  int regi;
+  char *from, *to;
+
+  for (regi = FP0_REGNUM; regi < FP0_REGNUM + 32; regi++)
+    {
+      if ((regno == -1) || (regno == regi))
+	{
+	  from = (char *) &registers[REGISTER_BYTE (regi)];
+	  to = (char *) &(fpregsetp[regi - FP0_REGNUM]);
+	  memcpy(to, from, REGISTER_RAW_SIZE (regi));
+	}
+    }
+
+#if 0
+  if ((regno == -1) || (regno == FCRCS_REGNUM))
+    fpregsetp[32] = *(unsigned int *) &registers[REGISTER_BYTE(FCRCS_REGNUM)];
+#endif
+}
+
+/* Map gdb internal register number to ptrace ``address''.
+   These ``addresses'' are defined in <mips/ptrace.h> */
+
+#define REGISTER_PTRACE_ADDR(regno) \
+   (regno < 32 ? 		regno   \
+  : regno == PC_REGNUM ?	PC	\
+  : regno == CAUSE_REGNUM ?	CAUSE	\
+  : regno == HI_REGNUM ?	MMHI	\
+  : regno == LO_REGNUM ?	MMLO	\
+  : regno == FCRCS_REGNUM ?	FPC_CSR	\
+  : regno == FCRIR_REGNUM ?	FPC_EIR	\
+  : regno >= FP0_REGNUM ?	FPR_BASE + (regno - FP0_REGNUM) \
+  : 0)
+
+/* Return the ptrace ``address'' of register REGNO. */
+
+CORE_ADDR
+register_addr (regno, blockend)
+     int regno;
+     CORE_ADDR blockend;
+{
+  if(regno < 0 || regno >= NUM_REGS)
+    error ("Bogon register number %d.", regno);
+
+  return REGISTER_PTRACE_ADDR (regno);
+}
diff -urN linux-2.0.30.orig/include/asm-mips/ptrace.h linux-2.0.30/include/asm-mips/ptrace.h
--- linux-2.0.30.orig/include/asm-mips/ptrace.h	Sat Oct 11 21:13:51 1997
+++ linux-2.0.30/include/asm-mips/ptrace.h	Sun Jul  5 01:52:05 1998
@@ -15,6 +15,14 @@
 
 #include <linux/types.h>
 
+#define PC		0
+#define CAUSE		1
+#define MMLO		3
+#define MMHI		4
+#define FPC_CSR		5	/* XXX */
+#define FPC_EIR		4	/* XXX */
+#define FPR_BASE	5	/* XXX */
+
 #ifndef __ASSEMBLY__
 /*
  * This struct defines the way the registers are stored on the stack during a
@@ -59,6 +67,6 @@
 extern void (*show_regs)(struct pt_regs *);
 #endif /* !(__ASSEMBLY__) */
 
-#endif
+#endif /* __KERNEL__ */
 
 #endif /* __ASM_MIPS_PTRACE_H */

---

From: Mike Shaver <[email-masked]>
Date: Mon, 06 Jul 1998 13:38:30 -0400

> don't make sense as gcc automatically enables -fomit-frame-pointer when

Turns out it's there only to save the FP so that you can use gdb to look
at the NSPR thread stacks during debugging.  So, the fact that gcc
removes it when building optimized isn't a problem.

For the record, NSPR threads aren't clone() threads; they're
setjmp/longjmp things.

Mike

-- 
517588.35 442847.89

---

From: [email-masked]
Date: Mon, 6 Jul 1998 20:31:53 +0200

> For the record, NSPR threads aren't clone() threads; they're

Usless effort, on MIPS debugging works without having a frame pointer.

  RalF