Subject: Bug

From: Ulf Carlsson <[email-masked]>
Date: Fri, 4 Sep 1998 20:51:47 +0200 (CEST)

Hi,

I think you forgot a break in the middle of a switch statement, setting
order to 3 is pretty nonsense otherwise.
I compiled a new kernel with my patch, and I couldn't see any changes. The
VCED is probably handled correctly by the interrupt anyway.

patch applies to arch/mips/mm/init.c

--- init.c.org  Fri Sep  4 20:34:11 1998
+++ init.c      Fri Sep  4 20:45:40 1998
@@ -126,6 +126,7 @@
        case CPU_R4400SC:
        case CPU_R4400MC:
                order = 3;
+               break;
        default:
                order = 0;
        }

- Ulf

---

From: [email-masked]
Date: Fri, 4 Sep 1998 23:25:28 +0200

> VCED is probably handled correctly by the interrupt anyway.

Thanks, applied.  Note that this bug just resulted in somewhat reduced
performance at cost of 28kb more memory used.  On SC CPUs we use 8
different empty_zero_page pages to avoid VCED errors completly.

  Ralf