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From: Ulf Carlsson <grim@zigzegv.ml.org>
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To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
cc: Richard Hartensveld <richardh@infopact.nl>,
        "linux@cthulhu.engr.sgi.com" <linux@cthulhu.engr.sgi.com>
Subject: Re: crosscompiling on debian/i386
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On Thu, 1 Oct 1998, Thomas Bogendoerfer wrote:

> no he tries to crosscompile with gcc-2.7.2.x a new kernel from CVS.
> This does no longer work out of the box, because we've changed the 
> #ifdef _LANGUAGE_ASSEMBLY to the egcs predefined ones. And these aren't
> defined in the gcc-2.7 spec file.
> 
> I don't have a patch handy, but simply changing -D__LANGUAGE_ASSMBLEY__ to
> -D_LANGUAGE_ASSEMBLY and -D__LANGUAGE_C__ to -D_LANGUAGE_C in the spec
> file worked for me.

I've already changed those defines.

I don't have a patch (I don't have the old file anylonger), but I can send
the whole file (/usr/local/lib/gcc-lib/mips-linux/2.7.2.2/specs)

It's attached.

- Ulf


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From owner-linux@cthulhu.engr.sgi.com  Fri Oct  2 09:42:36 1998
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Date: Fri, 02 Oct 1998 18:46:04 +0200
From: Richard Hartensveld <richardh@infopact.nl>
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To: Ulf Carlsson <grim@zigzegv.ml.org>
CC: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        "linux@cthulhu.engr.sgi.com" <linux@cthulhu.engr.sgi.com>
Subject: Re: crosscompiling on debian/i386
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Ulf Carlsson wrote:

> On Thu, 1 Oct 1998, Thomas Bogendoerfer wrote:
>
> > no he tries to crosscompile with gcc-2.7.2.x a new kernel from CVS.
> > This does no longer work out of the box, because we've changed the
> > #ifdef _LANGUAGE_ASSEMBLY to the egcs predefined ones. And these aren't
> > defined in the gcc-2.7 spec file.
> >
> > I don't have a patch handy, but simply changing -D__LANGUAGE_ASSMBLEY__ to
> > -D_LANGUAGE_ASSEMBLY and -D__LANGUAGE_C__ to -D_LANGUAGE_C in the spec
> > file worked for me.
>
> I've already changed those defines.
>
> I don't have a patch (I don't have the old file anylonger), but I can send
> the whole file (/usr/local/lib/gcc-lib/mips-linux/2.7.2.2/specs)
>

Works perfectly, i've just build the first kernel with it and i'm  now gonna
try to get al the output on the
serial console. (challenge S).

Richard



From owner-linux@cthulhu.engr.sgi.com  Sat Oct  3 09:14:26 1998
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Date: Sat, 3 Oct 1998 18:00:09 +0200
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To: "William J. Earl" <wje@fir.engr.sgi.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux@cthulhu.engr.sgi.com
Subject: Re: VCEI/VCED handling
References: <19980929011414.43485@alpha.franken.de> <19980929015003.E2215@uni-koblenz.de> <19980929232455.30571@alpha.franken.de> <19980930015819.D3920@uni-koblenz.de> <199809300121.SAA21169@fir.engr.sgi.com>
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On Tue, Sep 29, 1998 at 06:21:03PM -0700, William J. Earl wrote:

>        On the machines without VCE detection (R4000PC, R4600, R5000),
> the zero page is safe, because it is read-only.  Anonymous pages
> are not an issue, since they are not double-mapped.
> 
>        What is wrong with going from the mem_map_t.inode to the
> inode.i_mmap list of mappings, and thence to the PTEs?  IRIX, at least
> before IRIX 6.5, does the equivalent to solve this problem.

Nothing - anymore.  On older kernels your suggestion wouldn't have worked
for SYSV IPC, so I forgot about that possibility ...

>  > Mapping shared writeable pages uncached is not the solution.  The virtual
>  > coherency problem in Linux/MIPS may happen between multiple userspace
>  > mappings or userspace and kernelspace, that is KSEG0, mappings.  While
>  > we could disable caching for certain pages in the hope that we'll only
>  > end up with a few uncached pages making KSEG0 uncached is completly
>  > unacceptable performancewise.  However, if we don't, then we might end up
>  > with aliases between userspace pages and KSEG0 pages.
> 
>       You can use KSEG2 instead of KSEG0 for all pages which might be
> mapped into user space.  IRIX mostly does that, and keeps the KSEG2 mapping
> around only as long as necessary, and then only with the current virtual
> color (the color which currently has write ownership of the page) locked
> (which means that references via other colors block until the kernel
> gives up its mapping).  

It is my understanding that read/write syscalls used on mmaped file is the
only instance of that problem we need to deal with.  I think we can do so by
modifying update_vm_cache to fit the special needs of certain cache
architectures and introducing something similar to be used when reading.

The KSEG2 approach is definately much nicer for that than what we're using
right now for ptrace reading / writing to other processes' address space.

Btw, it looks like the MIPS NT HAL do the same thing.  At least the interfaces
provides by HAL.DLL strongly suggest so.

Oh, and somebody just promised to snail me a R4000SC module so I hope I can
tackle the SC problems rsn and make some more people lucky.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sun Oct  4 14:09:13 1998
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Date: Sun, 4 Oct 1998 03:32:05 +0200
From: ralf@uni-koblenz.de
To: Jakub Jelinek <jj@sunsite.ms.mff.cuni.cz>, ANeuper@guug.de
Cc: aeb@cwi.nl, LeBlanc@mcc.ac.uk, fasten@informatik.uni-bonn.de,
        shaver@netscape.com, linux@cthulhu.engr.sgi.com
Subject: Re: SGI partitions / fdisk
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On Sat, Oct 03, 1998 at 09:57:47PM +0200, Jakub Jelinek wrote:

I've got some more fdisk patches around which make fdisk work correctly
with PC style partitions on big endian machines.  So I can now partition
all auxilary disks on my Indy and move them with my PC and Indy/Linux.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sun Oct  4 04:23:23 1998
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Date: Sun, 4 Oct 1998 13:23:12 +0200 (CEST)
From: Ulf Carlsson <grim@zigzegv.ml.org>
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Subject: HAL2
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Hi,

As you know IRIX uses an audio library to provide audio support for user
level applications. The implementation of my HAL2 driver will exist in
kernel space, and a user level library will provide higher level interface
to the applications (the same interface as libaudio.a in IRIX). Do we know
what the interface between libaudio.a and the Irix kernel looks like or am
I free to do what I want?

The code I've written so far is based upon this idea.

Is this the Right Thing to do it?

Is there any further information except audio.h and hal.h which I don't
have? 

- Ulf


From owner-linux@cthulhu.engr.sgi.com  Sun Oct  4 05:06:34 1998
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Date: Sun, 4 Oct 1998 14:06:40 +0200 (CEST)
From: Ulf Carlsson <grim@zigzegv.ml.org>
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To: Alan Cox <alan@lxorguk.ukuu.org.uk>
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Subject: Re: HAL2
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On Sun, 4 Oct 1998, Alan Cox wrote:

> > level applications. The implementation of my HAL2 driver will exist in
> > kernel space, and a user level library will provide higher level interface
> > to the applications (the same interface as libaudio.a in IRIX). Do we know
> > what the interface between libaudio.a and the Irix kernel looks like or am
> > I free to do what I want?
> > 
> > The code I've written so far is based upon this idea.
> > 
> > Is this the Right Thing to do it?
> 
> Not IMHO, well not unless it also supports the sound ioctls that every
> other Linux platform does as well. 

If you run Linux on a sparc, it provides access to an interface,
/dev/audio, similar to the one you find in Solaris (I don't have Solaris,
but the include file, asm-sparc/audioio.h tells me that it does). 

You just told me that you thought my way to do it was an incorrect way og
doing it, tell me how it should be done instead. 

- Ulf


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From: alan@lxorguk.ukuu.org.uk (Alan Cox)
Subject: Re: HAL2
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> level applications. The implementation of my HAL2 driver will exist in
> kernel space, and a user level library will provide higher level interface
> to the applications (the same interface as libaudio.a in IRIX). Do we know
> what the interface between libaudio.a and the Irix kernel looks like or am
> I free to do what I want?
> 
> The code I've written so far is based upon this idea.
> 
> Is this the Right Thing to do it?

Not IMHO, well not unless it also supports the sound ioctls that every
other Linux platform does as well. 


From owner-linux@cthulhu.engr.sgi.com  Sun Oct  4 05:12:00 1998
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From: alan@lxorguk.ukuu.org.uk (Alan Cox)
Subject: Re: HAL2
To: grim@zigzegv.ml.org (Ulf Carlsson)
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> If you run Linux on a sparc, it provides access to an interface,
> /dev/audio, similar to the one you find in Solaris (I don't have Solaris,
> but the include file, asm-sparc/audioio.h tells me that it does). 

Yes

> You just told me that you thought my way to do it was an incorrect way og
> doing it, tell me how it should be done instead. 

Supporting the Indy ioctls is fine. However like the sparc, ppc, m68k,
ix86, alpha and arm you need to support the common OSS API. I don't know
if supporting the OSS API is sufficient alone to write libaudio over since
I dont know a ton about the internals of the libaudio stuff on SGI's.

Basically though the OSS API is a common API across all the linux platforms.

Alan


From owner-linux@cthulhu.engr.sgi.com  Sun Oct  4 07:45:07 1998
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Date: Sun, 4 Oct 1998 16:38:40 +0200
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Ulf Carlsson <grim@zigzegv.ml.org>
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: HAL2
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On Sun, Oct 04, 1998 at 01:23:12PM +0200, Ulf Carlsson wrote:
> level applications. The implementation of my HAL2 driver will exist in
> kernel space, and a user level library will provide higher level interface
> to the applications (the same interface as libaudio.a in IRIX). Do we know
> what the interface between libaudio.a and the Irix kernel looks like or am
> I free to do what I want?

For IRIX compatibilty, we may want to implement the same interface as
IRIX has. But for Linux compatiblity we should have something, which fits
into the current Linux sound devices scheme. And as the Linux interface is 
available in source, I would go that way. And when you do the libaudio.a 
stuff based on the Linux sound devices, it will also be available for other 
Linux architectures.

Maybe it's even possible to get IRIX compatible sound, with a user level
only solution.

Thomas.

-- 
See, you not only have to be a good coder to create a system like Linux,
you have to be a sneaky bastard too ;-)
                   [Linus Torvalds in <4rikft$7g5@linux.cs.Helsinki.FI>]

From owner-linux@cthulhu.engr.sgi.com  Sun Oct  4 16:01:27 1998
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Date: Mon, 5 Oct 1998 00:59:46 +0200
From: ralf@uni-koblenz.de
To: Andries.Brouwer@cwi.nl, ANeuper@guug.de, jj@sunsite.ms.mff.cuni.cz
Cc: LeBlanc@mcc.ac.uk, fasten@informatik.uni-bonn.de,
        linux@cthulhu.engr.sgi.com, shaver@netscape.com
Subject: Re: SGI partitions / fdisk
References: <UTC199810042124.XAA67442.aeb@texel.cwi.nl>
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On Sun, Oct 04, 1998 at 11:24:18PM +0200, Andries.Brouwer@cwi.nl wrote:

> > I've got some more fdisk patches around which make fdisk work correctly
> > with PC style partitions on big endian machines.
> 
> They are welcome, although it may well be that I have done
> this same work already. Have you looked at a recent fdisk?

No.  My work is based on whatever is shipping with RedHat 5.1.  Where can
I get the latest and hottest release of linux-utils?

> Btw - there will soon be a new release of util-linux,
> including fdisk etc, so this is a good moment to dig up
> all fdisk patches you may have.

Yes, it would be.  Actually since fdisk has been hacked up so badly I
think a major cleanup wouldn't be bad.

(Any followups please to ralf@bofh.de, not ralf@uni-koblenz.de.  The later
address will from tomorrow on be unreachable for as much as several days.)

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sun Oct  4 16:04:49 1998
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Date: Mon, 5 Oct 1998 01:03:46 +0200
From: ralf@uni-koblenz.de
To: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: Death of Milo
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Hi all,

Thomas and me have finally decided to put in the bit of work to
kill Milo.  When we're done with that all ARC platforms, be they
SGI or little endian, will use the same code which will basically
be what we're using now for the Indy plus a couple of megatons of
ARC workarounds.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Mon Oct  5 02:10:01 1998
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unsubscribe

From owner-linux@cthulhu.engr.sgi.com  Mon Oct  5 02:17:47 1998
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Quoting Kris Boulez (kris@belbone.be):
> unsubscribe
<blush>
	Sorry ...
</blush>

Kris
-- 
Kris Boulez				kris@belbone.be

From owner-linux@cthulhu.engr.sgi.com  Thu Oct  8 03:01:15 1998
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Date: Thu, 8 Oct 1998 12:01:12 +0200 (CEST)
From: Ulf Carlsson <grim@zigzegv.ml.org>
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Subject: R4600PC upgrade
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Hi,

I received a R4600PC today (thanks Lukas), and I happily went to my Indy
and plugged it in instead of my R4000SC. It failed on the diagnostics test
though. 

Exception: <vector=Normal>
Status register: 0x30004803<CU1,CU0,IM7,IM4,IPL=???,MODE=KERNEL,EXL,IE>
Cause register: 0x4000<CE=0,IP7,EXC=INT>
Exception PC: 0xbfc0b598
Interrupt exception
CPU Parity Error Interrupt
Local I/O interrupt register 1: 0x80 <VR/GIO2>
CPU parity error register: 0x80b<B0,B1,B3,SYSAD_PAR>
CPU parity error: address: 0x1fc0b598
NESTED EXCEPTION #1 at EPC: 9fc3df00; first exception at PC: bfc0b598

I don't have a clue at the moment.

- Ulf


From owner-linux@cthulhu.engr.sgi.com  Thu Oct  8 03:21:50 1998
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Date: Thu, 8 Oct 1998 12:21:49 +0200 (CEST)
From: Ulf Carlsson <grim@zigzegv.ml.org>
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Two major types of data errors can occur in data transmission:

	* hard errors, which are permanent, arise from broken
	  interconnects, internal shorts, or open leads.

	* soft errors, which are transient, are caused by system noise,
	  power surges, and alpha particles.

Hard errors must be corrected by physical repair of the damaged
equipment and restoration of data from backup. Soft errors can be
corrected by using error checking and correcting codes

--

Oups... sounds really bad.

- Ulf


From owner-linux@cthulhu.engr.sgi.com  Thu Oct  8 07:34:50 1998
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Date: Thu, 8 Oct 1998 15:33:41 +0100 (BST)
From: Leon Verrall <leon@reading.sgi.com>
Reply-To: Leon Verrall <leon@reading.sgi.com>
To: Ulf Carlsson <grim@zigzegv.ml.org>
cc: linux@cthulhu.engr.sgi.com
Subject: Re: R4600PC upgrade
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On Thu, 8 Oct 1998, Ulf Carlsson wrote:

> I received a R4600PC today (thanks Lukas), and I happily went to my Indy
> and plugged it in instead of my R4000SC. It failed on the diagnostics test
> though. 
> 
> Exception: <vector=Normal>
> Status register: 0x30004803<CU1,CU0,IM7,IM4,IPL=???,MODE=KERNEL,EXL,IE>
> Cause register: 0x4000<CE=0,IP7,EXC=INT>
> Exception PC: 0xbfc0b598
> Interrupt exception
> CPU Parity Error Interrupt
> Local I/O interrupt register 1: 0x80 <VR/GIO2>
> CPU parity error register: 0x80b<B0,B1,B3,SYSAD_PAR>
> CPU parity error: address: 0x1fc0b598
> NESTED EXCEPTION #1 at EPC: 9fc3df00; first exception at PC: bfc0b598

We have an Indy in the lab that does this occasionally. It's a bit old and
crappy. On that machine it's a problem with the processor seating or
connections. Often happens after a power cycle.

The cure is usually, take the top off the Indy and give the processor board
a good push down and generally push everything else around it home...

Leon

-- 
Leon Verrall - 01189 257734  \ "Don't cut your losses too soon,
Secondline Software Support  / 'cos you'll only be cutting your throat.
Silicon Graphics, Forum 1,   \ And answer a call while you still care at all
Station Rd., Theale, RG7 4RA / 'cos nobody will if you wont" (6:00 - DT)



From owner-linux@cthulhu.engr.sgi.com  Thu Oct  8 07:49:54 1998
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Date: Thu, 8 Oct 1998 16:50:09 +0200 (CEST)
From: Ulf Carlsson <grim@zigzegv.ml.org>
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On Thu, 8 Oct 1998, Leon Verrall wrote:

> The cure is usually, take the top off the Indy and give the processor board
> a good push down and generally push everything else around it home...

I gave it some _really_ good pushes, didn't work at all. Yes, my Indy is
old (and certainly very crappy). I have never got that error with the
R4000SC (I've also switched processors back after testing the R4600PC, and
the R4000SC still works). Do you think this fault can be caused by damage
from static electricity?

I'm really disappointed with myself, life, and everything if I vaporized
this processor and this great chance to run Linux.

- Ulf


From owner-linux@cthulhu.engr.sgi.com  Thu Oct  8 09:16:04 1998
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Date: Thu, 8 Oct 1998 17:03:35 +0200
From: ralf@uni-koblenz.de
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu, linux@cthulhu.engr.sgi.com
Subject: Re: Tags are dead alias Milo is dead part II
References: <19981007002547.44731@alpha.franken.de>
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On Wed, Oct 07, 1998 at 12:25:47AM +0200, Thomas Bogendoerfer wrote:

> In the process of making Milo obsolete I've also removed tags stuff. This
> was simple for the Indy and took only a few hours for the Olivetti. I hope
> it's also possible for the Decstation. Before I'll start commiting the changes
> we should make sure, how to solve the missing tags for all plattforms.
> 
> Another old code, which might be obsolete now is the wired entry stuff
> in arch/mips/kernel/head.S. It's already disabled for R4k CPUs and
> I would prefer to remove that stuff also for the other CPUs. If you
> need wired entries, I would propose using the add_wired_entry()
> function as I already do it for the JAZZ hardware (arch/mips/jazz/setup.c).

People should consider that TLB entries are a scarce resource.  Wiring them
can seriously impact performance.  (Which reminds me of the lock warning
bit in the 68851 - Moto people we seriously assuming somebody could wire all
ATC (that is TLB in Moto slang) entries ...)

Our current 32 bit page table structure is good for mapping everything in
the lowest 4gb of physical address space.  Things outside of this area are
the only things which will need to be mapped by some other mean.  We've
so far used wired entries which in most cases they're a bad idea for the
above mentioned reason.  Since loading and flushing a single TLB entry is
a quite cheap thing on MIPS parts of the kernel could do things like

	struct wired {
		caddr_t physical;
		caddr_t virtual;
		u32	mask;
		u32	usage;
		u8 entry;
	} gfx_entry = {
		GFX_PBASE,
		GFX_VBASE,
		PM_4M
	};

	entry = load_wired_entry(&gfx_entry);

	... /* Munge mapped address space */

	flush_wired_entry(entry);

Applied to the G364 drivers (which as of now is still MIPS specific anyway)
this means that we'll avoid TLB trashing in the case of scrolling and have
the full TLB available for userland.

The second alternative which can be used where it's ok to disable interrupts
is to access memory using one of the XKPHYS segments.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Thu Oct  8 11:16:50 1998
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Ulf Carlsson <grim@zigzegv.ml.org>
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: R4600PC upgrade
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Ulf Carlsson writes:
 > Hi,
 > 
 > I received a R4600PC today (thanks Lukas), and I happily went to my Indy
 > and plugged it in instead of my R4000SC. It failed on the diagnostics test
 > though. 
...
     If your machine is an early R4000SC machine, you may well need a new
PROM to go with the newer processor.  The final PROM, supplied with all
R5000 systems, works with all processors, but a given older PROM generally
does not work with newer processors.  The error message looks like the
result of using an obsolete PROM.

From owner-linux@cthulhu.engr.sgi.com  Thu Oct  8 13:03:55 1998
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Date: Thu, 8 Oct 1998 21:58:34 +0200
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: ralf@uni-koblenz.de
Cc: linux-mips@fnet.fr, linux-mips@vger.rutgers.edu,
        linux@cthulhu.engr.sgi.com
Subject: Re: Tags are dead alias Milo is dead part II
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On Thu, Oct 08, 1998 at 05:03:35PM +0200, ralf@uni-koblenz.de wrote:
> Applied to the G364 drivers (which as of now is still MIPS specific anyway)
> this means that we'll avoid TLB trashing in the case of scrolling and have
> the full TLB available for userland.

I don't believe this will buy us anything. When we add a temporary TLB we need
do clear one TLB, which might be used by the userland. So we end up loading
our wired entry, killing it, and later the user process has to reload the 
TLB again. This way we force TLB trashing, with one wired entry more we
_might_ get a little bit more TLB trashing.

As you might know, I'm using three wired entries for the Magnum, and I don't 
think doing the same trick for the other entries is a real good idea. When 
we make them temporary, we have to mess with TLBs on every interrupt.

Thomas.

-- 
   This device has completely bogus header. Compaq scores again :-|
It's a host bridge, but it should be called ghost bridge instead ;^)
                                        [Martin `MJ' Mares on linux-kernel]

From owner-linux@cthulhu.engr.sgi.com  Thu Oct  8 13:33:15 1998
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To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: ralf@uni-koblenz.de, linux-mips@fnet.fr, linux-mips@vger.rutgers.edu,
        linux@cthulhu.engr.sgi.com
Subject: Re: Tags are dead alias Milo is dead part II
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Thomas Bogendoerfer writes:
 > On Thu, Oct 08, 1998 at 05:03:35PM +0200, ralf@uni-koblenz.de wrote:
 > > Applied to the G364 drivers (which as of now is still MIPS specific anyway)
 > > this means that we'll avoid TLB trashing in the case of scrolling and have
 > > the full TLB available for userland.
 > 
 > I don't believe this will buy us anything. When we add a temporary TLB we need
 > do clear one TLB, which might be used by the userland. So we end up loading
 > our wired entry, killing it, and later the user process has to reload the 
 > TLB again. This way we force TLB trashing, with one wired entry more we
 > _might_ get a little bit more TLB trashing.
 > 
 > As you might know, I'm using three wired entries for the Magnum, and I don't 
 > think doing the same trick for the other entries is a real good idea. When 
 > we make them temporary, we have to mess with TLBs on every interrupt.

     You could do what IRIX does in some cases, which is to save and restore
the TLB entry you replace.  Beware of doing this, however, if your code could
take a page fault.


From owner-linux@cthulhu.engr.sgi.com  Fri Oct  9 16:18:19 1998
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Date: Fri, 9 Oct 1998 19:17:16 -0400 (EDT)
From: Jeremy John Welling <jwelling@engin.umich.edu>
To: linux@cthulhu.engr.sgi.com
Subject: Re: R4600PC upgrade
In-Reply-To: <199810081815.LAA04238@fir.engr.sgi.com>
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I agree.  I got a message almost exactly like this when I went from 4400
to 5000.  I have still have my 4400 prom if you need it.  Just let me know
where to send it.

Jeremy Welling

On Thu, 8 Oct 1998, William J. Earl wrote:

> Ulf Carlsson writes:
>  > Hi,
>  > 
>  > I received a R4600PC today (thanks Lukas), and I happily went to my Indy
>  > and plugged it in instead of my R4000SC. It failed on the diagnostics test
>  > though. 
> ...
>      If your machine is an early R4000SC machine, you may well need a new
> PROM to go with the newer processor.  The final PROM, supplied with all
> R5000 systems, works with all processors, but a given older PROM generally
> does not work with newer processors.  The error message looks like the
> result of using an obsolete PROM.
> 



From owner-linux@cthulhu.engr.sgi.com  Sat Oct 10 11:35:22 1998
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From: Brian Toscano <btoscano@shell.monmouth.com>
Message-Id: <199810101834.OAA20742@shell.monmouth.com>
Subject: R4400SC
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Hi all,

I've just signed on to this list and have procmail working reliably.  I
asked this once before, but I don't think it went out.

I've got an R4400SC-150 Indy and I'm wondering if its supported.  The Web
site and mailing list seem to offer conflicting information.   I was attempting
a net install from an i386 RedHat 5.1 box and it grabs the kernel okay, but
dies trying to mount the root partition with a VFS error. 

Thanks,
Brian Toscano
btoscano@monmouth.com
brian@cs.njit.edu



From owner-linux@cthulhu.engr.sgi.com  Sat Oct 10 12:11:13 1998
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On Sat, 10 Oct 1998, Brian Toscano wrote:

> I've got an R4400SC-150 Indy and I'm wondering if its supported.  The Web
> site and mailing list seem to offer conflicting information.   I was attempting
> a net install from an i386 RedHat 5.1 box and it grabs the kernel okay, but
> dies trying to mount the root partition with a VFS error. 

Not a chance at the moment...

Ralf will have a R4000SC CPU to play with next week, and I guess he will
solve our problems with the SC CPUs within a couple of weeks if he just
has some spare time.

- Ulf


From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 11:31:08 1998
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Fernando D. Mato Mira wrote:

> Hello,
>
> What would one need to do to port what is running of SGI/Linux to
> Indigo R4400 150MHz Elan?

One would need to write device drivers for:
- SCSI
- ethernet
- display or serial

I thought the indigo used either gio64 or gio32.  I might be wrong.

Have I missed anything?

- Alex


From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 15:06:11 1998
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Date: Mon, 12 Oct 1998 20:15:09 +0200
From: ralf@uni-koblenz.de
To: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: R4000SC
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Hi all,

today I've received an R4000SC module which has been sent to me by Ulf
Carlsson.  Thanks Ulf!  I'm quite confident that after finishing todays
sad duties I'll be able to fix the problem quite fast.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 11:22:43 1998
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Date: Mon, 12 Oct 1998 20:22:18 +0200
To: linux@cthulhu.engr.sgi.com
From: "Fernando D. Mato Mira" <matomira@acm.org>
Subject: I am interested in helping port to Indigo
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Hello,

What would one need to do to port what is running of SGI/Linux to 
Indigo R4400 150MHz Elan?

Regards,




From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 11:29:14 1998
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To: "Fernando D. Mato Mira" <matomira@acm.org>
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Fernando D. Mato Mira writes:
 > Hello,
 > 
 > What would one need to do to port what is running of SGI/Linux to 
 > Indigo R4400 150MHz Elan?

     By "Indigo R4400", I assume you mean "Indigo2 R4400".  As far as
I know, we only supported the R4000 in the "Indigo R4000".  The 
kernel should be mostly compatible, aside from some details about
clocks, the addition of the EISA bus, and the absence of the video
port.  The big issue is the graphics.  Elan has downloaded microcode,
although you might make do with what is downloaded by the PROM.
Unfortunately, I cannot at present supply documentation for the
interface exported by that microcode (partly because I don't have
any ready to hand).  


From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 11:48:17 1998
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To: Alex deVries <adevries@engsoc.carleton.ca>
Cc: "Fernando D. Mato Mira" <matomira@acm.org>, linux@cthulhu.engr.sgi.com
Subject: Re: I am interested in helping port to Indigo
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Alex deVries writes:
 > Fernando D. Mato Mira wrote:
 > 
 > > Hello,
 > >
 > > What would one need to do to port what is running of SGI/Linux to
 > > Indigo R4400 150MHz Elan?
 > 
 > One would need to write device drivers for:
 > - SCSI
 > - ethernet
 > - display or serial
 > 
 > I thought the indigo used either gio64 or gio32.  I might be wrong.

     The original Indigo (R3000-based) used a different chip set from
the Indigo R4000, Indy, and Indigo2, which shared a common memory controller.
The latter machines use vary a bit in the details of their peripheral
chips, the parts are mostly either the same or different mainly in being
later revisions in some of the systems.  The Indigo2 added EISA bus support
(along with GIO). 

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 11:58:37 1998
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From: "Fernando D. Mato Mira" <matomira@acm.org>
Subject: Re: I am interested in helping port to Indigo
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At 11:28 AM 10/12/98 -0700, you wrote:

> > What would one need to do to port what is running of SGI/Linux to 
> > Indigo R4400 150MHz Elan?
>
>     By "Indigo R4400", I assume you mean "Indigo2 R4400".  As far as

Nope. Indigo "1" R4400 indeed. 

And yes, it's GIO32.




From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 13:49:43 1998
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> Perhaps you can supply us with a hinv output and picture of it, as I
>have never heard of an Indigo with a R4400...

SGI did indeed build these with both 100 and 150 MHz processors.
It was called the IP20.

-- 

Rob Lembree                Strategic Software Organization

Silicon Graphics, Inc.                  http://www.sgi.com
One Cabot Road                             rob@lembree.com
Hudson, MA 01749                           lembree@sgi.com
Phone: 978-567-2141                      FAX: 978-567-2341

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From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 14:14:32 1998
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Rob Lembree writes:
 > > Perhaps you can supply us with a hinv output and picture of it, as I
 > >have never heard of an Indigo with a R4400...
 > 
 > SGI did indeed build these with both 100 and 150 MHz processors.
 > It was called the IP20.
...
      I was familiar with the IP20.  I didn't realize that we had shipped
any 150 MHZ R4400 processors for the IP20.

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 12:38:19 1998
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From: darkaeon <darkaeon@kotetsu.cubicsky.com>
Organization: Inertia Development
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To: linux@cthulhu.engr.sgi.com
Subject: Re: I am interested in helping port to Indigo
References: <199810121822.UAA15293@link.csem.ch>
	 <199810121822.UAA15293@link.csem.ch> <199810121858.UAA15444@link.csem.ch>
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Fernando D. Mato Mira wrote:

> At 11:28 AM 10/12/98 -0700, you wrote:
>
> > > What would one need to do to port what is running of SGI/Linux to
> > > Indigo R4400 150MHz Elan?
> >
> >     By "Indigo R4400", I assume you mean "Indigo2 R4400".  As far as
>
> Nope. Indigo "1" R4400 indeed.
>
> And yes, it's GIO32.

  Perhaps you can supply us with a hinv output and picture of it, as I
have never heard of an Indigo with a R4400...

-Steve



From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 14:31:57 1998
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Subject: Re: I am interested in helping port to Indigo
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		 <199810121822.UAA15293@link.csem.ch> <199810121858.UAA15444@link.csem.ch> <362274D9.7348FD5C@kotetsu.cubicsky.com>
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Here's a hinv from an R4400 Indigo:

CPU: MIPS R4400 Processor Chip Revision: 4.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0
1 100 MHZ IP20 Processor
Main memory size: 48 Mbytes
Secondary unified instruction/data cache size: 1 Mbyte on Processor 0
Instruction cache size: 16 Kbytes
Data cache size: 16 Kbytes
Integral SCSI controller 0: Version WD33C93B, revision C
  Disk drive: unit 1 on SCSI controller 0
  Disk drive: unit 2 on SCSI controller 0
On-board serial ports: 2
On-board bi-directional parallel port
Graphics board: GR2-Elan
Integral Ethernet: ec0, version 1
Iris Audio Processor: revision 10
Galileo video  (ev1): unit 0, revision 2.  601 option connected.  

-- 

Rob Lembree                Strategic Software Organization

Silicon Graphics, Inc.                  http://www.sgi.com
One Cabot Road                             rob@lembree.com
Hudson, MA 01749                           lembree@sgi.com
Phone: 978-567-2141                      FAX: 978-567-2341

PGP: 1F EE F8 58 30 F1 B1 20  C5 4F 12 21 AD 0D 6B 29

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 12 14:37:55 1998
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Subject: Re: I am interested in helping port to Indigo
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			 <199810121822.UAA15293@link.csem.ch> <199810121858.UAA15444@link.csem.ch> <362274D9.7348FD5C@kotetsu.cubicsky.com> <36226B20.B2C5F6FF@sgi.com>
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> 
> > Perhaps you can supply us with a hinv output and picture of it, as I
> >have never heard of an Indigo with a R4400...
> 

[dreamtime:~] hinv
CPU: MIPS R4400 Processor Chip Revision: 5.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0
1 150 MHZ IP20 Processor
Main memory size: 48 Mbytes
Secondary unified instruction/data cache size: 1 Mbyte on Processor 0
Instruction cache size: 16 Kbytes
Data cache size: 16 Kbytes
Integral SCSI controller 0: Version WD33C93B, revision C
  Disk drive: unit 1 on SCSI controller 0
  Disk drive: unit 2 on SCSI controller 0
  Disk drive: unit 3 on SCSI controller 0
On-board serial ports: 2
On-board bi-directional parallel port
Graphics board: GR2-XS24
Integral Ethernet: ec0, version 1
Iris Audio Processor: revision 10

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 13 06:44:32 1998
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Date: Tue, 13 Oct 1998 15:44:13 +0200
To: linux@cthulhu.engr.sgi.com
From: "Fernando D. Mato Mira" <matomira@acm.org>
Subject: Re: I am interested in helping port to Indigo
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<html>
At 02:30 PM 10/12/98 -0700, darkaeon wrote:<br>
<br>
&gt;=A0 Perhaps you can supply us with a hinv output and picture of it, as
I<br>
&gt;have never heard of an Indigo with a R4400...<br>
<br>
<font face=3D"Courier New, Courier">1 150 MHZ IP20 Processor<br>
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0<br>
CPU: MIPS R4400 Processor Chip Revision: 5.0<br>
On-board serial ports: 2<br>
On-board bi-directional parallel port<br>
Data cache size: 16 Kbytes<br>
Instruction cache size: 16 Kbytes<br>
Secondary unified instruction/data cache size: 1 Mbyte on Processor
0<br>
Main memory size: 256 Mbytes<br>
Integral Ethernet: ec0, version 1<br>
Integral SCSI controller 0: Version WD33C93B, revision C<br>
&nbsp; Tape drive: unit 7 on SCSI controller 0: DAT<br>
&nbsp; Tape drive: unit 6 on SCSI controller 0: QIC 150<br>
&nbsp; CDROM: unit 5 on SCSI controller 0<br>
&nbsp; Disk drive: unit 4 on SCSI controller 0<br>
&nbsp; Disk drive: unit 3 on SCSI controller 0<br>
&nbsp;&nbsp;&nbsp; Disk drive / removable media: unit 2 on SCSI
controller 0: 720K/1.44M floppy<br>
&nbsp; Disk drive: unit 1 on SCSI controller 0<br>
Iris Audio Processor: revision 10<br>
Graphics board: GR2-Elan<br>
<br>
<br>
There're a couple of old pictures att
<a href=3D"http://www.vrai.com/" eudora=3D"autourl">www.vrai.com</a>, but ho=
w
could you tell? :-)<br>
<br>
BTW, 6.2 disk is #3. Used to nvram OSLoadPartition to #1, slide 5.3
in<br>
and compile for MIPS ABI 1.0 . I should still get a big disk for 6.5 dual
boot..<br>
<br>
<br>
<br>
<br>
</font>
<BR>

<font face=3D"Courier New, Courier">Fernando D. Mato
Mira=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <br>
Real-Time SW Eng &amp; Networking=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <br>
Advanced Systems Engineering Division<br>
CSEM - Centre Suisse d'Electronique et de
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=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <br>
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=A0=A0=A0 email:=A0 matomira@acm.org<br>
CH-2007 Neuchatel=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0 tel: +41 (32) 720-5157<br>
Switzerland=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
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 eudora=3D"autourl">www.csem.ch</a>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0=A0<a href=3D"http://www.vrai.com/" eudora=3D"autourl">www.vrai.=
com</a>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0
<a href=3D"http://ligwww.epfl.ch/matomira.html" eudora=3D"autourl">http://li=
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From owner-linux@cthulhu.engr.sgi.com  Tue Oct 13 15:34:30 1998
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Date: Tue, 13 Oct 1998 21:59:27 +0200
From: ralf@uni-koblenz.de
To: Vladimir Roganov <roganov@niisi.msk.ru>, linux-mips@fnet.fr,
        linux@cthulhu.engr.sgi.com, linux-mips@vger.rutgers.edu,
        linux-kernel@vger.rutgers.edu
Subject: get_mmu_context()
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Ok, here is a draft version of an agressively optimized version of
get_mmu_context().  I just didn't like the idea of referencing
global variables in get_mmu_context() if avoidable.  The code below
will work on both R3000 and R4000 with no performance penalty for
being generic.  The trick is to patch the operands of two machine
instructions at runtime, shoot me.

The code below should be integrated into <asm/mmu_context.h>.  The
CPU specific code in arch/mips/mm/... will then just have to include
that header file and call r3000_asid_setup rsp. r4xx0_asid_setup.

Have fun,

  Ralf

#define ASID_VERSION_SHIFT 16
#define ASID_VERSION_MASK  ((~0UL) << ASID_VERSION_SHIFT)
#define ASID_FIRST_VERSION (1UL << ASID_VERSION_SHIFT)

unsigned long asid_cache = ASID_FIRST_VERSION;

/* The next two macros know that they will only be assembled once
   per kernel.  */
#define ASID_VERSION_INC					\
 ({ unsigned long __asid_inc;					\
   __asm__(".globl\tasid_inc\n"					\
           "asid_inc:\n\t"					\
           "li\t%0,0\t\t\t#patched\n\t"				\
           :"=r" (__asid_inc));					\
   __asid_inc; })

#define ASID_OVERFLOW(asid)					\
 ({ unsigned long __res;					\
   __asm__(".global\tasid_overflow\n"				\
           "asid_overflow:\n\t"					\
           "sltu\t%0,%1,0\t\t\t#patched\n\t"			\
           :"=r" (__res)					\
           :"r" (asid));					\
   __res; })

extern inline void get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
{
	/* check if it's legal.. */
	if (ASID_OVERFLOW(asid & ~ASID_VERSION_MASK)) {
		/* start a new version, invalidate all old asid's */
		flush_tlb_all();
		asid = (asid & ASID_VERSION_MASK) + ASID_FIRST_VERSION;
		if (!asid)
			asid = ASID_FIRST_VERSION;
	}
	asid_cache = asid + ASID_VERSION_INC;
	mm->context = asid;			 /* full version + asid */
}

extern void get_mmu_context(struct task_struct *p)
{
	struct mm_struct *mm = p->mm;

	if (mm) {
		unsigned long asid = asid_cache;
		/* Check if our ASID is of an older version and thus invalid */
		if ((mm->context ^ asid) & ASID_VERSION_MASK)
			get_new_mmu_context(mm, asid);
	}
}

extern inline void __asid_setup(unsigned long asid_inc, unsigned long asid_cmp)
{
	extern u32 asid_inc;
	extern u32 asid_overflow;

	asid_inc = (asid_inc & 0xffff0000) | asid_inc;
	flush_icache_range(&asid_inc, 4);
	asid_overflow = (asid_overflow & 0xffff0000) | asid_cmp;
	flush_icache_range(&asid_overflow, 4);
}

extern inline void r3000_asid_setup(void)
{
	__asid_setup(0x40, 0xfc1);
}

extern inline void r4xx0_asid_setup(void)
{
	__asid_setup(1, 0x100);
}

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 13 15:36:21 1998
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Date: Tue, 13 Oct 1998 22:00:43 +0200
From: ralf@uni-koblenz.de
To: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: R4000SC ...
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Hi all,

accepting the danger that I'm going to frustrate someone on this list -
I managed to get the R4000SC V3.0 going under Linux in less than two hours.
I'm now typing this email logged on from my Indy running from local disk
to another Linux machine.  The worst part was actually to get rid of all
the MIPS IV code on my machine before I could do anything useful again with
a MIPS III CPU.

The patch which I'm going to commit will actually be quite a bit larger
than the fixes for the SC actually needed to be because large parts of
the support for the SC CPU were overly complex, better-than-nothing
implementations or supporting CPU configurations that aren't possible
at all.  Benefit of all this for everybody is 10kb less kernel code.

Time to fix the "CPU too expensive" panic ;-)

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Wed Oct 14 16:39:26 1998
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Date: Wed, 14 Oct 1998 14:24:43 +0200
From: ralf@uni-koblenz.de
To: tsbogend@alpha.franken.de
Cc: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: Milo & R4000SC
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I've just found yet another SC problem.  Due bugs in a certain ARC firmware
in the FlushAllCaches() function Milo uses it's own cache flushing routine.
Which does not has the feature of flushing R4000 caches 32 times in a row,
it also doesn't correctly deal with R4000 second level caches.  It just
happens to work for the Magnum 4000SCs because they use a unified second
level cache.

Any success in finally getting rid of Milo?

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 15 19:54:43 1998
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Date: Thu, 15 Oct 1998 01:49:55 +0200
From: ralf@uni-koblenz.de
To: Rik van Riel <H.H.vanRiel@phys.uu.nl>
Cc: Vladimir Roganov <roganov@niisi.msk.ru>, linux-mips@fnet.fr,
        linux@cthulhu.engr.sgi.com, linux-mips@vger.rutgers.edu,
        linux-kernel@vger.rutgers.edu
Subject: Re: get_mmu_context()
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On Wed, Oct 14, 1998 at 02:45:45PM +0000, Rik van Riel wrote:

> > Ok, here is a draft version of an agressively optimized version of
> > get_mmu_context().  I just didn't like the idea of referencing
> > global variables in get_mmu_context() if avoidable.  The code below
> > will work on both R3000 and R4000 with no performance penalty for
> > being generic.  The trick is to patch the operands of two machine
> > instructions at runtime, shoot me.
> 
> ROFL! No offense to the code, I'm sure it works, but
> this just _has_ to be the funniest piece of source
> code to appear on the lists this month...
> 
> Self-modifying code -- this is so much fun :)

Lame example of self modifying code, it doesn't even modify the instructions
and only on bootup.

> > extern inline void r3000_asid_setup(void)
> > 
> > extern inline void r4xx0_asid_setup(void)
> 
> Very nice Ralf... My compliments on this piece
> of code -- I can only imagine the amount of
> phantasy and inspiration that was needed to
> create it...

Guess why I had to post it :-)  Seriously, I didn't like the proposed
alternative and some of the older machines which have main memory latencies
like 1400ns for shure win each time when _not_ using memory.  Even in
case of a l1 hit the amount of time wasted for the load should still be
visible in context switching times.  So, no mercy.  Patch as patch can.
And maintenance isn't the issue.  I messed it up, I maintain it :-)

  Ralf

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Date: Thu, 15 Oct 1998 12:56:02 +0200
From: ralf@uni-koblenz.de
To: Ulf Carlsson <grim@zigzegv.ml.org>
Cc: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: Re: R4000SC ...
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On Wed, Oct 14, 1998 at 06:13:31PM +0200, Ulf Carlsson wrote:

> Can you please explain to me what the fixes actually needed for the SC were? I
> am quite interested.

Ok, here we go again.  Attached the patch which I checked in yesterday.
Should tell most easy what I've changed:

 - The VCE exceptions need special handling in the general exception vector.
   In particular it's important that we cannot do any cached loads / stores
   before we've brought caches back to a sane state.  So all the old handlers
   in entry.S and traps.c had to go away.
 - Some of the cache operations defined in r4xx0.c use Hit_*_SD operations to
   work on the caches.  These have the nice property that they will also
   invalidate any primary cache line in both icache and dcache that maps to
   the affected secondary cache line.  In other words code sequences like

       blast_dcache16_page(start);
       if(text)
               blast_icache16_page(start);
       blast_scache16_page(start);

   can simply be replaced by

       blast_scache16_page(start);

   This change does not represent any kind of bug, it's just important
   performance work because cache instructions are expensive even if there
   is no work to do, that is no writebacks or invalidates.  Aside due to the
   massive loop unrolling used in that code we just saved us close to 10kb
   in kernel size.
 - We had code to support a cache configuration with a data cache linesize
   of 32 bytes and second level linesize of 16 bytes.  Configurations where
   the second level linesize is smaller than the primary cache linesize are
   however forbidden, so away with the code.
 - As you remember I disabled the use of the Create_Dirty_Excl_D based
   versions of clear_page and copy_page for R4000 / R4400 SC and MC versions
   as part of the first round of SC fixes.  Now I implemented a set of four
   routines optimized for each possible second level cache linesize.  Right
   now there are only new variants of clear_page; copy_page will come asap.
   I attempted to implement optimized variants using both Create_Dirty_Excl_SD
   and Create_Dirty_Excl_D in clear_page but the resulting kernel crashed
   immediately.  Not shure what the cause is.
 - The untested draft variant of head.S which I mailed to you was not word-
   aligning the address used to index the primary cache tag array.  The
   effect is somewhat hidden, just occasionally programs will die with
   SIGBUS.  No idea why this is necessary.
 - One structure in sgiseeq needed extra padding.  This was not an actual
   SC-bug; the driver would have failed on any machine with cachelines
   larger than 64 bytes.  I increased the number of fill bytes to make the
   driver work with 128 byte linesized caches which is the largest available
   for the IP22.

Somebody asked me why the general exception handler or the VCED / VCEI
exception handlers never crash with a VCE exception resulting in a infinite
loop.  First of all don't do any loads or stores before we've serviced a
VCED / VCEI exception, so we can never catch any VCED exception.  Second,
a VCED / VCEI exception will only occur in case of both a primary and
secondary cache hit where the second level cache virtual index is different
from the actual virtual address' index bits.  In normal live this will
never happen since the exception handlers are only accessed via KSEG0 but
never mapped.  In other words mmaping /dev/mem and just _reading_ the wrong
RAM addresses is a safe way to crash the machine.  Well, you're not supposed
to even try that.

  Ralf

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diff -u linux/arch/mips/kernel/entry.S:1.14 linux/arch/mips/kernel/entry.S:1.15
--- linux/arch/mips/kernel/entry.S:1.14	Tue Sep  8 21:11:46 1998
+++ linux/arch/mips/kernel/entry.S	Wed Oct 14 22:26:26 1998
@@ -152,10 +152,8 @@
 		BUILD_HANDLER(cpu,cpu,sti,silent)		/* #11 */
 		BUILD_HANDLER(ov,ov,sti,silent)			/* #12 */
 		BUILD_HANDLER(tr,tr,sti,silent)			/* #13 */
-		BUILD_HANDLER(vcei,vcei,sti,verbose)		/* #14 */
 		BUILD_HANDLER(fpe,fpe,fpe,silent)		/* #15 */
 		BUILD_HANDLER(watch,watch,sti,verbose)		/* #23 */
-		BUILD_HANDLER(vced,vced,sti,verbose)		/* #31 */
 		BUILD_HANDLER(reserved,reserved,sti,verbose)	/* others */
 
 /*
diff -u linux/arch/mips/kernel/head.S:1.12 linux/arch/mips/kernel/head.S:1.13
--- linux/arch/mips/kernel/head.S:1.12	Tue May 26 08:16:52 1998
+++ linux/arch/mips/kernel/head.S	Wed Oct 14 22:26:27 1998
@@ -19,6 +19,7 @@
 #include <linux/tasks.h>
 
 #include <asm/asm.h>
+#include <asm/cacheops.h>
 #include <asm/current.h>
 #include <asm/offset.h>
 #include <asm/processor.h>
@@ -34,10 +35,10 @@
 	/*
 	 * Reserved space for exception handlers.
 	 * Necessary for machines which link their kernels at KSEG0.
-	 * FIXME: We could overwrite some of the useless handlers
-	 * with those actually being used.
+	 * FIXME: Use the initcode feature to get rid of unused handler
+	 * variants.
 	 */
-	.fill	520
+	.fill	0x280
 /*	
  * This is space for the interrupt handlers.
  * After trap_init() they are located at virtual address KSEG0.
@@ -322,16 +323,48 @@
 	NESTED(except_vec3_r4000, 0, sp)
 	.set	noat
 	mfc0	k1, CP0_CAUSE
-
-	/* XXX Have to check for VCE's _before_ we do a load or store. */
-
-	la	k0, exception_handlers
 	andi	k1, k1, 0x7c
+	li	k0, 31<<2
+	beq	k1, k0, handle_vced
+	 li	k0, 14<<2
+	beq	k1, k0, handle_vcei
+	 la	k0, exception_handlers
 	addu	k0, k0, k1
 	lw	k0, (k0)
 	nop
 	jr	k0
 	 nop
+
+/*
+ * Big shit, we now may have two dirty primary cache lines for the same
+ * physical address.  We can savely invalidate the line pointed to by
+ * c0_badvaddr because after return from this exception handler the load /
+ * store will be re-executed.
+ */
+handle_vced:
+	mfc0	k0, CP0_BADVADDR
+ li k1, -4
+ and k0, k1
+	mtc0	zero, CP0_TAGLO
+ //	nop;nop
+	cache	Index_Store_Tag_D,(k0)
+ //	nop;nop
+	cache	Hit_Writeback_Inv_SD,(k0)
+	lui	k0, %hi(vced_count)
+	lw	k1, %lo(vced_count)(k0)
+	addiu	k1, 1
+	sw	k1, %lo(vced_count)(k0)
+	eret
+
+handle_vcei:
+	mfc0	k0, CP0_BADVADDR
+	cache	Hit_Writeback_Inv_SD,(k0)		# also cleans pi
+	lui	k0, %hi(vcei_count)
+	lw	k1, %lo(vcei_count)(k0)
+	addiu	k1, 1
+	sw	k1, %lo(vcei_count)(k0)
+	eret
+
 	END(except_vec3_r4000)
 	.set	at
 
diff -u linux/arch/mips/kernel/proc.c:1.3 linux/arch/mips/kernel/proc.c:1.4
--- linux/arch/mips/kernel/proc.c:1.3	Thu Oct  2 23:55:16 1997
+++ linux/arch/mips/kernel/proc.c	Wed Oct 14 22:27:49 1998
@@ -12,6 +12,7 @@
 #include <asm/watch.h>
 
 unsigned long unaligned_instructions;
+unsigned int vced_count, vcei_count;
 
 /*
  * BUFFER is PAGE_SIZE bytes long.
@@ -21,6 +22,7 @@
  */
 int get_cpuinfo(char *buffer)
 {
+	char fmt [64];
 	const char *cpu_name[] = CPU_NAMES;
 	const char *mach_group_names[] = GROUP_NAMES;
 	const char *mach_unknown_names[] = GROUP_UNKNOWN_NAMES;
@@ -71,6 +73,11 @@
 	               dedicated_iv_available ? "yes" : "no");
 	len += sprintf(buffer + len, "hardware watchpoint\t: %s\n",
 	               watch_available ? "yes" : "no");
+
+	sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
+	        vce_available ? "%d" : "not available");
+	len += sprintf(buffer + len, fmt, 'D', vced_count);
+	len += sprintf(buffer + len, fmt, 'I', vcei_count);
 
 	return len;
 }
diff -u linux/arch/mips/kernel/traps.c:1.19 linux/arch/mips/kernel/traps.c:1.20
--- linux/arch/mips/kernel/traps.c:1.19	Thu Aug 20 18:33:18 1998
+++ linux/arch/mips/kernel/traps.c	Wed Oct 14 22:26:26 1998
@@ -55,9 +55,7 @@
 extern asmlinkage void handle_cpu(void);
 extern asmlinkage void handle_ov(void);
 extern asmlinkage void handle_tr(void);
-extern asmlinkage void handle_vcei(void);
 extern asmlinkage void handle_fpe(void);
-extern asmlinkage void handle_vced(void);
 extern asmlinkage void handle_watch(void);
 extern asmlinkage void handle_reserved(void);
 
@@ -65,6 +63,7 @@
 
 char watch_available = 0;
 char dedicated_iv_available = 0;
+char vce_available = 0;
 
 void (*ibe_board_handler)(struct pt_regs *regs);
 void (*dbe_board_handler)(struct pt_regs *regs);
@@ -359,24 +358,6 @@
 	force_sig(SIGILL, current);
 }
 
-void do_vcei(struct pt_regs *regs)
-{
-	/*
-	 * Only possible on R4[04]00[SM]C. No handler because I don't have
-	 * such a cpu.  Theory says this exception doesn't happen.
-	 */
-	panic("Caught VCEI exception - should not happen");
-}
-
-void do_vced(struct pt_regs *regs)
-{
-	/*
-	 * Only possible on R4[04]00[SM]C. No handler because I don't have
-	 * such a cpu.  Theory says this exception doesn't happen.
-	 */
-	panic("Caught VCE exception - should not happen");
-}
-
 void do_watch(struct pt_regs *regs)
 {
 	/*
@@ -513,11 +494,8 @@
 	case CPU_R4400MC:
 	case CPU_R4000SC:
 	case CPU_R4400SC:
-		/* XXX The following won't work because we _cannot_
-		 * XXX perform any load/store before the VCE handler.
-		 */
-		set_except_vector(14, handle_vcei);
-		set_except_vector(31, handle_vced);
+		vce_available = 1;
+		/* Fall through ...  */
 	case CPU_R4000PC:
 	case CPU_R4400PC:
 	case CPU_R4200:
@@ -533,13 +511,16 @@
 		else
 			memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
 
-		/*
-		 * The idea is that this special r4000 general exception
-		 * vector will check for VCE exceptions before calling
-		 * out of the exception array.  XXX TODO
-		 */
+		/* Cache error vector  */
 		memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80);
-		memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
+
+		if (vce_available) {
+			memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000,
+			       0x180);
+		} else {
+			memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic,
+			       0x100);
+		}
 
 		save_fp_context = r4k_save_fp_context;
 		restore_fp_context = r4k_restore_fp_context;
diff -u linux/arch/mips/mm/r4xx0.c:1.28 linux/arch/mips/mm/r4xx0.c:1.29
--- linux/arch/mips/mm/r4xx0.c:1.28	Tue Aug 18 22:45:08 1998
+++ linux/arch/mips/mm/r4xx0.c	Wed Oct 14 22:29:59 1998
@@ -41,7 +41,7 @@
 static int ic_lsize, dc_lsize;       /* LineSize in bytes */
 
 /* Secondary cache (if present) parameters. */
-static unsigned long scache_size, sc_lsize;	/* Again, in bytes */
+static unsigned int scache_size, sc_lsize;	/* Again, in bytes */
 
 #include <asm/cacheops.h>
 #include <asm/r4kcache.h>
@@ -78,10 +78,7 @@
  * - a version which handles the buggy R4600 v1.x
  * - a version which handles the buggy R4600 v2.0
  * - Finally a last version without fancy cache games for the SC and MC
- *   versions of R4000 and R4400.  Cache instructions are quite expensive
- *   and I guess using them for both the primary and the second level cache
- *   wouldn't be worth the effort.
- *   This needs to be verified by benchmarking.
+ *   versions of R4000 and R4400.
  */
 
 static void r4k_clear_page_d16(unsigned long page)
@@ -245,14 +242,84 @@
 	restore_flags(flags);
 }
 
-static void r4k_clear_page(unsigned long page)
+/*
+ * The next 4 versions are optimized for all possible scache configurations
+ * of the SC / MC versions of R4000 and R4400 ...
+ *
+ * Todo: For even better performance we should have a routine optimized for
+ * every legal combination of dcache / scache linesize.  When I (Ralf) tried
+ * this the kernel crashed shortly after mounting the root filesystem.  CPU
+ * bug?  Weirdo cache instruction semantics?
+ */
+static void r4k_clear_page_s16(unsigned long page)
+{
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips3\n\t"
+		"daddiu\t$1,%0,%2\n"
+		"1:\tcache\t%3,(%0)\n\t"
+		"sd\t$0,(%0)\n\t"
+		"sd\t$0,8(%0)\n\t"
+		"cache\t%3,16(%0)\n\t"
+		"sd\t$0,16(%0)\n\t"
+		"sd\t$0,24(%0)\n\t"
+		"daddiu\t%0,64\n\t"
+		"cache\t%3,-32(%0)\n\t"
+		"sd\t$0,-32(%0)\n\t"
+		"sd\t$0,-24(%0)\n\t"
+		"cache\t%3,-16(%0)\n\t"
+		"sd\t$0,-16(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sd\t$0,-8(%0)\n\t"
+		".set\tmips0\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (page)
+		:"0" (page),
+		 "I" (PAGE_SIZE),
+		 "i" (Create_Dirty_Excl_SD)
+		:"$1","memory");
+}
+
+static void r4k_clear_page_s32(unsigned long page)
+{
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips3\n\t"
+		"daddiu\t$1,%0,%2\n"
+		"1:\tcache\t%3,(%0)\n\t"
+		"sd\t$0,(%0)\n\t"
+		"sd\t$0,8(%0)\n\t"
+		"sd\t$0,16(%0)\n\t"
+		"sd\t$0,24(%0)\n\t"
+		"daddiu\t%0,64\n\t"
+		"cache\t%3,-32(%0)\n\t"
+		"sd\t$0,-32(%0)\n\t"
+		"sd\t$0,-24(%0)\n\t"
+		"sd\t$0,-16(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sd\t$0,-8(%0)\n\t"
+		".set\tmips0\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (page)
+		:"0" (page),
+		 "I" (PAGE_SIZE),
+		 "i" (Create_Dirty_Excl_SD)
+		:"$1","memory");
+}
+
+static void r4k_clear_page_s64(unsigned long page)
 {
 	__asm__ __volatile__(
 		".set\tnoreorder\n\t"
 		".set\tnoat\n\t"
 		".set\tmips3\n\t"
 		"daddiu\t$1,%0,%2\n"
-		"1:\tsd\t$0,(%0)\n\t"
+		"1:\tcache\t%3,(%0)\n\t"
+		"sd\t$0,(%0)\n\t"
 		"sd\t$0,8(%0)\n\t"
 		"sd\t$0,16(%0)\n\t"
 		"sd\t$0,24(%0)\n\t"
@@ -267,7 +334,44 @@
 		".set\treorder"
 		:"=r" (page)
 		:"0" (page),
-		 "I" (PAGE_SIZE)
+		 "I" (PAGE_SIZE),
+		 "i" (Create_Dirty_Excl_SD)
+		:"$1","memory");
+}
+
+static void r4k_clear_page_s128(unsigned long page)
+{
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips3\n\t"
+		"daddiu\t$1,%0,%2\n"
+		"1:\tcache\t%3,(%0)\n\t"
+		"sd\t$0,(%0)\n\t"
+		"sd\t$0,8(%0)\n\t"
+		"sd\t$0,16(%0)\n\t"
+		"sd\t$0,24(%0)\n\t"
+		"sd\t$0,32(%0)\n\t"
+		"sd\t$0,40(%0)\n\t"
+		"sd\t$0,48(%0)\n\t"
+		"sd\t$0,56(%0)\n\t"
+		"daddiu\t%0,128\n\t"
+		"sd\t$0,-64(%0)\n\t"
+		"sd\t$0,-56(%0)\n\t"
+		"sd\t$0,-48(%0)\n\t"
+		"sd\t$0,-40(%0)\n\t"
+		"sd\t$0,-32(%0)\n\t"
+		"sd\t$0,-24(%0)\n\t"
+		"sd\t$0,-16(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sd\t$0,-8(%0)\n\t"
+		".set\tmips0\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (page)
+		:"0" (page),
+		 "I" (PAGE_SIZE),
+		 "i" (Create_Dirty_Excl_SD)
 		:"$1","memory");
 }
 
@@ -529,7 +633,10 @@
 	restore_flags(flags);
 }
 
-static void r4k_copy_page(unsigned long to, unsigned long from)
+/*
+ * These are for R4000SC / R4400MC
+ */
+static void r4k_copy_page_s16(unsigned long to, unsigned long from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -539,7 +646,8 @@
 		".set\tnoat\n\t"
 		".set\tmips3\n\t"
 		"daddiu\t$1,%0,%8\n"
-		"1:\tlw\t%2,(%1)\n\t"
+		"1:\tcache\t%9,(%0)\n\t"
+		"lw\t%2,(%1)\n\t"
 		"lw\t%3,4(%1)\n\t"
 		"lw\t%4,8(%1)\n\t"
 		"lw\t%5,12(%1)\n\t"
@@ -547,6 +655,7 @@
 		"sw\t%3,4(%0)\n\t"
 		"sw\t%4,8(%0)\n\t"
 		"sw\t%5,12(%0)\n\t"
+		"cache\t%9,16(%0)\n\t"
 		"lw\t%2,16(%1)\n\t"
 		"lw\t%3,20(%1)\n\t"
 		"lw\t%4,24(%1)\n\t"
@@ -555,6 +664,7 @@
 		"sw\t%3,20(%0)\n\t"
 		"sw\t%4,24(%0)\n\t"
 		"sw\t%5,28(%0)\n\t"
+		"cache\t%9,32(%0)\n\t"
 		"daddiu\t%0,64\n\t"
 		"daddiu\t%1,64\n\t"
 		"lw\t%2,-32(%1)\n\t"
@@ -565,6 +675,208 @@
 		"sw\t%3,-28(%0)\n\t"
 		"sw\t%4,-24(%0)\n\t"
 		"sw\t%5,-20(%0)\n\t"
+		"cache\t%9,-16(%0)\n\t"
+		"lw\t%2,-16(%1)\n\t"
+		"lw\t%3,-12(%1)\n\t"
+		"lw\t%4,-8(%1)\n\t"
+		"lw\t%5,-4(%1)\n\t"
+		"sw\t%2,-16(%0)\n\t"
+		"sw\t%3,-12(%0)\n\t"
+		"sw\t%4,-8(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sw\t%5,-4(%0)\n\t"
+		".set\tmips0\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (dummy1), "=r" (dummy2),
+		 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
+		:"0" (to), "1" (from),
+		 "I" (PAGE_SIZE),
+		 "i" (Create_Dirty_Excl_SD));
+}
+
+static void r4k_copy_page_s32(unsigned long to, unsigned long from)
+{
+	unsigned long dummy1, dummy2;
+	unsigned long reg1, reg2, reg3, reg4;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips3\n\t"
+		"daddiu\t$1,%0,%8\n"
+		"1:\tcache\t%9,(%0)\n\t"
+		"lw\t%2,(%1)\n\t"
+		"lw\t%3,4(%1)\n\t"
+		"lw\t%4,8(%1)\n\t"
+		"lw\t%5,12(%1)\n\t"
+		"sw\t%2,(%0)\n\t"
+		"sw\t%3,4(%0)\n\t"
+		"sw\t%4,8(%0)\n\t"
+		"sw\t%5,12(%0)\n\t"
+		"lw\t%2,16(%1)\n\t"
+		"lw\t%3,20(%1)\n\t"
+		"lw\t%4,24(%1)\n\t"
+		"lw\t%5,28(%1)\n\t"
+		"sw\t%2,16(%0)\n\t"
+		"sw\t%3,20(%0)\n\t"
+		"sw\t%4,24(%0)\n\t"
+		"sw\t%5,28(%0)\n\t"
+		"cache\t%9,32(%0)\n\t"
+		"daddiu\t%0,64\n\t"
+		"daddiu\t%1,64\n\t"
+		"lw\t%2,-32(%1)\n\t"
+		"lw\t%3,-28(%1)\n\t"
+		"lw\t%4,-24(%1)\n\t"
+		"lw\t%5,-20(%1)\n\t"
+		"sw\t%2,-32(%0)\n\t"
+		"sw\t%3,-28(%0)\n\t"
+		"sw\t%4,-24(%0)\n\t"
+		"sw\t%5,-20(%0)\n\t"
+		"lw\t%2,-16(%1)\n\t"
+		"lw\t%3,-12(%1)\n\t"
+		"lw\t%4,-8(%1)\n\t"
+		"lw\t%5,-4(%1)\n\t"
+		"sw\t%2,-16(%0)\n\t"
+		"sw\t%3,-12(%0)\n\t"
+		"sw\t%4,-8(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sw\t%5,-4(%0)\n\t"
+		".set\tmips0\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (dummy1), "=r" (dummy2),
+		 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
+		:"0" (to), "1" (from),
+		 "I" (PAGE_SIZE),
+		 "i" (Create_Dirty_Excl_SD));
+}
+
+static void r4k_copy_page_s64(unsigned long to, unsigned long from)
+{
+	unsigned long dummy1, dummy2;
+	unsigned long reg1, reg2, reg3, reg4;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips3\n\t"
+		"daddiu\t$1,%0,%8\n"
+		"1:\tcache\t%9,(%0)\n\t"
+		"lw\t%2,(%1)\n\t"
+		"lw\t%3,4(%1)\n\t"
+		"lw\t%4,8(%1)\n\t"
+		"lw\t%5,12(%1)\n\t"
+		"sw\t%2,(%0)\n\t"
+		"sw\t%3,4(%0)\n\t"
+		"sw\t%4,8(%0)\n\t"
+		"sw\t%5,12(%0)\n\t"
+		"lw\t%2,16(%1)\n\t"
+		"lw\t%3,20(%1)\n\t"
+		"lw\t%4,24(%1)\n\t"
+		"lw\t%5,28(%1)\n\t"
+		"sw\t%2,16(%0)\n\t"
+		"sw\t%3,20(%0)\n\t"
+		"sw\t%4,24(%0)\n\t"
+		"sw\t%5,28(%0)\n\t"
+		"daddiu\t%0,64\n\t"
+		"daddiu\t%1,64\n\t"
+		"lw\t%2,-32(%1)\n\t"
+		"lw\t%3,-28(%1)\n\t"
+		"lw\t%4,-24(%1)\n\t"
+		"lw\t%5,-20(%1)\n\t"
+		"sw\t%2,-32(%0)\n\t"
+		"sw\t%3,-28(%0)\n\t"
+		"sw\t%4,-24(%0)\n\t"
+		"sw\t%5,-20(%0)\n\t"
+		"lw\t%2,-16(%1)\n\t"
+		"lw\t%3,-12(%1)\n\t"
+		"lw\t%4,-8(%1)\n\t"
+		"lw\t%5,-4(%1)\n\t"
+		"sw\t%2,-16(%0)\n\t"
+		"sw\t%3,-12(%0)\n\t"
+		"sw\t%4,-8(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sw\t%5,-4(%0)\n\t"
+		".set\tmips0\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (dummy1), "=r" (dummy2),
+		 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
+		:"0" (to), "1" (from),
+		 "I" (PAGE_SIZE),
+		 "i" (Create_Dirty_Excl_SD));
+}
+
+static void r4k_copy_page_s128(unsigned long to, unsigned long from)
+{
+	unsigned long dummy1, dummy2;
+	unsigned long reg1, reg2, reg3, reg4;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips3\n\t"
+		"daddiu\t$1,%0,%8\n"
+		"1:\tcache\t%9,(%0)\n\t"
+		"lw\t%2,(%1)\n\t"
+		"lw\t%3,4(%1)\n\t"
+		"lw\t%4,8(%1)\n\t"
+		"lw\t%5,12(%1)\n\t"
+		"sw\t%2,(%0)\n\t"
+		"sw\t%3,4(%0)\n\t"
+		"sw\t%4,8(%0)\n\t"
+		"sw\t%5,12(%0)\n\t"
+		"lw\t%2,16(%1)\n\t"
+		"lw\t%3,20(%1)\n\t"
+		"lw\t%4,24(%1)\n\t"
+		"lw\t%5,28(%1)\n\t"
+		"sw\t%2,16(%0)\n\t"
+		"sw\t%3,20(%0)\n\t"
+		"sw\t%4,24(%0)\n\t"
+		"sw\t%5,28(%0)\n\t"
+		"lw\t%2,32(%1)\n\t"
+		"lw\t%3,36(%1)\n\t"
+		"lw\t%4,40(%1)\n\t"
+		"lw\t%5,44(%1)\n\t"
+		"sw\t%2,32(%0)\n\t"
+		"sw\t%3,36(%0)\n\t"
+		"sw\t%4,40(%0)\n\t"
+		"sw\t%5,44(%0)\n\t"
+		"lw\t%2,48(%1)\n\t"
+		"lw\t%3,52(%1)\n\t"
+		"lw\t%4,56(%1)\n\t"
+		"lw\t%5,60(%1)\n\t"
+		"sw\t%2,48(%0)\n\t"
+		"sw\t%3,52(%0)\n\t"
+		"sw\t%4,56(%0)\n\t"
+		"sw\t%5,60(%0)\n\t"
+		"daddiu\t%0,128\n\t"
+		"daddiu\t%1,128\n\t"
+		"lw\t%2,-64(%1)\n\t"
+		"lw\t%3,-60(%1)\n\t"
+		"lw\t%4,-56(%1)\n\t"
+		"lw\t%5,-52(%1)\n\t"
+		"sw\t%2,-64(%0)\n\t"
+		"sw\t%3,-60(%0)\n\t"
+		"sw\t%4,-56(%0)\n\t"
+		"sw\t%5,-52(%0)\n\t"
+		"lw\t%2,-48(%1)\n\t"
+		"lw\t%3,-44(%1)\n\t"
+		"lw\t%4,-40(%1)\n\t"
+		"lw\t%5,-36(%1)\n\t"
+		"sw\t%2,-48(%0)\n\t"
+		"sw\t%3,-44(%0)\n\t"
+		"sw\t%4,-40(%0)\n\t"
+		"sw\t%5,-36(%0)\n\t"
+		"lw\t%2,-32(%1)\n\t"
+		"lw\t%3,-28(%1)\n\t"
+		"lw\t%4,-24(%1)\n\t"
+		"lw\t%5,-20(%1)\n\t"
+		"sw\t%2,-32(%0)\n\t"
+		"sw\t%3,-28(%0)\n\t"
+		"sw\t%4,-24(%0)\n\t"
+		"sw\t%5,-20(%0)\n\t"
 		"lw\t%2,-16(%1)\n\t"
 		"lw\t%3,-12(%1)\n\t"
 		"lw\t%4,-8(%1)\n\t"
@@ -580,9 +892,11 @@
 		:"=r" (dummy1), "=r" (dummy2),
 		 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
 		:"0" (to), "1" (from),
-		 "I" (PAGE_SIZE));
+		 "I" (PAGE_SIZE),
+		 "i" (Create_Dirty_Excl_SD));
 }
 
+
 /*
  * If you think for one second that this stuff coming up is a lot
  * of bulky code eating too many kernel cache lines.  Think _again_.
@@ -632,15 +946,6 @@
 	restore_flags(flags);
 }
 
-static inline void r4k_flush_cache_all_s16d32i32(void)
-{
-	unsigned long flags;
-
-	save_and_cli(flags);
-	blast_dcache32(); blast_icache32(); blast_scache16();
-	restore_flags(flags);
-}
-
 static inline void r4k_flush_cache_all_s32d32i32(void)
 {
 	unsigned long flags;
@@ -718,12 +1023,8 @@
 				pmd = pmd_offset(pgd, start);
 				pte = pte_offset(pmd, start);
 
-				if(pte_val(*pte) & _PAGE_VALID) {
-					blast_dcache16_page(start);
-					if(text)
-						blast_icache16_page(start);
+				if(pte_val(*pte) & _PAGE_VALID)
 					blast_scache16_page(start);
-				}
 				start += PAGE_SIZE;
 			}
 			restore_flags(flags);
@@ -763,12 +1064,8 @@
 				pmd = pmd_offset(pgd, start);
 				pte = pte_offset(pmd, start);
 
-				if(pte_val(*pte) & _PAGE_VALID) {
-					blast_dcache16_page(start);
-					if(text)
-						blast_icache16_page(start);
+				if(pte_val(*pte) & _PAGE_VALID)
 					blast_scache32_page(start);
-				}
 				start += PAGE_SIZE;
 			}
 			restore_flags(flags);
@@ -807,12 +1104,8 @@
 				pmd = pmd_offset(pgd, start);
 				pte = pte_offset(pmd, start);
 
-				if(pte_val(*pte) & _PAGE_VALID) {
-					blast_dcache16_page(start);
-					if(text)
-						blast_icache16_page(start);
+				if(pte_val(*pte) & _PAGE_VALID)
 					blast_scache64_page(start);
-				}
 				start += PAGE_SIZE;
 			}
 			restore_flags(flags);
@@ -851,56 +1144,8 @@
 				pmd = pmd_offset(pgd, start);
 				pte = pte_offset(pmd, start);
 
-				if(pte_val(*pte) & _PAGE_VALID) {
-					blast_dcache16_page(start);
-					if(text)
-						blast_icache16_page(start);
+				if(pte_val(*pte) & _PAGE_VALID)
 					blast_scache128_page(start);
-				}
-				start += PAGE_SIZE;
-			}
-			restore_flags(flags);
-		}
-	}
-}
-
-static void r4k_flush_cache_range_s16d32i32(struct mm_struct *mm,
-					    unsigned long start,
-					    unsigned long end)
-{
-	struct vm_area_struct *vma;
-	unsigned long flags;
-
-	if(mm->context == 0)
-		return;
-
-	start &= PAGE_MASK;
-#ifdef DEBUG_CACHE
-	printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
-#endif
-	vma = find_vma(mm, start);
-	if(vma) {
-		if(mm->context != current->mm->context) {
-			r4k_flush_cache_all_s16d32i32();
-		} else {
-			pgd_t *pgd;
-			pmd_t *pmd;
-			pte_t *pte;
-			int text;
-
-			save_and_cli(flags);
-			text = vma->vm_flags & VM_EXEC;
-			while(start < end) {
-				pgd = pgd_offset(mm, start);
-				pmd = pmd_offset(pgd, start);
-				pte = pte_offset(pmd, start);
-
-				if(pte_val(*pte) & _PAGE_VALID) {
-					blast_dcache32_page(start);
-					if(text)
-						blast_icache32_page(start);
-					blast_scache16_page(start);
-				}
 				start += PAGE_SIZE;
 			}
 			restore_flags(flags);
@@ -939,12 +1184,8 @@
 				pmd = pmd_offset(pgd, start);
 				pte = pte_offset(pmd, start);
 
-				if(pte_val(*pte) & _PAGE_VALID) {
-					blast_dcache32_page(start);
-					if(text)
-						blast_icache32_page(start);
+				if(pte_val(*pte) & _PAGE_VALID)
 					blast_scache32_page(start);
-				}
 				start += PAGE_SIZE;
 			}
 			restore_flags(flags);
@@ -983,12 +1224,8 @@
 				pmd = pmd_offset(pgd, start);
 				pte = pte_offset(pmd, start);
 
-				if(pte_val(*pte) & _PAGE_VALID) {
-					blast_dcache32_page(start);
-					if(text)
-						blast_icache32_page(start);
+				if(pte_val(*pte) & _PAGE_VALID)
 					blast_scache64_page(start);
-				}
 				start += PAGE_SIZE;
 			}
 			restore_flags(flags);
@@ -1027,12 +1264,8 @@
 				pmd = pmd_offset(pgd, start);
 				pte = pte_offset(pmd, start);
 
-				if(pte_val(*pte) & _PAGE_VALID) {
-					blast_dcache32_page(start);
-					if(text)
-						blast_icache32_page(start);
+				if(pte_val(*pte) & _PAGE_VALID)
 					blast_scache128_page(start);
-				}
 				start += PAGE_SIZE;
 			}
 			restore_flags(flags);
@@ -1117,16 +1350,6 @@
 	}
 }
 
-static void r4k_flush_cache_mm_s16d32i32(struct mm_struct *mm)
-{
-	if(mm->context != 0) {
-#ifdef DEBUG_CACHE
-		printk("cmm[%d]", (int)mm->context);
-#endif
-		r4k_flush_cache_all_s16d32i32();
-	}
-}
-
 static void r4k_flush_cache_mm_s32d32i32(struct mm_struct *mm)
 {
 	if(mm->context != 0) {
@@ -1225,12 +1448,8 @@
 		if(text)
 			blast_icache16_page_indexed(page);
 		blast_scache16_page_indexed(page);
-	} else {
-		blast_dcache16_page(page);
-		if(text)
-			blast_icache16_page(page);
+	} else
 		blast_scache16_page(page);
-	}
 out:
 	restore_flags(flags);
 }
@@ -1282,12 +1501,8 @@
 		if(text)
 			blast_icache16_page_indexed(page);
 		blast_scache32_page_indexed(page);
-	} else {
-		blast_dcache16_page(page);
-		if(text)
-			blast_icache16_page(page);
+	} else
 		blast_scache32_page(page);
-	}
 out:
 	restore_flags(flags);
 }
@@ -1340,12 +1555,8 @@
 		if(text)
 			blast_icache16_page_indexed(page);
 		blast_scache64_page_indexed(page);
-	} else {
-		blast_dcache16_page(page);
-		if(text)
-			blast_icache16_page(page);
+	} else
 		blast_scache64_page(page);
-	}
 out:
 	restore_flags(flags);
 }
@@ -1399,70 +1610,8 @@
 		if(text)
 			blast_icache16_page_indexed(page);
 		blast_scache128_page_indexed(page);
-	} else {
-		blast_dcache16_page(page);
-		if(text)
-			blast_icache16_page(page);
+	} else
 		blast_scache128_page(page);
-	}
-out:
-	restore_flags(flags);
-}
-
-static void r4k_flush_cache_page_s16d32i32(struct vm_area_struct *vma,
-					   unsigned long page)
-{
-	struct mm_struct *mm = vma->vm_mm;
-	unsigned long flags;
-	pgd_t *pgdp;
-	pmd_t *pmdp;
-	pte_t *ptep;
-	int text;
-
-	/*
-	 * If ownes no valid ASID yet, cannot possibly have gotten
-	 * this page into the cache.
-	 */
-	if(mm->context == 0)
-		return;
-
-#ifdef DEBUG_CACHE
-	printk("cpage[%d,%08lx]", (int)mm->context, page);
-#endif
-	save_and_cli(flags);
-	page &= PAGE_MASK;
-	pgdp = pgd_offset(mm, page);
-	pmdp = pmd_offset(pgdp, page);
-	ptep = pte_offset(pmdp, page);
-
-	/* If the page isn't marked valid, the page cannot possibly be
-	 * in the cache.
-	 */
-	if(!(pte_val(*ptep) & _PAGE_VALID))
-		goto out;
-
-	text = (vma->vm_flags & VM_EXEC);
-	/*
-	 * Doing flushes for another ASID than the current one is
-	 * too difficult since stupid R4k caches do a TLB translation
-	 * for every cache flush operation.  So we do indexed flushes
-	 * in that case, which doesn't overly flush the cache too much.
-	 */
-	if(mm->context != current->mm->context) {
-		/* Do indexed flush, too much work to get the (possible)
-		 * tlb refills to work correctly.
-		 */
-		page = (KSEG0 + (page & (scache_size - 1)));
-		blast_dcache32_page_indexed(page);
-		if(text)
-			blast_icache32_page_indexed(page);
-		blast_scache16_page_indexed(page);
-	} else {
-		blast_dcache32_page(page);
-		if(text)
-			blast_icache32_page(page);
-		blast_scache16_page(page);
-	}
 out:
 	restore_flags(flags);
 }
@@ -1517,12 +1666,8 @@
 		if(text)
 			blast_icache32_page_indexed(page);
 		blast_scache32_page_indexed(page);
-	} else {
-		blast_dcache32_page(page);
-		if(text)
-			blast_icache32_page(page);
+	} else
 		blast_scache32_page(page);
-	}
 out:
 	restore_flags(flags);
 }
@@ -1577,12 +1722,8 @@
 		if(text)
 			blast_icache32_page_indexed(page);
 		blast_scache64_page_indexed(page);
-	} else {
-		blast_dcache32_page(page);
-		if(text)
-			blast_icache32_page(page);
+	} else
 		blast_scache64_page(page);
-	}
 out:
 	restore_flags(flags);
 }
@@ -1635,12 +1776,8 @@
 		if(text)
 			blast_icache32_page_indexed(page);
 		blast_scache128_page_indexed(page);
-	} else {
-		blast_dcache32_page(page);
-		if(text)
-			blast_icache32_page(page);
+	} else
 		blast_scache128_page(page);
-	}
 out:
 	restore_flags(flags);
 }
@@ -1832,15 +1969,10 @@
 {
 	page &= PAGE_MASK;
 	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
-		unsigned long flags;
-
 #ifdef DEBUG_CACHE
 		printk("cram[%08lx]", page);
 #endif
-		save_and_cli(flags);
-		blast_dcache16_page(page);
 		blast_scache16_page(page);
-		restore_flags(flags);
 	}
 }
 
@@ -1848,15 +1980,10 @@
 {
 	page &= PAGE_MASK;
 	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
-		unsigned long flags;
-
 #ifdef DEBUG_CACHE
 		printk("cram[%08lx]", page);
 #endif
-		save_and_cli(flags);
-		blast_dcache16_page(page);
 		blast_scache32_page(page);
-		restore_flags(flags);
 	}
 }
 
@@ -1864,15 +1991,10 @@
 {
 	page &= PAGE_MASK;
 	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
-		unsigned long flags;
-
 #ifdef DEBUG_CACHE
 		printk("cram[%08lx]", page);
 #endif
-		save_and_cli(flags);
-		blast_dcache16_page(page);
 		blast_scache64_page(page);
-		restore_flags(flags);
 	}
 }
 
@@ -1880,31 +2002,10 @@
 {
 	page &= PAGE_MASK;
 	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
-		unsigned long flags;
-
 #ifdef DEBUG_CACHE
 		printk("cram[%08lx]", page);
 #endif
-		save_and_cli(flags);
-		blast_dcache16_page(page);
 		blast_scache128_page(page);
-		restore_flags(flags);
-	}
-}
-
-static void r4k_flush_page_to_ram_s16d32i32(unsigned long page)
-{
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
-		unsigned long flags;
-
-#ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
-#endif
-		save_and_cli(flags);
-		blast_dcache32_page(page);
-		blast_scache16_page(page);
-		restore_flags(flags);
 	}
 }
 
@@ -1912,15 +2013,10 @@
 {
 	page &= PAGE_MASK;
 	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
-		unsigned long flags;
-
 #ifdef DEBUG_CACHE
 		printk("cram[%08lx]", page);
 #endif
-		save_and_cli(flags);
-		blast_dcache32_page(page);
 		blast_scache32_page(page);
-		restore_flags(flags);
 	}
 }
 
@@ -1928,15 +2024,10 @@
 {
 	page &= PAGE_MASK;
 	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
-		unsigned long flags;
-
 #ifdef DEBUG_CACHE
 		printk("cram[%08lx]", page);
 #endif
-		save_and_cli(flags);
-		blast_dcache32_page(page);
 		blast_scache64_page(page);
-		restore_flags(flags);
 	}
 }
 
@@ -1944,15 +2035,10 @@
 {
 	page &= PAGE_MASK;
 	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
-		unsigned long flags;
-
 #ifdef DEBUG_CACHE
 		printk("cram[%08lx]", page);
 #endif
-		save_and_cli(flags);
-		blast_dcache32_page(page);
 		blast_scache128_page(page);
-		restore_flags(flags);
 	}
 }
 
@@ -2026,20 +2112,10 @@
 r4k_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size)
 {
 	unsigned long end, a;
-	unsigned int flags;
 
 	if (size >= scache_size) {
 		flush_cache_all();
-	} else {
-		save_and_cli(flags);
-		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
-		while (1) {
-			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
-			if (a == end) break;
-			a += dc_lsize;
-		}
-		restore_flags(flags);
+		return;
 	}
 
 	a = addr & ~(sc_lsize - 1);
@@ -2081,20 +2157,10 @@
 r4k_dma_cache_inv_sc(unsigned long addr, unsigned long size)
 {
 	unsigned long end, a;
-	unsigned int flags;
 
 	if (size >= scache_size) {
 		flush_cache_all();
-	} else {
-		save_and_cli(flags);
-		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
-		while (1) {
-			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
-			if (a == end) break;
-			a += dc_lsize;
-		}
-		restore_flags(flags);
+		return;
 	}
 
 	a = addr & ~(sc_lsize - 1);
@@ -2546,8 +2612,8 @@
 	}
 	restore_flags(flags);
 	addr -= begin;
-	printk("Secondary cache sized at %dK linesize %d\n", (int) (addr >> 10),
-	       sc_lsize);
+	printk("Secondary cache sized at %dK linesize %d\n",
+	       (int) (addr >> 10), sc_lsize);
 	scache_size = addr;
 	return 1;
 }
@@ -2602,13 +2668,10 @@
 			flush_page_to_ram = r4k_flush_page_to_ram_s16d16i16;
 			break;
 		case 32:
-			flush_cache_all = r4k_flush_cache_all_s16d32i32;
-			flush_cache_mm = r4k_flush_cache_mm_s16d32i32;
-			flush_cache_range = r4k_flush_cache_range_s16d32i32;
-			flush_cache_page = r4k_flush_cache_page_s16d32i32;
-			flush_page_to_ram = r4k_flush_page_to_ram_s16d32i32;
-			break;
+			panic("Invalid cache configuration detected");
 		};
+		clear_page = r4k_clear_page_s16;
+		copy_page = r4k_copy_page_s16;
 		break;
 	case 32:
 		switch(dc_lsize) {
@@ -2627,6 +2690,9 @@
 			flush_page_to_ram = r4k_flush_page_to_ram_s32d32i32;
 			break;
 		};
+		clear_page = r4k_clear_page_s32;
+		copy_page = r4k_copy_page_s32;
+		break;
 	case 64:
 		switch(dc_lsize) {
 		case 16:
@@ -2644,6 +2710,9 @@
 			flush_page_to_ram = r4k_flush_page_to_ram_s64d32i32;
 			break;
 		};
+		clear_page = r4k_clear_page_s64;
+		copy_page = r4k_copy_page_s64;
+		break;
 	case 128:
 		switch(dc_lsize) {
 		case 16:
@@ -2661,10 +2730,10 @@
 			flush_page_to_ram = r4k_flush_page_to_ram_s128d32i32;
 			break;
 		};
+		clear_page = r4k_clear_page_s128;
+		copy_page = r4k_copy_page_s128;
 		break;
 	}
-	clear_page = r4k_clear_page;
-	copy_page = r4k_copy_page;
 	dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc;
 	dma_cache_inv = r4k_dma_cache_inv_sc;
 }
diff -u linux/drivers/net/sgiseeq.c:1.8 linux/drivers/net/sgiseeq.c:1.9
--- linux/drivers/net/sgiseeq.c:1.8	Wed Aug 19 23:55:06 1998
+++ linux/drivers/net/sgiseeq.c	Wed Oct 14 22:22:48 1998
@@ -86,7 +86,7 @@
 	/* Ptrs to the descriptors in KSEG1 uncached space. */
 	struct sgiseeq_rx_desc *rx_desc;
 	struct sgiseeq_tx_desc *tx_desc;
-	unsigned long _padding[14]; /* Pad out to largest cache line size. */
+	unsigned long _padding[30]; /* Pad out to largest cache line size. */
 
 	struct sgiseeq_rx_desc rxvector[SEEQ_RX_BUFFERS];
 	struct sgiseeq_tx_desc txvector[SEEQ_TX_BUFFERS];
diff -u linux/include/asm-mips/processor.h:1.17 linux/include/asm-mips/processor.h:1.18
--- linux/include/asm-mips/processor.h:1.17	Tue Aug 18 22:46:41 1998
+++ linux/include/asm-mips/processor.h	Wed Oct 14 22:31:12 1998
@@ -30,8 +30,10 @@
 extern char wait_available;		/* only available on R4[26]00 */
 extern char cyclecounter_available;	/* only available from R4000 upwards. */
 extern char dedicated_iv_available;	/* some embedded MIPS like Nevada */
+extern char vce_available;		/* Supports VCED / VCEI exceptions */
 
 extern struct mips_cpuinfo boot_cpu_data;
+extern unsigned int vced_count, vcei_count;
 
 #ifdef __SMP__
 extern struct mips_cpuinfo cpu_data[];

--envbJBWh7q8WU6mo--

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 15 12:09:27 1998
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From: "Kostadis Roussos" <kostadis@sgi.com>
To: <linux@cthulhu.engr.sgi.com>
Subject: Looking for mkfs for IRIX to build ext2 disk
Date: Thu, 15 Oct 1998 12:09:13 -0700
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Hi!

	Sorry for the newbie question, but does there exist a port to IRIX of the
tools to build an ext2 partition?

cheers,
kostadis


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> It does not add performance I can see.

Your code is actually a bit shorter, so I'll mix something based on your
version and my code patching thing.  It must be good, Rik sent me fan
email ;-)

The performance hit will come into the game as soon as one tries to
build a generic kernel for both R3000 and R4000.  The R3000 PID and the
R4000 ASID mechanism are slightly different and the simple approach
to fix that is to use global variables.  Which affects both your version
and the current version.

Which I want to avoid because in worst case that means we'll have to eat
a latency of over 1400ns per cache line to fetch from memory.  This number
is measured on a R4000SC with 100Mhz.  That is enough to show up right
away on the context switch times which now look fairly nice as long as we
don't have to swallow cache faults.

(Let me dig out a cite from somebody ``Some systems seem to think a system
call without a cache miss is a day without sunshine.  :-)'')

Talking about cache faults & context switching times.  Especially on the
R4000 with it's 8kb direct mapped cache _every_ context switch will
result in cache misses which explain the fairly lousy context switch times
on R4000.  R4400 isn't much better.  For the case when we have the perfect
most cache friendly layout we can switch between two processes without
taking page faults.

Things got worse when we switched to 8kb, 8kb aligned, stacks as delivered
by __get_free_pages(1,...).  It's somewhat better on R4600 and R5000 which
have set associative caches but still they could need some optimization.
Also R3000 with it's typically 2 x 64kb per cache direct mapped caches will
looks relativly better in that aspect.

> So, I don't understand why idea of using all free upper bits as asid
> extension is bad  -- same time it increases security it allows to
> increment
> version automatically when asid overflow occurs.

No.  It gives us a view bits more, but way not enough.  The mmu context code
we have has been copied almost unmodified from the Alpha which from EV5 on
also supports ASNs.  The big difference between the Alpha and the MIPS
implementation is that on the Alpha the type ``unsigned long'' which is
used for counting ASN and ASN version number has 64 bit.  Assuming UP and
the worst case which is 2^7 ASNs they still have 2^57 versions before a
version overflow will happen.  In other words, assuming 1,000,000 context
switches per second they still have almost 600,000 years before an ASN
collission may occur.

The MIPS implementation does worse, especially for the R3000 where waste the
lowest 6 bits which effectivly truncates our ASID (or PID) to 26 bits.
Assuming just 100,000 context switches we'll wrap around after just a bit
more than 11 minutes.  I think we can do more than 100,000 context switches
per second on a reasonable R3000 system.

A possible actual solution could be to extend the ASID / PID counter to
64 bit.  This adds some overhead which I'd get rid of if possible at all.
Ideas for that wanted.

Btw, is any of the R3000 machines stable enough to run lmbench?  I'm
interested to get results, best the raw result file from
lmbench/results/mips-linux/.  Reminds me to run lmbench on my RS3230.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 15 13:53:55 1998
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To: linux@cthulhu.engr.sgi.com
Subject: Partial Success Report
From: Jeff Coffin <jcoffin@sv.usweb.com>
Date: 15 Oct 1998 13:50:31 -0700
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Hi All, 

I've been reading this list for the past many months as I slowly and
infrequently try to bring a dead Indy R5000 back to life, then get
Linux up on it.  The box had a dead disk and still has a bad graphics
board, but I've managed to get IRIX installed and operational on one
disk, another one installed and fx'd from IRIX; all from the serial
console (minicom) and remote X on my x86 Linux (RedHat 5.1) box.

I think there's something very wrong with the gfx card 'cause when I
try to start X under IRIX it complains about a failed context switch
and loops with the same error message for a few iterations, then
hangs. (Sorry I don't have the message with me, it's at home.  I can
post tonight it if it's relevant)

Last night I got the HardHat kernel to boot via the bootp method
described in the Howto and, as expected from the experiences of
Richard Hartensveld, it hung looking for a console.  I then grabbed
newer kernels (2.1.116 and 2.1.121) from the /pub/test on the ftp
server and attmepted to get them loaded by the same mechanism, but
both of them hang after loading via tftp.

I don't know where to go from here, so I'm looking for ideas.  Hinv
and the boot log from the hardhat kernel boot are below.

I'm thinking about removing the gfx board entirely and seeing if that
has any effect, will that do me any good?

Any help or suggestions would be appreciated.


--jeff


>> hinv
              System: IP22
           Processor: 180 Mhz R5000, with FPU
Primary I-cache size: 32 Kbytes
Primary D-cache size: 32 Kbytes
Secondary cache size: 512 Kbytes
         Memory size: 64 Mbytes
            Graphics: GR3-XZ
           SCSI Disk: scsi(0)disk(2)
           SCSI Disk: scsi(0)disk(3)
               Audio: Iris Audio Processor: version A2 revision 4.1.0



boot:
Command Monitor.  Type "exit" to return to the menu.
>> $linux
72912+9440+3024+331696+23768d+3644+5808 entry: 0x8bf9a950
Setting $netaddr to 192.168.0.30 (from server lil)
Obtaining /vmlinux from server lil
PROMLIB: SGI ARCS firmware Version 1 Revision 10
PROMLIB: Total free ram 64270336 bytes (62764K,61MB)
ARCH: SGI-IP22
CPU: MIPS-R5000 FPU<MIPS-R5000FPC> ICACHE DCACHE SCACHE
Loading R4000 MMU routines.
CPU revision is: 00002310.
Primary instruction cache 32kb, linesize 32 bytes)
Primary data cache 32kb, linesize 32 bytes)
Linux version 2.1.100 (root@alex3.med.iacnet.com) (gcc version 2.7.2) #29 Thu J8
MC: SGI memory controller Revision 3
R4600/R5000 SCACHE size 512K, linesize 32 bytes.
calculating r4koff... 000dbda6(900518)
zs0: console input
zs0: console I/O
Calibrating delay loop... 179.81 BogoMIPS
Memory: 60444k/196196k available (1216k kernel code, 2684k data)
Swansea University Computer Society NET3.039 for Linux 2.1
NET3: Unix domain sockets 0.16 for Linux NET3.038.
Swansea University Computer Society TCP/IP for NET3.037
IP Protocols: ICMP, UDP, TCP
Checking for 'wait' instruction...  available.
POSIX conformance testing by UNIFIX
Starting kswapd v 1.5
Adv: about to run setup()
initialize_kbd: Keyboard reset failed, no ACK
SGI Zilog8530 serial driver version 1.00
Keyboard timeout
Keyboard timeout
tty00 at 0xbfbd9838 (irq = 21) is a Zilog8530
tty01 at 0xbfbd9830 (irq = 21) is a Zilog8530
Ramdisk driver initialized : 16 ramdisks of 4096K size
loop: registered device at major 7
WD93: Driver version 1.25 compiled on Jul  7 1998 at 16:59:57
 debug_flags=0x00
wd33c93-0: chip=WD33c93B/13 no_sync=0xff no_dma=0scsi0 : SGI WD93
scsi : 1 host.
 sending SDTR 0103013f0csync_xfer=2c  Vendor: SGI       Model: IBM DORS-32160  D
  Type:   Direct-Access                      ANSI SCSI revision: 02
Detected scsi disk sda at scsi0, channel 0, id 2, lun 0
 sending SDTR 0103013f0csync_xfer=2c  Vendor: SEAGATE   Model: ST31055N        2
  Type:   Direct-Access                      ANSI SCSI revision: 02
Detected scsi disk sdb at scsi0, channel 0, id 3, lun 0
scsi : detected 2 SCSI disks total.
SCSI device sda: hdwr sector= 512 bytes. Sectors= 4197405 [2049 MB] [2.0 GB]
SCSI device sdb: hdwr sector= 512 bytes. Sectors= 2069860 [1010 MB] [1.0 GB]
sgiseeq.c: David S. Miller (dm@engr.sgi.com)
eth0: SGI Seeq8003 08:00:69:0a:43:7c
Sending BOOTP requests.... OK
IP-Config: Got BOOTP answer from 192.168.0.20, my address is 192.168.0.30
Partition check:
 sda: sda1 sda2 sda3 sda4
 sdb: sdb1 sdb2 sdb3 sdb4 sdb5 sdb6
Looking up port of RPC 100003/2 on 192.168.0.20
Looking up port of RPC 100005/1 on 192.168.0.20
VFS: Mounted root (nfs filesystem).
Adv: done running setup()
Freeing unused kernel memory: 44k freed
Warning: unable to open an initial console
                                     


From owner-linux@cthulhu.engr.sgi.com  Thu Oct 15 14:16:08 1998
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Date: Thu, 15 Oct 1998 22:59:23 +0200
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: ralf@uni-koblenz.de
Cc: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: Re: Milo & R4000SC
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On Wed, Oct 14, 1998 at 02:24:43PM +0200, ralf@uni-koblenz.de wrote:
> Any success in finally getting rid of Milo?

Milo was already gone, when I posted my questions about tags. My kernel
is also nearly free of tags, only the RM200 code contains some pieces.

Thomas.

-- 
   This device has completely bogus header. Compaq scores again :-|
It's a host bridge, but it should be called ghost bridge instead ;^)
                                        [Martin `MJ' Mares on linux-kernel]

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 15 14:58:03 1998
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Date: Thu, 15 Oct 1998 23:58:47 +0200
From: Ulf Carlsson <grim@zigzegv.ml.org>
To: Kostadis Roussos <kostadis@sgi.com>
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: Looking for mkfs for IRIX to build ext2 disk
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On Thu, Oct 15, 1998 at 12:09:13PM -0700, Kostadis Roussos wrote:
> Hi!
> 
> 	Sorry for the newbie question, but does there exist a port to IRIX of the
> tools to build an ext2 partition?

Yep, they were part of the obsolete installer (by Alan Cox?).

Get /pub/mips-linux/GettingStarted/Linux-installer-0.2.tar.gz.

That package is *really* great and it has actually saved my ass quite a few
times (the possibility to open the ext2 partition and create a /dev/console and
is sometimes still needed, when Alex's hardhat installer is out of its mind).

- Ulf

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 15 15:16:31 1998
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From: Ulf Carlsson <grim@zigzegv.ml.org>
To: Jeff Coffin <jcoffin@sv.usweb.com>, linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
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Hello,

> Last night I got the HardHat kernel to boot via the bootp method
> described in the Howto and, as expected from the experiences of
> Richard Hartensveld, it hung looking for a console.  I then grabbed
> newer kernels (2.1.116 and 2.1.121) from the /pub/test on the ftp
> server and attmepted to get them loaded by the same mechanism, but
> both of them hang after loading via tftp.

It *should* find an initial console if you have mounted the root filesystem from
the hardhat CD correctly. 

You can probably install hardhat on a i386 box in your local network if you
want, and boot directly into an already installed hardhat via nfs-root. That
hardhat default installer is _very_ annoying, it crashes all the time.. (signal
11, out of memory etc..), I don't know if this would solve your problems - but
it helped me... :)
Give the --root <rootdir> option to rpm, and install the needed rpms from the cd

> I don't know where to go from here, so I'm looking for ideas.  Hinv
> and the boot log from the hardhat kernel boot are below.
> 
> I'm thinking about removing the gfx board entirely and seeing if that
> has any effect, will that do me any good?

It would probably not make much difference, "Warning: unable to open an initial
console" isn't caused by a gfx board neither an old kernel, but from an
incorrect /dev/console.

I'm currently running hardhat diskless, I'm only using the IRIX harddrive when
I boot (the bootp command is loaded from the harddrive).

- Ulf

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 15 16:51:23 1998
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To: Ulf Carlsson <grim@zigzegv.ml.org>, linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
References: <m3ww618s88.fsf@lil.sv.usweb.com> <19981016001717.B2072@zigzegv.ml.org>
From: Jeff Coffin <jcoffin@sv.usweb.com>
Date: 15 Oct 1998 16:46:29 -0700
In-Reply-To: Ulf Carlsson's message of Fri, 16 Oct 1998 00:17:17 +0200
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Ulf Carlsson <grim@zigzegv.ml.org> writes:

> It *should* find an initial console if you have mounted the root
> filesystem from the hardhat CD correctly. 

Maybe that's the problem, it all *looks* right.  Is this the case for
the harthat kernel as well as the 2.1.116 and 2.1.121 versions off the
FTP server?

Let's see if I have this straight:

from the PROM, it I do

boot bootp():/vmlinux

and NFS is configured properly (more or less as per the HowTo) on the
i386 box, the kernel will boot and find the NFS root filesystem as
configured in exports or do I need to pass the kernel the nfsroot
param to get it to properly mount the install root?

> It would probably not make much difference, "Warning: unable to open
> an initial console" isn't caused by a gfx board neither an old
> kernel, but from an incorrect /dev/console. 

That's what I thought.  I was speculating that the hardware trouble
was causing the kerel hangs.

> I'm currently running hardhat diskless, I'm only using the IRIX
> harddrive when I boot (the bootp command is loaded from the
> harddrive). 

Not from the PROM?  How does that work?  (I'm new to SGI's and getting
IRIX up at all from just a CD and a new hard drive was a "learning
experience") 

I'll play with it some more tonight or tomorrow when i have the time.

Thanks for the suggestions.


--jeff

From owner-linux@cthulhu.engr.sgi.com  Fri Oct 16 12:46:15 1998
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Message-ID: <19981016214659.A2754@zigzegv.ml.org>
Date: Fri, 16 Oct 1998 21:46:59 +0200
From: Ulf Carlsson <grim@zigzegv.ml.org>
To: Jeff Coffin <jcoffin@sv.usweb.com>, linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
References: <m3ww618s88.fsf@lil.sv.usweb.com> <19981016001717.B2072@zigzegv.ml.org> <m3pvbt8k2y.fsf@lil.sv.usweb.com>
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In-Reply-To: <m3pvbt8k2y.fsf@lil.sv.usweb.com>; from Jeff Coffin on Thu, Oct 15, 1998 at 04:46:29PM -0700
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On Thu, Oct 15, 1998 at 04:46:29PM -0700, Jeff Coffin wrote:

> > It would probably not make much difference, "Warning: unable to open
> > an initial console" isn't caused by a gfx board neither an old
> > kernel, but from an incorrect /dev/console. 
> 
> That's what I thought.  I was speculating that the hardware trouble
> was causing the kerel hangs.

Are we sure that the XZ chipset you have is supported? Get a newport one :)

> > I'm currently running hardhat diskless, I'm only using the IRIX
> > harddrive when I boot (the bootp command is loaded from the
> > harddrive). 
> 
> Not from the PROM?  How does that work?  (I'm new to SGI's and getting
> IRIX up at all from just a CD and a new hard drive was a "learning
> experience") 

I thought the bootp command was loaded from the IRIX partition, because it
didn't work when I removed the IRIX harddrive, atleast it didn't with my old
PROM.  It claimed that it couldn't find the bootp() command - maybe I'm out of
my mind, I'll check next time I remove the cover...

- Ulf

From owner-linux@cthulhu.engr.sgi.com  Fri Oct 16 18:11:36 1998
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Date: Sat, 17 Oct 1998 00:44:08 +0200
From: ralf@uni-koblenz.de
To: Vladimir Roganov <roganov@niisi.msk.ru>, linux-mips@fnet.fr,
        linux@cthulhu.engr.sgi.com, linux-mips@vger.rutgers.edu
Subject: Re: get_mmu_context()
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--mP3DRpeJDSE+ciuQ
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Ok, here is the first working and tested version of my runtime patched
get_mmu_context thing.  While writing the code I noticed that the code
patching stuff is actually already a part of what I was intending to implement
since long time like for example getting rid of function pointers and can
be used to optimize many more things throughout the kernel.  So while some
parts already look somewhat generic I'd like to make them really generic.
The thing is probably going to look somewhat similar to the Sparc btfixup
code which I'm going to read now.

  Ralf

--mP3DRpeJDSE+ciuQ
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename=asid-patch

Index: linux/arch/mips/mm/andes.c
diff -u linux/arch/mips/mm/andes.c:1.5 linux/arch/mips/mm/andes.c:1.6
--- linux/arch/mips/mm/andes.c:1.5	Fri May  1 08:33:13 1998
+++ linux/arch/mips/mm/andes.c	Fri Oct 16 21:22:42 1998
@@ -1,9 +1,8 @@
-/*
+/* $Id: andes.c,v 1.6 1998/10/16 19:22:42 ralf Exp $
+ *
  * andes.c: MMU and cache operations for the R10000 (ANDES).
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- *
- * $Id: andes.c,v 1.5 1998/05/01 06:33:13 ralf Exp $
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -13,6 +12,7 @@
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/sgialib.h>
+#include <asm/mmu_context.h>
 
 extern unsigned long mips_tlb_entries;
 
@@ -104,6 +104,7 @@
 	flush_tlb_mm = andes_flush_tlb_mm;
 	flush_tlb_range = andes_flush_tlb_range;
 	flush_tlb_page = andes_flush_tlb_page;
+	andes_asid_setup();
     
         add_wired_entry = andes_add_wired_entry;
 
Index: linux/arch/mips/mm/fault.c
diff -u linux/arch/mips/mm/fault.c:1.10 linux/arch/mips/mm/fault.c:1.11
--- linux/arch/mips/mm/fault.c:1.10	Thu Sep 17 00:50:44 1998
+++ linux/arch/mips/mm/fault.c	Fri Oct 16 21:22:42 1998
@@ -1,4 +1,4 @@
-/* $Id: fault.c,v 1.10 1998/09/16 22:50:44 ralf Exp $
+/* $Id: fault.c,v 1.11 1998/10/16 19:22:42 ralf Exp $
  *
  *  arch/mips/mm/fault.c
  *
@@ -26,7 +26,7 @@
 
 extern void die(char *, struct pt_regs *, unsigned long write);
 
-unsigned long asid_cache = ASID_FIRST_VERSION;
+unsigned long asid_cache;
 
 /*
  * Macro for exception fixup code to access integer registers.
Index: linux/arch/mips/mm/init.c
diff -u linux/arch/mips/mm/init.c:1.12 linux/arch/mips/mm/init.c:1.13
--- linux/arch/mips/mm/init.c:1.12	Thu Sep 17 00:50:44 1998
+++ linux/arch/mips/mm/init.c	Fri Oct 16 21:22:42 1998
@@ -1,4 +1,4 @@
-/* $Id: init.c,v 1.12 1998/09/16 22:50:44 ralf Exp $
+/* $Id: init.c,v 1.13 1998/10/16 19:22:42 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -33,6 +33,7 @@
 #ifdef CONFIG_SGI
 #include <asm/sgialib.h>
 #endif
+#include <asm/mmu_context.h>
 
 /*
  * Define this to effectivly disable the userpage colouring shit.
@@ -463,4 +464,36 @@
 	val->totalram <<= PAGE_SHIFT;
 	val->sharedram <<= PAGE_SHIFT;
 	return;
+}
+
+/* Fixup an immediate instruction  */
+__initfunc(static void __i_insn_fixup(unsigned int **start, unsigned int **stop,
+                         unsigned int i_const))
+{
+	unsigned int **p, *ip;
+
+	for (p = start;p < stop; p++) {
+		ip = *p;
+		*ip = (*ip & 0xffff0000) | i_const;
+	}
+}
+
+#define i_insn_fixup(section, const)					  \
+do {									  \
+	extern unsigned int *__start_ ## section;			  \
+	extern unsigned int *__stop_ ## section;			  \
+	__i_insn_fixup(&__start_ ## section, &__stop_ ## section, const); \
+} while(0)
+
+/* Caller is assumed to flush the caches before the first context switch.  */
+__initfunc(void __asid_setup(unsigned int inc, unsigned int mask,
+                             unsigned int version_mask,
+                             unsigned int first_version))
+{
+	i_insn_fixup(__asid_inc, inc);
+	i_insn_fixup(__asid_mask, mask);
+	i_insn_fixup(__asid_version_mask, version_mask);
+	i_insn_fixup(__asid_first_version, first_version);
+
+	asid_cache = first_version;
 }
Index: linux/arch/mips/mm/r2300.c
diff -u linux/arch/mips/mm/r2300.c:1.6 linux/arch/mips/mm/r2300.c:1.7
--- linux/arch/mips/mm/r2300.c:1.6	Tue Aug 18 22:45:08 1998
+++ linux/arch/mips/mm/r2300.c	Fri Oct 16 21:22:43 1998
@@ -1,9 +1,8 @@
-/*
+/* $Id: r2300.c,v 1.7 1998/10/16 19:22:43 ralf Exp $
+ *
  * r2300.c: R2000 and R3000 specific mmu/cache code.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- *
- * $Id: r2300.c,v 1.6 1998/08/18 20:45:08 ralf Exp $
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -14,6 +13,7 @@
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/sgialib.h>
+#include <asm/mmu_context.h>
 
 extern unsigned long mips_tlb_entries;
 
@@ -274,6 +274,7 @@
 	flush_tlb_mm = r2300_flush_tlb_mm;
 	flush_tlb_range = r2300_flush_tlb_range;
 	flush_tlb_page = r2300_flush_tlb_page;
+	r3000_asid_setup();
 
 	load_pgd = r2300_load_pgd;
 	pgd_init = r2300_pgd_init;
Index: linux/arch/mips/mm/r4xx0.c
diff -u linux/arch/mips/mm/r4xx0.c:1.29 linux/arch/mips/mm/r4xx0.c:1.30
--- linux/arch/mips/mm/r4xx0.c:1.29	Wed Oct 14 22:29:59 1998
+++ linux/arch/mips/mm/r4xx0.c	Fri Oct 16 21:22:43 1998
@@ -1,4 +1,4 @@
-/* $Id: r4xx0.c,v 1.29 1998/10/14 20:29:59 ralf Exp $
+/* $Id: r4xx0.c,v 1.30 1998/10/16 19:22:43 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -2791,6 +2791,7 @@
 	flush_tlb_mm = r4k_flush_tlb_mm;
 	flush_tlb_range = r4k_flush_tlb_range;
 	flush_tlb_page = r4k_flush_tlb_page;
+	r4xx0_asid_setup();
 
 	load_pgd = r4k_load_pgd;
 	pgd_init = r4k_pgd_init;
Index: linux/arch/mips/mm/r6000.c
diff -u linux/arch/mips/mm/r6000.c:1.5 linux/arch/mips/mm/r6000.c:1.6
--- linux/arch/mips/mm/r6000.c:1.5	Tue Aug 18 22:45:09 1998
+++ linux/arch/mips/mm/r6000.c	Fri Oct 16 21:22:44 1998
@@ -1,4 +1,5 @@
-/* $Id: r6000.c,v 1.5 1998/08/18 20:45:09 ralf Exp $
+/* $Id: r6000.c,v 1.6 1998/10/16 19:22:44 ralf Exp $
+ *
  * r6000.c: MMU and cache routines for the R6000 processors.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
@@ -13,6 +14,7 @@
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/sgialib.h>
+#include <asm/mmu_context.h>
 
 __asm__(".set mips3"); /* because we know... */
 
@@ -180,6 +182,7 @@
 	flush_tlb_mm = r6000_flush_tlb_mm;
 	flush_tlb_range = r6000_flush_tlb_range;
 	flush_tlb_page = r6000_flush_tlb_page;
+	r6000_asid_setup();
 
 	load_pgd = r6000_load_pgd;
 	pgd_init = r6000_pgd_init;
Index: linux/arch/mips/mm/tfp.c
diff -u linux/arch/mips/mm/tfp.c:1.5 linux/arch/mips/mm/tfp.c:1.6
--- linux/arch/mips/mm/tfp.c:1.5	Fri May  1 08:31:34 1998
+++ linux/arch/mips/mm/tfp.c	Fri Oct 16 21:22:44 1998
@@ -1,4 +1,5 @@
-/*
+/* $Id: tfp.c,v 1.6 1998/10/16 19:22:44 ralf Exp $
+ *
  * tfp.c: MMU and cache routines specific to the r8000 (TFP).
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
@@ -13,6 +14,7 @@
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/sgialib.h>
+#include <asm/mmu_context.h>
 
 extern unsigned long mips_tlb_entries;
 
@@ -104,6 +106,7 @@
 	flush_tlb_mm = tfp_flush_tlb_mm;
 	flush_tlb_range = tfp_flush_tlb_range;
 	flush_tlb_page = tfp_flush_tlb_page;
+	tfp_asid_setup();
 
         add_wired_entry = tfp_add_wired_entry;
 
Index: linux/include/asm-mips/mmu_context.h
diff -u linux/include/asm-mips/mmu_context.h:1.2 linux/include/asm-mips/mmu_context.h:1.3
--- linux/include/asm-mips/mmu_context.h:1.2	Tue May  5 12:22:01 1998
+++ linux/include/asm-mips/mmu_context.h	Fri Oct 16 21:22:54 1998
@@ -1,4 +1,4 @@
-/* $Id: mmu_context.h,v 1.2 1998/05/05 10:22:01 ralf Exp $
+/* $Id: mmu_context.h,v 1.3 1998/10/16 19:22:54 ralf Exp $
  *
  * Switch a MMU context.
  *
@@ -11,29 +11,61 @@
 #ifndef __ASM_MIPS_MMU_CONTEXT_H
 #define __ASM_MIPS_MMU_CONTEXT_H
 
-#define MAX_ASID 255
-
+/* Fuck.  The f-word is here so you can grep for it :-)  */
 extern unsigned long asid_cache;
 
-#define ASID_VERSION_SHIFT 16
-#define ASID_VERSION_MASK  ((~0UL) << ASID_VERSION_SHIFT)
-#define ASID_FIRST_VERSION (1UL << ASID_VERSION_SHIFT)
-
-extern inline void get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
-{
-	/* check if it's legal.. */
-	if ((asid & ~ASID_VERSION_MASK) > MAX_ASID) {
-		/* start a new version, invalidate all old asid's */
-		flush_tlb_all();
-		asid = (asid & ASID_VERSION_MASK) + ASID_FIRST_VERSION;
-		if (!asid)
+/* I patch, therefore I am ...  */
+#define ASID_INC(asid)						\
+ ({ unsigned long __asid = asid;				\
+   __asm__("1:\taddiu\t%0,0\t\t\t\t# patched\n\t"		\
+           ".section\t__asid_inc,\"a\"\n\t"			\
+           ".word\t1b\n\t"					\
+           ".previous"						\
+           :"=r" (__asid)					\
+           :"0" (__asid));					\
+   __asid; })
+#define ASID_MASK(asid)						\
+ ({ unsigned long __asid = asid;				\
+   __asm__("1:\tandi\t%0,%1,0\t\t\t# patched\n\t"			\
+           ".section\t__asid_mask,\"a\"\n\t"			\
+           ".word\t1b\n\t"					\
+           ".previous"						\
+           :"=r" (__asid)					\
+           :"r" (__asid));					\
+   __asid; })
+#define ASID_VERSION_MASK					\
+ ({ unsigned long __asid;					\
+   __asm__("1:\tli\t%0,0\t\t\t\t# patched\n\t"			\
+           ".section\t__asid_version_mask,\"a\"\n\t"		\
+           ".word\t1b\n\t"					\
+           ".previous"						\
+           :"=r" (__asid));					\
+   __asid; })
+#define ASID_FIRST_VERSION					\
+ ({ unsigned long __asid = asid;				\
+   __asm__("1:\tli\t%0,0\t\t\t\t# patched\n\t"			\
+           ".section\t__asid_first_version,\"a\"\n\t"		\
+           ".word\t1b\n\t"					\
+           ".previous"						\
+           :"=r" (__asid));					\
+   __asid; })
+
+#define ASID_FIRST_VERSION_R3000 0x1000
+#define ASID_FIRST_VERSION_R4000 0x100
+
+extern inline void
+get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
+{
+	if (!ASID_MASK((asid = ASID_INC(asid)))) {
+		flush_tlb_all(); /* start new asid cycle */
+		if (!asid)      /* fix version if needed */
 			asid = ASID_FIRST_VERSION;
 	}
-	asid_cache = asid + 1;
-	mm->context = asid;			 /* full version + asid */
+	mm->context = asid_cache = asid;
 }
 
-extern inline void get_mmu_context(struct task_struct *p)
+extern inline void
+get_mmu_context(struct task_struct *p)
 {
 	struct mm_struct *mm = p->mm;
 
@@ -72,5 +104,31 @@
 	get_mmu_context(tsk);
 	set_entryhi(tsk->mm->context);
 }
+
+extern void __asid_setup(unsigned int inc, unsigned int mask,
+                         unsigned int version_mask, unsigned int first_version);
+
+extern inline void r3000_asid_setup(void)
+{
+	__asid_setup(0x40, 0xfc0, 0xf000, ASID_FIRST_VERSION_R3000);
+}
+
+extern inline void r6000_asid_setup(void)
+{
+	panic("r6000_asid_setup: implement me");	/* No idea ...  */
+}
+
+extern inline void tfp_asid_setup(void)
+{
+	panic("tfp_asid_setup: implement me");	/* No idea ...  */
+}
+
+extern inline void r4xx0_asid_setup(void)
+{
+	__asid_setup(1, 0xff, 0xff00, ASID_FIRST_VERSION_R4000);
+}
+
+/* R10000 has the same ASID mechanism as the R4000.  */
+#define andes_asid_setup r4xx0_asid_setup
 
 #endif /* __ASM_MIPS_MMU_CONTEXT_H */

--mP3DRpeJDSE+ciuQ--

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Date: Fri, 16 Oct 1998 21:15:22 -0400 (EDT)
From: Jeremy John Welling <jwelling@engin.umich.edu>
To: linux@cthulhu.engr.sgi.com
Subject: XZ
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Are XZ graphics supported? 



From owner-linux@cthulhu.engr.sgi.com  Sat Oct 17 16:57:25 1998
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Date: Sat, 17 Oct 1998 04:01:48 +0200
From: ralf@uni-koblenz.de
To: Ulf Carlsson <grim@zigzegv.ml.org>, Jeff Coffin <jcoffin@sv.usweb.com>,
        linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
References: <m3ww618s88.fsf@lil.sv.usweb.com> <19981016001717.B2072@zigzegv.ml.org> <m3pvbt8k2y.fsf@lil.sv.usweb.com> <19981016214659.A2754@zigzegv.ml.org>
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On Fri, Oct 16, 1998 at 09:46:59PM +0200, Ulf Carlsson wrote:

> I thought the bootp command was loaded from the IRIX partition, because it
> didn't work when I removed the IRIX harddrive, atleast it didn't with my old
> PROM.  It claimed that it couldn't find the bootp() command - maybe I'm out of
> my mind, I'll check next time I remove the cover...

bootp() is just a ARC filename which is either interpreted by the PROM
command interpreter or by sash where sash afaik is nothing other than the
PROMs compiled with special flags.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sat Oct 17 02:35:23 1998
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Date: Sat, 17 Oct 1998 11:16:45 +0200
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Jeff Coffin <jcoffin@sv.usweb.com>, linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
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On Thu, Oct 15, 1998 at 01:50:31PM -0700, Jeff Coffin wrote:
> Last night I got the HardHat kernel to boot via the bootp method
> described in the Howto and, as expected from the experiences of
> Richard Hartensveld, it hung looking for a console.

Could you please lookup major and minor number of /dev/console on
your root filesystem ? It should be major 5 and minor 2 to work
properly with the serial console.

>  I then grabbed
> newer kernels (2.1.116 and 2.1.121) from the /pub/test on the ftp
> server and attmepted to get them loaded by the same mechanism, but
> both of them hang after loading via tftp.

please try to boot these kernels with bootp()/vmlinux console=ttyS0 (also
try ttyS1) and a terminal hooked up to one of the serial ports (in .116
ttyS0 is port 2 and ttyS1 is port 1; I've changed that in .121, but I'm not
sure if this fix is already in the precompiled kernel). It's possible, 
that I've messed up the card detection so, that it panics, when there is 
no newport installed.

Thomas.

-- 
   This device has completely bogus header. Compaq scores again :-|
It's a host bridge, but it should be called ghost bridge instead ;^)
                                        [Martin `MJ' Mares on linux-kernel]

From owner-linux@cthulhu.engr.sgi.com  Sat Oct 17 02:35:23 1998
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Date: Sat, 17 Oct 1998 11:17:25 +0200
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Jeremy John Welling <jwelling@engin.umich.edu>, linux@cthulhu.engr.sgi.com
Subject: Re: XZ
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On Fri, Oct 16, 1998 at 09:15:22PM -0400, Jeremy John Welling wrote:
> Are XZ graphics supported? 

If XZ isn't another name for newport, then no.

Thomas.

-- 
   This device has completely bogus header. Compaq scores again :-|
It's a host bridge, but it should be called ghost bridge instead ;^)
                                        [Martin `MJ' Mares on linux-kernel]

From owner-linux@cthulhu.engr.sgi.com  Sat Oct 17 17:01:07 1998
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Date: Sun, 18 Oct 1998 01:56:24 +0200
From: ralf@uni-koblenz.de
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Jeremy John Welling <jwelling@engin.umich.edu>,
        linux@cthulhu.engr.sgi.com
Subject: Re: XZ
References: <19981016214659.A2754@zigzegv.ml.org> <Pine.SOL.4.02.9810162113360.7062-100000@azure.engin.umich.edu> <19981017111725.D1121@alpha.franken.de>
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On Sat, Oct 17, 1998 at 11:17:25AM +0200, Thomas Bogendoerfer wrote:

> If XZ isn't another name for newport, then no.

XL is the official name for the Newport.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sat Oct 17 17:09:02 1998
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Date: Sun, 18 Oct 1998 02:09:54 +0200
From: Ulf Carlsson <grim@zigzegv.ml.org>
To: ralf@uni-koblenz.de, Jeff Coffin <jcoffin@sv.usweb.com>,
        linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
References: <m3ww618s88.fsf@lil.sv.usweb.com> <19981016001717.B2072@zigzegv.ml.org> <m3pvbt8k2y.fsf@lil.sv.usweb.com> <19981016214659.A2754@zigzegv.ml.org> <19981017040148.C4768@uni-koblenz.de>
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On Sat, Oct 17, 1998 at 04:01:48AM +0200, ralf@uni-koblenz.de wrote:
> On Fri, Oct 16, 1998 at 09:46:59PM +0200, Ulf Carlsson wrote:
> 
> bootp() is just a ARC filename which is either interpreted by the PROM
> command interpreter or by sash where sash afaik is nothing other than the
> PROMs compiled with special flags.

The command 'boot bootp():' requires a harddrive, but I can run 'bootp():'
diskless. Does the 'boot' part of the command tell the PROM to use sash?

- Ulf

From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 16:14:07 1998
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Date: Sun, 18 Oct 1998 11:52:28 +0200
From: ralf@uni-koblenz.de
To: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: lmbench results for RISC/os
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Hi,

if anybody has results of a preferably current lmbench running on a Magnum
4000 and/or Magnum 4000SC under RISC/os then I'd appreciate a copy of the
raw result file.  The comparison of Linux with RISC/os maybe unfair now
that RISC/os is dead for a couple of years but it's still the official
UNIX for these machines, so ...

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 07:57:37 1998
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Message-ID: <19981018165826.A15078@zigzegv.ml.org>
Date: Sun, 18 Oct 1998 16:58:26 +0200
From: Ulf Carlsson <grim@zigzegv.ml.org>
To: btoscano@shell.monmouth.com
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Subject: 2.1.121 with R4[04]00SC support
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Hi,

For Brian Toscano and everyone else who can't compile their own kernels, I've
compiled a kernel with Ralf's SC fixes (the latest CVS tree) for your needs.
It's available at ftp://ballyhoo.ml.org/sgi-linux/linux-2.1.121.tar.gz.

It has BOOTP, NFS-Root and all the stuff you'll need to install Hardhat.

Have fun!

- Ulf

From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 10:33:10 1998
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Subject: Re: XZ
In-Reply-To: <19981018015624.H4768@uni-koblenz.de> from "ralf@uni-koblenz.de" at "Oct 18, 98 01:56:24 am"
To: ralf@uni-koblenz.de
Date: Sun, 18 Oct 1998 10:32:26 -0700 (PDT)
Cc: tsbogend@alpha.franken.de, jwelling@engin.umich.edu,
        linux@cthulhu.engr.sgi.com
From: kyriazis@sgi.com (George Kyriazis)
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In a previous episode, ralf@uni-koblenz.de claimed:
> On Sat, Oct 17, 1998 at 11:17:25AM +0200, Thomas Bogendoerfer wrote:
> 
> > If XZ isn't another name for newport, then no.
> 
> XL is the official name for the Newport.
> 
I am not familiar with what Linux exactly is ported on, but my guess would be
only Newport.

XZ is a non-Newport based card for Indy.  XZ has more-or-less the same
internal architecture as Elan/Extreme, so it's probably a safe bet that
is it not supported.

  --george
-- 
-----------------------------------------------------------------------------
George Kyriazis  | Silicon Graphics, Inc., 8U-590 |  kyriazis@sgi.com
                 | 2011 N. Shoreline Blvd.        |  650-933-2828
                 | Mt. View, CA 94043             | 

From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 12:53:03 1998
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On 16-Oct-98 Gleb O. Rajko wrote:

> On Thu, 15 Oct 1998 ralf@uni-koblenz.de wrote:
> 
>> 
>> The performance hit will come into the game as soon as one tries to
>> build a generic kernel for both R3000 and R4000.  The R3000 PID and the
>> R4000 ASID mechanism are slightly different and the simple approach
>> to fix that is to use global variables.  Which affects both your version
>> and the current version.
> We are going to provide support for building generic kernels in the near 
> future if somebody who holds r4k will help us and will try our patches 
> on a r4k box. I think the best time to start is when r3k will be synced 
> with the main branch. Perhaps, Harald may answer when it might occur.

Hmmm, I'm not shure about this. If we really want to support generic kernels,
that'll shurely needs some more work than a little patching in get_mmu_context.
Remember, Vladimir, we needed to make changes in extremely performance critical
parts of the kernel which Ralf propably won't like to have for the R4000 case. Most
of them are actually compiled conditionally.

To make those changes generic needs either a reasonable amount of hacking or
avoidable code duplication. In fact, if we really don't care about self modifying
code we should be able to remove some code duplication, for example in the fpu
stuff.

I'd personally prefer to have a few things sorted out before I check the R3000 stuff
in. What's common opinion on this?

---
Regards,
Harald

From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 16:18:02 1998
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Date: Mon, 19 Oct 1998 01:10:43 +0200
From: ralf@uni-koblenz.de
To: kyriazis@sgi.com
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: XZ
References: <19981018015624.H4768@uni-koblenz.de> <199810181732.KAA51624@jibe.engr.sgi.com>
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On Sun, Oct 18, 1998 at 10:32:26AM -0700, George Kyriazis wrote:

> In a previous episode, ralf@uni-koblenz.de claimed:
> > On Sat, Oct 17, 1998 at 11:17:25AM +0200, Thomas Bogendoerfer wrote:
> > 
> > > If XZ isn't another name for newport, then no.
> > 
> > XL is the official name for the Newport.
> > 
> I am not familiar with what Linux exactly is ported on, but my guess would be
> only Newport.
> 
> XZ is a non-Newport based card for Indy.  XZ has more-or-less the same
> internal architecture as Elan/Extreme, so it's probably a safe bet that
> is it not supported.

Correct.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 17:14:41 1998
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To: ralf@uni-koblenz.de
Cc: Ulf Carlsson <grim@zigzegv.ml.org>, Jeff Coffin <jcoffin@sv.usweb.com>,
        linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
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	<19981016001717.B2072@zigzegv.ml.org>
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ralf@uni-koblenz.de writes:
 > On Fri, Oct 16, 1998 at 09:46:59PM +0200, Ulf Carlsson wrote:
 > 
 > > I thought the bootp command was loaded from the IRIX partition, because it
 > > didn't work when I removed the IRIX harddrive, atleast it didn't with my old
 > > PROM.  It claimed that it couldn't find the bootp() command - maybe I'm out of
 > > my mind, I'll check next time I remove the cover...
 > 
 > bootp() is just a ARC filename which is either interpreted by the PROM
 > command interpreter or by sash where sash afaik is nothing other than the
 > PROMs compiled with special flags.

       That is, bootp() is part of a path.  There is no bootp command.

       sash, unlike most PROMs, has one or more (read-only) disk file
systems bound into it.  On Indy, older sash versions can read efs volumes,
and newer ones can also read xfs volumes.


From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 17:15:28 1998
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: ralf@uni-koblenz.de
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Jeremy John Welling <jwelling@engin.umich.edu>,
        linux@cthulhu.engr.sgi.com
Subject: Re: XZ
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ralf@uni-koblenz.de writes:
 > On Sat, Oct 17, 1998 at 11:17:25AM +0200, Thomas Bogendoerfer wrote:
 > 
 > > If XZ isn't another name for newport, then no.
 > 
 > XL is the official name for the Newport.

    XZ is one of the variants of the Elan/Extreme series of cards,
which have one or more geometry engines on the card.  The geometry
engines need microcode downloaded for full functionality, and the
interfaces are not externally documented, so it is hard to build
linux support without access to the IRIX source for reference.

From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 17:16:32 1998
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From: "William J. Earl" <wje@fir.engr.sgi.com>
To: Ulf Carlsson <grim@zigzegv.ml.org>
Cc: ralf@uni-koblenz.de, Jeff Coffin <jcoffin@sv.usweb.com>,
        linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
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	<19981016001717.B2072@zigzegv.ml.org>
	<m3pvbt8k2y.fsf@lil.sv.usweb.com>
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Ulf Carlsson writes:
 > On Sat, Oct 17, 1998 at 04:01:48AM +0200, ralf@uni-koblenz.de wrote:
 > > On Fri, Oct 16, 1998 at 09:46:59PM +0200, Ulf Carlsson wrote:
 > > 
 > > bootp() is just a ARC filename which is either interpreted by the PROM
 > > command interpreter or by sash where sash afaik is nothing other than the
 > > PROMs compiled with special flags.
 > 
 > The command 'boot bootp():' requires a harddrive, but I can run 'bootp():'
 > diskless. Does the 'boot' part of the command tell the PROM to use sash?

      Try

	boot -f bootp():

This avoids trying to load sash.

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 19 17:55:14 1998
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Date: Mon, 19 Oct 1998 03:29:46 +0200
From: ralf@uni-koblenz.de
To: "Gleb O. Rajko" <rajko@mech.math.msu.su>, linux-mips@fnet.fr
Cc: Vladimir Roganov <roganov@niisi.msk.ru>, linux@cthulhu.engr.sgi.com
Subject: Re: get_mmu_context()
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On Fri, Oct 16, 1998 at 07:04:48PM +0400, Gleb O. Rajko wrote:

> We are going to provide support for building generic kernels in the near 
> future if somebody who holds r4k will help us and will try our patches 
> on a r4k box. I think the best time to start is when r3k will be synced 
> with the main branch. Perhaps, Harald may answer when it might occur.

If you are in doubt about any R4k related changes feel free to send them
to me.

> > Which I want to avoid because in worst case that means we'll have to eat
> > a latency of over 1400ns per cache line to fetch from memory.  This number
> > is measured on a R4000SC with 100Mhz.  That is enough to show up right
> > away on the context switch times which now look fairly nice as long as we
> > don't have to swallow cache faults.
> > 
> Perhaps, we may use global vars in most cases and patch code at bootup 
> for critical ones.

Yes.  We can actually do even more in that direction like for example
eleminating calls via pointers as used throughout the mm.  We insert jal
instructions and patch the address as needed.  Or we even overwrite the
call by nops if the routine is emtpy.

> > The MIPS implementation does worse, especially for the R3000 where waste the
> > lowest 6 bits which effectivly truncates our ASID (or PID) to 26 bits.
> > Assuming just 100,000 context switches we'll wrap around after just a bit
> > more than 11 minutes.  I think we can do more than 100,000 context switches
> > per second on a reasonable R3000 system.

> As I understand the only place where change the version is in 
> get_new_mmu_context(). Thus, if the version overflows we may create a new 
> process which will share its address space with other due to the same 
> ASID and varsion pair. Am I right ?  

Correct.

> > Btw, is any of the R3000 machines stable enough to run lmbench?  I'm
> > interested to get results, best the raw result file from
> > lmbench/results/mips-linux/.  Reminds me to run lmbench on my RS3230.

> Ok. I will try to run lmbench while Vladimir will think about your ideas :-)

:-)

Btw, lmbench has in the past helped me to kill several interesting bugs.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Sun Oct 18 23:44:53 1998
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Date: Mon, 19 Oct 1998 08:44:45 +0200
To: linux@cthulhu.engr.sgi.com
From: "Fernando D. Mato Mira" <matomira@acm.org>
Subject: Re: XZ
In-Reply-To: <199810190015.RAA15185@fir.engr.sgi.com>
References: <19981018015624.H4768@uni-koblenz.de>
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At 05:15 PM 10/18/98 -0700, you wrote:
>    XZ is one of the variants of the Elan/Extreme series of cards,
>which have one or more geometry engines on the card.  The geometry
>engines need microcode downloaded for full functionality, and the
>interfaces are not externally documented, so it is hard to build
>linux support without access to the IRIX source for reference.

What about just getting the console running (no X server)?
How do GR2 (Indigo Elan) and GR3 (Indigo II Elan) differ in terms of
programming?



Fernando D. Mato Mira                    
Real-Time SW Eng & Networking            
Advanced Systems Engineering Division
CSEM - Centre Suisse d'Electronique et de
Microtechnique                                 
Jaquet-Droz 1                         email:  matomira@acm.org
CH-2007 Neuchatel                       tel: +41 (32) 720-5157
Switzerland                             FAX: +41 (32) 720-5720

<http://www.csemne.ch/>www.csem.ch                  <http://www.vrai.com/>w
ww.vrai.com              
<http://ligwww.epfl.ch/matomira.html>http://ligwww.epfl.ch/matomira.html  

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 19 17:55:14 1998
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Date: Mon, 19 Oct 1998 12:18:04 +0200
From: ralf@uni-koblenz.de
To: Harald Koerfgen <harald.koerfgen@netcologne.de>, linux-mips@fnet.fr
Cc: linux@cthulhu.engr.sgi.com, Vladimir Roganov <roganov@niisi.msk.ru>
Subject: Re: get_mmu_context()
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On Sun, Oct 18, 1998 at 09:53:18PM +0200, Harald Koerfgen wrote:

> > We are going to provide support for building generic kernels in the near 
> > future if somebody who holds r4k will help us and will try our patches 
> > on a r4k box. I think the best time to start is when r3k will be synced 
> > with the main branch. Perhaps, Harald may answer when it might occur.
> 
> Hmmm, I'm not shure about this. If we really want to support generic kernels,
> that'll shurely needs some more work than a little patching in

There is a number of machines, most popular some DECstation, which are
available with both CPU architectures.

> get_mmu_context.  Remember, Vladimir, we needed to make changes in extremely
> performance critical parts of the kernel which Ralf propably won't like to
> have for the R4000 case. Most of them are actually compiled conditionally.

The other location for which patching might be useful are primarily the
differences between the R3000 and R4000 status register, especially the
KU rsp. KSU bits.  What other places do you have in mind?

> To make those changes generic needs either a reasonable amount of hacking or
> avoidable code duplication. In fact, if we really don't care about self
> modifying code we should be able to remove some code duplication, for
> example in the fpu stuff.

People should consider that we'll be able to hide the self modifications
in C code very nicely.  I would not go for anything which I consider a
maintenance problem or major uglyness.

Let me explain how the approach from my recent patch works:

#define ASID_INC(asid)                                         \
 ({ unsigned long __asid = asid;                               \
   __asm__("1:\taddiu\t%0,0\t\t\t\t# patched\n\t"              \
           ".section\t__asid_inc,\"a\"\n\t"                    \
           ".word\t1b\n\t"                                     \
           ".previous"                                         \
           :"=r" (__asid)                                      \
           :"0" (__asid));                                     \
   __asid; })

This macro will be used in a place where the C compiler is known to produce
an addiu instruction.  The trick is now that we collect the instruction's
address in a special section, __asid_inc in that case.  As a special
service the GNU linker will generate the symbols __start_<name> and
__stop_<name> if the section name <name> is a valid C symbol name.  So
after boot we can easily insert the right operands into the instruction:

/* Fixup an immediate instruction  */
static void __i_insn_fixup(unsigned int **start, unsigned int **stop,
                           unsigned int i_const)
{
       unsigned int **p, *ip;

       for (p = start;p < stop; p++) {
               ip = *p;
               *ip = (*ip & 0xffff0000) | i_const;
       }
}

#define i_insn_fixup(section, const)                                     \
do {                                                                     \
       extern unsigned int *__start_ ## section;                         \
       extern unsigned int *__stop_ ## section;                          \
       __i_insn_fixup(&__start_ ## section, &__stop_ ## section, const); \
} while(0)

void __asid_setup(unsigned int inc, unsigned int mask,
                             unsigned int version_mask,
                             unsigned int first_version)
{
       i_insn_fixup(__asid_inc, inc);
[...]

The technique itself can be used in quite a number more of places.  All
variables which are computed at boot time and never again changed later on
are good candidates.  Think for example of the variables dcache_size,
icache_size, scache_size, dcache_lsize, icache_lsize, scache_lsize.

Todo: we don't want a separate section per patched instruction.  Easy to
fix.  We also want to get rid of the special section just like other
initfunc stuff.

The next class of things to patch are the zillion of function calls using
function pointers.  We can insert a jal instruction and patch it's
destination address.  Candidates for that include calls to flush_cache_all,
flush_cache_mm, flush_cache_range, flush_cache_page, flush_cache_sigtramp,
flush_tlb_all, flush_tlb_mm, flush_tlb_range, flush_tlb_page, add_wired_entry,
clear_page, copy_page.

Both parts, patching immediate opperands and function calls can be dealt
with similar to the approach in the userland dynamic linker, that initially
the function called is the dynamic linker's kernel equivalent which will
choose the right thing to do.

Extra goodie for the R3000 fraction: Many functions called via above
mentioned pointers are empty, calls to them may be eleminated by overwriting
the calling jal with nops.  Say goodbye to another hand full of cycles.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 19 12:54:32 1998
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Subject: Re: XZ
In-Reply-To: <199810190644.IAA17078@link.csem.ch> from "Fernando D. Mato Mira" at "Oct 19, 98 08:44:45 am"
To: matomira@acm.org (Fernando D. Mato Mira)
Date: Mon, 19 Oct 1998 12:53:40 -0700 (PDT)
Cc: linux@cthulhu.engr.sgi.com
From: kyriazis@sgi.com (George Kyriazis)
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In a previous episode, Fernando D. Mato Mira claimed:
> At 05:15 PM 10/18/98 -0700, you wrote:
> >    XZ is one of the variants of the Elan/Extreme series of cards,
> >which have one or more geometry engines on the card.  The geometry
> >engines need microcode downloaded for full functionality, and the
> >interfaces are not externally documented, so it is hard to build
> >linux support without access to the IRIX source for reference.
> 
> What about just getting the console running (no X server)?
> How do GR2 (Indigo Elan) and GR3 (Indigo II Elan) differ in terms of
> programming?
> 
I did some asking around.  Here's what I found:

* In order to do anything, you have to download microcode.

* The monitor PROM downloads a mini-microcode that could be used.  I am
  not sure what the entry points look like to the PROM.  I think this
  is the safest bet.

* The full-functioning microcode (that does 3d) is downloaded at boot
  time before the X server initializes.
 
* The people that I asked are not clear about the programming differences
  between GR2 and GR3.  Certainly they are the same for OpenGL-level
  programming.  My guess is that there are differences in the CPU interfacing
  and video back end.  User-level code is the same, but kernel initialization
  and management code may be different.

* Getting things up and running on a GR-type (Express) architecture is 
  definetely more difficult than Newport.

* Documentation will be hard to find.  Documentation for programming the
  microcoded engines, even harder.  You could, of course, use the existing
  microcode.

  --george
-- 
-----------------------------------------------------------------------------
George Kyriazis  | Silicon Graphics, Inc., 8U-590 |  kyriazis@sgi.com
                 | 2011 N. Shoreline Blvd.        |  650-933-2828
                 | Mt. View, CA 94043             | 

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 20 09:02:20 1998
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Date: Tue, 20 Oct 1998 03:41:38 +0200
From: ralf@uni-koblenz.de
To: kyriazis@sgi.com, "Fernando D. Mato Mira" <matomira@acm.org>
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: XZ
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On Mon, Oct 19, 1998 at 12:53:40PM -0700, George Kyriazis wrote:

> * The monitor PROM downloads a mini-microcode that could be used.  I am
>   not sure what the entry points look like to the PROM.  I think this
>   is the safest bet.

> * Documentation will be hard to find.  Documentation for programming the
>   microcoded engines, even harder.  You could, of course, use the existing
>   microcode.

For now that looks like the best strategy.  Anyway, as step one all we
want is text output.  This can be achived by using the ARC firmware.
That may be slow, but it's working and it gives us an instant driver for
any number of console devices people might have come up with in the past.
The Sparc guys, btw already have a prom console driver.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 19 21:08:04 1998
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To: ralf@uni-koblenz.de
Subject: Re: get_mmu_context() 
Cc: linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com
In-reply-to: Your message of "Mon, 19 Oct 1998 12:18:04 +0200."
		<19981019121804.F387@uni-koblenz.de> 
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Date: Mon, 19 Oct 1998 22:07:26 -0600
From: Warner Losh <imp@village.org>
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Wouldn't it be easier to have ld to have variant fixup records?  That
way you could patch all instances at run time, much like we do when we
load stuff now...

You are basically duplicating the functionality of the linker here for
no good reason.  Actually, besides the non-standard aspect of it,
there is a good reason: it is easier to hack like this than to do
battle with the bfd and/or boot blocks to get this to happen. :-)

It is a way cool hack, don't get me wrong, but it just seems that it
would be more useful to be generic like that.

Warner

From owner-linux@cthulhu.engr.sgi.com  Mon Oct 19 21:22:06 1998
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From: ariel@oz.engr.sgi.com (Ariel Faigon)
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Subject: Re: get_mmu_context()
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Forwarding message from David, his email probably changed
so it bounced...

----- Forwarded message from owner-linux@cthulhu -----

From: "David S. Miller" <davem@dm.cobaltmicro.com>
To: imp@village.org
CC: ralf@uni-koblenz.de, linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com
In-reply-to: <199810200407.WAA03233@harmony.village.org> (message from Warner
	Losh on Mon, 19 Oct 1998 22:07:26 -0600)
Subject: Re: get_mmu_context()
References: <19981019121804.F387@uni-koblenz.de>  <Pine.SV4.3.91.981016185136.876A-100000@mech.math.msu.su> <XFMail.981018215318.harald.koerfgen@netcologne.de> <199810200407.WAA03233@harmony.village.org>

   Date: Mon, 19 Oct 1998 22:07:26 -0600
   From: Warner Losh <imp@village.org>

   Wouldn't it be easier to have ld to have variant fixup records?
   That way you could patch all instances at run time, much like we do
   when we load stuff now...

See sparc32's btfixup in the kernel sources for the best
implementation I've ever seen.

Later,
David S. Miller
davem@dm.cobaltmicro.com

----- End of forwarded message from owner-linux@cthulhu -----

-- 
Peace, Ariel

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 20 15:39:08 1998
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Date: Tue, 20 Oct 1998 19:31:16 +0200
From: ralf@uni-koblenz.de
To: Warner Losh <imp@village.org>
Cc: linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com
Subject: Re: get_mmu_context()
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On Mon, Oct 19, 1998 at 10:07:26PM -0600, Warner Losh wrote:

> Wouldn't it be easier to have ld to have variant fixup records?  That
> way you could patch all instances at run time, much like we do when we
> load stuff now...
> 
> You are basically duplicating the functionality of the linker here for
> no good reason.  Actually, besides the non-standard aspect of it,
> there is a good reason: it is easier to hack like this than to do
> battle with the bfd and/or boot blocks to get this to happen. :-)
> 
> It is a way cool hack, don't get me wrong, but it just seems that it
> would be more useful to be generic like that.

Neither compiler, assembler nor linker can solve the problem for us
because it requires knowledge of facts which we usually don't know before
running on the target machine.  On the other side as soon as we run on
the machine we know these details.  They're constants, so why not making
optimal use of them?

As alternative to achieve the same level of efficience imagine the
following configuration dialogue:

#
# Cache configuration
#
Does your machine have a second level cache (CONFIG_L2_CACHE) [N/y] y
  Is your CPU an Indy R4600SC or R5000SC (CONFIG_L2_INDY) [N/y]
  l2 linesize (16, 32, 64, 128) [128]
  Split Scache (CONFIG_L2_SPLIT) [N/y] 
  Do your VCE exceptions work (CONFIG_R4000SC_V2) [N/y]
Primary instruction cache linesize (16, 32) [16]
Primary data cache linesize (16, 32) [16]

Oh, there is more fun we'd need to ask for like DRAM controller versions
for Magnums etc.  Cool vomit bag, isn't it ;-)

Things look different for fixed configuration systems like for example
the Cobalt Qube.  But we have to deal with zillion of system variants.

You're right in that things should become more generic and I have ideas
to make them more generic.  For the moment being I don't want to continue
on that since 2.2 is coming soon and more important things are still to do.
That's should however be an interesting 2.3 project.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 20 16:37:46 1998
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To: ralf@uni-koblenz.de
Subject: Re: get_mmu_context() 
Cc: linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com
In-reply-to: Your message of "Tue, 20 Oct 1998 19:31:16 +0200."
		<19981020193116.C478@uni-koblenz.de> 
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Date: Tue, 20 Oct 1998 17:36:53 -0600
From: Warner Losh <imp@village.org>
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In message <19981020193116.C478@uni-koblenz.de> ralf@uni-koblenz.de writes:
: running on the target machine.  On the other side as soon as we run on
: the machine we know these details.  They're constants, so why not making
: optimal use of them?

I'm confused then...

: You're right in that things should become more generic and I have ideas
: to make them more generic.  For the moment being I don't want to continue
: on that since 2.2 is coming soon and more important things are still to do.
: That's should however be an interesting 2.3 project.

Yes.  Basically something has load the kernel, and that something
could do the fixups.  Basically it would be a relocation record with a
"tag" on it that said what systems to do it on.

However, I do see your point that when you want to have the varients
based on cache size, memory controller, cache line size, etc it gets
really ugly....

It would be a cool project, however...

Warner

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 20 18:32:21 1998
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Date: Wed, 21 Oct 1998 01:50:47 +0200
From: ralf@uni-koblenz.de
To: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: Haifa scheduler bug in egcs 1.0.2
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Hi all,

I've resolved a bug report of Ulf Carlson whose kernel compiles resulted
died with:

gcc -D__KERNEL__ -I/home/ulfc/kernels/sgi-lin/linux/include -Wall \
-Wstrict-prototypes -O2 -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic \
-mcpu=r4600 -mips2 -pipe    arch/mips/mm/r6000.c   -o arch/mips/mm/r6000

{standard input}: Assembler messages:
{standard input}:385: Warning: Unmatched %hi reloc
{standard input}:488: Internal error!
Assertion failure in tc_gen_reloc at ./config/tc-mips.c line 10203.
Please report this bug.
make: *** [arch/mips/mm/r6000] Error 1

This is caused by bad assembler code like:

[...]
        lui     $11,%hi(r6000_flush_cache_mm) # high
        lui     $12,%hi(r6000_flush_cache_range) # high
        lui     $17,%hi(r6000_flush_tlb_all) # high
        lui     $2,%hi(r6000_flush_tlb_mm) # high
        lui     $3,%hi(r6000_flush_tlb_range) # high
        lui     $4,%hi(r6000_flush_tlb_page) # high
        lui     $5,%hi(r6000_load_pgd) # high
        lui     $6,%hi(r6000_pgd_init) # high
        lui     $7,%hi(r6000_update_mmu_cache) # high
        lui     $8,%hi(r6000_show_regs) # high
        lui     $9,%hi(r6000_add_wired_entry) # high
        lui     $10,%hi(r6000_user_mode) # high
[...]

Relocating the code generated from this source later on will not be
possible for ld.  As knows this and dies ungracefully.

I was able to track this down to the Haifa scheduler which seems to be
incompatible with the -msplit-addresses used for kernel compiles.  For
now I suggest to recompile egcs without the Haifa scheduler.  Egcs by
default doesn't enable the Haifa scheduler and there is a reason why.

This egcs 1.0.2 bug is a platform independent bug.  Since currently
egcs does not support -msplit-addresses for PIC code, that is all userland
this bug will only hit some low level stuff.

Alex or somebody else, could you make an update to the egcs package
with the haifa scheduler disabled?  Thanks!

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Wed Oct 21 12:31:27 1998
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From: Harald Koerfgen <harald.koerfgen@netcologne.de>
To: linux-mips@fnet.fr
Subject: Re: get_mmu_context()
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On 19-Oct-98 ralf@uni-koblenz.de wrote:
> On Sun, Oct 18, 1998 at 09:53:18PM +0200, Harald Koerfgen wrote:

[...]
> There is a number of machines, most popular some DECstation, which are
> available with both CPU architectures.

Yup.
 
> The other location for which patching might be useful are primarily the
> differences between the R3000 and R4000 status register, especially the
> KU rsp. KSU bits.  What other places do you have in mind?

Agreed. There are indeed other places where code could be reintegrated,
r2300_switch.S and r4k_switch.S come to mind.

On the other hand, there is code which should be seperated for performance reasons,
mainly the RESTORE_ALL macros thus affecting entry.S and scall_o32.S. Actually these
problems are solved by conditional compiling.
 
>> To make those changes generic needs either a reasonable amount of hacking or
>> avoidable code duplication. In fact, if we really don't care about self
>> modifying code we should be able to remove some code duplication, for
>> example in the fpu stuff.
> 
> People should consider that we'll be able to hide the self modifications
> in C code very nicely.  I would not go for anything which I consider a
> maintenance problem or major uglyness.

Good.
 
> Let me explain how the approach from my recent patch works:

[explanation snipped]
 
> Todo: we don't want a separate section per patched instruction.  Easy to
> fix.  We also want to get rid of the special section just like other
> initfunc stuff.

That sounds great. We could even put all ISA dependant code into seperate
sections and get rid of all the ISA sections, which aren't needed.
 
> The next class of things to patch are the zillion of function calls using
> function pointers.  We can insert a jal instruction and patch it's
> destination address.  Candidates for that include calls to flush_cache_all,
> flush_cache_mm, flush_cache_range, flush_cache_page, flush_cache_sigtramp,
> flush_tlb_all, flush_tlb_mm, flush_tlb_range, flush_tlb_page, add_wired_entry,
> clear_page, copy_page.
> 
> Both parts, patching immediate opperands and function calls can be dealt
> with similar to the approach in the userland dynamic linker, that initially
> the function called is the dynamic linker's kernel equivalent which will
> choose the right thing to do.
> 
> Extra goodie for the R3000 fraction: Many functions called via above
> mentioned pointers are empty, calls to them may be eleminated by overwriting
> the calling jal with nops.  Say goodbye to another hand full of cycles.

That sounds even better :-).
---
Regards,
Harald

From owner-linux@cthulhu.engr.sgi.com  Wed Oct 21 17:47:39 1998
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Date: Thu, 22 Oct 1998 02:44:08 +0200
From: ralf@uni-koblenz.de
To: "David S. Miller" <davem@dm.cobaltmicro.com>
Cc: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
Subject: Re: Haifa scheduler bug in egcs 1.0.2
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On Tue, Oct 20, 1998 at 06:39:21PM -0700, David S. Miller wrote:

>    Relocating the code generated from this source later on will not be
>    possible for ld.  As knows this and dies ungracefully.
> 
> Then why is this a supposed bug in Haifa?  It looks to me there is a
> problem with how %hi relocs are assosciated with %lo ones in binutils.

It's not necessarily a bug in Haida itself but it gets visible when Haifa
is enabled.  I haven't looked closely at the involved egcs code yet.

> The code you showed me looks perfectly legal.

For ECOFF and ELF, relocations against symbols are done in two parts, with
a hi16 relocation and a lo16 relocation.  Each relocation has only 16 bits of
space to store an addend and a carry may have to be propagated between
the two.  This means that in order for the linker to handle carries
correctly, it must be able to locate both the hi16 and the lo16 relocation.
Object files which don't contain any other information except the order in
the relocation table which could be used to find the hi16 / lo16 relocs which
belong together.

The code I showed cannot be represented in a ELF or ECOFF object such that
the linker still knows which hi16 and which lo16 relocations are associated
with each other.  Therefore it is not possible for the linker to correctly
do the hi16 relocations.  Btw, all MIPS assemblers I know of will warn or
even error about that fragment.

The ABI is quite strict in that aspect, it wants one lo16 per hi16 for the
same symbol.  Binutils relax that by allowing an arbitrary number of hi16
and one lo16 for the same symbol.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Wed Oct 21 17:56:50 1998
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To: linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
From: Jeff Coffin <jcoffin@sv.usweb.com>
Date: 21 Oct 1998 17:56:11 -0700
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Fogot to CC the list on this....

Thomas Bogendoerfer <tsbogend@alpha.franken.de> writes:

> Could you please lookup major and minor number of /dev/console on
> your root filesystem ? It should be major 5 and minor 2 to work
> properly with the serial console.

I fixed it, do I need to change systty too perhps?:

[root@lil dev]# ls -l
total 0
crw-------   1 root     disk       5,   2 Oct 21 13:25 console
crw-------   1 root     disk       4,   0 May 11 08:48 console.dist
crw-rw-r--   1 root     root       1,   3 May 11 08:48 null
brw-r-----   1 root     disk       1,   1 May 11 08:48 ram
crw-------   1 root     disk       4,   0 May 11 08:48 systty
crw-------   1 root     root       4,   1 May 11 08:48 tty1
crw-------   1 root     root       4,   2 May 11 08:48 tty2
crw-------   1 root     root       4,   3 May 11 08:48 tty3
crw-------   1 root     root       4,   4 May 11 08:48 tty4
crw-------   1 root     root       4,   5 May 11 08:48 tty5

> please try to boot these kernels with bootp()/vmlinux console=ttyS0 (also
> try ttyS1) and a terminal hooked up to one of the serial ports (in .116
> ttyS0 is port 2 and ttyS1 is port 1; I've changed that in .121, but I'm not
> sure if this fix is already in the precompiled kernel). It's possible, 
> that I've messed up the card detection so, that it panics, when there is 
> no newport installed.

Nope, didn't work.  The 116 kernel makes the power light blink red to
green ad infinitum and the 121 version appears to load, but the
console is elsewhere.  I'm using port 1 for the serial connection
(it's setup thusly in the PROM)

The default kernel still boots OK and appears to mount the nfsroot:

Looking up port of RPC 100003/2 on 192.168.0.20
Looking up port of RPC 100005/1 on 192.168.0.20
VFS: Mounted root (nfs filesystem).
Adv: done running setup() 

but then nothing....                                                     

BTW, I'm doing the whole thing from a serial console (minicom).  The
gfx card doesn't work from IRIX either.  One of these days I'll
replace it, but it's not real high on my list of things to buy for
$200+.


--jeff


From owner-linux@cthulhu.engr.sgi.com  Wed Oct 21 23:26:36 1998
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From: ariel@oz.engr.sgi.com (Ariel Faigon)
Message-Id: <199810220626.XAA32028@oz.engr.sgi.com>
Subject: (fwd) was bug in haifa scheduler (or not)
To: linux@cthulhu.engr.sgi.com (SGI/Linux mailing list)
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[just forwarding a bounce]

From: "David S. Miller" <davem@dm.cobaltmicro.com>
To: ralf@uni-koblenz.de
CC: linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu
In-reply-to: <19981022024408.A360@uni-koblenz.de> (ralf@uni-koblenz.de)
Subject: Re: Haifa scheduler bug in egcs 1.0.2
References: <19981021015047.G1830@uni-koblenz.de> <199810210139.SAA22458@dm.cobaltmicro.com> <19981022024408.A360@uni-koblenz.de>

   Date: Thu, 22 Oct 1998 02:44:08 +0200
   From: ralf@uni-koblenz.de

   The ABI is quite strict in that aspect, it wants one lo16 per hi16
   for the same symbol.  Binutils relax that by allowing an arbitrary
   number of hi16 and one lo16 for the same symbol.

I completely understand how hi16/lo16 relocations work on MIPS, but
thanks for reiterating it to me once more.

All you have shown me is a bug in the MIPS ABI, one of thousands.

Therefore, there is no reason binutils cannot handle this sanely, and
be fixed to do so.

Later,
David S. Miller
davem@dm.cobaltmicro.com

----- End of forwarded message from owner-linux@cthulhu -----

-- 
Peace, Ariel

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 22 12:13:11 1998
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Date: Thu, 22 Oct 1998 21:06:18 +0200
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Jeff Coffin <jcoffin@sv.usweb.com>, linux@cthulhu.engr.sgi.com
Subject: Re: Partial Success Report
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On Wed, Oct 21, 1998 at 05:56:11PM -0700, Jeff Coffin wrote:
> > Could you please lookup major and minor number of /dev/console on
> > your root filesystem ? It should be major 5 and minor 2 to work
> > properly with the serial console.
> 
> I fixed it, do I need to change systty too perhps?:

no, but I've got major and minor wrong. It's major 5 and minor 1.

Thomas.

-- 
   This device has completely bogus header. Compaq scores again :-|
It's a host bridge, but it should be called ghost bridge instead ;^)
                                        [Martin `MJ' Mares on linux-kernel]

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 27 07:36:19 1998
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Date: Tue, 27 Oct 1998 05:47:54 +0100
From: ralf@uni-koblenz.de
To: Warner Losh <imp@village.org>
Cc: linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com
Subject: Re: MIPS R3230?
References: <199810262335.QAA12729@harmony.village.org>
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On Mon, Oct 26, 1998 at 04:35:05PM -0700, Warner Losh wrote:

> I've seen lots of traffic about people asking for various MIPS
> systems.  Today, I saved a R3230 from an ignoble fate in a
> dumpster...  It is running RISC/OS 4.52B (or was that 4.50B) and has
> the source to all the driver on the disk....  I also have the boot
> tapes and 3' of documentation.
> 
> Has anybody actually tried to get Linux working on this machine?

I have a RS3230 clone running a RISC/os 4.52 variant and a VME variant
of that machine based on a R4700, also running RISC/os on my desk to
which I'm currently porting Linux.

  Ralf

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Date: Tue, 27 Oct 1998 05:54:34 +0100
From: ralf@uni-koblenz.de
To: Eric Jorgensen <alhaz@xmission.com>, linux-mips@fnet.fr,
        linux-mips@vger.rutgers.edu, linux@cthulhu.engr.sgi.com
Subject: Re: MIPS R3230?
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On Mon, Oct 26, 1998 at 05:03:00PM -0700, Eric Jorgensen wrote:

> 	On the other hand, I don't have a complete distribution of RISCos on
> either of them. They both mounted most of the /usr tree (or whatever it
> is on riscos) via NFS, some machine they can't talk to anymore. 

Linux and related software have become a tomb stone for several old network
stacks and apps which crash, lockup or do other funnies.

The bad things is that these old MIPS machines need to boot from network
via a MIPS proprietary protocol named BFS of which no implementation is
floating around anymore.  Except David Monroe's implementation, that is.
If anybody still got his bfsd 1.01 source archive around, please drop me
a note.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 27 07:36:09 1998
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Date: Tue, 27 Oct 1998 05:57:31 +0100
From: ralf@uni-koblenz.de
To: Mitchell Blank Jr <mitch@execpc.com>, linux-mips@fnet.fr,
        linux@cthulhu.engr.sgi.com
Subject: Re: R5000 Unused memory (was: R4000SC...)
References: <19981017104618.A3076@zigzegv.ml.org> <19981018111145.J4768@uni-koblenz.de> <19981019111501.A16024@zigzegv.ml.org> <1998102010305 <19981020103052.G676@uni-koblenz.de> <19981021134544.A30452@zigzegv.ml.org> <19981021233814.A3030@alpha.franken.de> <19981022090933.A879@bun.falkenberg.se> <362F69B5.AB94E713@xmission.com> <19981022194442.27891@execpc.com>
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On Thu, Oct 22, 1998 at 07:44:42PM -0500, Mitchell Blank Jr wrote:

> Eric Jorgensen wrote:
> > 	Yes and no. Personally I find the concept of running a modern system
> > without available swap somewhat perilous.
> 
> What about if you don't have any disk nor any rw filesystems?  Not unusual
> in imbedded applications.  The only way to get around it now apparently is
> to set up a ram disk and swap to that -- hardly effecient or useful
> (except in the case where some RAM is slower).
> 
> A typical UNIX workstation or server should always have swap -- there are
> always some gettys or something that might as well be swapped out to make
> room for more disk cache.  There are applications, however, where swap
> is just not an option.

Linux cannot swap to NFS, so that behaviour in absence is pretty much a
showstopper for diskless apps.

  Ralf

From owner-linux@cthulhu.engr.sgi.com  Tue Oct 27 15:57:49 1998
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Date: Wed, 28 Oct 1998 00:59:01 +0100
From: Ulf Carlsson <ulfc@bun.falkenberg.se>
To: ralf@uni-koblenz.de
Cc: linux@cthulhu.engr.sgi.com
Subject: HAL2 interrupt
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Hi,

I mailed you a few days ago, maybe that mail got dropped somewhere or maybe you
were to busy too read, anyhow ..

Now I'm asking again, do you know which interrupt number I should request for
the PBUS DMA:s. I can't handle the interrupts correctly without the knowledge of
interrupt numbers, and I'm afraid the spec didn't tell me anything about this
(atleast not the ones I've read). Also, is everything else I need for dealing
these interrupts ok (I haven't been able to check)? Maybe I could setup some
bogus irq detection stuff to figure this out on my own, but to save some bogus
programming I'm asking you instead.

It would be nice if you even explained *how* you know..

I think I'm pretty much done with a simple playback/recording driver now, still
untested though (probably +1000 serious bugs and race conditions, but I'll fix
that..).

Thanks,
Ulf

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 29 00:10:07 1998
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Date: Wed, 28 Oct 1998 23:26:52 +0100
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Ulf Carlsson <ulfc@bun.falkenberg.se>, ralf@uni-koblenz.de
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: HAL2 interrupt
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On Wed, Oct 28, 1998 at 12:59:01AM +0100, Ulf Carlsson wrote:
> Now I'm asking again, do you know which interrupt number I should request for
> the PBUS DMA:s. I can't handle the interrupts correctly without the knowledge of

for me it looks like SGINT_HPCDMA should be the first PBUS DMA interrupt.
But looking further into the indyIRQ.S and indy_int.c indicates, that these
interrupts aren't implemented, yet.

> It would be nice if you even explained *how* you know..

use the source Luke.

Thomas.

-- 
   This device has completely bogus header. Compaq scores again :-|
It's a host bridge, but it should be called ghost bridge instead ;^)
                                        [Martin `MJ' Mares on linux-kernel]

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 29 02:11:42 1998
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Date: Thu, 29 Oct 1998 11:12:11 +0100
From: Ulf Carlsson <ulfc@bun.falkenberg.se>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>, ralf@uni-koblenz.de
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: HAL2 interrupt
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On Wed, Oct 28, 1998 at 11:26:52PM +0100, Thomas Bogendoerfer wrote:
> On Wed, Oct 28, 1998 at 12:59:01AM +0100, Ulf Carlsson wrote:
> > Now I'm asking again, do you know which interrupt number I should request for
> > the PBUS DMA:s. I can't handle the interrupts correctly without the knowledge of
> 
> for me it looks like SGINT_HPCDMA should be the first PBUS DMA interrupt.
> But looking further into the indyIRQ.S and indy_int.c indicates, that these
> interrupts aren't implemented, yet.

The problem is that the sgiseeq and the sgiwd93 use HPC DMA as well, but they're
sharing local interrupt 0 (MIPS IRQ 2), and using some status register to
differentiate them. If I were writing a sgiwd93 driver or a sgiseeq driver, my
first guess would have been that they were using the SGINT_HPCDMA interrupts.

Well, looks like I'm out of luck, I'll do some trial & error.

Ralf?

- Ulf

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 29 14:14:20 1998
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Date: Thu, 29 Oct 1998 23:10:09 +0100
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Ulf Carlsson <ulfc@bun.falkenberg.se>, ralf@uni-koblenz.de
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: HAL2 interrupt
References: <19981028005901.C23849@zigzegv.ml.org> <19981028232652.A2587@alpha.franken.de> <19981029111211.B28553@zigzegv.ml.org>
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On Thu, Oct 29, 1998 at 11:12:11AM +0100, Ulf Carlsson wrote:
> The problem is that the sgiseeq and the sgiwd93 use HPC DMA as well, but they're

yes, but they aren't using PBUS DMA channels, because they aren't connected
to the PBUS.

> sharing local interrupt 0 (MIPS IRQ 2), and using some status register to
> differentiate them. If I were writing a sgiwd93 driver or a sgiseeq driver, my
> first guess would have been that they were using the SGINT_HPCDMA interrupts.

SCSI and ethernet are special HPC devices, so they get handled in a different
way.

> Well, looks like I'm out of luck, I'll do some trial & error.

try interrupt 12, which should be the HPC3 interrupt (sgint23.h). After
getting an HPC3 interrupt you have to look in HPC3 register istat0 and 
istat1 for the interrupt source. I guess DaveM wanted to map these
interrupt sources to SGINT_HPCDMA, but never got to implement it.

Thomas.

-- 
   This device has completely bogus header. Compaq scores again :-|
It's a host bridge, but it should be called ghost bridge instead ;^)
                                        [Martin `MJ' Mares on linux-kernel]

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 29 14:28:32 1998
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Date: Thu, 29 Oct 1998 23:29:27 +0100
From: Ulf Carlsson <ulfc@bun.falkenberg.se>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>, ralf@uni-koblenz.de
Cc: linux@cthulhu.engr.sgi.com
Subject: Re: HAL2 interrupt
References: <19981028005901.C23849@zigzegv.ml.org> <19981028232652.A2587@alpha.franken.de> <19981029111211.B28553@zigzegv.ml.org> <19981029231009.A3756@alpha.franken.de>
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> > Well, looks like I'm out of luck, I'll do some trial & error.
> 
> try interrupt 12, which should be the HPC3 interrupt (sgint23.h). After
> getting an HPC3 interrupt you have to look in HPC3 register istat0 and 
> istat1 for the interrupt source. I guess DaveM wanted to map these
> interrupt sources to SGINT_HPCDMA, but never got to implement it.

Thanks, I'll do this tonight or tomorrow.

By the way, I have patched the kernel to support ksymoops (with stack tracing,
call tracing and code dump), and Keith Owens has patched ksymoops to support
MIPS. There was some sort of show_registers() function in traps.c which wasn't
used. I rewrote that function and made it work (yes, the original function
didn't work at all). Sounds interesting, doesn't it? I'll send you the patch
tomorrow...

- Ulf

From owner-linux@cthulhu.engr.sgi.com  Thu Oct 29 14:32:26 1998
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To: linux@cthulhu.engr.sgi.com
Subject: Prices on Indy
Date: Thu, 29 Oct 1998 15:31:32 -0700
From: Warner Losh <imp@village.org>
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I'm looking at a couple of Indy machines that have 50MHz R4400 CPUs in
them.  What's the going price for this?  There is no memory or disks
or much of anything else included with these machines.  What's a good
price?  The person I'm talking to wants $210

Also, I have a chance to get full systems (with 80M-128M memory,
500M-1G disk) for $525.  This includes monitors, etc.

Warner

From owner-linux@cthulhu.engr.sgi.com  Fri Oct 30 04:32:32 1998
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Message-ID: <19981030133319.A3845@bun.falkenberg.se>
Date: Fri, 30 Oct 1998 13:33:19 +0100
From: Ulf Carlsson <ulfc@bun.falkenberg.se>
To: ralf@uni-koblenz.de
Cc: linux-mips@fnet.fr, linux-mips@vger.rutgers.edu,
        linux@cthulhu.engr.sgi.com
Subject: ksymoops support for MIPS
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--oyUTqETQ0mS9luUI
Content-Type: text/plain; charset=us-ascii

Hi Ralf,

I've modified arch/mips/kernel/traps.c to support ksymoops, and Keith Owens has
modified ksymoops to support MIPS. A new version of ksymoops will show up within
a few days at ftp://ftp.ocs.com.au/pub/ksymoops.tar.gz. I have a later version
of ksymoops which works, but I prefer not to spam you :)

Can't you please include this patch in the CVS tree?

- Ulf

--oyUTqETQ0mS9luUI
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="traps.c.diff"

--- linux/arch/mips/kernel/traps.c-orig	Thu Oct 29 17:23:19 1998
+++ linux/arch/mips/kernel/traps.c	Fri Oct 30 13:25:21 1998
@@ -6,6 +6,7 @@
  *
  * Copyright 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
  * Modified for R3000 by Paul M. Antoine, 1995, 1996
+ * Complete output from die() by Ulf Carlsson, 1998
  */
 #include <linux/config.h>
 #include <linux/init.h>
@@ -80,50 +81,61 @@
  * This routine abuses get_user()/put_user() to reference pointers
  * with at least a bit of error checking ...
  */
-void show_registers(char * str, struct pt_regs * regs, long err)
+void show_stack(unsigned int *sp)
 {
-	int	i;
-	int	*stack;
-	u32	*sp, *pc, addr, module_start, module_end;
-	extern	char start_kernel, _etext;
+	int i;
+	unsigned int *stack;
 
-	sp = (u32 *)regs->regs[29];
-	pc = (u32 *)regs->cp0_epc;
+	stack = sp;
+	i = 0;
 
-	show_regs(regs);
+	printk("Stack:");
+	while ((unsigned long) stack & (PAGE_SIZE - 1)) {
+		unsigned long stackdata;
 
-	/*
-	 * Dump the stack
-	 */
-	printk("Process %s (pid: %ld, stackpage=%08lx)\nStack: ",
-		current->comm, current->pid, (unsigned long)current);
-	for(i=0;i<5;i++)
-		printk("%08x ", *sp++);
-	stack = (int *) sp;
+		if (__get_user(stackdata, stack++)) {
+			printk(" (Bad stack address)");
+			break;
+		}
 
-	for(i=0; i < kstack_depth_to_print; i++) {
-		unsigned int stackdata;
+		printk(" %08lx", stackdata);
 
-		if (((u32) stack & (PAGE_SIZE -1)) == 0)
-			break;
-		if (i && ((i % 8) == 0))
-			printk("\n       ");
-		if (get_user(stackdata, stack++) < 0) {
-			printk("(Bad stack address)");
+		if (++i > 40) {
+			printk(" ...");
 			break;
 		}
-		printk("%08x ", stackdata);
+
+		if (i % 8 == 0)
+			printk("\n      ");
 	}
-	printk("\nCall Trace: ");
-	stack = (int *)sp;
-	i = 1;
+}
+
+void show_trace(unsigned int *sp)
+{
+	int i;
+	unsigned int *stack;
+	unsigned long kernel_start, kernel_end;
+	unsigned long module_start, module_end;
+	extern char _stext, _etext;
+
+	stack = sp;
+	i = 0;
+
+	kernel_start = (unsigned long) &_stext;
+	kernel_end = (unsigned long) &_etext;
 	module_start = VMALLOC_START;
 	module_end = module_start + MODULE_RANGE;
-	while (((unsigned long)stack & (PAGE_SIZE -1)) != 0) {
-		if (get_user(addr, stack++) < 0) {
-			printk("(Bad address)\n");
+
+	printk("\nCall Trace:");
+
+	while ((unsigned long) stack & (PAGE_SIZE -1)) {
+		unsigned long addr;
+
+		if (__get_user(addr, stack++)) {
+			printk(" (Bad stack address)\n");
 			break;
 		}
+
 		/*
 		 * If the address is either in the text segment of the
 		 * kernel, or in the region which contains vmalloc'ed
@@ -132,26 +144,33 @@
 		 * down the cause of the crash will be able to figure
 		 * out the call path that was taken.
 		 */
-		if (((addr >= (u32) &start_kernel) &&
-		     (addr <= (u32) &_etext)) ||
-		    ((addr >= module_start) && (addr <= module_end))) {
-			if (i && ((i % 8) == 0))
-				printk("\n       ");
-			printk("%08x ", addr);
-			i++;
+
+		if ((addr >= kernel_start && addr < kernel_end) ||
+		    (addr >= module_start && addr < module_end)) { 
+
+			printk(" [<%08lx>]", addr);
+			if (++i > 40) {
+				printk(" ...");
+				break;
+			}
 		}
 	}
+}
 
-	printk("\nCode : ");
-	if ((KSEGX(pc) == KSEG0 || KSEGX(pc) == KSEG1) &&
-	    (((unsigned long) pc & 3) == 0))
-	{
-		for(i=0;i<5;i++)
-			printk("%08x ", *pc++);
-		printk("\n");
+void show_code(unsigned int *pc)
+{
+	long i;
+
+	printk("\nCode:");
+
+	for(i = -3 ; i < 6 ; i++) {
+		unsigned long insn;
+		if (__get_user(insn, pc + i)) {
+			printk(" (Bad address in epc)\n");
+			break;
+		}
+		printk("%c%08lx%c",(i?' ':'<'),insn,(i?' ':'>'));
 	}
-	else
-		printk("(Bad address in epc)\n");
 }
 
 void die(const char * str, struct pt_regs * regs, unsigned long err)
@@ -162,6 +181,12 @@
 	console_verbose();
 	printk("%s: %04lx\n", str, err & 0xffff);
 	show_regs(regs);
+	printk("Process %s (pid: %ld, stackpage=%08lx)\n",
+		current->comm, current->pid, (unsigned long) current);
+	show_stack((unsigned int *) regs->regs[29]);
+	show_trace((unsigned int *) regs->regs[29]);
+	show_code((unsigned int *) regs->cp0_epc);
+	printk("\n");
 	do_exit(SIGSEGV);
 }
 

--oyUTqETQ0mS9luUI--

From owner-linux@cthulhu.engr.sgi.com  Fri Oct 30 18:27:21 1998
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Date: Fri, 30 Oct 1998 18:24:54 -0800 (PST)
Message-Id: <199810310224.SAA02277@piecomputer.engr.sgi.com>
From: Bob Mende Pie <mende@piecomputer.engr.sgi.com>
To: linux@cthulhu.engr.sgi.com
CC: dmk@cthulhu.engr.sgi.com
Subject: Downtime notice
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There will be a short downtime on linus.linux.sgi.com on monday morning
(PST) to reseat (or replace) a questionable SIMM.

                    /Bob...                    mailto:mende@sgi.com
              http://reality.sgi.com/mende            KF6EID

From owner-linux@cthulhu.engr.sgi.com  Fri Oct 30 18:28:43 1998
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From: ariel@oz.engr.sgi.com (Ariel Faigon)
Message-Id: <199810310228.SAA34114@oz.engr.sgi.com>
Subject: Re: Linus is down ? (fwd)
To: linux@cthulhu.engr.sgi.com (SGI/Linux mailing list)
Date: Fri, 30 Oct 1998 18:28:50 -0800 (PST)
Reply-To: ariel@cthulhu.engr.sgi.com (Ariel Faigon)
Organization: Silicon Graphics Inc.
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Just FYI.

linus had many memory parity errors (most fixed by the CPU, but
one eventually failed) this afternoon which caused it to hang.
David rebooted it and will be replacing the bad SIMM early next week.


David said:
:
:Please notify the community that there
:will downtime with *very* short notice.
:-- 
:
:                                              dmk
:dmk@n2rdt.engr.sgi.com                                            N2RDT
:David M. Katinsky                             Systems Administrator/SGI
:


-- 
Peace, Ariel

