Subject: More oddities in traps.c

From: "Kevin D. Kissell" <[email-masked]>
Date: Fri, 21 Apr 2000 10:39:51 +0200

So while we're on the topic of cruft in arch/mips/kernel/traps.c,
does anyone know why the cache error exception vector is
overwritten with a copy of the TLB miss handler as part of
vector setup on R4xxx and R5xxx CPUs?
__

Kevin D. Kissell
MIPS Technologies European Architecture Lab
[email-masked]
Tel. +33.4.78.38.70.67
FAX. +33.4.78.38.70.68

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From: Ralf Baechle <[email-masked]>
Date: Fri, 21 Apr 2000 09:55:06 -0700

> vector setup on R4xxx and R5xxx CPUs?

{\cruft[stupid_answer] Cache errors are that rare that nobody complained so
far ...}

Fixing ...

  Ralf