Subject: Re: CVS [email-masked]: linux

From: Ralf Baechle <[email-masked]>
Date: Thu, 7 Sep 2000 01:45:21 +0200

On Wed, Sep 06, 2000 at 04:36:29PM -0700, Kanoj Sarcar wrote:

> 	Compile fix: flush only L2 cache.

That's wrong, sysmips(FLUSH_CACHE) is supposed to flush all caches.

  Ralf

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From: Kanoj Sarcar <[email-masked]>
Date: Wed, 6 Sep 2000 16:51:19 -0700 (PDT)

> That's wrong, sysmips(FLUSH_CACHE) is supposed to flush all caches.

The act of flushing the L2 cache, should include flushing the L1
cache, whether done by software or processor provided primitives, 
to guarantee the inclusion principle.

Notwithstanding, feel free to add in a call to flush_cache_l1()
(and I don't know whether you want to flush the i and d caches
both, or just one), making sure there are no compile breakages.
(the breakage that I fixed was due to the fact that there is no
__flush_cache_all for mips64).

Kanoj

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From: Ralf Baechle <[email-masked]>
Date: Thu, 7 Sep 2000 02:02:37 +0200

> to guarantee the inclusion principle.

The inclusion principle is not true for all processor types.

> __flush_cache_all for mips64).

Sorry, that line leaked in from my private tree.

  Ralf

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From: Kanoj Sarcar <[email-masked]>
Date: Wed, 6 Sep 2000 17:05:18 -0700 (PDT)

> The inclusion principle is not true for all processor types.

Which processor is supported out of the mips64 tree that does
not obey the inclusion principle?

Kanoj

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From: Ralf Baechle <[email-masked]>
Date: Thu, 7 Sep 2000 02:26:52 +0200

> not obey the inclusion principle?

The R4600SC and R5000SC IP22.  RM7000 (patches pending) and probably most
future MIPS CPUs.

  Ralf