Subject: MIPS R5Kc core configuration

From: [email-masked]
Date: Wed, 14 Feb 2001 19:02:40 +0200

Hello,

I have recently started to work with the new R5Kc core from MIPS.
It is defined to be 64 Bit. I wonder if you know of other processors
that are also 64
bits that can be safely used for kernel configuration (R10000 maybe?).

Sincerely yours,
Michael Shmulevich
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Jungo - R&D 
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---

From: [email-masked]
Date: Thu, 15 Feb 2001 18:14:49 +0200

Paul,

What I meant is: when configuring linux for some specific MIPS CPU,
right now there is no MIPS64 CPU option (like there was MIPS32 for
Atlas), therefore I don't know what CPU configuration may be used for
5Kc core. 

Do we have an FPU? What are the permitted CP register operations, and
how do we set up the kernel for 64 bit architecture. I guess there were
another 64 bit CPUs that are configured like the LJA0004 MIPS-5KC that
is sitting on our Core board. 

Are you suggesting that QED's 5261 is a close shot?

Thanks,
Michael.

Paul Kleist wrote:
> 
> Hi Michael,
> 
> what do you mean by the phrase 'that can be used for kernel
> configuration' ?
> 
> You can look at eg. QED or NEC websites for other 64 bit mips
> processors, but they
> are not nescessarily identical implementations so do not be sure that
> you can use
> another processor instead of 5Kc which is a MIPS64 implementation.
> 
> The QED5261 is *close*, and we do have 200/100 MHz boards (core/bus
> freq) that can run
> on Atlas/Malta, and this cpuboard run our Linux also.
> 
> Regards
> Paul Kleist
> 
> [email-masked] wrote:
> >
> > Hello,
> >
> --
> _    _ ____  ___    Paul Kleist        Mailto:[email-masked]
> |\  /|||___)(___    MIPS Denmark       Direct: +45 44 86 55 43
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-- 
Sincerely yours,
Michael Shmulevich

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From: "Kevin D. Kissell" <[email-masked]>
Date: Thu, 15 Feb 2001 18:14:00 +0100

The 5KC should run an 4KC MIPS32 kernel with
no modifications if you want to run in 32-bit "mode".
As far as 64-bit operation is concerned, the 5KC
gives you an option that the R4xxx and R5xxx do
not, which is to enable 64-bit load/store/math operations
without also enabling 64-bit addressing.  But the
UX/KX bits in the Status register have the same
semantics on the 5KC as on the 4xxx and R5xxx,
as do the 64-bit memory management registers
and exceptions.  Yes, the R5261 would be a pretty
close match, though not perfect:  The basic 5KC
has no FPU, and the 5KC cache geometry cannot
be assumed based on the PrID register, and should
be inferred from the Config registers in the same
manner as on a 4KC, though of course as an expedient
you can set the cache size/associativity for the 5KC
in the kernel source to correpsond to your Core
board CPU.

        Kevin K.