Subject: Re: Re: 8259 spurious interrupt (IRQ1,IRQ7,IRQ12..)

From: Zhang Fuxin <[email-masked]>
Date: Thu, 20 Sep 2001 9:52:0 +0800

hi,Jun Sun，

在 2001-09-19 12:39:00 you wrote：
>
>> >It is typically much easier to modify PCI device BARS so that they do coincide
>> >with the same physical address.   You can control that by using the correct
>> >starting address for PCI MEM space in pci_auto.c resource assignment.
>> It seems a good way to solve the ioremap problem and X problem.But virt_to_bus
>> & bus_to_virt problem remains?
>> 
>
>What is the virt_to_bus() problem?  Is the address beyond 512MB (phy addr)? 
No,I mean problem caused different cpu & pci address space.from pci's view,
the main memory is at address 0x80000000-0x90000000 in p6032.But for cpu,
they are 0x0-0x10000000.So current virt_to_bus & bus_to_virt won't work.

>If PCI mem (BUS) address is identical to phy addr, you should not have problem
>unless the address is beyond 512MB.
yes:).When i solve the 8259,i will try to make them same.
>
>BTW, virt_to_bus()/bus_to_virt() are deprecicated.  See
>Documentation/DMA-mapping.txt.
I think the "depreciated" is only for direct usage: they are used in
arch/mips/pci-dma.c to implement new interface pci_alloc_consistent.
And there are still many driver using them(grep tell me).Am i missing
something?
>Jun

Regards
            Zhang Fuxin
            [email-masked]

---

From: Zhang Fuxin <[email-masked]>
Date: Thu, 20 Sep 2001 10:25:0 +0800

hi,Ralf Baechle，

    The mannual says:

     Tips on programming south bridge interrupt controller(s)

  The interrupt controllers inside the south bridge chip have to be software-compatible with the dual Intel 8259 controllers fitted to ver y old 
PCs.There are two 8-bit controllers inside the south bridge,aslave whose
interrupt output becomes one of the eight inputs of the master controller.
The 8259 is a ver y old device,dating from around 1980. Under the influence 
of contemporar y minicomputer designs,the 8259 made a brave attempt to build 
an interrupt prior ity system in hardware for Intel 8-bit and 8086 CPUs.With 
the benefit of 20 years hindsight, we can see this was pretty silly (but that
’s a lot of hindsight, and the people who did it were much younger then).
When separated from its Intel CPU,the 8259 is unable to do exciting things like automatically causing the CPU to vector to an appropriate interrupt 
vector location. Experience shows that allowing it to do anything complicated 
is likely to lead to trouble,so we suggest:
   1. Don’t use the 8259’s prior ity logic. Instead, place both the master and slave controller into what the Intel manuals call Special Mask Mode.This disables all interrupt prior itisation; now any active and unmasked
interr upt input will activate the interrupt output, which is enough.

2. Do not ever read the ISR (‘‘in-ser vice’’) registers.They don’t make sense outside of the prior ity scheme.If you want to know what individual interrupt lines are doing, look in the IRR (‘‘interr upt request’’) registers instead.

3. Conclude each interrupt service routine with a ‘‘Specific end-of-interrupt (EOI)’’ command to the 8259. In special mask mode this does
n't do anything to the priority,but it does serve to clear a latched 
interrupt, if there is one.(There are other ways of doing this).

-----------------
 I have tried to put both 8259 into Special mask mode( write OCW3=0x6a to 0x20
and 0xa0).But it doesn't stop spurious IRQ12.But so far I have see only IRQ7
and IRQ12.
  A skim over 82371(PIIX) manual I find something that may relate: XBCS 
register(0x4e),which can control mouse support at IRQ12,and keyb,rtc support.
Because p6032 use multi-IO controller to provide keyb,mouse,rtc,I guess
it may lead to some problem; 0x60,a read to it clear mouse/keyb interrupt
if mouse/keyb support is enabled in XBCS; 0x4d0,0x4d1,set level/edge sense
mode per interrupt.
  But sadly up to now i have tried several combination,none can stop spurious
IRQ12. I have to add a read to 0x60 to prevent endless spurious IRQ12 when it 
happens.
  Another fact is the 82371 manual is 82371FB & 82371SB,but the chip on the
board is 82371EB.I will try to find the exact manual later.

在 2001-09-19 18:41:00 you wrote：
>On Wed, Sep 19, 2001 at 11:27:14AM +0100, Phil Thompson wrote:
>
>> Make sure you read the section in the P6032 manual "Tips on programming
>> south bridge interrupt controller(s)" - page 31. I don't see how the 8259
>> code that's part of the MIPS tree can ever be used without changes.
>
>Can you elaborate?  It's actually being used without problems.
>
>  Ralf

Regards
            Zhang Fuxin
            [email-masked]

---

From: Phil Thompson <[email-masked]>
Date: Thu, 20 Sep 2001 09:45:14 +0100

> -----Original Message-----
> From: Ralf Baechle [mailto:[email-masked]]
> Sent: 19 September 2001 17:41
> To: Phil Thompson
> Cc: 'Zhang Fuxin'; [email-masked]
> Subject: Re: Re: 8259 spurious interrupt (IRQ1,IRQ7,IRQ12..)
> 
> 

The P6032 documentation recommends using Special Mask Mode to disable the
8259's priority logic so that reading the ISR register gives you the set of
pending interrupts. I took that at face value, so you need to program the
mode and need a function to return the set of pending interrupts (although
you could use i8259A_irq_pending() in loop).

Phil

---

From: Jun Sun <[email-masked]>
Date: Thu, 20 Sep 2001 10:07:33 -0700

Zhang Fuxin wrote:
> 
> hi,Jun Sun£¬
> 
> ÔÚ 2001-09-19 12:39:00 you wrote£º
> >

You should make sys memory appears starting from 0x0 in PCI memory as well. 
That was part of what I meant by making PCI memory address and CPU physical
address identical.

> And there are still many driver using them(grep tell me).Am i missing

Hmm, I am not too sure here.  My understanding is any new driver should try
*not* to use it.  pci-dma.c may use it because of lack of other means or just
a quick hack.

Jun