Subject: 8259 spurious interrupt (IRQ1,IRQ7,IRQ12..)

From: Zhang Fuxin <[email-masked]>
Date: Tue, 18 Sep 2001 18:33:35 +0800

hi,all
  I have finally been able to get a copy of sgi cvs code:).Now I have
changed my p6032 code to use new[time,pci,irq] code and it seems a 
lot cleaner.But still problems.
  I keep seeing spurious interrupt when starting xwindows.And 
sometimes without x. If the machine is doing heavy io(e.g.,unzip & 
untar mozilla source) when I startx,it will probably enter an 
endless loop of spurious interrupt or lead to unaligned instruction 
access shortly after(with epc=0x1,ra=0x1) and die.
  I have seen spurious IRQ1,IRQ7 and IRQ12,and the endless loop case
is IRQ12--ps2 mouse interrupt.
  Can somebody give me a clue? What I know is that 8259 may generate
spurious IRQ7 & IRQ15. But how can the others happen,buggy hw?And 
what may cause a kernel unaligned instruction access?

  My hw is p6032 rev.B eval board with idtRC64474 cpu.

  BTW,is that current code has no support for different PCI & CPU 
address space?In p6032 default setting,PCI memory address 0 is 
CPU physical address 0x10000000,and main memory is 0-0x10000000
for CPU,but 0x80000000-0x90000000 for pci. So I have to change 
ioremap,virt_to_bus & bus_to_virt. I think this problem should 
exist in many nonpc hw,could you point me a clean way?

  Thanks in advance.

Regards
            Zhang Fuxin
            [email-masked]

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From: "Gleb O. Raiko" <[email-masked]>
Date: Tue, 18 Sep 2001 16:16:17 +0400

> exist in many nonpc hw,could you point me a clean way?

Change them.

Regards,
Gleb.

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From: Jun Sun <[email-masked]>
Date: Tue, 18 Sep 2001 10:09:26 -0700

> lot cleaner.But still problems.

Cool.  Very glad to hear that.

> what may cause a kernel unaligned instruction access?

Are you using arch/mips/i8259.c file?

One possibility is your irq dispatching code.  If it loops to deliver all
pending interrupts, what you described may happen (assuming there is a real
hardware connecting to those irq sources).

> exist in many nonpc hw,could you point me a clean way?

For now, we do assume PCI memeory space is identical to physical address
space.  To remove the restriction cleanly is not a small task.

It is typically much easier to modify PCI device BARS so that they do coincide
with the same physical address.   You can control that by using the correct
starting address for PCI MEM space in pci_auto.c resource assignment.  

Jun