Subject: MIPS 32bit and 64bit mode

From: han han <[email-masked]>
Date: Fri, 26 Oct 2001 10:30:04 -0700 (PDT)

Hi all,

Does Anybody help me to clear some concepts about MIPS
5kc?
How to detect and set a MIPS 5kc chip working in 32bit
or 64bit mode? or the chip can automatically enter
proper mode when it fetchs an MIPS 32/64 instruction?

Also, does MIPS 5kc have some 64bit instructions? 

Thanks a lot in advance,

--Han

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From: "Kevin D. Kissell" <[email-masked]>
Date: Fri, 26 Oct 2001 19:54:37 +0200

> Also, does MIPS 5kc have some 64bit instructions? 

I guess somebody (probably me) need to write a
MIPS32/MIPS64 FAQ one of these days.

To answer your last question first, yes, the MIPS5Kc
has the full compliment of 64-bit integer instructions.
It does not have the integrated FPU of the 5Kf, however,
so you have neither 32-bit nor 64-bit FP instructions.

There are two kinds of "64-bit-ness" to consider:
64-bit data types and 64-bit addresses.   In kernel
mode, a MIPS64 CPU always has access to 64-bit
data types, but to have 64-bit instructions in user
mode, one needs to explicitly enable them in the
CP0.Status register.

In pre-MIPS64 64-bit MIPS CPUs such as the
R4000 and R5000, user mode access to 64-bit
data types was only possible if 64-bit addressing
was also enabled for user mode by setting the
CP0.Status.UX bit.  Kernel mode 64-bit addressing
is independently enabled by setting the CP0.Status.KX
bit.  In MIPS64 (e.g. the 5Kc), it is also possible to enable 
64-bit data types in user mode *without* 64-bit addressing
by setting the CP0.Status.PX bit (bit 23).

            Regards,

            Kevin K.

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From: George Gensure <[email-masked]>
Date: Fri, 26 Oct 2001 13:54:59 -0400 (EDT)

is the 5kc the same processor as the r5k?

George

-- 
George R. Gensure       Computer Science House Member
[email-masked]       Sophomore, Rochester Institute of Technology
Computer Science

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From: "Kevin D. Kissell" <[email-masked]>
Date: Fri, 26 Oct 2001 20:05:40 +0200

> is the 5kc the same processor as the r5k?

If by "r5k" you mean the R5000(tm), no it isn't.
The MIPS 5Kc(tm) is a newer syntesizable 64-bit 
MIPS CPU core from MIPS Technologies.

            Kevin K.

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From: han han <[email-masked]>
Date: Fri, 26 Oct 2001 11:54:52 -0700 (PDT)

> mode, one needs to explicitly enable them in the

But, how does MIPS 5kc work with 32bit Linux kernel?
Do you means there is no difference between 32 bit
mode and 64 bit mode for MIPS 5kc in kernel mode?

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From: "Kevin D. Kissell" <[email-masked]>
Date: Fri, 26 Oct 2001 21:42:13 +0200

> But, how does MIPS 5kc work with 32bit Linux kernel?

If the KX, UX, and PX bits of the CP0 Status register
are all zero, a MIPS5Kc is essentaillly functioning as
a 32-bit CPU.  The registers are still 64 bits, and
arithmetic operations will cause all 64 bits of the
destination to be written, but this is outside of the
"event horizon" of the program so long as 64-bit
data and addressing is not enabled.  The 64-bit
5Kc can, and does, boot the same Linux kernel as 
the 32-bit 4Kc.  MIPS64 is a strict superset of MIPS32.

> mode and 64 bit mode for MIPS 5kc in kernel mode?

There is no such thing as "32-bit mode" and "64-bit
mode", not really.  There are 64-bit data-type instructions
(e.g. "LD", "DADD") and, logically independently, there
is 64-bit addressing for loads and stores - which includes 
LW and LB as well as LD.  64-bit data is always enabled 
in kernel mode on a MIPS64 part.  For 64-bit data in User 
mode, and for 64-bit addressing in *either* mode, there are 
explicit enables.

            Kevin K.