Subject: Re: [update] [patch] linux: Cache coherency fixes

From: Carsten Langgaard <[email-masked]>
Date: Thu, 01 Aug 2002 10:31:46 +0200

What happen with this patch.
I think it's ok to apply and no one has made any objection.

/Carsten

"Maciej W. Rozycki" wrote:

> Hello,
>
>  The following patch fixes all the places the default caching policy is
> used but various local hacks are coded.  Also the sc coherency algorithm
> is configured for R4k processors which was previously left as set (or not)
> by the firmware.  A side effect is <asm-mips64/pgtable-bits.h> is created
> and all conditional CPU options are set somehow.  Tested on an R4400SC
> (for both MIPS and MIPS64) and on an R3400.
>
>  Admittedly, CONF_CM_DEFAULT is defined in a bit weird way, but I couldn't
> figure any better one that wouldn't result in a serious but unnecessary
> header bloat.  If anyone has a better idea, please share any suggestions
> here.
>
>  OK to apply?
>
>   Maciej
>
> --
> +  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
> +--------------------------------------------------------------+
> +        e-mail: [email-masked], PGP key available        +
>
> patch-mips-2.4.19-rc1-20020726-cache-coherency-5
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/config-shared.in linux-mips-2.4.19-rc1-20020726/arch/mips/config-shared.in
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/config-shared.in     2002-07-25 20:11:36.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips/config-shared.in   2002-07-27 22:14:21.000000000 +0000
> @@ -403,6 +403,10 @@ fi
>  if [ "$CONFIG_MIPS_AU1000" != "y" ]; then
>     define_bool CONFIG_MIPS_AU1000 n
>  fi
> +
> +if [ "$CONFIG_SMP" != "y" ]; then
> +   define_bool CONFIG_SMP n
> +fi
>  endmenu
>
>  mainmenu_option next_comment
> @@ -492,6 +496,17 @@ if [ "$CONFIG_CPU_R3000" = "y" ]; then
>  else
>     define_bool CONFIG_CPU_HAS_SYNC y
>  fi
> +if [ "$CONFIG_CPU_R4X00" = "y" -o "$CONFIG_CPU_SB1" = "y" ]; then
> +   define_bool CONFIG_CPU_CACHE_COHERENCY $CONFIG_SMP
> +else
> +   define_bool CONFIG_CPU_CACHE_COHERENCY n
> +fi
> +if [ "$CONFIG_VTAG_ICACHE" != "y" ]; then
> +   define_bool CONFIG_VTAG_ICACHE n
> +fi
> +if [ "$CONFIG_CPU_HAS_PREFETCH" != "y" ]; then
> +   define_bool CONFIG_CPU_HAS_PREFETCH n
> +fi
>  endmenu
>
>  mainmenu_option next_comment
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-mips32.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-mips32.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-mips32.c        2002-05-30 02:57:43.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-mips32.c      2002-07-27 22:59:42.000000000 +0000
> @@ -657,11 +657,7 @@ void __init ld_mmu_mips32(void)
>  {
>         unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
>
> -#ifdef CONFIG_MIPS_UNCACHED
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
> -#else
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
> -#endif
> +       change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
>
>         probe_icache(config);
>         probe_dcache(config);
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-r4k.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-r4k.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-r4k.c   2002-07-15 02:57:47.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-r4k.c 2002-07-27 22:59:22.000000000 +0000
> @@ -1480,11 +1480,7 @@ void __init ld_mmu_r4xx0(void)
>  {
>         unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
>
> -#ifdef CONFIG_MIPS_UNCACHED
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
> -#else
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
> -#endif
> +       change_cp0_config(CONF_CM_CMASK | CONF_CU, CONF_CM_DEFAULT);
>
>         probe_icache(config);
>         probe_dcache(config);
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-r5432.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-r5432.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-r5432.c 2001-12-01 05:26:01.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-r5432.c       2002-07-27 23:01:23.000000000 +0000
> @@ -455,7 +455,7 @@ void __init ld_mmu_r5432(void)
>  {
>         unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
>
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
> +       change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
>
>         probe_icache(config);
>         probe_dcache(config);
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-rm7k.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-rm7k.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-rm7k.c  2002-05-30 02:57:46.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-rm7k.c        2002-07-27 23:02:21.000000000 +0000
> @@ -319,9 +319,7 @@ void __init ld_mmu_rm7k(void)
>                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
>         }
>
> -#ifndef CONFIG_MIPS_UNCACHED
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
> -#endif
> +       change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
>
>         probe_icache(config);
>         probe_dcache(config);
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-sb1.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-sb1.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-sb1.c   2002-05-30 02:57:46.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-sb1.c 2002-07-27 23:04:17.000000000 +0000
> @@ -519,6 +519,6 @@ void ld_mmu_sb1(void)
>         _flush_cache_sigtramp = sb1_flush_cache_sigtramp;
>         _flush_icache_all = sb1_flush_icache_all;
>
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_COW);
> +       change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
>         flush_cache_all();
>  }
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-tx49.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-tx49.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-tx49.c  2002-05-30 02:57:46.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-tx49.c        2002-07-27 23:05:01.000000000 +0000
> @@ -387,11 +387,7 @@ void __init ld_mmu_tx49(void)
>         if (mips_configk0 != -1)
>                 change_cp0_config(CONF_CM_CMASK, mips_configk0);
>         else
> -#ifdef CONFIG_MIPS_UNCACHED
> -               change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
> -#else
> -               change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
> -#endif
> +               change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
>
>         probe_icache(config);
>         probe_dcache(config);
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/c-mips64.c linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/c-mips64.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/c-mips64.c      2002-07-24 16:12:11.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/c-mips64.c    2002-07-27 23:07:05.000000000 +0000
> @@ -654,11 +654,7 @@ void __init ld_mmu_mips64(void)
>  {
>         unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
>
> -#ifdef CONFIG_MIPS_UNCACHED
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
> -#else
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
> -#endif
> +       change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
>
>         probe_icache(config);
>         probe_dcache(config);
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/c-sb1.c linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/c-sb1.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/c-sb1.c 2002-05-30 02:57:51.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/c-sb1.c       2002-07-27 23:07:42.000000000 +0000
> @@ -518,6 +518,6 @@ void ld_mmu_sb1(void)
>         _flush_cache_sigtramp = sb1_flush_cache_sigtramp;
>         _flush_icache_all = sb1_flush_icache_all;
>
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_COW);
> +       change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
>         flush_cache_all();
>  }
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/r4xx0.c linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/r4xx0.c
> --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/r4xx0.c 2002-06-20 02:57:39.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/r4xx0.c       2002-07-27 23:09:09.000000000 +0000
> @@ -2268,11 +2268,7 @@ void __init ld_mmu_r4xx0(void)
>  {
>         unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
>
> -#ifdef CONFIG_MIPS_UNCACHED
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
> -#else
> -       change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
> -#endif /* UNCACHED */
> +       change_cp0_config(CONF_CM_CMASK | CONF_CU, CONF_CM_DEFAULT);
>
>         probe_icache(config);
>         probe_dcache(config);
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips/mipsregs.h linux-mips-2.4.19-rc1-20020726/include/asm-mips/mipsregs.h
> --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips/mipsregs.h    2002-07-21 19:21:19.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips/mipsregs.h  2002-07-27 22:57:03.000000000 +0000
> @@ -374,6 +374,7 @@
>  #define CONF_CM_CACHABLE_CUW           6
>  #define CONF_CM_CACHABLE_ACCELERATED   7
>  #define CONF_CM_CMASK                  7
> +#define CONF_CU                                (1 <<  3)
>  #define CONF_DB                                (1 <<  4)
>  #define CONF_IB                                (1 <<  5)
>  #define CONF_SC                                (1 << 17)
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips/pgtable-bits.h linux-mips-2.4.19-rc1-20020726/include/asm-mips/pgtable-bits.h
> --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips/pgtable-bits.h        2002-06-30 17:18:30.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips/pgtable-bits.h      2002-07-27 23:00:05.000000000 +0000
> @@ -12,7 +12,8 @@
>
>  #include <linux/config.h>
>
> -/* Note that we shift the lower 32bits of each EntryLo[01] entry
> +/*
> + * Note that we shift the lower 32bits of each EntryLo[01] entry
>   * 6 bits to the left. That way we can convert the PFN into the
>   * physical address by a single 'and' operation and gain 6 additional
>   * bits for storing information which isn't present in a normal
> @@ -74,9 +75,9 @@
>  #define _CACHE_CACHABLE_WA          (1<<9)  /* R4600 only              */
>  #define _CACHE_UNCACHED             (2<<9)  /* R4[0246]00              */
>  #define _CACHE_CACHABLE_NONCOHERENT (3<<9)  /* R4[0246]00              */
> -#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00 only           */
> -#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00 only           */
> -#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00 only           */
> +#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00MC only         */
> +#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00MC only         */
> +#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00MC only         */
>  #define _CACHE_UNCACHED_ACCELERATED (7<<9)  /* R10000 only             */
>
>  #endif
> @@ -87,12 +88,21 @@
>
>  #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
>
> -#ifdef CONFIG_MIPS_UNCACHED
> +
> +#if defined(CONFIG_MIPS_UNCACHED)
> +
>  #define PAGE_CACHABLE_DEFAULT  _CACHE_UNCACHED
> -#elif CONFIG_CPU_SB1
> +
> +#elif defined(CONFIG_CPU_CACHE_COHERENCY)
> +
>  #define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_COW
> +
>  #else
> +
>  #define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_NONCOHERENT
> +
>  #endif
>
> +#define CONF_CM_DEFAULT                (PAGE_CACHABLE_DEFAULT >> 9)
> +
>  #endif /* _ASM_CACHINGMODES_H */
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/mipsregs.h linux-mips-2.4.19-rc1-20020726/include/asm-mips64/mipsregs.h
> --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/mipsregs.h  2002-06-29 03:02:05.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips64/mipsregs.h        2002-07-27 22:57:22.000000000 +0000
> @@ -374,6 +374,7 @@
>  #define CONF_CM_CACHABLE_CUW           6
>  #define CONF_CM_CACHABLE_ACCELERATED   7
>  #define CONF_CM_CMASK                  7
> +#define CONF_CU                                (1 <<  3)
>  #define CONF_DB                                (1 <<  4)
>  #define CONF_IB                                (1 <<  5)
>  #define CONF_SC                                (1 << 17)
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/pgtable-bits.h linux-mips-2.4.19-rc1-20020726/include/asm-mips64/pgtable-bits.h
> --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/pgtable-bits.h      1970-01-01 00:00:00.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips64/pgtable-bits.h    2002-07-27 23:00:24.000000000 +0000
> @@ -0,0 +1,79 @@
> +/*
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License.  See the file "COPYING" in the main directory of this archive
> + * for more details.
> + *
> + * Copyright (C) 1994 - 2001 by Ralf Baechle at alii
> + * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
> + * Copyright (C) 2002  Maciej W. Rozycki
> + */
> +#ifndef __ASM_MIPS64_PGTABLE_BITS_H
> +#define __ASM_MIPS64_PGTABLE_BITS_H
> +
> +#include <linux/config.h>
> +
> +/*
> + * Note that we shift the lower 32bits of each EntryLo[01] entry
> + * 6 bits to the left. That way we can convert the PFN into the
> + * physical address by a single 'and' operation and gain 6 additional
> + * bits for storing information which isn't present in a normal
> + * MIPS page table.
> + *
> + * Similar to the Alpha port, we need to keep track of the ref
> + * and mod bits in software.  We have a software "yeah you can read
> + * from this page" bit, and a hardware one which actually lets the
> + * process read from the page.  On the same token we have a software
> + * writable bit and the real hardware one which actually lets the
> + * process write to the page, this keeps a mod bit via the hardware
> + * dirty bit.
> + *
> + * Certain revisions of the R4000 and R5000 have a bug where if a
> + * certain sequence occurs in the last 3 instructions of an executable
> + * page, and the following page is not mapped, the cpu can do
> + * unpredictable things.  The code (when it is written) to deal with
> + * this problem will be in the update_mmu_cache() code for the r4k.
> + */
> +#define _PAGE_PRESENT               (1<<0)  /* implemented in software */
> +#define _PAGE_READ                  (1<<1)  /* implemented in software */
> +#define _PAGE_WRITE                 (1<<2)  /* implemented in software */
> +#define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
> +#define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
> +#define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
> +#define _PAGE_GLOBAL                (1<<6)
> +#define _PAGE_VALID                 (1<<7)
> +#define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
> +#define _PAGE_DIRTY                 (1<<8)  /* The MIPS dirty bit      */
> +#define _PAGE_SILENT_WRITE          (1<<8)
> +#define _CACHE_CACHABLE_NO_WA       (0<<9)  /* R4600 only              */
> +#define _CACHE_CACHABLE_WA          (1<<9)  /* R4600 only              */
> +#define _CACHE_UNCACHED             (2<<9)  /* R4[0246]00              */
> +#define _CACHE_CACHABLE_NONCOHERENT (3<<9)  /* R4[0246]00              */
> +#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00MC only         */
> +#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00MC only         */
> +#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00MC only         */
> +#define _CACHE_UNCACHED_ACCELERATED (7<<9)  /* R10000 only             */
> +#define _CACHE_MASK                 (7<<9)
> +
> +#define __READABLE     (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
> +#define __WRITEABLE    (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
> +
> +#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
> +
> +
> +#if defined(CONFIG_MIPS_UNCACHED)
> +
> +#define PAGE_CACHABLE_DEFAULT  _CACHE_UNCACHED
> +
> +#elif defined(CONFIG_CPU_CACHE_COHERENCY)
> +
> +#define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_COW
> +
> +#else
> +
> +#define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_NONCOHERENT
> +
> +#endif
> +
> +#define CONF_CM_DEFAULT                (PAGE_CACHABLE_DEFAULT >> 9)
> +
> +#endif /* __ASM_MIPS64_PGTABLE_BITS_H */
> diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/pgtable.h linux-mips-2.4.19-rc1-20020726/include/asm-mips64/pgtable.h
> --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/pgtable.h   2002-07-08 16:46:37.000000000 +0000
> +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips64/pgtable.h 2002-07-27 23:31:48.000000000 +0000
> @@ -155,64 +155,9 @@ extern void (*_flush_icache_page)(struct
>  #define VMALLOC_END    \
>         (VMALLOC_START + ((1 << PGD_ORDER) * PTRS_PER_PTE * PAGE_SIZE))
>
> -/*
> - * Note that we shift the lower 32bits of each EntryLo[01] entry
> - * 6 bits to the left. That way we can convert the PFN into the
> - * physical address by a single 'and' operation and gain 6 additional
> - * bits for storing information which isn't present in a normal
> - * MIPS page table.
> - *
> - * Similar to the Alpha port, we need to keep track of the ref
> - * and mod bits in software.  We have a software "yeah you can read
> - * from this page" bit, and a hardware one which actually lets the
> - * process read from the page.  On the same token we have a software
> - * writable bit and the real hardware one which actually lets the
> - * process write to the page, this keeps a mod bit via the hardware
> - * dirty bit.
> - *
> - * Certain revisions of the R4000 and R5000 have a bug where if a
> - * certain sequence occurs in the last 3 instructions of an executable
> - * page, and the following page is not mapped, the cpu can do
> - * unpredictable things.  The code (when it is written) to deal with
> - * this problem will be in the update_mmu_cache() code for the r4k.
> - */
> -#define _PAGE_PRESENT               (1<<0)  /* implemented in software */
> -#define _PAGE_READ                  (1<<1)  /* implemented in software */
> -#define _PAGE_WRITE                 (1<<2)  /* implemented in software */
> -#define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
> -#define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
> -#define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
> -#define _PAGE_GLOBAL                (1<<6)
> -#define _PAGE_VALID                 (1<<7)
> -#define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
> -#define _PAGE_DIRTY                 (1<<8)  /* The MIPS dirty bit      */
> -#define _PAGE_SILENT_WRITE          (1<<8)
> -#define _CACHE_CACHABLE_NO_WA       (0<<9)  /* R4600 only              */
> -#define _CACHE_CACHABLE_WA          (1<<9)  /* R4600 only              */
> -#define _CACHE_UNCACHED             (2<<9)  /* R4[0246]00              */
> -#define _CACHE_CACHABLE_NONCOHERENT (3<<9)  /* R4[0246]00              */
> -#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00 only           */
> -#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00 only           */
> -#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00 only           */
> -#define _CACHE_UNCACHED_ACCELERATED (7<<9)  /* R10000 only             */
> -#define _CACHE_MASK                 (7<<9)
> -
> -#define __READABLE     (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
> -#define __WRITEABLE    (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
> -
> -#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
> -
> -#ifdef CONFIG_MIPS_UNCACHED
> -#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
> -#else /* ! UNCACHED */
> -#ifdef CONFIG_SGI_IP22
> -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
> -#else /* ! IP22 */
> -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
> -#endif /* IP22 */
> -#endif /* UNCACHED */
> +#include <asm/pgtable-bits.h>
>
> -#define PAGE_NONE      __pgprot(_PAGE_PRESENT | PAGE_CACHABLE_DEFAULT)
> +#define PAGE_NONE      __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
>  #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
>                         PAGE_CACHABLE_DEFAULT)
>  #define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_READ | \
> @@ -222,7 +167,7 @@ extern void (*_flush_icache_page)(struct
>  #define PAGE_KERNEL    __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
>                         _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT)
>  #define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
> -                       _CACHE_UNCACHED)
> +                       PAGE_CACHABLE_DEFAULT)
>  #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
>                         __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
>

--
_    _ ____  ___   Carsten Langgaard   Mailto:[email-masked]
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com

---

From: Ralf Baechle <[email-masked]>
Date: Thu, 1 Aug 2002 15:25:00 +0200

> header bloat.  If anyone has a better idea, please share any suggestions

Looks mostly right except that the code in config-shared.in which deciedes
if a system is coherent is wrong.  Basically it assumes every R10000 or
every uniprocessor system is non-coherent and that's wrong.  As coherency
between CPUs and for DMA I/O is basically the same thing I've changed your
code from the use of CONFIG_CPU_CACHE_COHERENCY to CONFIG_NONCOHERENT_IO
which did already exist; I don't think we need another config symbol to
handle this.  Will apply once I did a few test builds and patches the
whole thing into 2.5 ...

  Ralf

---

From: "Maciej W. Rozycki" <[email-masked]>
Date: Thu, 1 Aug 2002 18:05:17 +0200 (MET DST)

> handle this.  Will apply once I did a few test builds and patches the

 Huh?  Coherent caching mode can be used for a few processors only, namely
R4[04]00MC and presumably SB1 (inferred from the sources), i.e. the ones
that support the interprocessor coherency protocol.  If you know of any
other processor that supports the protocol, I'd be pleased to see a
reference to a spec -- I hoped someone, possibly you, would fill the
missing bits when I proposed the patch a month ago.  Nobody bothered,
though, sigh...

 I see your changes are broken conceptually, as the caching mode for the
TLB should be inferred from the CPU configuration in the first place and
not the system selection (actually it should be best selected ath the run
time).  Hence I'd invert the flag, since most systems are non-coherent,
and only permit it for certain processors.  Using a non-coherent
configuration for an UP system that supports coherency (do SGI IP27 and
SiByte SB1250 have another agent in the chipset that may issue coherent
requests regardless of the number of processors started?) results in a
performance hit only due to superfluous invalidations, but using a
coherent configuration for a processor/system that doesn't support it may
lead to a hard to debug hang with no apparent reason (as I wrote
previously, even NMI/Reset stopped working on my system -- I had to hit
the power switch). 

 I'll cook another patch to fix what got broken.

  Maciej

---

From: Ralf Baechle <[email-masked]>
Date: Thu, 1 Aug 2002 18:49:29 +0200

> missing bits when I proposed the patch a month ago.  Nobody bothered,

R10000.

> and only permit it for certain processors.

Back in time I prefered CONFIG_NONCOHERENT_IO over CONFIG_COHERENT_IO
because the noncoherent case needs additional code and in general I'm
trying to reduce the number of the #if !defined conditionals for easier
readability.

The R10000 is our standard example why looking at the processor type doesn't
work.  It's used in coherent mode in IP27 but in coherent mode but in
coherent mode in IP28 or IP32.  Otoh I don't know of any system that
supports coherency but also is being used with non-coherent processors.

>  Using a non-coherent
> requests regardless of the number of processors started?)

Yes.  That's how coherency is working - all agents have to support coherent
requests or coherency simply won't work.  So basically we'd be trully
picky we'd have to verify that all agents, processor and other support
coherency but just using the system type seems to be sufficient.

> results in a

Using a non-coherent mode on IP27 may result in nice, hard to trackdown bus
errors.

  Ralf

---

From: "Maciej W. Rozycki" <[email-masked]>
Date: Thu, 1 Aug 2002 19:14:05 +0200 (MET DST)

> R10000.

 OK.  Any specs anywhere?

> trying to reduce the number of the #if !defined conditionals for easier

 Hmm, what's wrong with "#ifndef"?  Not much less readable than "#ifdef",
IMO. 

> supports coherency but also is being used with non-coherent processors.

 Yep, I suppose so, but the first criterion should be the CPU anyway.
Basically:

1. Does the CPU support coherency?

2. If so, does the system?

I'm going to express it this way in the config script.

> coherency but just using the system type seems to be sufficient.

 Well, inferring from docs and my experience it's not needed.  A system
may simply require areas used for DMA to be marked as non-coherent by
CPUs.  Often uncached accesses are used to prevent spoiling the caches
anyway.

> Using a non-coherent mode on IP27 may result in nice, hard to trackdown bus

 Weird, but I accept it as a fact.  Still a bus error expresses more than
a hang. ;-)

---

From: Ralf Baechle <[email-masked]>
Date: Thu, 1 Aug 2002 19:58:20 +0200

>  OK.  Any specs anywhere?

techpubs.sgi.com should have a somewhat older manual (must have!) and
www.necel.com as well.  The geniouses at NEC stripped the description of
the cache instruction from their manual so it you really want both manuals.

>  Hmm, what's wrong with "#ifndef"?  Not much less readable than "#ifdef",

Just a small detail.  Nest conditions several times and the spaghetti
starts :-)

> I'm going to express it this way in the config script.

Have fun expressing if a R4000 variant supports coherency :-)  You can't
if you don't want to introduce even more R4000 types or subtypes.

> CPUs.  Often uncached accesses are used to prevent spoiling the caches

None such MIPS system known where this is a sensible mode of operation -
and I've hacked quite a number of platforms.  Anyway, if there were such
systems they'd either have to be considered as coherent or as non-coherent.
Our current model doesn't permit any finer grained configuration and unless
such a system actually exists I don't think we should introduce one.

Btw, I've seen a fairly new system in which the non-coherent bits in some
agent are not working at all - it's easier to implement that way ...

>  Weird, but I accept it as a fact.  Still a bus error expresses more than

Not so weired.  The system is still operating in coherent mode; that also
means the directory caches still think they know where a particular memory
address is cached.  It's possible to operate an IP27 in non-coherent mode
for I/O only by also reconfiguring the whole chipset but that turned out to
be always slower and harder to get the software correct, so it's not used
except for debugging with a logic analyzer; details are mindbogglingly
complex.

  Ralf

---

From: "Maciej W. Rozycki" <[email-masked]>
Date: Thu, 1 Aug 2002 20:49:18 +0200 (MET DST)

> the cache instruction from their manual so it you really want both manuals.

 Thanks for the reference.

> Just a small detail.  Nest conditions several times and the spaghetti

 Well, that should be avoided whether the condition is positive or
negative.  Comments after "#else", "#elif" and "#end" might help a bit if
a discipline is kept. 

> if you don't want to introduce even more R4000 types or subtypes.

 Who said I don't want to? ;-)  Not a big deal at this stage.

> systems they'd either have to be considered as coherent or as non-coherent.

 Thanks for the clarification.

> such a system actually exists I don't think we should introduce one.

 Sure, but a one point we'll have an option to select the model at the run
time anyway.  At least this is one of goals I'd like to see fulfilled in
the future.

---

From: Dan Malek <[email-masked]>
Date: Thu, 01 Aug 2002 15:18:51 -0400

> Just a small detail.  Nest conditions several times and the spaghetti

Other cache coherency challenged processor architectures have adopted
the same CONFIG_NONCOHERENT_IO configuration option.  Some of these
could eventually find their way into generic kernel software and clean
up the architecture specific code.

	-- Dan

---

From: Thiemo Seufer <[email-masked]>
Date: Thu, 1 Aug 2002 19:06:49 +0200

Ralf Baechle wrote:
[snip]
> coherent mode in IP28 or IP32.  Otoh I don't know of any system that

JFTR: non-coherent mode in IP28 or IP32.

Thiemo

---

From: Carsten Langgaard <[email-masked]>
Date: Fri, 02 Aug 2002 10:10:24 +0200

> missing bits when I proposed the patch a month ago.  Nobody bothered,

The 20Kc has support for cache coherency, but it doesn't support Coherent
Update on Write (CUW), it only support Coherent exclusive (CE).

The way I implemented the coherency support locally, was I used a boot option
(coherency), where I could tell whether I wanted to run coherent or not.
The dma cache routines would then either be the normal (non-coherent version)
or a empty function.
As my system (a Malta board) can have different daughter cards attached, I can
have different CPUs and system controllers and I really like the idea, that I
can run the same kernel on all the different system setups.
So if the kernel was started with the "coherency" option, I checked whether or
not the CPU and system controller has support for coherency or not, if one or
both didn't support coherency, I die telling the user that the system didn't
support coherency.
In both the coherency and non-coherency case, I used the write-back
non-coherent cache attribute, as the 20Kc still responses to Intervention and
Invalidate request from the system controller.
The coherent exclusive cache attribute is really only needed in multi CPU
systems. I don't know if other CPU works the same way as the 20Kc.

---

From: Carsten Langgaard <[email-masked]>
Date: Fri, 02 Aug 2002 10:23:53 +0200

> coherency but just using the system type seems to be sufficient.

The Malta board is a system that both run coherent and non-coherent, so I would
prefer, that we either make the coherency a configuration option or make it
possible to determine at run time.

---

From: "Maciej W. Rozycki" <[email-masked]>
Date: Fri, 2 Aug 2002 10:36:57 +0200 (MET DST)

> possible to determine at run time.

 The latter, definitely.

---

From: Ralf Baechle <[email-masked]>
Date: Fri, 2 Aug 2002 12:16:00 +0200

> JFTR: non-coherent mode in IP28 or IP32.

Yep, you're right.  I hope everybody concluded that from my non-coherent
sentence ;-)

---

From: Ralf Baechle <[email-masked]>
Date: Fri, 2 Aug 2002 12:38:05 +0200

On Fri, Aug 02, 2002 at 10:23:53AM +0200, Carsten Langgaard wrote:

> The Malta board is a system that both run coherent and non-coherent, so I
> would prefer, that we either make the coherency a configuration option or
> make it possible to determine at run time.

Definately the latter then.  The price to pay is small and I don't think
forcing the use to change the kernel when just changing CPU modules is
acceptable.

  Ralf

---

From: "Maciej W. Rozycki" <[email-masked]>
Date: Mon, 5 Aug 2002 14:04:39 +0200 (MET DST)

>  I'll cook another patch to fix what got broken.

 OK, here is my proposal, based on my assumptions and the feedback I
received.

 The intent is as follows: systems that want coherent I/O mark it by
setting CONFIG_COHERENT_SYSTEM to "y" and CONFIG_NONCOHERENT_IO is then
set to "n" if both CONFIG_COHERENT_SYSTEM is "y" and the selected CPU
supports it; otherwise it's set to "y".  This implementation retains the
current semantics, (hopefully) provides the least confusion and should be
a reasonable temporary solution until we have a run-time selection. 

 Any comments?

  Maciej

patch-mips-2.4.19-rc1-20020802-cache-coherency-7
diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020802.macro/arch/mips/config-shared.in linux-mips-2.4.19-rc1-20020802/arch/mips/config-shared.in
--- linux-mips-2.4.19-rc1-20020802.macro/arch/mips/config-shared.in	2002-08-03 14:03:11.000000000 +0000
+++ linux-mips-2.4.19-rc1-20020802/arch/mips/config-shared.in	2002-08-03 14:23:38.000000000 +0000
@@ -108,7 +108,6 @@ if [ "$CONFIG_ACER_PICA_61" = "y" ]; the
    define_bool CONFIG_I8259 y
    define_bool CONFIG_ISA y
    define_bool CONFIG_MIPS_JAZZ y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_ROTTEN_IRQ y
    define_bool CONFIG_OLD_TIME_C y
@@ -118,7 +117,6 @@ if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_PCI y
    define_bool CONFIG_NEW_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
    define_int  MAX_HWIFS 1
 fi
@@ -128,7 +126,6 @@ if [ "$CONFIG_MIPS_PB1100" = "y" ]; then
    define_bool CONFIG_PCI y
    define_bool CONFIG_PCI_AUTO n
    define_bool CONFIG_NEW_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_SWAP_IO_SPACE y
    define_bool CONFIG_AU1000_USB_DEVICE y
@@ -139,12 +136,10 @@ if [ "$CONFIG_MIPS_PB1500" = "y" ]; then
    define_bool CONFIG_PCI y
    define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_NEW_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
 fi
 if [ "$CONFIG_ALGOR_P4032" = "y" ]; then
    define_bool CONFIG_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_OLD_TIME_C y
 fi
 if [ "$CONFIG_MIPS_COBALT" = "y" ]; then
@@ -152,18 +147,15 @@ if [ "$CONFIG_MIPS_COBALT" = "y" ]; then
    define_bool CONFIG_PCI y
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
 fi
 if [ "$CONFIG_DECSTATION" = "y" ]; then
    define_bool CONFIG_IRQ_CPU y
    define_bool CONFIG_NEW_IRQ y
-   define_bool CONFIG_NONCOHERENT_IO y
 fi
 if [ "$CONFIG_MIPS_EV64120" = "y" ]; then
    define_bool CONFIG_PCI y
    define_bool CONFIG_ISA n
    define_bool CONFIG_MIPS_GT64120 y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_OLD_TIME_C y
 fi
 if [ "$CONFIG_MIPS_EV96100" = "y" ]; then
@@ -171,7 +163,6 @@ if [ "$CONFIG_MIPS_EV96100" = "y" ]; the
    define_bool CONFIG_MIPS_GT96100 y
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_SWAP_IO_SPACE y
 fi
@@ -179,7 +170,6 @@ if [ "$CONFIG_MIPS_IVR" = "y" ]; then
    define_bool CONFIG_PCI y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_NEW_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_IT8172_CIR y
    define_bool CONFIG_NEW_IRQ y
@@ -190,7 +180,6 @@ if [ "$CONFIG_HP_LASERJET" = "y" ]; then
    define_bool CONFIG_NEW_TIME_C y
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI y
    #not yet define_bool CONFIG_PCI_AUTO y
 fi
@@ -199,7 +188,6 @@ if [ "$CONFIG_MIPS_ITE8172" = "y" ]; the
    define_bool CONFIG_IT8712 y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_NEW_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_IT8172_CIR y
    define_bool CONFIG_NEW_IRQ y
@@ -210,7 +198,6 @@ if [ "$CONFIG_MIPS_ATLAS" = "y" ]; then
    define_int CONFIG_L1_CACHE_SHIFT 5
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI y
    define_bool CONFIG_SWAP_IO_SPACE y
 fi
@@ -222,7 +209,6 @@ if [ "$CONFIG_MIPS_MAGNUM_4000" = "y" -o
    define_bool CONFIG_FB y
    define_bool CONFIG_FB_G364 y
    define_bool CONFIG_MIPS_JAZZ y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_OLD_TIME_C y
 fi
@@ -233,7 +219,6 @@ if [ "$CONFIG_MIPS_MALTA" = "y" ]; then
    define_int CONFIG_L1_CACHE_SHIFT 5
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_SWAP_IO_SPACE y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_PCI y
@@ -242,7 +227,6 @@ if [ "$CONFIG_MIPS_SEAD" = "y" ]; then
    define_int CONFIG_L1_CACHE_SHIFT 5
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI n
 fi
 if [ "$CONFIG_MOMENCO_OCELOT" = "y" ]; then
@@ -250,14 +234,12 @@ if [ "$CONFIG_MOMENCO_OCELOT" = "y" ]; t
    define_bool CONFIG_SYSCLK_100 y
    define_bool CONFIG_SWAP_IO_SPACE y
    define_bool CONFIG_NEW_IRQ y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_OLD_TIME_C y
 fi
 if [ "$CONFIG_DDB5074" = "y" ]; then
    define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
    define_bool CONFIG_I8259 y
    define_bool CONFIG_ISA y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_NEW_TIME_C y
@@ -277,7 +259,6 @@ if [ "$CONFIG_DDB5476"  = "y" ]; then
    define_bool CONFIG_NEW_PCI y
    define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
 fi
 if [ "$CONFIG_DDB5477" = "y" ]; then
    define_bool CONFIG_PCI y
@@ -285,7 +266,6 @@ if [ "$CONFIG_DDB5477" = "y" ]; then
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_IRQ_CPU y
    define_bool CONFIG_NEW_PCI y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_DUMMY_KEYB y
    define_bool CONFIG_I8259 y
@@ -297,7 +277,6 @@ if [ "$CONFIG_NEC_OSPREY" = "y" ]; then
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_IRQ_CPU y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_DUMMY_KEYB y
    define_bool CONFIG_SCSI n
 fi
@@ -307,7 +286,6 @@ if [ "$CONFIG_NEC_EAGLE" = "y" ]; then
    define_bool CONFIG_IRQ_CPU y
    define_bool CONFIG_NEW_TIME_C y
    define_bool CONFIG_VR41XX_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_ISA n
    define_bool CONFIG_PCI y
    define_bool CONFIG_NEW_PCI y
@@ -318,7 +296,6 @@ fi
 if [ "$CONFIG_NINO" = "y" ]; then
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
 fi
 if [ "$CONFIG_SGI_IP22" = "y" ]; then
@@ -330,10 +307,8 @@ if [ "$CONFIG_SGI_IP22" = "y" ]; then
    define_bool CONFIG_SWAP_IO_SPACE y
    define_bool CONFIG_IRQ_CPU y
    define_int CONFIG_L1_CACHE_SHIFT 5
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_SGI y
    define_bool CONFIG_SWAP_IO_SPACE y
@@ -345,6 +320,7 @@ if [ "$CONFIG_SGI_IP27" = "y" ]; then
    define_bool CONFIG_PCI y
    define_bool CONFIG_QL_ISP_A64 y
    define_int CONFIG_L1_CACHE_SHIFT 7
+   define_bool CONFIG_COHERENT_SYSTEM y
 fi
 if [ "$CONFIG_SGI_IP32" = "y" ]; then
    define_bool CONFIG_ARC_MEMORY y
@@ -353,7 +329,6 @@ if [ "$CONFIG_SGI_IP32" = "y" ]; then
    define_bool CONFIG_BOOT_ELF32 y
    define_int CONFIG_L1_CACHE_SHIFT 5
    define_bool CONFIG_MAPPED_PCI_IO n
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_PCI y
 fi
@@ -362,13 +337,13 @@ if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; th
    define_bool CONFIG_NEW_TIME_C y
    define_bool CONFIG_DUMMY_KEYB y
    define_bool CONFIG_SWAP_IO_SPACE y
+   define_bool CONFIG_COHERENT_SYSTEM y
 fi
 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
    define_bool CONFIG_ARC32 y
    define_bool CONFIG_I8259 y
    define_bool CONFIG_ISA y
    define_bool CONFIG_NEW_IRQ y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_OLD_TIME_C y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_PCI y
@@ -380,7 +355,6 @@ if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; 
    define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_SWAP_IO_SPACE y
    define_bool CONFIG_PC_KEYB y
 fi
@@ -391,7 +365,6 @@ if [ "$CONFIG_ZAO_CAPCELLA" = "y" ]; the
    define_bool CONFIG_IRQ_CPU y
    define_bool CONFIG_NEW_TIME_C y
    define_bool CONFIG_VR41XX_TIME_C y
-   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_ISA n
    define_bool CONFIG_PCI y
    define_bool CONFIG_NEW_PCI y
@@ -415,7 +388,8 @@ choice 'CPU type' \
 	 R39XX	CONFIG_CPU_TX39XX \
 	 R41xx	CONFIG_CPU_VR41XX \
 	 R4300	CONFIG_CPU_R4300 \
-	 R4x00	CONFIG_CPU_R4X00 \
+	 R4x00	CONFIG_CPU_R4X00XX \
+	 R4x00MC CONFIG_CPU_R4X00MC \
 	 R49XX	CONFIG_CPU_TX49XX \
 	 R5000	CONFIG_CPU_R5000 \
 	 R5432	CONFIG_CPU_R5432 \
@@ -426,6 +400,10 @@ choice 'CPU type' \
 	 RM7000	CONFIG_CPU_RM7000 \
 	 SB1	CONFIG_CPU_SB1" R4x00
 
+if [ "$CONFIG_CPU_R4X00XX"  = "y" -o "$CONFIG_CPU_R4X00MC" = "y" ]; then
+   define_bool CONFIG_CPU_R4X00 y
+fi
+
 if [ "$CONFIG_CPU_MIPS32" = "y" ]; then
    define_bool CONFIG_CPU_HAS_PREFETCH y
    bool '  Support for Virtual Tagged I-cache' CONFIG_VTAG_ICACHE
@@ -492,6 +470,19 @@ if [ "$CONFIG_CPU_R3000" = "y" ]; then
 else
    define_bool CONFIG_CPU_HAS_SYNC y
 fi
+if [ "$CONFIG_CPU_MIPS32"  = "y" -o \
+     "$CONFIG_CPU_MIPS64"  = "y" -o \
+     "$CONFIG_CPU_R4X00MC" = "y" -o \
+     "$CONFIG_CPU_R10000"  = "y" -o \
+     "$CONFIG_CPU_SB1"     = "y" ]; then
+   if [ "$CONFIG_COHERENT_SYSTEM" = "y" ]; then
+      define_bool CONFIG_NONCOHERENT_IO n
+   else
+      define_bool CONFIG_NONCOHERENT_IO y
+   fi
+else
+   define_bool CONFIG_NONCOHERENT_IO y
+fi
 endmenu