Subject: A question on Linux SMP and cache coherency

From: Adam Kiepul <[email-masked]>
Date: Thu, 23 Jan 2003 15:17:25 -0800

Hi,

I would really appreciate if anyone could tell me whether Hardware-maintained cache coherency between processors is required for Linux SMP operation.
Thank you very much,

Adam Kiepul

---

From: Ralf Baechle <[email-masked]>
Date: Fri, 24 Jan 2003 15:31:31 +0100

On Thu, Jan 23, 2003 at 03:17:25PM -0800, Adam Kiepul wrote:

> I would really appreciate if anyone could tell me whether
> Hardware-maintained cache coherency between processors is required for
> Linux SMP operation.

(Sending just one copy of a posting is sufficient ...)

There have been imho fairly ridiculous attempts at constructing dual-core
SMPs for the use with Linux/MIPS by changing the kernel to 16kB page
size [1] and using write through-caches plus some extra hacks.  Needless
to say the solution is about as stupid as something can be and is probably
going to perform worse than a uniprocessor ...

  Ralf

[1] good idea for other reasons but completly stupid in this context