Subject: Re: CVS [email-masked]: linux

From: Atsushi Nemoto <[email-masked]>
Date: Mon, 16 Jun 2003 10:19:11 +0900 (JST)

>>>>> On Sun, 15 Jun 2003 01:47:13 +0100, [email-masked] said:
> Modified files:
> 	arch/mips64    : Tag: linux_2_4 Makefile 
> 	include/asm-mips64: Tag: linux_2_4 processor.h r4kcache.h 

> Log message:
> 	Support GT64120 boards with 64-bit kernels also.

This corrupts mips64/mm/c-r4k.c.  Please apply this patch also.

diff -u linux-mips-cvs/arch/mips64/mm/c-r4k.c linux.new/arch/mips64/mm/c-r4k.c
--- linux-mips-cvs/arch/mips64/mm/c-r4k.c	Mon Apr 28 09:44:53 2003
+++ linux.new/arch/mips64/mm/c-r4k.c	Mon Jun 16 09:59:38 2003
@@ -26,7 +26,6 @@
 
 /* Primary cache parameters. */
 static unsigned long icache_size, dcache_size, scache_size;
-unsigned long icache_way_size, dcache_way_size, scache_way_size;
 static unsigned long scache_size;
 
 #include <asm/cacheops.h>
@@ -848,8 +847,8 @@
 		panic("Improper R4000SC processor configuration detected");
 
 	/* compute a couple of other cache variables */
-	icache_way_size = icache_size / c->icache.ways;
-	dcache_way_size = dcache_size / c->dcache.ways;
+	c->icache.waysize = icache_size / c->icache.ways;
+	c->dcache.waysize = dcache_size / c->dcache.ways;
 
 	c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
 	c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
@@ -862,7 +861,7 @@
 	 */
 	if (current_cpu_data.cputype != CPU_R10000 &&
 	    current_cpu_data.cputype != CPU_R12000)
-		if (dcache_way_size > PAGE_SIZE)
+		if (c->dcache.waysize > PAGE_SIZE)
 		        c->dcache.flags |= MIPS_CACHE_ALIASES;
 
 	if (config & 0x8)		/* VI bit */
diff -u linux-mips-cvs/arch/mips64/mm/sc-rm7k.c linux.new/arch/mips64/mm/sc-rm7k.c
--- linux-mips-cvs/arch/mips64/mm/sc-rm7k.c	Fri Apr 18 10:23:12 2003
+++ linux.new/arch/mips64/mm/sc-rm7k.c	Mon Jun 16 09:59:59 2003
@@ -20,8 +20,6 @@
 /* Secondary cache parameters. */
 #define scache_size	(256*1024)	/* Fixed to 256KiB on RM7000 */
 
-extern unsigned long icache_way_size, dcache_way_size;
-
 #include <asm/r4kcache.h>
 
 int rm7k_tcache_enabled;
---
Atsushi Nemoto

---

From: Atsushi Nemoto <[email-masked]>
Date: Mon, 16 Jun 2003 10:42:24 +0900 (JST)

>>>>> On Mon, 16 Jun 2003 10:19:11 +0900 (JST), Atsushi Nemoto <[email-masked]> said:

>> Support GT64120 boards with 64-bit kernels also.

nemoto> This corrupts mips64/mm/c-r4k.c.  Please apply this patch also.

And I doubt that 'unsigned short' is enough for the 'waysize'
(especially for scache).  How about this?

diff -u linux-mips-cvs/include/asm-mips64/processor.h linux.new/include/asm-mips64/processor.h
--- linux-mips-cvs/include/asm-mips64/processor.h	Mon Jun 16 09:33:42 2003
+++ linux.new/include/asm-mips64/processor.h	Mon Jun 16 10:40:19 2003
@@ -50,8 +50,8 @@
 	unsigned short linesz;	/* Size of line in bytes */
 	unsigned short ways;	/* Number of ways */
 	unsigned short sets;	/* Number of lines per set */
-	unsigned short waysize;	/* Bytes per way */
-	unsigned int waybit;	/* Bits to select in a cache set */
+	unsigned short waybit;	/* Bits to select in a cache set */
+	unsigned int waysize;	/* Bytes per way */
 	unsigned int flags;	/* Flags describing cache properties */
 };
 
---
Atsushi Nemoto

---

From: Atsushi Nemoto <[email-masked]>
Date: Mon, 16 Jun 2003 10:58:39 +0900 (JST)

>>>>> On Mon, 16 Jun 2003 10:42:24 +0900 (JST), Atsushi Nemoto <[email-masked]> said:

nemoto> And I doubt that 'unsigned short' is enough for the 'waysize'
nemoto> (especially for scache).  How about this?

Then this is a patch to sync 32-bit version.

diff -ur linux-mips-cvs/arch/mips/mm/c-r4k.c linux.new/arch/mips/mm/c-r4k.c
--- linux-mips-cvs/arch/mips/mm/c-r4k.c	Mon Apr 28 09:44:52 2003
+++ linux.new/arch/mips/mm/c-r4k.c	Mon Jun 16 10:43:21 2003
@@ -26,7 +26,6 @@

 

 	if (config & 0x8)		/* VI bit */
diff -ur linux-mips-cvs/arch/mips/mm/c-tx39.c linux.new/arch/mips/mm/c-tx39.c
--- linux-mips-cvs/arch/mips/mm/c-tx39.c	Tue May  6 09:40:58 2003
+++ linux.new/arch/mips/mm/c-tx39.c	Mon Jun 16 10:46:54 2003
@@ -25,9 +25,7 @@
 
 /* For R3000 cores with R4000 style caches */
 static unsigned long icache_size, dcache_size;		/* Size in bytes */
-static unsigned long icache_way_size, dcache_way_size;	/* Size divided by ways */
 #define scache_size 0
-#define scache_way_size 0

@@ -473,15 +471,15 @@
 		break;
 	}
 
-	icache_way_size = icache_size / current_cpu_data.icache.ways;
-	dcache_way_size = dcache_size / current_cpu_data.dcache.ways;
+	current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
+	current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
 
 	current_cpu_data.icache.sets =
-		icache_way_size / current_cpu_data.icache.linesz;
+		current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
 	current_cpu_data.dcache.sets =
-		dcache_way_size / current_cpu_data.dcache.linesz;
+		current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
 
-	if (dcache_way_size > PAGE_SIZE)
+	if (current_cpu_data.dcache.waysize > PAGE_SIZE)
 		current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
 
 	current_cpu_data.icache.waybit = 0;
diff -ur linux-mips-cvs/arch/mips/mm/sc-rm7k.c linux.new/arch/mips/mm/sc-rm7k.c
--- linux-mips-cvs/arch/mips/mm/sc-rm7k.c	Fri Apr 18 10:23:03 2003
+++ linux.new/arch/mips/mm/sc-rm7k.c	Mon Jun 16 10:44:02 2003
@@ -20,8 +20,6 @@
 /* Secondary cache parameters. */
 #define scache_size	(256*1024)	/* Fixed to 256KiB on RM7000 */

 int rm7k_tcache_enabled;
diff -ur linux-mips-cvs/include/asm-mips/processor.h linux.new/include/asm-mips/processor.h
--- linux-mips-cvs/include/asm-mips/processor.h	Thu May  8 10:28:23 2003
+++ linux.new/include/asm-mips/processor.h	Mon Jun 16 10:43:04 2003
@@ -34,11 +34,12 @@
  * Descriptor for a cache
  */
 struct cache_desc {
-	unsigned short linesz;
-	unsigned short ways;
-	unsigned int sets;
-	unsigned int waybit;	/* Bits to select in a cache set */
-	unsigned int flags;	/* Flags describingcache properties */
+	unsigned short linesz;	/* Size of line in bytes */
+	unsigned short ways;	/* Number of ways */
+	unsigned short sets;	/* Number of lines per set */
+	unsigned short waybit;	/* Bits to select in a cache set */
+	unsigned int waysize;	/* Bytes per way */
+	unsigned int flags;	/* Flags describing cache properties */
 };
 
 /*
diff -ur linux-mips-cvs/include/asm-mips/r4kcache.h linux.new/include/asm-mips/r4kcache.h
--- linux-mips-cvs/include/asm-mips/r4kcache.h	Mon Apr 28 09:44:57 2003
+++ linux.new/include/asm-mips/r4kcache.h	Mon Jun 16 10:42:51 2003
@@ -140,7 +140,7 @@
 static inline void blast_dcache16(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + dcache_way_size;
+	unsigned long end = start + current_cpu_data.dcache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
 	unsigned long ws_end = current_cpu_data.dcache.ways << 
 	                       current_cpu_data.dcache.waybit;
@@ -179,7 +179,7 @@
 static inline void blast_icache16(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + icache_way_size;
+	unsigned long end = start + current_cpu_data.icache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 	unsigned long ws_end = current_cpu_data.icache.ways <<
 	                       current_cpu_data.icache.waybit;
@@ -218,7 +218,7 @@
 static inline void blast_scache16(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + scache_way_size;
+	unsigned long end = start + current_cpu_data.scache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
 	unsigned long ws_end = current_cpu_data.scache.ways << 
 	                       current_cpu_data.scache.waybit;
@@ -283,7 +283,7 @@
 static inline void blast_dcache32(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + dcache_way_size;
+	unsigned long end = start + current_cpu_data.dcache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
 	unsigned long ws_end = current_cpu_data.dcache.ways <<
 	                       current_cpu_data.dcache.waybit;
@@ -322,7 +322,7 @@
 static inline void blast_icache32(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + icache_way_size;
+	unsigned long end = start + current_cpu_data.icache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 	unsigned long ws_end = current_cpu_data.icache.ways <<
 	                       current_cpu_data.icache.waybit;
@@ -361,7 +361,7 @@
 static inline void blast_scache32(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + scache_way_size;
+	unsigned long end = start + current_cpu_data.scache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
 	unsigned long ws_end = current_cpu_data.scache.ways << 
 	                       current_cpu_data.scache.waybit;
@@ -426,7 +426,7 @@
 static inline void blast_icache64(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + icache_way_size;
+	unsigned long end = start + current_cpu_data.icache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 	unsigned long ws_end = current_cpu_data.icache.ways <<
 	                       current_cpu_data.icache.waybit;
@@ -465,7 +465,7 @@
 static inline void blast_scache64(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + scache_way_size;
+	unsigned long end = start + current_cpu_data.scache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
 	unsigned long ws_end = current_cpu_data.scache.ways << 
 	                       current_cpu_data.scache.waybit;
@@ -530,7 +530,7 @@
 static inline void blast_scache128(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + scache_way_size;
+	unsigned long end = start + current_cpu_data.scache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
 	unsigned long ws_end = current_cpu_data.scache.ways << 
 	                       current_cpu_data.scache.waybit;
---
Atsushi Nemoto