Subject: bootloader problem

From: "He Jin" <[email-masked]>
Date: Mon, 16 Jun 2003 17:32:40 +0800

Hi, everybody,

I met a problem when debuging a bootloader in IT8172G+RM5231A platform, it's like this:

the bootloader had 2 parts, the first part executes in ROM (0xbfc00000-0xbfc0xxxx) and
it move another part from ROM into SDRAM, then jump to the SDRAM entry point to continue.

In the ROM resident code, if I initialized&flushed the cache, it can jump to SDRAM entry
continue normally. However,if I comment out those cache related code and make cache disabled, 
it seems can not jump to SDRAM entry. 

Who can tell me why I must initialize&flush when cache disabled ? 

Thanks a lot!

He Jin

---

From: "Kevin D. Kissell" <[email-masked]>
Date: Mon, 16 Jun 2003 13:20:02 +0200

> Who can tell me why I must initialize&flush when cache disabled ? 

Precisely what do you mean by "cache disabled",
and what is the address of the SDRAM entry?

            Kevin K.

---

From: "Joseph Chiu" <[email-masked]>
Date: Mon, 16 Jun 2003 16:49:29 -0700

Hi,
Is there a (proper) way to add a page entry in the TLB it's always valid?
Specifically, accesses to memory-mapped hardware (PCMCIA) causes the kernel
to oops under heavy interrupt loading.
It seems to me that the page entry in the TLB is getting flushed out under
the activity; and when the ioremap'd memory region is accesses, the
exception handling for the missing translation does not run.

I'm afraid my two days of googling hasn't turned up the right information.
I think I just don't know the right terminology and I hope someone can at
least point me in the right direction.
Thanks.
Joseph
(I am running 2.4.18)