Subject: Re: [RFC] synchronized CPU count registers on SMP machines

From: [email-masked] (Tor Arntsen)
Date: Thu, 5 Jun 2003 11:23:02 +0200

On Jun 5,  0:27, Ralf Baechle wrote:
>On Wed, Jun 04, 2003 at 03:39:30PM -0700, Jun Sun wrote:
>
>> 1) clocks on different CPUs don't have the same frequency
>> 2) clocks on different CPUs drift to each other
>> 2) some fancy power saving feature such as frequency scaling
>> 
>> But I think for a foreseeable future most MIPS SMP machines
>> don't have the above issues (true?).  And it is probably worthwile
>> to synchronize count registers for them.
>
>1) and 2) affect most SGI systems.
>
>  Ralf

1) sometimes to the extreme, on SGI Challenge systems:
 
>hinv -c processor
Processor 0: 150 MHZ IP19 
CPU: MIPS R4400 Processor Chip Revision: 5.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0
Processor 1: 150 MHZ IP19 
CPU: MIPS R4400 Processor Chip Revision: 5.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0
Processor 2: 200 MHZ IP19 
CPU: MIPS R4400 Processor Chip Revision: 6.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0
Processor 3: 200 MHZ IP19 
CPU: MIPS R4400 Processor Chip Revision: 6.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0

(and the secondary cache sizes are 1MB and 4MB respectively as well)

-Tor