Subject: wired tlb entry?

From: "Joseph Chiu" <[email-masked]>
Date: Mon, 16 Jun 2003 17:36:58 -0700

Hi,
Is there a (proper) way to add a page entry in the TLB it's always valid?
Specifically, accesses to memory-mapped hardware (PCMCIA) causes the kernel
to oops under heavy interrupt loading.
It seems to me that the page entry in the TLB is getting flushed out under
the activity; and when the ioremap'd memory region is accesses, the
exception handling for the missing translation does not run.

I'm afraid my two days of googling hasn't turned up the right information.
I think I just don't know the right terminology and I hope someone can at
least point me in the right direction.
Thanks.
Joseph
(I am running 2.4.18-mips)

--
Joseph Chiu, Senior Engineer, Omnilux, Inc.
[email-masked]  (626) 535-2819
The sun will come up tomorrow.  Bet your bottom dollar that tomorrow,
things'll be back.

---

From: Pete Popov <[email-masked]>
Date: 17 Jun 2003 10:18:54 -0700

> (I am running 2.4.18-mips)

So is this a kernel from linux-mips.org?  Are you using the 36 bit I/O
patch in that kernel, or the pseudo-address translation hack that I
removed later? What pcmcia I/O card are you using and what tests are you
running?

Pete

---

From: "Joseph Chiu" <[email-masked]>
Date: Tue, 17 Jun 2003 11:12:36 -0700

(Sorry for the double-send of the original inquiry to the list -- I actually
got bounce notices from my mailer...)

This is the kernel from almost a year ago with the changes you made to
support the 36-bit phys addr. access on the Au1xxx.
The Au1x00 PCMCIA (CS release 3.1.22) initialization maps phys_mem f80000000
to virt_io c0000000.

I am running HostAP (0.0.3) on top of this PCMCIA support, using a
Prism3-based WiFi card.

During transmit/receive activity, the hardware interrupt invokes the
prism2_interrupt() in hostap_cs.o which, in turn reads and writes from
registers using the virtual i/o address of c0000000.

Under light and moderate loading, there are no problems.  After heavy
traffic loads, the system eventually dies with accesses to address c000xxxx
(one address gets hit 95% of the time - and there were other addresses a few
other times, but always in the c000xxxx address range).

Thanks,
Joseph

-----Original Message-----
From: Pete Popov [mailto:[email-masked]]
Sent: Tuesday, June 17, 2003 10:19 AM
To: Joseph Chiu
Cc: Linux MIPS mailing list
Subject: Re: wired tlb entry?

Pete

---

From: Pete Popov <[email-masked]>
Date: 17 Jun 2003 11:16:40 -0700

Any chance you can try 2.4.21-pre4 (latest linux-mips) before we go any
further?

Pete

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From: "Joseph Chiu" <[email-masked]>
Date: Tue, 17 Jun 2003 11:51:13 -0700

Michael Guo suggested add_wired_entry -- I'm giving that a try now.  I'm
trying to stick to "the kernel that we trust" (from the perspective here)
because I'm worried about what I end up breaking trying to take a new
kernel.

I am behind the time, though, so I'll try to test out 2.4.21-pre4 when I get
back (I'm not available to run the tests during the rest of this week).

Thanks,
Joseph

-----Original Message-----
From: Pete Popov [mailto:[email-masked]]
Sent: Tuesday, June 17, 2003 11:17 AM
To: Joseph Chiu
Cc: Linux MIPS mailing list
Subject: RE: wired tlb entry?

Pete

---

From: Ralf Baechle <[email-masked]>
Date: Wed, 25 Jun 2003 06:59:16 +0200

> back (I'm not available to run the tests during the rest of this week).

Usual warning - wired entries are almost always a bad idea.  TLB entries
are a scarce resource and wiring will reduce the number available for
random replacement even further raising the amount of CPU burned in the
TLB reload handler.

  Ralf

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From: "Joseph Chiu" <[email-masked]>
Date: Wed, 25 Jun 2003 11:05:49 -0700

> random replacement even further raising the amount of CPU burned in the

Thanks Ralf.  It is "just one" wired global TLB entry (admiteddly, out of a
paltry 32).   Using the wired entry has fixed the immediate problem at hand,
so I decided it's worth it for now.

Joseph

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From: "Steven J. Hill" <[email-masked]>
Date: Thu, 26 Jun 2003 21:02:14 -0400

> so I decided it's worth it for now.
If you can, which board is this on?

-Steve

---

From: "Joseph Chiu" <[email-masked]>
Date: Fri, 27 Jun 2003 10:38:36 -0700

This is on our own board.  We're developing a optical wireless transceiver
system (see www.omnilux.net) and we use the Au1000 as the central
controller.

It's a pretty simple board -- the au1000 static bus interfaces connects to
FLASH, and two external peripheral devices; one of them being a PCMCIA card.
(We put the card directly on the bus -- no "end user proofing" buffers or
any such things).

The non-PCMCIA peripheral sits within the directly accessible low memory
range.  In fact, outside of user pages, the only thing that needs TLB is the
small windows pointing to the PCMCIA card.

Joseph
-----Original Message-----
From: Steven J. Hill [mailto:[email-masked]]
Sent: Thursday, June 26, 2003 6:02 PM
To: Joseph Chiu
Cc: Ralf Baechle; Pete Popov; Linux MIPS mailing list
Subject: Re: wired tlb entry?

-Steve