Subject: [PATCH] Fix r4k cache handling

From: Thiemo Seufer <[email-masked]>
Date: Tue, 1 Jul 2003 18:21:22 +0200

Hello Ralf,

I need the appended patch for my 5000/50, which has a R4000SC.

Thiemo

diff -BurpNX /home/ths/dontdiff linux-orig/arch/mips/mm/c-r4k.c linux/arch/mips/mm/c-r4k.c
--- linux-orig/arch/mips/mm/c-r4k.c	Tue May 13 23:32:50 2003
+++ linux/arch/mips/mm/c-r4k.c	Tue Jul  1 18:01:44 2003
@@ -27,7 +27,6 @@
 /* Primary cache parameters. */
 static unsigned long icache_size, dcache_size, scache_size;
 unsigned long icache_way_size, dcache_way_size, scache_way_size;
-static unsigned long scache_size;
 
 #include <asm/cacheops.h>
 #include <asm/r4kcache.h>
@@ -1084,6 +1083,11 @@ static void __init setup_scache(void)
 	     current_cpu_data.isa_level == MIPS_CPU_ISA_M64) &&
 	    !(current_cpu_data.scache.flags & MIPS_CACHE_NOT_PRESENT))
 		panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+
+	/* compute a couple of other cache variables */
+	scache_way_size = scache_size / c->scache.ways;
+
+	c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
 
 	printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
 	       scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
diff -BurpNX /home/ths/dontdiff linux-orig/include/asm-mips/r4kcache.h linux/include/asm-mips/r4kcache.h
--- linux-orig/include/asm-mips/r4kcache.h	Wed Apr 23 17:17:05 2003
+++ linux/include/asm-mips/r4kcache.h	Tue Jul  1 17:45:00 2003
@@ -111,6 +111,8 @@ static inline void invalidate_tcache_pag
 	cache_op(Page_Invalidate_T, addr);
 }
 
+extern unsigned long icache_way_size, dcache_way_size, scache_way_size;
+
 #define cache16_unroll32(base,op)				\
 	__asm__ __volatile__("					\
 		.set noreorder;					\