Subject: RM7k cache_flush_sigtramp

From: Fuxin Zhang <[email-masked]>
Date: Thu, 31 Jul 2003 09:56:08 +0800

hi,

r4k_cache_flush_sigtrap seems not enough for RM7000 cpus because
there is a writebuffer between L1 dcache & L2 cache,so the written back
block may not be seen by icache. This small patch fixes crashes of my
Xserver
on ev64240.

--- r4kcache.h.ori 2003-07-31 09:51:01.000000000 +0800
+++ r4kcache.h 2003-07-31 09:51:57.000000000 +0800
@@ -94,6 +94,9 @@
".set noreorder\n\t"
".set mips3\n"
"1:\tcache %0,(%1)\n"
+#ifdef CONFIG_CPU_RM7000
+ "sync\n\t"
+#endif
"2:\t.set mips0\n\t"
".set reorder\n\t"
".section\t__ex_table,\"a\"\n\t"

---

From: Ralf Baechle <[email-masked]>
Date: Thu, 31 Jul 2003 13:46:39 +0200

On Thu, Jul 31, 2003 at 09:56:08AM +0800, Fuxin Zhang wrote:
> Date:	Thu, 31 Jul 2003 09:56:08 +0800
> From:	Fuxin Zhang <[email-masked]>
> To:	MAKE FUN PRANK CALLS <[email-masked]>
        ^^^^^^^^^^^^^^^^^^^^

Funny name for the list :-)

> Xserver on ev64240.

It would seem a similar fix is also needed in other places then?

  Ralf

---

From: Fuxin Zhang <[email-masked]>
Date: Thu, 31 Jul 2003 20:57:59 +0800

>>To:	MAKE FUN PRANK CALLS <[email-masked]>
I have not thought about it further. But
  1. I implement wb_flush for this board,using sync and uncached read. 
Just in case
      so many buffer on the cpu and system bridge will surprise me.
  2. There are still occasionally oops, especially with IO 
activities,e.g.,when fscking a disk.

What would should suggest to look at? Some flushes will go through all 
levels of cache,
I think they should be safe. Will check later.

Thanks.