Subject: RE: How to request an IRQ for NMI on MIPS Processor

From: "Liu Hongming (Alan)" <[email-masked]>
Date: Tue, 11 Nov 2003 10:51:50 +0800

hi Malik,

when using request_irq(...),the parameter irq is a value specified by you,
of course,when porting linux for your board,you should have specified value
for every IRQ. 0--5 only means CPU pin for interrupt,unless that only one
interrupt
may occur on this pin,you will use other value in request_irq,instead of
0-5.
 
all in all, when we touch request_irq,it is board specific.When your board
has
been made out,all interrupts have specific route to cpu(unless you have IRQ
router,since embedded,need this??).If you have more external interrupts than
cpu pins,maybe you have cascaded many interrupt using one cpu pin.So,
the parameter irq in request_irq is determined by your board and your
porting
for interrupt handling.Just ask that guy that ported linux.He will tell
you.If you
are using linux ported by others,have a look at BSP codes.
 
Regards,
Alan Liu
 
-----Original Message-----
From: Adeel Malik [mailto:[email-masked]]
Sent: Tuesday, November 04, 2003 7:56 PM
To: [email-masked]
Subject: How to request an IRQ for NMI on MIPS Processor

Hi All,
          In my embedded design, I intend to use NMI of MIPS 4Kc processor
(rather than IRQ0 or IRQ1 .....) for an external Interrupt Source. The
external Interrupt source is a video capture device which interrupts the
MIPS 4Kc CPU via its NMI (Non-Maskable Interrupt) line, whenever it has one
complete frame. I need to write the driver for that device in Linux-2.4.20.
The request_irq function provided by Linux takes a digit value from 0 to 5
to map external interrupt sources to any one of CPUs Interrupt pins. How can
I request and implement my interrupt handler routine for the NMI of MIPS
processor ?.
 
Regards,
ADEEL MALIK,

---

From: Ralf Baechle <[email-masked]>
Date: Tue, 11 Nov 2003 04:40:12 +0100

Liu,

> are using linux ported by others,have a look at BSP codes.

your answer is correct for normal interrupts, not the NMI.  The NMI goes
through the firmware and none of the board support code so far bothered
to make it available via request_irq as it has several severe limitations.
To repeat one of my prior postings about the NMI:

NMI on MIPS is pretty much miss-designed for use in application code; it's
use should be limited to debugging and recovery from catastrophical
failure.  The reason for this is the way this exception is handled:
                                                                                
  - the BEV, TS, SR, NMI and ERL bits in c0_status are overwritten - that is
    their old state is lost.
  - c0_errorepc is overwritten - again that means the old value is lost so
    in case the NMI interrupts an exception handler that uses this register
    such as the cache error handler you can not resume execution.
  - the program counter is set to 0xbfc00000.  Most likely a slow flash
    memory is mapped at this address but in any case it's an uncached
    segment of the address space so execution will be even slower.
  - execution will pass through the firmware.  That means you can only
    use the NMI at all if firmware provides some kind of hook.
                                                                                
It seems pretty clear to me that the MIPS designers never intended the
NMI for anything else than catastrophic events.

  Ralf