Subject: Re: CVS [email-masked]: linux

From: "Maciej W. Rozycki" <[email-masked]>
Date: Mon, 2 Feb 2004 16:13:28 +0100 (CET)

On Mon, 2 Feb 2004 [email-masked] wrote:

> 	PMC-Sierra says that the workaround for errata #18 of the R4600 V1.7
> 	and a similar erratum in V2.0 don't require disabling of interrupts,
> 	so remove that code.

 How do we assure tails of interrupt handlers don't trigger the errata?

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: [email-masked], PGP key available        +

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From: Ralf Baechle <[email-masked]>
Date: Mon, 2 Feb 2004 16:23:07 +0100

>  How do we assure tails of interrupt handlers don't trigger the errata?

The problem can only be triggered if instructions surrounding the
cacheop use the dcache; exceptions such as interrupts are not relevant.

Which I'm really happy about.  Disabling interrupts is a problem in cases
were we can't avoid page faults.

  Ralf

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From: "Maciej W. Rozycki" <[email-masked]>
Date: Tue, 3 Feb 2004 16:30:33 +0100 (CET)

> cacheop use the dcache; exceptions such as interrupts are not relevant.

 Why?  How is an "eret" with its preceding instructions different to other 
instructions?  There may be a data cache miss soon before an "eret" and 
the response buffer may contain data.  And you may get an exeption right 
before a CACHE instruction.

> were we can't avoid page faults.

 I worry this is unsafe and given the unlikeliness of getting an interrupt
just between the dummy load and the CACHE instruction, this change creates
a completely obscure bug that'll bite unpredictably and possibly
invisibly, just corrupting data, every once and then.  But the situation
may be not that bad -- what does exactly happen when the erratum gets 
triggered?  Missing a Create_Dirty_Excl_D operation should itself be a 
performance hit only, but given the problems reported I suppose data gets 
corrupted, either in the cache or in the main memory.  Am I right?

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From: Ralf Baechle <[email-masked]>
Date: Tue, 3 Feb 2004 16:49:35 +0100

> corrupted, either in the cache or in the main memory.  Am I right?

I don't know details but since the person who answered my question was
directly working on the CPU design I have to take that as authoritative
information and after all, the systems seems stable.

Daring a guess, the CPU restarts the pipeline following an eret therefore
instructions preceeding the eret can't cause the problem.

  Ralf

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From: "Maciej W. Rozycki" <[email-masked]>
Date: Tue, 3 Feb 2004 17:04:44 +0100 (CET)

> information and after all, the systems seems stable.

 OK then.

> instructions preceeding the eret can't cause the problem.

 That's possible.