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To: linux-mips@linux-mips.org
Subject: possible overflow in __udelay
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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Current __udelay implementation will cause internal overflow on the
first multiplication.

Basically, the multiplication is:

X = usecs * 2**64 / (100000 / HZ)

And maximum input usecs value is 5000 (MAX_UDELAY_MS * 1000).

If usecs == 5000 and HZ == 1000, X is 5 * 2**64.  Of course this can
not be held in 64bit variable.

How should we avoid the overflow?


1. Use smaller HZ.

HZ < 200 should be OK.


2. Use smaller MAX_UDELAY_MS.

The arch specific delay.h can provide its own MAX_UDELAY_MS.
MAX_UDELAY_MS == 1 should be OK.


3. Use smaller multiplier.

This example should be OK (but lose some precision on larger HZ)

#if HZ < (1000 / MAX_UDELAY_MS)
	usecs *= (0x8000000000000000UL / (500000 / HZ));
#elif HZ < ((1000 / MAX_UDELAY_MS) << 1)
	usecs *= (0x8000000000000000UL / (500000 / HZ)) >> 1;
	lpj <<= 1
#elif HZ < ((1000 / MAX_UDELAY_MS) << 2)
	usecs *= (0x8000000000000000UL / (500000 / HZ)) >> 2;
	lpj <<= 2
#else
	usecs *= (0x8000000000000000UL / (500000 / HZ)) >> 3;
	lpj <<= 3
#endif


Any idea?

---
Atsushi Nemoto

From anemo@mba.ocn.ne.jp Thu Jul  1 14:16:20 2004
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To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
Subject: 2.4 pci_dma_sync_sg fix
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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pci_dma_sync_sg in 2.4 tree seems broken.  pci_map_sg were fixed a
while ago.  Please fix pci_dma_sync_sg also.

Here is a patch.

Index: pci.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/pci.h,v
retrieving revision 1.24.2.16
diff -u -r1.24.2.16 pci.h
--- pci.h	17 Nov 2003 01:07:45 -0000	1.24.2.16
+++ pci.h	1 Jul 2004 13:10:48 -0000
@@ -270,20 +270,28 @@
  */
 static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
 				   struct scatterlist *sg,
-				   int nelems, int direction)
+				   int nents, int direction)
 {
-#ifdef CONFIG_NONCOHERENT_IO
 	int i;
-#endif
 
 	if (direction == PCI_DMA_NONE)
 		out_of_line_bug();
 
-	/* Make sure that gcc doesn't leave the empty loop body.  */
-#ifdef CONFIG_NONCOHERENT_IO
-	for (i = 0; i < nelems; i++, sg++)
-		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
-#endif
+	for (i = 0; i < nents; i++, sg++) {
+		if (sg->address && sg->page)
+			out_of_line_bug();
+		else if (!sg->address && !sg->page)
+			out_of_line_bug();
+
+		if (sg->address) {
+			dma_cache_wback_inv((unsigned long)sg->address,
+			                    sg->length);
+		} else {
+			dma_cache_wback_inv((unsigned long)
+				(page_address(sg->page) + sg->offset),
+				sg->length);
+		}
+	}
 }
 
 /*
---
Atsushi Nemoto

From ralf@linux-mips.org Thu Jul  1 14:22:43 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org
Subject: Re: 2.4 pci_dma_sync_sg fix
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On Thu, Jul 01, 2004 at 10:21:20PM +0900, Atsushi Nemoto wrote:

> pci_dma_sync_sg in 2.4 tree seems broken.  pci_map_sg were fixed a
> while ago.  Please fix pci_dma_sync_sg also.

Leave the #ifdef stuff there - or otherwise gcc might optimize this into
empty loops ...

  Ralf

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Subject: Re: 2.4 pci_dma_sync_sg fix
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>>>>> On Thu, 1 Jul 2004 15:22:40 +0200, Ralf Baechle <ralf@linux-mips.org> said:

ralf> Leave the #ifdef stuff there - or otherwise gcc might optimize
ralf> this into empty loops ...

The loop contains paranoid out_of_line_bug, so it never be optimized
to empty.

---
Atsushi Nemoto

From ralf@linux-mips.org Thu Jul  1 17:03:52 2004
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From: Ralf Baechle <ralf@linux-mips.org>
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Subject: Re: 2.4 pci_dma_sync_sg fix
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On Thu, Jul 01, 2004 at 10:45:35PM +0900, Atsushi Nemoto wrote:

> >>>>> On Thu, 1 Jul 2004 15:22:40 +0200, Ralf Baechle <ralf@linux-mips.org> said:
> 
> ralf> Leave the #ifdef stuff there - or otherwise gcc might optimize
> ralf> this into empty loops ...
> 
> The loop contains paranoid out_of_line_bug, so it never be optimized
> to empty.

Indeed and I think that's a bit of overkill.  I've never seen these
assertions catch any bugs - and 2.4 isn't exactly new anymore.  Anyway,
even if the loop was empty gcc would not eleminate it.

  Ralf

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From macro@linux-mips.org Fri Jul  2 16:09:35 2004
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On Tue, 29 Jun 2004, Ralf Baechle wrote:

> How about you leave CONFIG_HAVE_STD_PC_SERIAL_PORT disabled for Malta then
> and supply your own MALTA_SERIAL_PORT_DEFNS instead then?  That would
> require some small changes to no longer nest the CONFIG_SERIAL_MANY_PORTS
> ifdef inside CONFIG_HAVE_STD_PC_SERIAL_PORT - about as below.

 I couldn't care less about CONFIG_SERIAL_MANY_PORTS for Malta -- the
ports it adds are AFAIK all ISA boards.  While in theory one can have a
PCI-ISA bridge and a bus extender on an option card (such devices exist,
I'm told), I don't think it's possible to use one with Malta as it already
includes a PCI-ISA bridge onboard.  If there's a need for such stuff in
the future, it can be added then.  After a brief look at the sources I
think the option itself might actually depend on CONFIG_ISA.

 So I propose the following simpler patch instead.  I'd like to have the
comment included so that no one tries to "fix" the order in the future
without a careful consideration.  It works for me.

 OK to apply?

  Maciej

patch-mips-2.4.26-20040531-mips-serial-2
diff -up --recursive --new-file linux-mips-2.4.26-20040531.macro/include/asm-mips/serial.h linux-mips-2.4.26-20040531/include/asm-mips/serial.h
--- linux-mips-2.4.26-20040531.macro/include/asm-mips/serial.h	2004-06-13 23:16:56.000000000 +0000
+++ linux-mips-2.4.26-20040531/include/asm-mips/serial.h	2004-07-02 00:40:52.000000000 +0000
@@ -410,14 +410,23 @@
 #define DDB5477_SERIAL_PORT_DEFNS
 #endif
 
+/*
+ * The order matters here and should be as follows:
+ *
+ * 1. board-specific ports (please keep sorted)
+ * 2. STD_SERIAL_PORT_DEFNS
+ * 3. EXTRA_SERIAL_PORT_DEFNS
+ * 4. HUB6_SERIAL_PORT_DFNS
+ *
+ * otherwise serial line numbers may change across
+ * kernel builds if configuration changes. --macro
+ */
 #define SERIAL_PORT_DFNS			\
 	ATLAS_SERIAL_PORT_DEFNS			\
 	AU1000_SERIAL_PORT_DEFNS		\
 	COBALT_SERIAL_PORT_DEFNS		\
 	DDB5477_SERIAL_PORT_DEFNS		\
 	EV96100_SERIAL_PORT_DEFNS		\
-	EXTRA_SERIAL_PORT_DEFNS			\
-	HUB6_SERIAL_PORT_DFNS			\
 	ITE_SERIAL_PORT_DEFNS           	\
 	IVR_SERIAL_PORT_DEFNS           	\
 	JAZZ_SERIAL_PORT_DEFNS			\
@@ -426,8 +435,11 @@
 	MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS	\
 	MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS	\
 	SEAD_SERIAL_PORT_DEFNS			\
-	STD_SERIAL_PORT_DEFNS			\
 	TITAN_SERIAL_PORT_DEFNS			\
-	TXX927_SERIAL_PORT_DEFNS
+	TXX927_SERIAL_PORT_DEFNS		\
+						\
+	STD_SERIAL_PORT_DEFNS			\
+	EXTRA_SERIAL_PORT_DEFNS			\
+	HUB6_SERIAL_PORT_DFNS
 
 #endif /* _ASM_SERIAL_H */
diff -up --recursive --new-file linux-mips-2.4.26-20040531.macro/include/asm-mips64/serial.h linux-mips-2.4.26-20040531/include/asm-mips64/serial.h
--- linux-mips-2.4.26-20040531.macro/include/asm-mips64/serial.h	2003-12-18 03:57:25.000000000 +0000
+++ linux-mips-2.4.26-20040531/include/asm-mips64/serial.h	2004-07-02 00:41:05.000000000 +0000
@@ -146,13 +146,23 @@
 #define IP27_SERIAL_PORT_DEFNS
 #endif /* CONFIG_SGI_IP27 */
 
+/*
+ * The order matters here and should be as follows:
+ *
+ * 1. board-specific ports (please keep sorted)
+ * 2. STD_SERIAL_PORT_DEFNS
+ *
+ * otherwise serial line numbers may change across
+ * kernel builds if configuration changes. --macro
+ */
 #define SERIAL_PORT_DFNS				\
 	IP27_SERIAL_PORT_DEFNS				\
 	MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS		\
 	MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS		\
 	SEAD_SERIAL_PORT_DEFNS				\
-	STD_SERIAL_PORT_DEFNS				\
-	TITAN_SERIAL_PORT_DEFNS
+	TITAN_SERIAL_PORT_DEFNS				\
+							\
+	STD_SERIAL_PORT_DEFNS
 
 #define RS_TABLE_SIZE	64
 

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       cond-mat@arXiv.org is a fully automated e-print archive for 
           condensed matter preprints (starting from April, 1992)

The list of subject classes within cond-mat is:

  Disordered Systems and Neural Networks,
  Materials Science (the mtrl-th archive has been moved into cond-mat),
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  Soft Condensed Matter,
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(From  Nov, 1994 though September 1996, there were also archives
 mtrl-th for materials theory, and supr-con for superconductivity.)


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-------------------------------------------------------------------------
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Outgoing mail from the e-print archive has the username no-reply
(to avoid problems due to occasional mail that bounces back).
Commands to the system should always be sent to arch-ive@arXiv.org
with the command in the subject field (e.g.  Subject: help).
Only one command at a time is accepted. Subscribers automatically
receive a listing of new titles/abstracts on days papers are received.

You will have a more pleasurable time using the archives if you read this
file carefully, read ALL responses you get to your interactions
with the archives, and follow the instructions therein.

This help file summarizes the email interface commands.

This information can be more easily accessed via the WorldWideWeb
at http://arXiv.org/help/ .

==========================================================================
Additional help is available by using the `get' command to retrieve the
following files:

(this file):    summary of e-mail commands

prep.txt:       how to prepare your abstract and paper for submission

submit.txt:     instructions for submitting to the archive

eput.txt:       instructions for e-mail submissions,
                including appraisal of different packaging formats

fput.txt:       how to use anonymous ftp to put and replace papers

utilities.txt:  utilities and applications to install for use
                with the archives, and where to find them for many platforms

sizes.txt:      how to slim down your PostScript files

==========================================================================

Summary of Commands for the e-Mail Interface:

All commands to arch-ive@xxx may be abbreviated by any truncation that includes
at least the first three letters (e.g. rep, sub, can, dis, lis, com, ...).
(The term arch-ive a generic one; substitute an appropriate archive name like
hep-th when actually doing something). The command must be given in the 
subject field (e.g., Subject: help ).


Commands for retrieving information
    (get, cget, uget, list, find, distribution):

  get <paper#>  <macroname>

    Returns paper specified by paper# (e.g. `get 9109001'), or macro specified
    by macroname.
    For abstracts alone, append .abs to the paper# (e.g. `get 9109001.abs').
    Multiple requests in one `get' are allowed and preferred.
    For example, `get 3 2.abs 9108001' returns multiple papers and abstracts.
    get defaults to the current year/month so that during 10/91,
    `get 1 2 5' or `get 01 2 005' will automatically prepend 9110's and the
    necessary zeroes to result in `get 9110001 9110002 9110005'.
    Numbers too large for the current year/month will have the previous
    year/month prepended. get also defaults to the current year, e.g.
    `get 9005' during  1995 gives `get 9509005', and months/numbers too big
    for the current year default to the previous year.
    You can freely mix formats, as in `get 1 08005 harvmac.tex 9109058 2.abs'.

    As of 1 Jan 1996, the get command returns a single uuencoded, gzipped,
    tar archive containing all files in a submission (except in the case
    of a submission consisting of a single file [e.g. TeX, PS, or PDF],
    which is instead just gzipped [i.e. not tarred] and uuencoded for e-mail).
    For utilities to unpack these, read utilities.txt
    (available via `get utilities.txt'). For those unable to process this new
    format, there is now the `uget' command.
    
  cget <paper#>

    Same as the get command, but the file is cut into multiple parts
    of size < 100 kB (195 blocks) to accommodate certain capricious
    or limited mail routers and to speed bitnet transmission.

  uget <paper#>

    Same as the get command, but files are unpacked from our storage
    format (gzipped tar files) and sent out individually. Meant for those
    unable to adapt to our new (1 Jan 1996) packaging. Users should feel
    encouraged to modernize to use gzip and tar (see utilities.txt
    for more info, including cross-platform availability) in order to use
    the normal get command.

  listing

    Returns list of year/month's currently available

  list <yymm's  macros  new  pastweek>

    Returns title/author's of papers currently held for given year/month
      subset, e.g. `list 9109'.
    `list macros' returns a list of the available TeX macros and various
      utilities such as reform and uufiles.
    `list new' resends the most recently sent title/abstract listing
      of papers received (typically from the previous day).
    `list pastweek' returns past week of title/author listings.
    For title/author/abstract's of papers held for given yr/mo subsets,
       append .abs: e.g.    `list 9109.abs 9110.abs'
    multiple requests allowed: e.g. `list 9109 9110.abs macros new pastweek'

  clist <yymm.abs ...>

    Same as the list command, but files are cut into multiple parts
    of size < 100 kB (195 blocks) to accommodate certain capricious
    or limited mail routers and to speed bitnet transmission.

  find <search-string>

    Searches the title/author list for search-string (either author or word in
    title, case insensitive) to retrieve paper number, e.g. `find goldstone'.
    Find defaults to the past 12 months, so for earlier years use e.g.
    `find goldstone 91'.

  distribution <name>

    Search for `name' in e-mail distribution list.


Commands for submitting information:
    (put, fput, replace, freplace, figures, add, cross, published)

  put

    Submit a paper (body of the message must be in the format
    described in prep.txt, available via `get prep.txt').
    Paper will be assigned a paper number, and added to the listings
    (do not `put'  the same paper to more than one e-print archive, instead use
    the `cross' command to cross list the paper). Never `put' the same
    paper twice. Instead use the `replace' command.
    The preferred format for `put' is TeX/LaTeX source. Please don't submit
    PostScript generated from TeX. We have an automatic TeX'ing script on-line
    that will generate PostScript from your TeX source. As of
    1 Jan 1996, all submissions are tested for automatic PostScript generation
    before they can be entered into the archives.
    See neworder.txt for more info.

  fput <filename1 ... filenameN>

    Submit a paper using ftp. First transfer files (filename1 ...) for
    paper via anonymous ftp to arXiv.org's /incoming ftp directory.
    Body of `fput' e-mail message is in same format as that of `put' command
    (i.e.  title/author and abstract fields delimited by \\'s), as described
    in prep.txt, but nothing need follow the final \\
    terminating the abstract. It is advisable to read the complete fput help
    before using (available via `get fput.txt' ).

  replace <paper#>

    Replace a paper specified by paper# with a revised version (only
    original submitter can do this, from the original e-mail account).
    The paper should be resubmitted in the same format as for the
    `put' command. Be sure to include the full abstract, since this is
    replaced as well, although it won't appear in the daily mailing
    (unless the `replace' is on the same day as the `put').
    The Comments: field (i.e. after Title: and Authors: ) should contain a
    short comment describing the severity of the changes so that others
    can determine if it is worth their time to get your paper again.
    Remember to include your original Comments: as well, because the
    replacement wipes these out, and
    the original comments still contain useful information.
    Any cross-listed entries, e.g. hep-ph/9204201 already cross-listed to
    hep-th, are automatically replaced, e.g. on hep-th,  when you replace
    hep-ph/9204201 on hep-ph -- additional action is no longer necessary.

    You must resend all files contained in your submission. You can only
    replace your entire submission. There is no way to replace only part
    of it (e.g. a single figure).

    In addition, replacements are subject to the same test for automatic
    processing as for puts.
    As of 1 Jan 1996, the text of the original submission is retained
    if it is replaced after the first day (i.e, if it has already appeared in a
    newlistings mailing). This is to prevent excessive backdating of content.
    (The original submissions are not currently publicly available, but
    will probably be made so at some later date.)
    If you are replacing a paper to update the results because of subsequent
    work by others, we require that you exercise professional
    courtesy and refer to this work, preferably in the Comments: field.
    (This avoids sticky priority disputes.)
    The replace command can be used to withdraw a paper from the archives.
    You cannot completely remove a paper that has appeared in a mailing;
    you can only replace it with a statement that it is withdrawn.

  freplace <paper#> <filename1 ... filenameN>

    Submit a replacement using anonymous ftp, where filename1 ... have
    already been deposited to arXiv.org's /incoming ftp directory.
    The paper number must be the FIRST argument.
    The body of an `freplace' message is the same as that for `fput'.
    Remember to include the full abstract.
    It is advisable to  read the complete `fput/freplace' help before using
    (available via `get fput.txt'). The caveats for the replace command
     apply here as well.

  figures <paper#>

    This command is now obsolete (1 Jan '96). All files should be sent in a
    single package. See eput.txt for more info.

  add <paper#>

    This command is now obsolete (1 Jan '96). If your mailer imposes size
    limits on outgoing mail, than you must use fput or freplace.

  cross <arch-ive/paper#>

    Cross-list paper from another e-print archive. e.g.
     a) first put paper To: hep-ph@arXiv.org which assigns it hep-ph/9204201
     b) wait until you see your paper listing in the next daily mailing.
        This is important because paper numbers are not permanent until then.
     c) then send an e-mail message (with blank message body)
                  To: astro-ph@arXiv.org
             Subject: cross hep-ph/9204201
        so that the hep-ph entry will appear as well on astro-ph.
       (NOTE: In the above case of a paper originally submitted to hep-ph,
        obviously do not send the cross-list command To: hep-ph@arXiv.org .)
    Generates abstract entry for daily listings and for access
    by `find' and `list' commands. Cross-listed papers must be obtained
    directly from the archive where the paper was originally submitted (i.e.
    hep-ph in example above).
       To cross-list to an archive that allows (or requires) subject classes,
       include your desired subject class at the end of the cross command, e.g.
                  To: physics@arXiv.org
             Subject: cross hep-th/9611010 Mathematical Methods in Physics
        This can also be used to cross-list submissions to different
       subject classes within an archive, e.g., for a submission originally
       submitted to the cond-mat archive with Subj-class: Materials Science,
                  To: cond-mat@arXiv.org
             Subject: cross cond-mat/9611010 Superconductivty
       will add Superconductivity as a secondary subject class.
    Note that cross-listings should not be abused and inappropriate crosses 
    will be removed.

  published <paper#> <reference>

    Adds a Journal reference to paper's entry, accessible via `find', `list',
    `list [].abs', `get [].abs' commands;
     e.g.,    `published 9107001 Rec. Jnl. 180 (1992) 101'.
    Journal-ref's should be complete bibliographic references, i.e. they
    should include the journal name, volume, year, and page number. Anything
    short of this belongs in the Comments: field.


Subscription commands
    (subscribe, cancel, subscribe all, cancel all):

  subscribe <your full name>

    Add new username to daily distribution list (e-mail address will
    automatically be extracted from return address), `your full name'
    is your full name (any number of words and initials) as you wish
    it to appear on the distribution list. <<<Note: `suscribe' is not
    a word>>> (It is of course no longer obvious why people subscribe
    for intrusive e-mail receipt of abstracts when they have www
    access on-demand from http://arXiv.org/ ). e-Mail addresses that
    bounce three consecutive times are automatically cancelled. If you do
    not receive a response to your `subscribe' message, it is most likely
    because your mailer is misconfigured and the return address in the
    From: line or Reply-To: line is broken. We have no way of contacting you
    if this is the case, so you are on your own to figure out what is wrong.

  cancel

    Remove user@nodename from daily distribution list. The e-mail address is
    extracted automatically, so cancel message must be sent from the same
    account as originally used to subscribe.
    Note that you may be subscribed instead through a remote listserv,
    or through some local preprint distribution list at your end.
    You can determine the origin of your subscription by examining the
    the header from the daily mailing you receive.
    If you no longer have access to your original subscription account,
    the administrators at arXiv.org may be able to cancel it for you.
    Send request as a comment, and be certain to
    to include the entire header of a daily abstract mailing that you have
    received so that we can determine how you are subscribed. (Do not send
    a useless header from the failed `cancel' or from a `get', etc.)

  subscribe all <password>

    Receive daily list of changes to database. The list of changes comes
    formatted in a form suitable for automated ftp scripts. The password
    will be added to the Subject: line of the daily message so that
    automated scripts can be reasonably sure that the messages are authentic.
    Don't use your account password. If you do not include a password
    then a random one will automatically be generated for you.

  cancel all

    Cancel previously entered `subscribe all'  (i.e. in order to no longer
    receive daily list of changes to database). `cancel all' will not
    cancel a regular subscription (one that sends you the complete abstracts
    each day). You must use the `cancel' command for
    each individual archive to which you are subscribed.


Miscellaneous commands
          (comment, help):

  comment

    Forward message for human perusal. If you have any doubts about
    how to submit something or where it should go, you can use this
    command to ask questions. They are usually answered on a one day
    turn around, often sooner. Style files of use to other authors
    can also be sent in, along with a one-line description of the style.

  help

    Returns this file.


---------------------------------------------------------------------

Do not make multiple requests for the same paper. If you receive nothing
(or if the response is slow) it means there is a problem at your end.

Anonymous ftp for getting and retrieving files is enabled on arXiv.org.
use   login: anonymous
      password: yourusername

  The relevant directories are  listings  and  papers  (the latter has
  subdirectories 9108, 9109, ...  ). If you are not already familiar with
  anonymous ftp, this is not a good place to practice.
  Papers can be put on the archives via anonymous ftp using `fput' and
  `freplace' (see above,  or `get fput.txt' for further info).

For european users, many of these databases are mirrored as
the equivalent arch-ive@babbage.sissa.it, which allows access both via the
above e-mail requests and via anonymous ftp.

WorldWideWeb access is available via  http://arXiv.org/
and other mirror sites worldwide

Some other e-print archives running the same software:

Physics
hep-th@arXiv.org             High Energy Physics - Theory, 8/91
hep-lat@arXiv.org            High Energy Physics - Lattice, 2/92
hep-ph@arXiv.org             High Energy Physics - Phenomenology, 3/92
astro-ph@arXiv.org           Astrophysics, 4/92
cond-mat@arXiv.org           Condensed Matter, 4/92
gr-qc@arXiv.org              General Relativity and Quantum Cosmology, 7/92
nucl-th@arXiv.org            Nuclear Theory, 10/92
chem-ph@arXiv.org            Chemical Physics, 3/94
hep-ex@arXiv.org             High Energy Physics - Experiment, 4/94
acc-phys@arXiv.org           Accelerator Physics, 11/94
mtrl-th@arXiv.org            Materials Theory, 11/94
supr-con@arXiv.org           Superconductivity, 11/94
nucl-ex@arXiv.org            Nuclear Experiment, 12/94
quant-ph@arXiv.org           Quantum Physics, 12/94
atom-ph@arXiv.org            Atomic, Molecular and Optical Physics, 9/95
plasm-ph@arXiv.org           Plasma Physics, 9/95
physics@arXiv.org            Physics, 10/96

Mathematics
alg-geom@arXiv.org           Algebraic Geometry, 2/92
funct-an@arXiv.org           Functional Analysis, 4/92
dg-ga@arXiv.org              Differential Geometry, 6/94
q-alg@qrXiv.org              Quantum Algebra and Topology, 12/94

Other
nlin-sys@arXiv.org           Nonlinear Sciences, 1/93
cmp-lg@arXiv.org             Computation and Language, 4/94
ao-sci@arXiv.org             Atmospheric-Oceanic Sciences, 2/95

---------------------------------------------------------------------
Disclaimer:
Problems printing a paper should be directed to its authors.
Papers will be entered in the listings in order of receipt on an impartial
basis and appearance of a paper is not intended in any way to convey
tacit approval of its assumptions, methods, or conclusions by any agent
(electronic, mechanical, or other).
We reserve the right to reject any inappropriate submissions.

This e-print archive should not be used to distribute non-technical information
(such as news or information about political causes of potential special
interest to the academic community). Finally, this is an e-print archive.
Submissions of an abstract without a paper will be rejected outright.


From anemo@mba.ocn.ne.jp Sat Jul  3 13:39:08 2004
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Message-Id: <20040703.214411.74757075.anemo@mba.ocn.ne.jp>
To: ralf@linux-mips.org
Cc: linux-mips@linux-mips.org
Subject: Re: 2.4 pci_dma_sync_sg fix
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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	<20040701135919.GA6906@linux-mips.org>
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>>>>> On Thu, 1 Jul 2004 15:59:19 +0200, Ralf Baechle <ralf@linux-mips.org> said:

>> The loop contains paranoid out_of_line_bug, so it never be
>> optimized to empty.

ralf> Indeed and I think that's a bit of overkill.  I've never seen
ralf> these assertions catch any bugs - and 2.4 isn't exactly new
ralf> anymore.  Anyway, even if the loop was empty gcc would not
ralf> eleminate it.

Then how about this?

Index: pci.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/pci.h,v
retrieving revision 1.24.2.16
diff -u -r1.24.2.16 pci.h
--- pci.h	17 Nov 2003 01:07:45 -0000	1.24.2.16
+++ pci.h	3 Jul 2004 12:30:36 -0000
@@ -281,8 +281,16 @@
 
 	/* Make sure that gcc doesn't leave the empty loop body.  */
 #ifdef CONFIG_NONCOHERENT_IO
-	for (i = 0; i < nelems; i++, sg++)
-		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
+	for (i = 0; i < nelems; i++, sg++) {
+		if (sg->address) {
+			dma_cache_wback_inv((unsigned long)sg->address,
+			                    sg->length);
+		} else {
+			dma_cache_wback_inv((unsigned long)
+				(page_address(sg->page) + sg->offset),
+				sg->length);
+		}
+	}
 #endif
 }
 

From milang@tal.org Sun Jul  4 11:12:43 2004
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From: "Kaj-Michael Lang" <milang@tal.org>
To: "linux-mips" <linux-mips@linux-mips.org>
Subject: something like sparc32/setarch for mips?
Date: Sun, 4 Jul 2004 13:16:35 +0300
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Is there something like sparc32 or setarch for mips ?

-- 
Kaj-Michael Lang , milang@tal.org

From yuasa@hh.iij4u.or.jp Sun Jul  4 16:30:02 2004
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Date: Mon, 5 Jul 2004 00:29:56 +0900
From: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: yuasa@hh.iij4u.or.jp, linux-mips <linux-mips@linux-mips.org>
Subject: [PATCH] vr41xx: fixes the compile error in giu.c
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Hi Ralf,

The following patch fixes the compile error in arch/mips/vr41xx/common/giu.c.

Please apply this patch to v2.6 CVS tree.

Yoichi

diff -urN -X dontdiff linux-orig/arch/mips/vr41xx/common/giu.c linux/arch/mips/vr41xx/common/giu.c
--- linux-orig/arch/mips/vr41xx/common/giu.c	Mon Jun 28 11:12:23 2004
+++ linux/arch/mips/vr41xx/common/giu.c	Mon Jul  5 00:11:01 2004
@@ -63,6 +63,12 @@
 
 static uint32_t giu_base;
 
+static struct irqaction giu_cascade = {
+	.handler	= no_action,
+	.mask		= CPU_MASK_NONE,
+	.name		= "cascade",
+};
+
 #define read_giuint(offset)		readw(giu_base + (offset))
 #define write_giuint(val, offset)	writew((val), giu_base + (offset))
 
@@ -303,7 +309,6 @@
 };
 
 static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS];
-static struct irqaction giu_cascade = {no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 
 static int no_irq_number(int irq)
 {

From yuasa@hh.iij4u.or.jp Sun Jul  4 16:32:44 2004
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To: Ralf Baechle <ralf@linux-mips.org>
Cc: yuasa@hh.iij4u.or.jp, linux-mips <linux-mips@linux-mips.org>
Subject: [PATCH] vr41xx: fixes the initialization error in icu.c
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Hi Ralf,

The following patch fixes the initialization error in arch/mips/vr41xx/common/icu.c.

Please apply this patch to v2.6 CVS tree.

Yoichi

diff -urN -X dontdiff linux-orig/arch/mips/vr41xx/common/icu.c linux/arch/mips/vr41xx/common/icu.c
--- linux-orig/arch/mips/vr41xx/common/icu.c	Thu May 27 02:11:11 2004
+++ linux/arch/mips/vr41xx/common/icu.c	Mon Jul  5 00:10:57 2004
@@ -51,6 +51,12 @@
 static uint32_t icu1_base;
 static uint32_t icu2_base;
 
+static struct irqaction icu_cascade = {
+	.handler	= no_action,
+	.mask		= CPU_MASK_NONE,
+	.name		= "cascade",
+};
+
 static unsigned char sysint1_assign[16] = {
 	0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
 static unsigned char sysint2_assign[16] = {
@@ -673,8 +679,6 @@
 early_initcall(vr41xx_icu_init);
 
 /*=======================================================================*/
-
-static struct irqaction icu_cascade = {no_action, 0, 0, "cascade", NULL, NULL};
 
 static inline void init_vr41xx_icu_irq(void)
 {

From sshtylyov@dev.rtsoft.ru Mon Jul  5 16:04:44 2004
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Hi.

     I have discovered that the gdb-low.S trashes the LO reg. instead of 
restoring it. This was fixed for the 2.6 kernels but, as it seems, was left 
unfixed in the earlier ones (run into this on 2.4.18/2.4.20). Here's the patch
against the lastest 2.4.x revision of the file...

Index: linux/arch/mips/kernel/gdb-low.S
===================================================================
RCS file: /home/cvs/linux/arch/mips/kernel/gdb-low.S,v
retrieving revision 1.11.2.3
diff -a -u -r1.11.2.3 gdb-low.S
--- linux/arch/mips/kernel/gdb-low.S	20 Feb 2003 18:19:01 -0000	1.11.2.3
+++ linux/arch/mips/kernel/gdb-low.S	5 Jul 2004 14:48:08 -0000
@@ -283,7 +283,7 @@
  		lw	v0,GDB_FR_HI(sp)
  		lw	v1,GDB_FR_LO(sp)
  		mthi	v0
-		mtlo	v0
+		mtlo	v1
  		lw	ra,GDB_FR_REG31(sp)
  		lw	fp,GDB_FR_REG30(sp)
  		lw	gp,GDB_FR_REG28(sp)


From thomas.kunze@xmail.net Tue Jul  6 09:12:21 2004
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Date: Tue, 06 Jul 2004 01:12:20 -0800
From: Thomas Kunze <thomas.kunze@xmail.net>
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Subject: Linux on SNI RM300E ?
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Hi,

i've tried to install Debian Woody MIPS on my SNI RM300E but i can't get it work.
bootp() and tftp() works. the bios load's the tftpboot.img over the net. after that
only an exception appears on the screen. the boot screen looks like this:

Obtaining /tftpboot/sash_pci from server
2027520+1762928+95120 entry 0x8800246C

EXCEPTION: <vector=UTLBMiss>
EXCEPTION pc: 0x8800246C
Cause register: 0x800C
Status register: 0x200010003
Bad Vaddress: 0x3C40

is anybody out there how can help me?

with best regards
thomas

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From thomas.kunze@xmail.net Tue Jul  6 10:14:22 2004
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Date: Tue, 06 Jul 2004 02:14:20 -0800
From: Thomas Kunze <thomas.kunze@xmail.net>
To: a.voropay@vmb-service.ru
Cc: linux-mips@linux-mips.org
Subject: RE: Linux on SNI RM300E ?
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Quoting Alexander Voropay <a.voropay@vmb-service.ru>:

>  AFAIK, the RM300E is an ARC compatible. (?)
i don't no. i saw something like that on the net. but nothing about that in the manuals
that i have.
> 
>  So, try to load "arcdiag" utility instead of kernel :
> 
> ftp://ftp.sra.co.jp/pub/os/NetBSD/misc/arc/
> 
i've downloaded the arcdiag-0.2 and served it via tftp. but the RM300E don't like that
file. it only says "Bad magic number". what does this mean (little/bigendian)? 

the same error-message appears when the to load mipsel boot-images.

with best regards
thomas

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From ica2_ts@csv.ica.uni-stuttgart.de Tue Jul  6 11:06:52 2004
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To: Thomas Kunze <thomas.kunze@xmail.net>
Cc: a.voropay@vmb-service.ru, linux-mips@linux-mips.org
Subject: Re: Linux on SNI RM300E ?
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Thomas Kunze wrote:
> Quoting Alexander Voropay <a.voropay@vmb-service.ru>:
> 
> >  AFAIK, the RM300E is an ARC compatible. (?)
> i don't no. i saw something like that on the net. but nothing about that in the manuals
> that i have.

It is, AFAIK. But the woody kernel is for a SGI Indy/Indigo2, not for
RM300E. The linux-mips.org tree has only support for RM200C, adding
support for RM300E is probably not that complicated if it is similiar
enough.

> >  So, try to load "arcdiag" utility instead of kernel :
> > 
> > ftp://ftp.sra.co.jp/pub/os/NetBSD/misc/arc/
> > 
> i've downloaded the arcdiag-0.2 and served it via tftp. but the RM300E don't like that
> file. it only says "Bad magic number". what does this mean (little/bigendian)? 

Wrong endianness. Your machine apparently has big endian firmware.


Thiemo

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Subject: RE: Linux on SNI RM300E ?
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>i've downloaded the arcdiag-0.2 and served it via tftp. but the RM300E
don't like that file.
>it only says "Bad magic number". what does this mean
(little/bigendian)? 

>the same error-message appears when the to load mipsel boot-images.

 Do you have an originas OS (SINIX ?) supplied with this server ?
Try a `file` GNU utility:
$ file <ANY_BINARIES_FROM_THE_ORIGINAL_OS>
or
$ file <KERNEL_IMAGE_FROM_THE_ORIGINAL_OS>

 Some modern loaders requires ELF binaries (not COFF) so you should
know a full binary file format to load (ELF/COFF/little/bigendian).


--
-=AV=-



From thomas.kunze@xmail.net Tue Jul  6 11:41:19 2004
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Date: Tue, 06 Jul 2004 03:41:17 -0800
From: Thomas Kunze <thomas.kunze@xmail.net>
To: a.voropay@vmb-service.ru
Cc: linux-mips@linux-mips.org
Subject: RE: Linux on SNI RM300E ?
References: <03a001c46342$84ce7210$0200000a@ALEC>
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>  Do you have an originas OS (SINIX ?) supplied with this server ?
> Try a `file` GNU utility:
> $ file <ANY_BINARIES_FROM_THE_ORIGINAL_OS>
> or
> $ file <KERNEL_IMAGE_FROM_THE_ORIGINAL_OS>
> 
>  Some modern loaders requires ELF binaries (not COFF) so you should
> know a full binary file format to load (ELF/COFF/little/bigendian).

yepp, sinix reliant 5.44 is installed and boots up. BUT, i have no login no password.
and the previous owner can't remember any login or password. also, i don't have any
orig. CD's for the RM300E. it seems that the machine is running in bigendian mode.

with best regards
thomas

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From jbglaw@dvmwest.gt.owl.de Tue Jul  6 11:45:54 2004
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From: Jan-Benedict Glaw <jbglaw@lug-owl.de>
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Subject: Re: Linux on SNI RM300E ?
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On Tue, 2004-07-06 03:41:17 -0800, Thomas Kunze <thomas.kunze@xmail.net>
wrote in message <1089110477.40ea81cd8e976@www.x-mail.net>:
> >  Do you have an originas OS (SINIX ?) supplied with this server ?
> > Try a `file` GNU utility:
> > $ file <ANY_BINARIES_FROM_THE_ORIGINAL_OS>
> > or
> > $ file <KERNEL_IMAGE_FROM_THE_ORIGINAL_OS>
> >=20
> >  Some modern loaders requires ELF binaries (not COFF) so you should
> > know a full binary file format to load (ELF/COFF/little/bigendian).
>=20
> yepp, sinix reliant 5.44 is installed and boots up. BUT, i have no login =
no password.
> and the previous owner can't remember any login or password. also, i don'=
t have any
> orig. CD's for the RM300E. it seems that the machine is running in bigend=
ian mode.

I don't know what filesystem Sinix used, maybe you can rip off the
disks and attach them to any other Linux box. Possibly you can mount the
filesystem(s), but even if not, you can use a hex editor to zero out
root's password on the raw disk :-)

MfG, JBG

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From thomas.kunze@xmail.net Tue Jul  6 11:48:09 2004
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From: Thomas Kunze <thomas.kunze@xmail.net>
To: "Thiemo Seufer" <ica2_ts@csv.ica.uni-stuttgart.de>
Cc: linux-mips@linux-mips.org
Subject: Re: Linux on SNI RM300E ?
References: <038c01c46334$38621de0$0200000a@ALEC> <1089105260.40ea6d6cf2f9c@www.x-mail.net> <20040706100647.GB21982@rembrandt.csv.ica.uni-stuttgart.de>
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Quoting Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>:

> It is, AFAIK. But the woody kernel is for a SGI Indy/Indigo2, not for
> RM300E. The linux-mips.org tree has only support for RM200C, adding
> support for RM300E is probably not that complicated if it is similiar
> enough.

OK. what are the next steps to get a bigendian bootimage for the RM300E? 
are there any sources available to compile for the RM300? 
is there a bootimage for the RM200C that i can give a try?

with best regards
thomas
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From ica2_ts@csv.ica.uni-stuttgart.de Tue Jul  6 12:41:05 2004
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Date: Tue, 6 Jul 2004 13:41:02 +0200
To: Thomas Kunze <thomas.kunze@xmail.net>
Cc: linux-mips@linux-mips.org
Subject: Re: Linux on SNI RM300E ?
Message-ID: <20040706114102.GC21982@rembrandt.csv.ica.uni-stuttgart.de>
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Thomas Kunze wrote:
> Quoting Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>:
> 
> > It is, AFAIK. But the woody kernel is for a SGI Indy/Indigo2, not for
> > RM300E. The linux-mips.org tree has only support for RM200C, adding
> > support for RM300E is probably not that complicated if it is similiar
> > enough.
> 
> OK. what are the next steps to get a bigendian bootimage for the RM300E? 
> are there any sources available to compile for the RM300? 
> is there a bootimage for the RM200C that i can give a try?

I would try current CVS HEAD, compile the RM200C configuration and
see where it dies. No need to bother about a complete boot image
at this stage. Welcome to the world of kernel porting. :-)

(You need a kernel converted to ECOFF for this, like it is done
for some other machines via elf2ecoff.)


Thiemo

From thomas.kunze@xmail.net Tue Jul  6 15:11:55 2004
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Date: Tue, 06 Jul 2004 07:11:53 -0800
From: Thomas Kunze <thomas.kunze@xmail.net>
To: linux-mips@linux-mips.org
Subject: bootimage for RM300E ?
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Quoting Alexander Voropay <a.voropay@vmb-service.ru>:

> 
> >OK. what are the next steps to get a bigendian bootimage for the
> RM300E? 
> >are there any sources available to compile for the RM300? 
> >is there a bootimage for the RM200C that i can give a try?
> 
> 1) Install a bigendian toolchain at the x86 host box and recompile the
> Linux kernel.
> P.5  http://howto.linux-mips.org/mips-howto.html

ok i downloaded toolchain. 
which kernel should i use? that one from kernel.org or from linux-mips.org ?
what should be done next, after create a kernel ? 
what do i need to create a bootimage for the RM300 ?
how must this bootimage looks like ?
any howto's ?

with best regards
thomas
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From jbglaw@dvmwest.gt.owl.de Tue Jul  6 16:16:09 2004
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On Tue, 2004-07-06 07:11:53 -0800, Thomas Kunze <thomas.kunze@xmail.net>
wrote in message <1089123113.40eab32979315@www.x-mail.net>:
> Quoting Alexander Voropay <a.voropay@vmb-service.ru>:
> > 1) Install a bigendian toolchain at the x86 host box and recompile the
> > Linux kernel.
> > P.5  http://howto.linux-mips.org/mips-howto.html
>=20
> ok i downloaded toolchain.=20
> which kernel should i use? that one from kernel.org or from linux-mips.or=
g ?

linux-mips.org, current CVS checkout. However, I can't tell you if
you're better off using HEAD or the linux_2_4 branch (probably HEAD,
though...).

> what should be done next, after create a kernel ?=20
> what do i need to create a bootimage for the RM300 ?
> how must this bootimage looks like ?
> any howto's ?

Try to feed the kernel image either as ELF or ECOFF via network. The
first step is to make the machine actually *accept* the image (let alone
properly executing it).

MfG, JBG

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From ralf@linux-mips.org Tue Jul  6 20:35:17 2004
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From: Ralf Baechle <ralf@linux-mips.org>
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On Tue, Jul 06, 2004 at 01:12:20AM -0800, Thomas Kunze wrote:

> i've tried to install Debian Woody MIPS on my SNI RM300E but i can't get
> it work.

I support the RM200C in the little endian configuration and I'm probably the
only user of Linux on an RM machine at all.  Afaik no little endian systems
have been shipped since SNI and Microsoft axed NT for MIPS making my
configuration extremly rare and I've not been able to obtain the big endian
firmware for the system - which is showing signs of upcoming hardware death
so whenever that happens I won't be able to support the SNI [1] code anymore.
Just to make life a little bit more misserable I only have hardware
documentation on the RM200/300 C (possibly D, would have to check) series
so I have not idea to what degree the architecture differs the RM300.

Conversion of the existing code to work on a big endian RM200/300C would
be easy to do though and I can help whoever wants to try ...

  Ralf

[1] RM hardware dumped in front of my door accepted ;-)

From ralf@linux-mips.org Tue Jul  6 20:38:49 2004
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On Tue, Jul 06, 2004 at 07:11:53AM -0800, Thomas Kunze wrote:

> ok i downloaded toolchain. 
> which kernel should i use? that one from kernel.org or from linux-mips.org ?

Wipe the word kernel.org from your brain ;-)

> what should be done next, after create a kernel ? 
> what do i need to create a bootimage for the RM300 ?
> how must this bootimage looks like ?

Just "make rm200_defconfig; make" which will build vmlinux.ecoff which is
the file which can be netbooted via bootp/tftp.  Same procedure as with
SGI machines basically so the usual howtos for SGI IP22 netbooting Linux
apply.

> any howto's ?

In the back of my brain.

  Ralf

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Date: Tue, 6 Jul 2004 16:00:50 -0700 (PDT)
From: Song Wang <wsonguci@yahoo.com>
Subject: kbuild support to build one module with multiple separate components? 
To: linux-mips@linux-mips.org
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Hi, Folks

I'm puzzled by the kbuild system in 2.6 kernel.
I want to write a kernel module, which consists of
several components. The module is produced by
linking these components. These components are located
in separate subdirectories (for example A, B,C). 
Each component is generated also by linking 
multiple files. (For example, a_1.c, a_2.c for
building A.o, b_1.c, b_2.c for building B.o, then A.o
and B.o
should be linked to produce mymodule.o) 

I know if I put all the files in a single directory
The makefile of the module looks like

obj-$(CONFIG_MYMODULE) += mymodule.o
mymodule-objs := a_1.o a_2.o b_1.o b_2.o c_1.o c_2.o

It should work. But it is really messy, especially
there are a lot of files or each component requires
different EXTRA_CFLAGS. However, if I write
separate Makefiles for each component in their own
subdirectory, the Makefile of component A looks like

obj-y := A.o (or obj-$(CONFIG_MYMODULE) +=  A.o)
A-objs := a_1.o a_2.o

And the Makefile of mymodule looks like
obj-$(CONFIG_MYMODULE) +=  A/

This is wrong, because kbuild will treat A as
independent module. All I want is to treat
A as component of the only module mymodule.o. It
should be linked to mymodule.o

Any idea on how to write a kbuild Makefile to
support such kind of single module produced
by linking multiple components and each component
is located in separate directory? Thanks.

-Song




		
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From macindiard@vsnl.net Wed Jul  7 04:22:17 2004
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From: "hemanth" <macindiard@vsnl.net>
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Subject: querries on cross compiler
Date: Wed, 7 Jul 2004 08:52:14 +0530
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Hi,

Iam trying to build a cross compiler for MIPS processor on
"i686-pc-linux-gcc" host. Iam getting some errors during the installation of
BINUTILS(binutils-2.9.1) i.e, after configure, when I type "make" Iam
getting errors. Can u please suggest how to remove these errors.

These are the errors,
root@localhost binutils-2.9.1]# make

make[1]: Entering directory `/root/cross_compiler/binutils-2.9.1/libiberty'

if [ -n "" ] && [ ! -d pic ]; then \

mkdir pic; \

else true; fi

touch stamp-picdir

echo "# !Automatically generated from ./functions.def"\

"- DO NOT EDIT!" >needed2.awk

grep '^DEFVAR(' < ./functions.def \

| sed -e '/DEFVAR/s|DEFVAR.\([^,]*\).*|/\1/ { printf "#ifndef
NEED_\1\\n#define NEED_\1\\n#endif\\n" }|' \

>>needed2.awk

grep '^DEFFUNC(' < ./functions.def \

| sed -e '/DEFFUNC/s|DEFFUNC.\([^,]*\).*|/\1/ { printf "#ifndef
NEED_\1\\n#define NEED_\1\\n#endif\\n" }|' \

>>needed2.awk

gcc -c -g -O2 -I. -I./../include ./dummy.c 2>/dev/null

make[1]: *** [dummy.o] Error 1

make[1]: Leaving directory `/root/cross_compiler/binutils-2.9.1/libiberty'

make: *** [all-libiberty] Error 2

regards,
Hemanth
MACIL
Electronics city
Bangalore



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Gave a shot at building a 2.6.7-bk13 kernel checkout (20040707) for SGI 
O2 w/ gcc-3.4.1.  Didn't get very far...

First was the old "accum" issue visited back in April[1].  Maciej posted 
a patch to 2.4, which I used to generate a similar patch for 2.6. 
arch/mips/kernel/time.c needed the same four removals of accum as the 
2.4 patch did, but there was one instance of "accum" in 
arch/mips/kernel/cpu-bugs64.c (which seems to be the one accum Maciej's 
2.4 patch removed from cpu-probe.c).  The attached patch removes these 
as per the discussion in April.

Following that, the build, while filled with a gazillion warnings about 
passing different var types to functions, built fine.  The resulting 
kernel even booted -- a little.  The second attached file has the Oops, 
which happens right after "Checking for the daddiu bug... no.".

Ideas on this, anyone?  I haven't tried this on a raq2/mipsel yet, but I 
can if needed


--Kumba


[1]: http://www.linux-mips.org/archives/linux-mips/2004-04/msg00049.html

-- 
"Such is oft the course of deeds that move the wheels of the world: 
small hands do them because they must, while the eyes of the great are 
elsewhere."  --Elrond

--------------060201020207080706050901
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System Maintenance Menu

1) Start System
2) Install System Software
3) Run Diagnostics
4) Recover System
5) Enter Command Monitor

Option? 5
Command Monitor.  Type "exit" to return to the menu.
>
>
> bootp(): root=/dev/sda3 console=ttyS0,38400
Setting $netaddr to 192.168.1.12 (from server )
Obtaining  from server
5034117+171179 entry: 0xffffffff8046f020
Linux version 2.6.7-mipscvs-20040707 (root@khazad-dum) (gcc version 3.4.1 (Gentoo Linux 3.4.1, ssp-3.4-2, pie-8.7.6.3)) #2 Wed Jul 7 04
:18:31 EDT 2004
ARCH: SGI-IP32
PROMLIB: ARC firmware Version 1 Revision 10
CPU revision is: 00002321
FPU revision is: 00002310
CRIME id a rev 1 at 0x0000000014000000
Determined physical RAM map:
 memory: 0000000000002000 @ 0000000000000000 (reserved)
 memory: 0000000000002000 @ 0000000000002000 (usable)
 memory: 00000000004f7000 @ 0000000000004000 (reserved)
 memory: 0000000000855000 @ 00000000004fb000 (usable)
 memory: 00000000002b0000 @ 0000000000d50000 (ROM data)
 memory: 0000000000100000 @ 0000000001000000 (reserved)
 memory: 0000000000300000 @ 0000000001100000 (ROM data)
 memory: 000000000ac00000 @ 0000000001400000 (usable)
On node 0 totalpages: 49152
  DMA zone: 49152 pages, LIFO batch:12
  Normal zone: 0 pages, LIFO batch:1
  HighMem zone: 0 pages, LIFO batch:1
Built 1 zonelists
Kernel command line: root=/dev/sda3 console=ttyS0,38400 root=/dev/sda3 console=ttyS0,38400
Primary instruction cache 32kB, physically tagged, 2-way, linesize 32 bytes.
Primary data cache 32kB 2-way, linesize 32 bytes.
R5000 SCACHE size 1024kB, linesize 32 bytes.
PID hash table entries: 1024 (order 10: 16384 bytes)
Calibrating system timer... 200 MHz CPU detected
Using 100.250 MHz high precision timer.
Console: colour dummy device 80x25
CRIME memory error at 0x3fffffe0 ST 0x0400a828<INV,RE,REID=0x28,NONFATAL>
Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
Memory: 181248k/184668k available (3279k kernel code, 3164k reserved, 1241k data, 396k init, 0k highmem)
Calibrating delay loop... 199.68 BogoMIPS
Mount-cache hash table entries: 256 (order: 0, 4096 bytes)
Checking for 'wait' instruction...  available.
Checking for the multiply/shift bug... no.
Checking for the daddi bug... no.
Checking for the daddiu bug... no.
CPU 0 Unable to handle kernel paging request at virtual address 0000000000000028, epc == ffffffff80088290, ra == ffffffff80088298
Oops in arch/mips/mm/fault.c::do_page_fault, line 167[#1]:
Cpu 0
$ 0   : 0000000000000000 0000000000000018 0000000000000000 ffffffff80398000
$ 4   : ffffffff81715d60 0000000000000000 0000000000000000 000000000000000d
$ 8   : ffffffff8bfd0068 ffffffffffffffff ffffffff8bfd0010 000000000000ffff
$12   : 0000000000000030 ffffffff8020bc44 ffffffff8bfd2e40 ffffffffffffffff
$16   : 0000000000000000 ffffffffffffffe9 ffffffff81715e60 ffffffff81715d60
$20   : ffffffffa13fb98c ffffffff81072430 ffffffff81054100 0000000000000000
$24   : 0000000000000001 0000000000000020
$28   : ffffffff8038c000 ffffffff8038fd80 0000000000000001 ffffffff80088298
Hi    : 0000000000000000
Lo    : 0000000000000e00
epc   : ffffffff80088290 pgd_current+0xfffffffeffb8d568/0xfffffffeffe3d050     Not tainted
ra    : ffffffff80088298 pgd_current+0xfffffffeffb8d570/0xfffffffeffe3d050
Status: 9401fce3    KX SX UX KERNEL EXL IE
Cause : 80000008
BadVA : 0000000000000028
PrId  : 00002321
Process swapper (pid: 0, threadinfo=ffffffff8038c000, task=ffffffff80398000)
Stack : 0000000000000004 0000000000000000 ffffffff803b97c0 0000000000000004
        0000000000000800 000000000000003c 000000000000003e 0000000000000004
        ffffffff8038fe20 0000000000000000 0000000000000000 ffffffff80004470
        0000000000800b00 ffffffffa13fb028 ffffffffa13fb98c ffffffff81072430
        ffffffff81054100 0000000000000000 0000000000000001 ffffffff8000c7f8
        000000000000003c ffffffff8003a928 ffffffff800102f8 ffffffffa13fb028
        0000000000000000 ffffffff81072430 00000000000013bf 0000000000000001
        0000000000800b00 0000000000000000 ffffffff8038ff70 dfffffffffffffff
        ffffffff804d3f50 0000000000000804 0000000000000001 0000000000000100
        0000000000000000 ffffffff804ef1a8 0000000000000000 0000000000000800
        ...
Call Trace:
 [<ffffffff80004470>] pgd_current+0xfffffffeffb09748/0xfffffffeffe3d050
 [<ffffffff8000c7f8>] pgd_current+0xfffffffeffb11ad0/0xfffffffeffe3d050
 [<ffffffff8003a928>] pgd_current+0xfffffffeffb3fc00/0xfffffffeffe3d050
 [<ffffffff800102f8>] pgd_current+0xfffffffeffb155d0/0xfffffffeffe3d050
 [<ffffffff80004470>] pgd_current+0xfffffffeffb09748/0xfffffffeffe3d050
 [<ffffffff8000441c>] pgd_current+0xfffffffeffb096f4/0xfffffffeffe3d050
 [<ffffffff8000aa80>] pgd_current+0xfffffffeffb0fd58/0xfffffffeffe3d050
 [<ffffffff8000441c>] pgd_current+0xfffffffeffb096f4/0xfffffffeffe3d050
 [<ffffffff8046f8d4>] pgd_current+0xfffffffefff74bac/0xfffffffefff932b8
 [<ffffffff8046f8cc>] pgd_current+0xfffffffefff74ba4/0xfffffffefff932b8
 [<ffffffff8046f0a0>] pgd_current+0xfffffffefff74378/0xfffffffefff932b8


Code: 0040982d  3c02804e  dc4251d0 <0c0255e6> dc440028  10400098  0040802d  0c02205a  0040202d
Kernel panic: Attempted to kill the idle task!
In idle task - not syncing

--------------060201020207080706050901
Content-Type: text/plain;
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--- arch/mips/kernel/time.c.orig	2004-07-07 03:56:59.819260432 -0400
+++ arch/mips/kernel/time.c	2004-07-07 03:58:16.645581056 -0400
@@ -278,7 +278,7 @@ static unsigned long fixed_rate_gettimeo
 	__asm__("multu	%1,%2"
 		: "=h" (res)
 		: "r" (count), "r" (sll32_usecs_per_cycle)
-		: "lo", "accum");
+		: "lo");
 
 	/*
 	 * Due to possible jiffies inconsistencies, we need to check
@@ -333,7 +333,7 @@ static unsigned long calibrate_div32_get
 	__asm__("multu  %1,%2"
 		: "=h" (res)
 		: "r" (count), "r" (quotient)
-		: "lo", "accum");
+		: "lo");
 
 	/*
 	 * Due to possible jiffies inconsistencies, we need to check
@@ -375,7 +375,7 @@ static unsigned long calibrate_div64_get
 				: "r" (timerhi), "m" (timerlo),
 				  "r" (tmp), "r" (USECS_PER_JIFFY),
 				  "r" (USECS_PER_JIFFY_FRAC)
-				: "hi", "lo", "accum");
+				: "hi", "lo");
 			cached_quotient = quotient;
 		}
 	}
@@ -389,7 +389,7 @@ static unsigned long calibrate_div64_get
 	__asm__("multu	%1,%2"
 		: "=h" (res)
 		: "r" (count), "r" (quotient)
-		: "lo", "accum");
+		: "lo");
 
 	/*
 	 * Due to possible jiffies inconsistencies, we need to check
--- arch/mips/kernel/cpu-bugs64.c.orig	2004-07-07 04:54:01.762046056 -0400
+++ arch/mips/kernel/cpu-bugs64.c	2004-07-07 04:54:26.501285120 -0400
@@ -82,7 +82,7 @@ static inline void mult_sh_align_mod(lon
 		".set	pop"
 		: "=&r" (lv1), "=r" (lw)
 		: "r" (m1), "r" (m2), "r" (s), "I" (0)
-		: "hi", "lo", "accum");
+		: "hi", "lo");
 	/* We have to use single integers for m1 and m2 and a double
 	 * one for p to be sure the mulsidi3 gcc's RTL multiplication
 	 * instruction has the workaround applied.  Older versions of

--------------060201020207080706050901--

From milang@tal.org Wed Jul  7 15:36:46 2004
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From: "Kaj-Michael Lang" <milang@tal.org>
To: <linux-mips@linux-mips.org>
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Subject: Re: querries on cross compiler
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> Iam trying to build a cross compiler for MIPS processor on
> "i686-pc-linux-gcc" host. Iam getting some errors during the installation
of
> BINUTILS(binutils-2.9.1) i.e, after configure, when I type "make" Iam
> getting errors. Can u please suggest how to remove these errors.

That binutils is extremly old, try using something a little more uptodate...
I'd recommend using crosstool to build you cross compiler.

-- 
Kaj-Michael Lang , milang@tal.org


From anemo@mba.ocn.ne.jp Wed Jul  7 15:52:01 2004
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Message-Id: <20040707.235723.74756758.anemo@mba.ocn.ne.jp>
To: linux-mips@linux-mips.org
Subject: Re: possible overflow in __udelay
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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>>>>> On Thu, 01 Jul 2004 21:14:56 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> said:

anemo> Current __udelay implementation will cause internal overflow on
anemo> the first multiplication.

anemo> Basically, the multiplication is:

anemo> X = usecs * 2**64 / (100000 / HZ)

anemo> And maximum input usecs value is 5000 (MAX_UDELAY_MS * 1000).

anemo> If usecs == 5000 and HZ == 1000, X is 5 * 2**64.  Of course
anemo> this can not be held in 64bit variable.

anemo> How should we avoid the overflow?

anemo> ....

Don't you really have any comments?

I believe, for example, mdelay(10) does not work properly on most MIPS
ports (except for DECSTATION and JAZZ which have smaller HZ value).

---
Atsushi Nemoto

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To: linux-mips@linux-mips.org
Subject: Re: possible overflow in __udelay
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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>>>>> On Wed, 07 Jul 2004 23:57:23 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> said:

anemo> I believe, for example, mdelay(10) does not work properly on
anemo> most MIPS ports (except for DECSTATION and JAZZ which have
anemo> smaller HZ value).

Oops, mdelay(10) should work.  But mdelay(5) (mdelay(MAX_UDELAY_MS))
does not work.

---
Atsushi Nemoto

From ralf@linux-mips.org Thu Jul  8 01:49:54 2004
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On Mon, May 31, 2004 at 08:21:01PM -0700, Randy.Dunlap wrote:

> irix_getdomainname() max size appears to be off by 1;
> other similar code in kernel uses __NEW_UTS_LEN as the max size,
> and <domainname> includes an extra byte for the terminating
> null character.
> 
> Does sysirix.c need to limit <len> to 63 instead of 64 for some
> reason?

I would know why - and it has other bugs also, so I removed it by the
normal Linux getdomainname(2) for SysV flavour syscalls, too.

  Ralf

From ralf@linux-mips.org Thu Jul  8 01:59:46 2004
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Date: Thu, 8 Jul 2004 02:59:45 +0200
From: Ralf Baechle <ralf@linux-mips.org>
To: Mika Kukkonen <mika@osdl.org>
Cc: Andrew Morton <akpm@osdl.org>, linux-mips@linux-mips.org
Subject: Re: MIPS defines __kernel_uid_t as int?
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On Wed, Jul 07, 2004 at 11:13:16AM -0700, Mika Kukkonen wrote:

> I was doing
> 	$ grep __kernel_uid_t include/*/posix_types.h
> 
> and noticed that MIPS is the only architecture that
> defines that to be signed (int) and not unsigned?
> 
> Same with __kernel_uid32_t. Is this intentional
> deviation or just an oversight?

Intentional but with a really weak reason.  Linux/MIPS uses the same
type definitions as SysV rsp. the MIPS ABI in it's EFT (Extended
Fundamental Types).  Not a great idea in retroperspective but that's a
choice made 10 years ago.

I don't think we'd break anything by changing this.  Objections to
changing it?

  Ralf

From ralf@linux-mips.org Thu Jul  8 02:43:33 2004
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Date: Thu, 8 Jul 2004 03:43:30 +0200
From: Ralf Baechle <ralf@linux-mips.org>
To: Kaj-Michael Lang <milang@tal.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Subject: Re: something like sparc32/setarch for mips?
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On Sun, Jul 04, 2004 at 01:16:35PM +0300, Kaj-Michael Lang wrote:

> Is there something like sparc32 or setarch for mips ?

Surprise.  It's called mips32 :-)  and - surprise #2 it's on
available on ftp.linux-mips.org.

  Ralf

From asridhars@gmail.com Thu Jul  8 07:38:45 2004
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Date: Thu, 8 Jul 2004 12:08:40 +0530
From: Sridhar Adagada <asridhars@gmail.com>
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Subject: Optimisation
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Hello everybody,

I am sorry if the mail is too long had to include assembly code, which
i am still learning.

I am trying some optimization on some my code.  Listed below is the
c-code of a function which is obvious,  but the assembly from compiler
with optimization for speed, is confusing to me can any one explain?

As you can see $6 is the length, my confusion is at the lines 12-14,
19, 20 why is the length added with 65535 and the comparison with 0
for max and the right shift.  The same operation is done the base ($7)
 can any one explain why this is needed.  Can i replace all these
three instructions with "ori $9 $0 $6"

One more thing does the instruction at line 25 "madl    $25, $24" do?

Any help with be greatly appresciated

Thanks
Sri

C-code:
short cal_xxx(short *abs, short *coef, short len, short base)
{
 short i;
 short sum = 0;

 for (i = 0; i < length; i++)
 {
   sum += ( (unsigned int)abs[i] * (unsigned int)coef[i] );
 }
 return ( ((sum + 1 << (base -1)) >> base) );
}

Assmebly code:
    1         .set    noat
    2         .set    noreorder
    3         .set    nomacro
    4         .text
    5         .align  4
    6         .globl  cal_xxx
    7 /*  short i;
    8     short sum = 0; */
    9         ori     $9, $0, 0
   10         ori     $3, $0, 0
   11 /*  for( i = 0; i < length; i++ ) */
   12         andi    $6, $6, 65535
   13         imax    $8, $6, 0
   14         srl     $10, $8, 3
   15         beq     $10, $0, .L62
   16         andi    $7, $7, 65535
   17         move    $2, $5
   18         move    $11, $4
   19         sll     $24, $10, 3
   20         andi    $9, $24, 65528
   21 .L78:
   22         lh      $25, 0($11)
   23         lh      $24, 0($2)
   24         mtlo    $3
   25         madl    $25, $24
   26         lh      $25, 2($11)
   27         lh      $24, 2($2)
   28         nop
   29         madl    $25, $24
   30         lh      $25, 4($11)
   31         lh      $24, 4($2)
   32         nop
   33         madl    $25, $24
   34         lh      $25, 6($11)
   35         lh      $24, 6($2)
   36         nop
   37         madl    $25, $24
   38         lh      $25, 8($11)
   39         lh      $24, 8($2)
   40         nop
   41         madl    $25, $24
   42         lh      $25, 10($11)
   43         lh      $24, 10($2)
   44         nop
   45         madl    $25, $24
   46         lh      $25, 12($11)
   47         lh      $24, 12($2)
   48         nop
   49         madl    $25, $24
   50         lh      $25, 14($11)
   51         lh      $24, 14($2)
   52         addiu   $10, $10, -1
   53         madl    $25, $24
   54         addiu   $11, $11, 16
   55         addiu   $2, $2, 16
   56         mflo    $3
   57         bne     $10, $0, .L78
   58         nop
   59         nop
   60 .L62:
   61         andi    $10, $8, 7
   62         beq     $10, $0, .L44
   63         sll     $9, $9, 1
   64         addu    $2, $5, $9
   65         addu    $25, $4, $9
   66         addiu   $10, $10, -1
   67 .L1000082:
   68         lh      $15, 0($2)
   69         lh      $24, 0($25)
   70         mtlo    $3
   71         madl    $24, $15
   72         addiu   $25, $25, 2
   73         addiu   $2, $2, 2
   74         mflo    $3
   75         bne     $10, $0, .L1000082
   76         addiu   $10, $10, -1
   77 .L44:
   78 /*     } for-end */
   79         addiu   $25, $7, -1
   80         ori     $15, $0, 1
   81         sllv    $24, $15, $25
   82         addu    $14, $3, $24
   83         srav    $13, $14, $7
   84         sll     $2, $13, 16
   85  #          .ef
   86         jr      $ra
   87         sra     $2, $2, 16
   88         .type   cal_xxx,@function
   89         .size   cal_xxx,.-cal_xxx
   90         .align  4
   91  #i     $9      local
   92  #sum   $3      local
   93
   94  #abs  $4      param
   95  #coef $5      param
   96  #length        $6      param
   97  #base  $7      param
   98
   99         .data
  100 .L139:
  101         .text
  102 /*  } end-function */

From geert@linux-m68k.org Thu Jul  8 09:46:21 2004
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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Ralf Baechle <ralf@linux-mips.org>
cc: "Randy.Dunlap" <rddunlap@osdl.org>,
	Linux/MIPS Development <linux-mips@linux-mips.org>
Subject: Re: [PATCH] MIPS getdomainname() off by 1;
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On Thu, 8 Jul 2004, Ralf Baechle wrote:
> On Mon, May 31, 2004 at 08:21:01PM -0700, Randy.Dunlap wrote:
> > irix_getdomainname() max size appears to be off by 1;
> > other similar code in kernel uses __NEW_UTS_LEN as the max size,
> > and <domainname> includes an extra byte for the terminating
> > null character.
> >
> > Does sysirix.c need to limit <len> to 63 instead of 64 for some
> > reason?
>
> I would know why - and it has other bugs also, so I removed it by the
> normal Linux getdomainname(2) for SysV flavour syscalls, too.

I saw you even removed it from 2.0. Woow! ;-)

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

From geert@linux-m68k.org Thu Jul  8 10:00:00 2004
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To: Sridhar Adagada <asridhars@gmail.com>
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On Thu, 8 Jul 2004, Sridhar Adagada wrote:
> As you can see $6 is the length, my confusion is at the lines 12-14,
> 19, 20 why is the length added with 65535 and the comparison with 0

It's not `added with 65535', but `ANDed with 65535'. MIPS32 has 32-bit integer
operations only. If you want to do 16-bit math, all data has to be masked.

Anyway, for performance, it's better to do 32-bit math only.

> short cal_xxx(short *abs, short *coef, short len, short base)
> {
>  short i;
>  short sum = 0;
>
>  for (i = 0; i < length; i++)
>  {
>    sum += ( (unsigned int)abs[i] * (unsigned int)coef[i] );

Why cast to unsigned int while sum is a short? Unless you really want to rely
on sum being a short, you better make it int and do the truncation to short
after the loop.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

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From: Sridhar Adagada <asridhars@gmail.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Subject: Re: Optimisation
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Thank you.  For some reason i have been reading ANDI ans ADDI.  But i
am still confused at lines 13, 14 and 15
  13         imax    $8, $6, 0
  14         srl     $10, $8, 3
  15         beq     $10, $0, .L62

Thanks for correcting me

Sri


On Thu, 8 Jul 2004 10:59:58 +0200 (MEST), Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Thu, 8 Jul 2004, Sridhar Adagada wrote:
> > As you can see $6 is the length, my confusion is at the lines 12-14,
> > 19, 20 why is the length added with 65535 and the comparison with 0
> 
> It's not `added with 65535', but `ANDed with 65535'. MIPS32 has 32-bit integer
> operations only. If you want to do 16-bit math, all data has to be masked.
> 
> Anyway, for performance, it's better to do 32-bit math only.
> 
> > short cal_xxx(short *abs, short *coef, short len, short base)
> > {
> >  short i;
> >  short sum = 0;
> >
> >  for (i = 0; i < length; i++)
> >  {
> >    sum += ( (unsigned int)abs[i] * (unsigned int)coef[i] );
> 
> Why cast to unsigned int while sum is a short? Unless you really want to rely
> on sum being a short, you better make it int and do the truncation to short
> after the loop.
> 
> Gr{oetje,eeting}s,
> 
>                                                Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                                            -- Linus Torvalds
>

From geert@sonycom.com Thu Jul  8 10:50:16 2004
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Date: Thu, 8 Jul 2004 15:18:35 +0530
From: Sridhar Adagada <asridhars@gmail.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Subject: Re: Optimisation
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Thank you! I got it now If the length is less then 7, the loop is
handled differently for the fast access of the abs and coef.

Thanks you very much
Sri

On Thu, 8 Jul 2004 14:51:59 +0530, Sridhar Adagada <asridhars@gmail.com> wrote:
> Thank you.  For some reason i have been reading ANDI ans ADDI.  But i
> am still confused at lines 13, 14 and 15
>  13         imax    $8, $6, 0
>  14         srl     $10, $8, 3
>  15         beq     $10, $0, .L62
> 
> Thanks for correcting me
> 
> Sri
> 
> 
> 
> 
> On Thu, 8 Jul 2004 10:59:58 +0200 (MEST), Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > On Thu, 8 Jul 2004, Sridhar Adagada wrote:
> > > As you can see $6 is the length, my confusion is at the lines 12-14,
> > > 19, 20 why is the length added with 65535 and the comparison with 0
> >
> > It's not `added with 65535', but `ANDed with 65535'. MIPS32 has 32-bit integer
> > operations only. If you want to do 16-bit math, all data has to be masked.
> >
> > Anyway, for performance, it's better to do 32-bit math only.
> >
> > > short cal_xxx(short *abs, short *coef, short len, short base)
> > > {
> > >  short i;
> > >  short sum = 0;
> > >
> > >  for (i = 0; i < length; i++)
> > >  {
> > >    sum += ( (unsigned int)abs[i] * (unsigned int)coef[i] );
> >
> > Why cast to unsigned int while sum is a short? Unless you really want to rely
> > on sum being a short, you better make it int and do the truncation to short
> > after the loop.
> >
> > Gr{oetje,eeting}s,
> >
> >                                                Geert
> >
> > --
> > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> >
> > In personal conversations with technical people, I call myself a hacker. But
> > when I'm talking to journalists I just say "programmer" or something like that.
> >                                                            -- Linus Torvalds
> >
>

From ralf@linux-mips.org Thu Jul  8 11:57:06 2004
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On Thu, Jul 08, 2004 at 10:46:19AM +0200, Geert Uytterhoeven wrote:

> > > Does sysirix.c need to limit <len> to 63 instead of 64 for some
> > > reason?
> >
> > I would know why - and it has other bugs also, so I removed it by the
> > normal Linux getdomainname(2) for SysV flavour syscalls, too.
> 
> I saw you even removed it from 2.0. Woow! ;-)

Yep :-)  But whoever is still runing 2.0 on MIPS must be suffering from a
suicidal tendences.  Too many bugs left unfixed.

  Ralf

From ralf@linux-mips.org Thu Jul  8 12:43:27 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: Sergei Shtylyov <sshtylyov@dev.rtsoft.ru>
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Subject: Re: LO reg. gets trashed by kgdb in 2.4.x and older kernels
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On Mon, Jul 05, 2004 at 07:05:14PM +0400, Sergei Shtylyov wrote:

>     I have discovered that the gdb-low.S trashes the LO reg. instead of 
> restoring it. This was fixed for the 2.6 kernels but, as it seems, was left 
> unfixed in the earlier ones (run into this on 2.4.18/2.4.20). Here's the 
> patch
> against the lastest 2.4.x revision of the file...

Thanks.  This also was an ancient bug probably dating back to late '94 or
early '95 so all branches other than 2.6 were affected.

  Ralf

From ralf@linux-mips.org Thu Jul  8 13:50:27 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: Trivial Patch Monkey <trivial@rustcorp.com.au>
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Subject: Re: [TRIVIAL] [TRIVIAL 2.6] arch_mips_pmc-sierra_yosemite_setup.c: kill
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Dear Patchmonkey,

On Wed, Jul 07, 2004 at 05:22:24PM +1000, Trivial Patch Monkey wrote:
> Subject: [TRIVIAL] [TRIVIAL 2.6] arch_mips_pmc-sierra_yosemite_setup.c: kill
> From: Trivial Patch Monkey <trivial@rustcorp.com.au>

>     ./arch/mips/pmc-sierra/yosemite/setup.c: asm/bootinfo.h is included more than once.
>   
>   Against 2.6.5. Thanks.

Applied,

  Ralf

From Volker.Jahns@thalreit.de Thu Jul  8 13:52:52 2004
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Subject: sharp mobilon hc-4100 
From: "Volker Jahns" <Volker.Jahns@thalreit.de>
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Linux on Sharp Mobilon HC-4100

I would like to have Linux boot on the Sharp HC-4100 and have tried a
couple of suitable kernels with the following outcome:

Booting
-------
netbsd tx3912               - netbsd 1.5.3 , keyboard functional
linux for philips velo      - vmlinux-2.4.0-test4-pre3 , keyboard not
functional


Booting, but framebuffer scrambled
----------------------------------
linux nino                  - vmlinux-2.4.17
linux sharp HC-4500/HC-4600 - vmlinux-2.3.21. vmlinux-2.3.47

I have tried to compile a kernel from versions - 2.4.20 and 2.4.0-test9 -
( sharp mobilon, philips velo, philips nino) which all boot but have the
framebuffer device scrambled.

Which kernel version is good to start from, and where would I find its code ?
Has somebody a working .config vor the Velo 500 available, so that I get
the correct options to have this damn framebuffer device working?


Please redirect, in case this should be the wrong place to post.
-- 
Volker Jahns, volker@thalreit.de, http://thalreit.de, DG7PM


From ricardo.mendoza@kanux.com Thu Jul  8 19:21:19 2004
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Volker Jahns wrote:
> Linux on Sharp Mobilon HC-4100
> 
> I would like to have Linux boot on the Sharp HC-4100 and have tried a
> couple of suitable kernels with the following outcome:
> 
> Booting
> -------
> netbsd tx3912               - netbsd 1.5.3 , keyboard functional
> linux for philips velo      - vmlinux-2.4.0-test4-pre3 , keyboard not
> functional
> 
> 
> Booting, but framebuffer scrambled
> ----------------------------------
> linux nino                  - vmlinux-2.4.17
> linux sharp HC-4500/HC-4600 - vmlinux-2.3.21. vmlinux-2.3.47
> 
> I have tried to compile a kernel from versions - 2.4.20 and 2.4.0-test9 -
> ( sharp mobilon, philips velo, philips nino) which all boot but have the
> framebuffer device scrambled.
> 
> Which kernel version is good to start from, and where would I find its code ?
> Has somebody a working .config vor the Velo 500 available, so that I get
> the correct options to have this damn framebuffer device working?
> 
> 
> Please redirect, in case this should be the wrong place to post.

Hi, sometimes the scrambled problem happens when you are using a linked 
inside ramdisk image and it corrupts the kernel itself in some way, it 
has happened to me quite many times with the nino kernel.

It would help to check your config, I can assure you that the 2.4.17 
nino code is working, I use it myself but on the nino, it might require 
some modifications for the Mobilon.

-- 
Ricardo Mendoza Meinhardt
ricardo.mendoza@kanux.com

.knxTech
Administrador Linux
Programador/PHP

"get ready for a bit of the old Ultra Violence"

From volker@thalreit.de Thu Jul  8 20:16:16 2004
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From: Volker Jahns <volker@thalreit.de>
To: Ricardo Mendoza <ricardo.mendoza@kanux.com>
Cc: linux-mips@linux-mips.org
Subject: Re: sharp mobilon hc-4100
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On Thu, Jul 08, 2004 at 02:21:11PM -0400, Ricardo Mendoza wrote:
> Volker Jahns wrote:
> >Linux on Sharp Mobilon HC-4100
> >
> >I would like to have Linux boot on the Sharp HC-4100 and have tried a
> >couple of suitable kernels with the following outcome:
> >

...


> It would help to check your config, I can assure you that the 2.4.17 
> nino code is working, I use it myself but on the nino, it might require 
> some modifications for the Mobilon.

Modifications are certainly a must:

e.g. 2.4.20 in drivers/video/tx3912fb.h thereis _only_  framebuffer definitions for the nino:
<pre>
#if defined(CONFIG_NINO_4MB) || defined(CONFIG_NINO_8MB)
#define FB_X_RES       240 
#define FB_Y_RES       320
#if defined(CONFIG_FBCON_CFB4)
#define FB_BPP         4
</pre>

while 2.4.0-test9 carries the _good_ information for the velo 1, velo 500 and for the helio ( the code for the nino is missing here). In drivers/video/r3912fb.h ( which seems to be the historic version of tx3912fb.h, ouch what a chaos :-(
<pre>
#ifdef CONFIG_PHILIPS_VELO
#       ifdef CONFIG_PHILIPS_VELO1
#               define FB_X_RES         480
#       elif defined(CONFIG_PHILIPS_VELO500)
#               define FB_X_RES         640
#       endif
#       define  FB_Y_RES        240
#       ifdef CONFIG_PHILIPS_VELO_4GRAY
#               define FB_BPP   2
#       else /* CONFIG_PHILIPS_VELO_16GRAY */
#               define FB_BPP   4
#       endif
#       define FB_IS_GREY     1
#       define FB_IS_INVERSE  0
#       define VIDEORAM_SIZE  (FB_X_RES * FB_Y_RES * FB_BPP / 8)
</pre>

On the other hand the mobilon needs 
<pre>
#               define FB_X_RES         640
#               define FB_X_RES         240
#               define FB_BPP           4
</pre>

This information ( and what else which might be of interest to make the LCD working on this thing) must have get lost on the kernel's way. I really wonder where to find a more or less functional version of the kernel code to start with.

-- 
Volker Jahns, Volker.Jahns@thalreit.de, http://thalreit.de, DG7PM

From tbm@cyrius.com Thu Jul  8 20:49:33 2004
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From: Martin Michlmayr <tbm@cyrius.com>
To: linux-mips@linux-mips.org
Subject: Re: sharp mobilon hc-4100
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* Volker Jahns <volker@thalreit.de> [2004-07-08 21:26]:
> On the other hand the mobilon needs 
> #               define FB_X_RES         640
> #               define FB_X_RES         240

I thought it was 800x480.  BTW, how do you boot this thing?  From
WinCE or can you override the ROM?

-- 
Martin Michlmayr
tbm@cyrius.com

From ricardo.mendoza@kanux.com Thu Jul  8 21:03:17 2004
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Volker Jahns wrote:

> 
> Modifications are certainly a must:
> 
> e.g. 2.4.20 in drivers/video/tx3912fb.h thereis _only_  framebuffer definitions for the nino:
> <pre>
> #if defined(CONFIG_NINO_4MB) || defined(CONFIG_NINO_8MB)
> #define FB_X_RES       240 
> #define FB_Y_RES       320
> #if defined(CONFIG_FBCON_CFB4)
> #define FB_BPP         4
> </pre>
> 
> while 2.4.0-test9 carries the _good_ information for the velo 1, velo 500 and for the helio ( the code for the nino is missing here). In drivers/video/r3912fb.h ( which seems to be the historic version of tx3912fb.h, ouch what a chaos :-(
> <pre>
> #ifdef CONFIG_PHILIPS_VELO
> #       ifdef CONFIG_PHILIPS_VELO1
> #               define FB_X_RES         480
> #       elif defined(CONFIG_PHILIPS_VELO500)
> #               define FB_X_RES         640
> #       endif
> #       define  FB_Y_RES        240
> #       ifdef CONFIG_PHILIPS_VELO_4GRAY
> #               define FB_BPP   2
> #       else /* CONFIG_PHILIPS_VELO_16GRAY */
> #               define FB_BPP   4
> #       endif
> #       define FB_IS_GREY     1
> #       define FB_IS_INVERSE  0
> #       define VIDEORAM_SIZE  (FB_X_RES * FB_Y_RES * FB_BPP / 8)
> </pre>
> 
> On the other hand the mobilon needs 
> <pre>
> #               define FB_X_RES         640
> #               define FB_X_RES         240
> #               define FB_BPP           4
> </pre>
> 
> This information ( and what else which might be of interest to make the LCD working on this thing) must have get lost on the kernel's way. I really wonder where to find a more or less functional version of the kernel code to start with.
> 

The 2.4.17 tree on Steven J. Hill's website is functional, I can give it
  to you if you cant find it, just let me know.

By the way, when I refer to functional is for the TX3912 generic stuff,
one thing for sure is that you _WILL_ need to make an specific machine
directory for the mobilon, and you can use the same code for it, after
removing the non-generic tx3912 stuff and perhaps changing some stuff
that matters only to the mobilon.

You can also try hacking on the nino files as if you were using a nino.

P.D. Remove the html tags

-- 
Ricardo Mendoza Meinhardt
ricardo.mendoza@kanux.com

.knxTech
Administrador Linux
Programador/PHP

"get ready for a bit of the old Ultra Violence"

From ralf@linux-mips.org Fri Jul  9 01:17:03 2004
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I've created a new mailing list maltalinux-cvs@linux-mips.org for tracking
of MIPS's stable Malta tree.  Unlike the main Linux CVS repository which
is more slanted towards development maltalinux-cvs is primarily oriented
towards stability on the Malta platform and it's processors.

Subscription to maltalinux-cvs@linux-mips.org is handled via Ecartis
(ecartis@linux-mips.org), just send an email with the words subscribe
maltalinux-cvs. In order to unsubscribe, send unsubscribe maltalinux-cvs.
Sending the word help will reveal further secrets about the advanced use
of Ecartis. At http://www.linux-mips.org/ecartis you'll also find a
web-based interface to Ecartis.

Similarly as with the main CVS tree the new tree may be followed in cvsweb
at http://www.linux-mips.org/cvsweb/malta/ in xcvs and via anon cvs by

  cvs -d :pserver:cvs@ftp.linux-mips.org:/home/cvs login
 (Only needed the first time you use anonymous CVS, the password is "cvs")
 cvs -d :pserver:cvs@ftp.linux-mips.org:/home/cvs co malta

  Ralf

From Volker.Jahns@thalreit.de Fri Jul  9 07:56:31 2004
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Date: Fri, 9 Jul 2004 08:56:26 +0200 (CEST)
Subject: Re: sharp mobilon hc-4100
From: "Volker Jahns" <Volker.Jahns@thalreit.de>
To: "Martin Michlmayr" <tbm@cyrius.com>
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> * Volker Jahns <volker@thalreit.de> [2004-07-08 21:26]:
>> On the other hand the mobilon needs
>> #               define FB_X_RES         640
>> #               define FB_X_RES         240
that is correct.
>
> I thought it was 800x480.  BTW, how do you boot this thing?  From
> WinCE or can you override the ROM?
pbsdboot :-( But if you have an idea on how to write the ROM, please let
me know.

-- 
Volker Jahns, volker@thalreit.de, http://thalreit.de, DG7PM

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Subject: Re: [Fwd: Re: sharp mobilon hc-4100]
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On Thu, Jul 08, 2004 at 04:03:10PM -0400, Ricardo Mendoza wrote:

> The 2.4.17 tree on Steven J. Hill's website is functional, I can give it
>  to you if you cant find it, just let me know.

Would be nice if somebody can resurrect this platform.  It's rotting
for too long and Steven even convinced me to remove it from 2.6.  I
hope we can add functional code back somewhen.

  Ralf

From ricardo.mendoza@kanux.com Fri Jul  9 16:46:47 2004
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Ralf Baechle wrote:

> Would be nice if somebody can resurrect this platform.  It's rotting
> for too long and Steven even convinced me to remove it from 2.6.  I
> hope we can add functional code back somewhen.

Hey Ralf, well as you know I have been getting involved in that, as far 
as today PCMCIA IDE kind of works, but the real plan is to develop a 
PCMCIA driver for the controller.

Im ricmm, perhaps now that vacations started for me I can really get 
into the stuff, I will let you know if I get into porting it to the 2.6 
kernel.


-- 
Ricardo Mendoza Meinhardt
ricardo.mendoza@kanux.com

.knxTech
Administrador Linux
Programador/PHP

"get ready for a bit of the old Ultra Violence"

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Well I'm hoping it isn't so strange to some of you folks and you'll be able 
to tell what's going on :)

Here's my problem:

Using MontaVista Linux 3.1 on a Toshiba RBTx4938 board. Using YAMON, when I 
download the kernel via the debug ethernet port it runs fine. If I download 
the kernel via the Tx4938 inbuilt ethernet controller, it crashes!

Memory checksumming and a quick manual memory dump inspection reveals that 
the kernel download went perfectly ok, and the image is completely and 
correctly downloaded to RAM.

The crash is occuring inside the function r4k_flush_icache_range().

I tried 'flush -i' and 'flush -d' on YAMON after the download but before the 
'go', but that didn't help. I also tried completely disabling caches and 
loading/running uncached, but it gave the same error.

Now, the final twist! Using an ICE, I set a breakpoint at the 
r4k_flush_icache_range function. Then I loaded the kernel as usual, ran it 
with the ICE, stepped through a few instructions inside the 
r4k_flush_icache_range function and then did a 'cont'. The kernel now booted 
fine!

If I don't set the breakpoint inside that function though, and just try to 
run with the ICE the same
error (Inst fetch/Load error) occurs.

I'm at a loss trying to figure out what's going on. I suspect it has 
something to do with caches perhaps (duh!), but have no clue what!  Anybody 
out there face a similar kind of a situation before?

Thanks in advance for any help offered.

Regards,
-Steve

_________________________________________________________________
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From ralf@linux-mips.org Fri Jul  9 22:57:02 2004
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Date: Fri, 9 Jul 2004 23:57:00 +0200
From: Ralf Baechle <ralf@linux-mips.org>
To: Song Wang <wsonguci@yahoo.com>
Cc: linux-mips@linux-mips.org
Subject: Re: kbuild support to build one module with multiple separate components?
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On Tue, Jul 06, 2004 at 04:00:50PM -0700, Song Wang wrote:

> This is wrong, because kbuild will treat A as
> independent module. All I want is to treat
> A as component of the only module mymodule.o. It
> should be linked to mymodule.o
> 
> Any idea on how to write a kbuild Makefile to
> support such kind of single module produced
> by linking multiple components and each component
> is located in separate directory? Thanks.

That's a limitation in the current kbuild system.  You either have to put
all files into a single directory or if you don't want that split your
module into several independant modules.  What I haven't tried is using
.a libraries but they're generally deprecated in kbuild.

  Ralf

From niels.sterrenburg@philips.com Sat Jul 10 08:34:15 2004
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Date: Sat, 10 Jul 2004 09:33:57 +0200 (CEST)
Subject: Re: Strange, strange occurence
From: "Niels Sterrenburg" <niels.sterrenburg@philips.com>
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Hi Steve,

When you set a breakpoint with the ice and step through,
for each step the ICE set's a breakpoint on the next instruction:
e.g.:
- modifies next instruction in memory (via CPU !!!)
  with a breakpoint instruction,
- and update the cache so that the breakpoint instruction is really in
memory and that i-cache is invalid.
(or something like that)

So indead you have a cache problem which is explanable solved/disapeared
by steppig through with the ICE.

Maybe a stupid question from me but why flushing an icache ?:
r4k_flush_icache_range

regards,

Niels

> Well I'm hoping it isn't so strange to some of you folks and you'll be
> able
> to tell what's going on :)
>
> Here's my problem:
>
> Using MontaVista Linux 3.1 on a Toshiba RBTx4938 board. Using YAMON, when
> I
> download the kernel via the debug ethernet port it runs fine. If I
> download
> the kernel via the Tx4938 inbuilt ethernet controller, it crashes!
>
> Memory checksumming and a quick manual memory dump inspection reveals that
> the kernel download went perfectly ok, and the image is completely and
> correctly downloaded to RAM.
>
> The crash is occuring inside the function r4k_flush_icache_range().
>
> I tried 'flush -i' and 'flush -d' on YAMON after the download but before
> the
> 'go', but that didn't help. I also tried completely disabling caches and
> loading/running uncached, but it gave the same error.
>
> Now, the final twist! Using an ICE, I set a breakpoint at the
> r4k_flush_icache_range function. Then I loaded the kernel as usual, ran it
> with the ICE, stepped through a few instructions inside the
> r4k_flush_icache_range function and then did a 'cont'. The kernel now
> booted
> fine!
>
> If I don't set the breakpoint inside that function though, and just try to
> run with the ICE the same
> error (Inst fetch/Load error) occurs.
>
> I'm at a loss trying to figure out what's going on. I suspect it has
> something to do with caches perhaps (duh!), but have no clue what!
> Anybody
> out there face a similar kind of a situation before?
>
> Thanks in advance for any help offered.
>
> Regards,
> -Steve
>
> _________________________________________________________________
> MSN 9 Dial-up Internet Access helps fight spam and pop-ups – now 2 months
> FREE! http://join.msn.click-url.com/go/onm00200361ave/direct/01/
>
>
>


From ralf@linux-mips.org Sat Jul 10 11:05:17 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: S C <theansweriz42@hotmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: Strange, strange occurence
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On Fri, Jul 09, 2004 at 06:50:00PM +0000, S C wrote:

> Using MontaVista Linux 3.1 on a Toshiba RBTx4938 board. Using YAMON, when I 
> download the kernel via the debug ethernet port it runs fine. If I download 
> the kernel via the Tx4938 inbuilt ethernet controller, it crashes!

If you're using a Montavista kernel you should report to Montavista.  We
don't have the source so any comment here is speculation.

> The crash is occuring inside the function r4k_flush_icache_range().
> 
> I tried 'flush -i' and 'flush -d' on YAMON after the download but before 
> the 'go', but that didn't help. I also tried completely disabling caches 
> and loading/running uncached, but it gave the same error.
> 
> Now, the final twist! Using an ICE, I set a breakpoint at the 
> r4k_flush_icache_range function. Then I loaded the kernel as usual, ran it 
> with the ICE, stepped through a few instructions inside the 
> r4k_flush_icache_range function and then did a 'cont'. The kernel now 
> booted fine!

As already pointed out by the other poster Niels Sterrenburg using a
debugger unavoidably changes the state of the system to be debugged.

For at least some of the TX49xx processors there is a problem under certain
circumstances if a flush of an I-cache line flushes that cache instruction
itself.  Make sure you're not getting hit by that one.

  Ralf

From bunk@fs.tum.de Mon Jul 12 01:16:09 2004
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From: Adrian Bunk <bunk@fs.tum.de>
To: ralf@linux-mips.org, kwalker@broadcom.com
Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org
Subject: 2.6: sound/oss/swarm_cs4297a.c still required?
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Hi,

in 2.6 (I've checked 2.6.7-mm7) sound/oss/swarm_cs4297a.c is no longer 
listed in sound/oss/Makefile. Was this accidential, or should this file 
be removed?

cu
Adrian

-- 

       "Is there not promise of rain?" Ling Tan asked suddenly out
        of the darkness. There had been need of rain for many days.
       "Only a promise," Lao Er said.
                                       Pearl S. Buck - Dragon Seed


From ralf@linux-mips.org Mon Jul 12 02:01:06 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: Adrian Bunk <bunk@fs.tum.de>
Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org
Subject: Re: 2.6: sound/oss/swarm_cs4297a.c still required?
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On Mon, Jul 12, 2004 at 02:16:04AM +0200, Adrian Bunk wrote:

> in 2.6 (I've checked 2.6.7-mm7) sound/oss/swarm_cs4297a.c is no longer 
> listed in sound/oss/Makefile. Was this accidential, or should this file 
> be removed?

Still partially merged only.

  Ralf

From KevinK@mips.com Mon Jul 12 16:19:07 2004
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Subject: Re: Strange, strange occurence
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[snip]
> > The crash is occuring inside the function r4k_flush_icache_range().
> > 
> > I tried 'flush -i' and 'flush -d' on YAMON after the download but before 
> > the 'go', but that didn't help. I also tried completely disabling caches 
> > and loading/running uncached, but it gave the same error.
> > 
> > Now, the final twist! Using an ICE, I set a breakpoint at the 
> > r4k_flush_icache_range function. Then I loaded the kernel as usual, ran it 
> > with the ICE, stepped through a few instructions inside the 
> > r4k_flush_icache_range function and then did a 'cont'. The kernel now 
> > booted fine!
> 
> As already pointed out by the other poster Niels Sterrenburg using a
> debugger unavoidably changes the state of the system to be debugged.
> 
> For at least some of the TX49xx processors there is a problem under certain
> circumstances if a flush of an I-cache line flushes that cache instruction
> itself.  Make sure you're not getting hit by that one.

It's not just the TX49xx series.  While many MIPS-compatible processors 
do handle the special case of flushing the active CACHE instruction itself, 
not all of them do, and the MIPS32 spec calls it out as having an "UNPREDICTABLE"
result.

A truly safe and general I-cache flush routine should itself run uncached,
but a cursory glance at the linux-mips.org sources makes me think
that we do not take that precaution by default - the flush_icache_range
pointer looks to be set to the address of r4k_flush_icache_range()
function, rather than its (uncacheable) alias in kseg1.  Is this something
that's fixed in a linker script, or are we just living dangerously?

            Regards,

            Kevin K.


From theansweriz42@hotmail.com Mon Jul 12 21:54:51 2004
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Hi Niels, Ralf, Kevin

Thanks for responding to my query! For the moment, I have fixed the 
symptoms, but still don't know what the problem is (it could be what you 
guys suspect it to be). The r4k_flush_icache_range() was being called from 
inside r4k_tlb_init() and the range being specified was KSEG0 to KSEG0 + 
0x80, i.e. the TLB handler. I commented out the call to 
r4k_flush_icache_range and now the kernel seems to boot normally! But I 
suspect I have not fixed a problem, merely sidestepped it.

So now maybe I should repeat the question Niels asked: why was that call 
necessary?

Thanks again,
-Steve.




>From: Ralf Baechle <ralf@linux-mips.org>
>To: S C <theansweriz42@hotmail.com>
>CC: linux-mips@linux-mips.org
>Subject: Re: Strange, strange occurence
>Date: Sat, 10 Jul 2004 12:04:12 +0200
>
>On Fri, Jul 09, 2004 at 06:50:00PM +0000, S C wrote:
>
> > Using MontaVista Linux 3.1 on a Toshiba RBTx4938 board. Using YAMON, 
>when I
> > download the kernel via the debug ethernet port it runs fine. If I 
>download
> > the kernel via the Tx4938 inbuilt ethernet controller, it crashes!
>
>If you're using a Montavista kernel you should report to Montavista.  We
>don't have the source so any comment here is speculation.
>
> > The crash is occuring inside the function r4k_flush_icache_range().
> >
> > I tried 'flush -i' and 'flush -d' on YAMON after the download but before
> > the 'go', but that didn't help. I also tried completely disabling caches
> > and loading/running uncached, but it gave the same error.
> >
> > Now, the final twist! Using an ICE, I set a breakpoint at the
> > r4k_flush_icache_range function. Then I loaded the kernel as usual, ran 
>it
> > with the ICE, stepped through a few instructions inside the
> > r4k_flush_icache_range function and then did a 'cont'. The kernel now
> > booted fine!
>
>As already pointed out by the other poster Niels Sterrenburg using a
>debugger unavoidably changes the state of the system to be debugged.
>
>For at least some of the TX49xx processors there is a problem under certain
>circumstances if a flush of an I-cache line flushes that cache instruction
>itself.  Make sure you're not getting hit by that one.
>
>   Ralf

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From theansweriz42@hotmail.com Mon Jul 12 22:23:41 2004
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And thinking about it a little more, I might as well clarfy my understanding 
while we're on the topic.

Here's a code snippet from r4k_tlb_init() in arch/mips/mm/c-r4k.c

memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
flush_icache_range(KSEG0, KSEG0 + 0x80);

So my understanding is that the TLB exception handler is being copied to the 
right memory location, and just in case some other TLB exception handler 
(YAMON's presumably) is residing in I-cache, to flush ( hit invalidate) it. 
Is this correct?

Shouldn't there be code to writeback_invalidate the exception handler from 
the data cache ? Presumably the memcpy causes the TLB handler to lodge 
itself in the D cache till it is moved to RAM (either explicitly or when 
some other lines replace the cache lines where the handler is), right?

Thanks in advance for helping me understand the issue here.

Regards,
-Steve.





>From: Ralf Baechle <ralf@linux-mips.org>
>To: S C <theansweriz42@hotmail.com>
>CC: linux-mips@linux-mips.org
>Subject: Re: Strange, strange occurence
>Date: Sat, 10 Jul 2004 12:04:12 +0200
>
>On Fri, Jul 09, 2004 at 06:50:00PM +0000, S C wrote:
>
> > Using MontaVista Linux 3.1 on a Toshiba RBTx4938 board. Using YAMON, 
>when I
> > download the kernel via the debug ethernet port it runs fine. If I 
>download
> > the kernel via the Tx4938 inbuilt ethernet controller, it crashes!
>
>If you're using a Montavista kernel you should report to Montavista.  We
>don't have the source so any comment here is speculation.
>
> > The crash is occuring inside the function r4k_flush_icache_range().
> >
> > I tried 'flush -i' and 'flush -d' on YAMON after the download but before
> > the 'go', but that didn't help. I also tried completely disabling caches
> > and loading/running uncached, but it gave the same error.
> >
> > Now, the final twist! Using an ICE, I set a breakpoint at the
> > r4k_flush_icache_range function. Then I loaded the kernel as usual, ran 
>it
> > with the ICE, stepped through a few instructions inside the
> > r4k_flush_icache_range function and then did a 'cont'. The kernel now
> > booted fine!
>
>As already pointed out by the other poster Niels Sterrenburg using a
>debugger unavoidably changes the state of the system to be debugged.
>
>For at least some of the TX49xx processors there is a problem under certain
>circumstances if a flush of an I-cache line flushes that cache instruction
>itself.  Make sure you're not getting hit by that one.
>
>   Ralf

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From KevinK@mips.com Mon Jul 12 22:51:07 2004
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Subject: Re: Strange, strange occurence
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> And thinking about it a little more, I might as well clarfy my understanding 
> while we're on the topic.
> 
> Here's a code snippet from r4k_tlb_init() in arch/mips/mm/c-r4k.c
> 
> memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
> flush_icache_range(KSEG0, KSEG0 + 0x80);
> 
> So my understanding is that the TLB exception handler is being copied to the 
> right memory location, and just in case some other TLB exception handler 
> (YAMON's presumably) is residing in I-cache, to flush ( hit invalidate) it. 
> Is this correct?
> 
> Shouldn't there be code to writeback_invalidate the exception handler from 
> the data cache ? Presumably the memcpy causes the TLB handler to lodge 
> itself in the D cache till it is moved to RAM (either explicitly or when 
> some other lines replace the cache lines where the handler is), right?
> 
> Thanks in advance for helping me understand the issue here.

Your intuition is correct, and the code in r4k_tlb_init() does look scary.
But at least in the linux-mips CVS tree, flush_icache_range() tests to see
if "cpu_has_ic_fills_f_dc" (CPU has Icache fills from Dcache, I presume)
is set, and if it isn't, it pushes the specified range out of the Dcache before
flushing the Icache.  I would speculate that either your c-r4k.c is out of
sync with yout tlb-r4k.c, or you erroneously have cpu_has_ic_fills_f_dc
set.

            Regards,

            Kevin K.




From KevinK@mips.com Mon Jul 12 23:35:46 2004
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> Your intuition is correct, and the code in r4k_tlb_init() does look scary.
> But at least in the linux-mips CVS tree, flush_icache_range() tests to see
> if "cpu_has_ic_fills_f_dc" (CPU has Icache fills from Dcache, I presume)
> is set, and if it isn't, it pushes the specified range out of the Dcache before
> flushing the Icache.  I would speculate that either your c-r4k.c is out of
> sync with yout tlb-r4k.c, or you erroneously have cpu_has_ic_fills_f_dc
> set.

Hmm.  On closer examination, there *is* a bug in the current r4k_flush_icache_range(),
in that it computes its cache flush loop for the I-cache based on the D-cache line size.
Those line sizes are *usually* the same.  By any chance are they different for the
TX49 family?  If the icache line is longer than the dcache line, there should be no
functional problem, just some wasted cycles.  But if the dcache line were, say, 
twice the length of the Icache line, only half of the icache lines would be invalidated...

            Regards,

            Kevin K.


From ralf@linux-mips.org Tue Jul 13 00:00:51 2004
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From: Ralf Baechle <ralf@linux-mips.org>
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On Mon, Jul 12, 2004 at 09:23:20PM +0000, S C wrote:

> And thinking about it a little more, I might as well clarfy my 
> understanding while we're on the topic.
> 
> Here's a code snippet from r4k_tlb_init() in arch/mips/mm/c-r4k.c
> 
> memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
> flush_icache_range(KSEG0, KSEG0 + 0x80);
> 
> So my understanding is that the TLB exception handler is being copied to 
> the right memory location, and just in case some other TLB exception 
> handler (YAMON's presumably) is residing in I-cache, to flush ( hit 
> invalidate) it. Is this correct?
> 
> Shouldn't there be code to writeback_invalidate the exception handler from 
> the data cache ?

flush_icache_range() does that where necessary.

> Presumably the memcpy causes the TLB handler to lodge 
> itself in the D cache till it is moved to RAM

Correct.  All MIPS processors [1] do their primary I-cache refills from
second or third level cache or memory - whatever hits first.  If code
was changed a flush of the data cache is required so the I-cache can
actually fetch the new data and because old stale code might still be
in the I-cache an I-cache flush is also required.

> (either explicitly or when 
> some other lines replace the cache lines where the handler is), right?
> 
> Thanks in advance for helping me understand the issue here.

  Ralf

[1] Exceptions are the R4000/R4400 SC and MC versions in a split S-cache
    configuration where the primary I-cache is refilled from the secondary
    I-cache which mean this flush has to flush the secondary data cache
    back to memory also.  Linux doesn't support this configuration because
    no known system uses it iow it's only a theoretically possible config.

    The second exception are the AMD MIPS32 processors where the I-cache
    is snooping the D-cache and therefore the D-cache flush can is
    unnecessary.

    The third exception are R1x000 in SMP configurations where I-caches
    snoop remote stores so coherency doesn't need any maintenance in
    software at all.  Only the I-cache of the CPU that did modify the code
    needs flushing.

From theansweriz42@hotmail.com Tue Jul 13 00:10:37 2004
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Hi Kevin and Ralf,

Thanks for your inputs and suggestions! In the case of the Tx49 family, the 
primary I and D cache lines are both the same size (8 words), so the problem 
you mention below will not arise.

  I didn't think about the meaning of cpu_has_ic_fills_f_dc before writing 
my previous mail, and I see now that my intuition (and your explanation 
helps) was correct.

  For the moment, the problem is fixed. But I'm going to try and get to the 
bottom of this when I have the time.

  Thanks,
-Steve.


>From: "Kevin D. Kissell" <KevinK@mips.com>
>To: "Kevin D. Kissell" <KevinK@mips.com>, "S C" 
><theansweriz42@hotmail.com>,        "Ralf Baechle" <ralf@linux-mips.org>
>CC: <linux-mips@linux-mips.org>
>Subject: Re: Strange, strange occurence
>Date: Tue, 13 Jul 2004 00:25:37 +0200
>
> > Your intuition is correct, and the code in r4k_tlb_init() does look 
>scary.
> > But at least in the linux-mips CVS tree, flush_icache_range() tests to 
>see
> > if "cpu_has_ic_fills_f_dc" (CPU has Icache fills from Dcache, I presume)
> > is set, and if it isn't, it pushes the specified range out of the Dcache 
>before
> > flushing the Icache.  I would speculate that either your c-r4k.c is out 
>of
> > sync with yout tlb-r4k.c, or you erroneously have cpu_has_ic_fills_f_dc
> > set.
>
>Hmm.  On closer examination, there *is* a bug in the current 
>r4k_flush_icache_range(),
>in that it computes its cache flush loop for the I-cache based on the 
>D-cache line size.
>Those line sizes are *usually* the same.  By any chance are they different 
>for the
>TX49 family?  If the icache line is longer than the dcache line, there 
>should be no
>functional problem, just some wasted cycles.  But if the dcache line were, 
>say,
>twice the length of the Icache line, only half of the icache lines would be 
>invalidated...
>
>             Regards,
>
>             Kevin K.
>

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From ralf@linux-mips.org Tue Jul 13 00:11:45 2004
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From: Ralf Baechle <ralf@linux-mips.org>
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On Mon, Jul 12, 2004 at 11:48:31PM +0200, Kevin D. Kissell wrote:

> Your intuition is correct, and the code in r4k_tlb_init() does look scary.

Not scarry at all.  flush_icache_range() has to do whatever is needed to
maintain I-cache coherency for the range passed in as the argument.  And
I don't think we should really have to deal with all the complicated
details of cache maintenance in a function like r4k_tlb_init().

> But at least in the linux-mips CVS tree, flush_icache_range() tests to see
> if "cpu_has_ic_fills_f_dc" (CPU has Icache fills from Dcache, I presume)

Right.  Cpu_has_ic_fills_f_dc is only non-zero for the AMD processors
where the I-cache is refilled from the D-cache.  For typical kernel
configurations The definition of cpu_has_ic_fills_f_dc is a constant so
the compiler can optimize this further.

  Ralf

From ralf@linux-mips.org Tue Jul 13 00:14:02 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: "Kevin D. Kissell" <KevinK@mips.com>
Cc: S C <theansweriz42@hotmail.com>, linux-mips@linux-mips.org
Subject: Re: Strange, strange occurence
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On Tue, Jul 13, 2004 at 12:25:37AM +0200, Kevin D. Kissell wrote:

> Hmm.  On closer examination, there *is* a bug in the current r4k_flush_icache_range(),
> in that it computes its cache flush loop for the I-cache based on the D-cache line size.
> Those line sizes are *usually* the same.  By any chance are they different for the
> TX49 family?  If the icache line is longer than the dcache line, there should be no
> functional problem, just some wasted cycles.  But if the dcache line were, say, 
> twice the length of the Icache line, only half of the icache lines would be invalidated...

Whoops.  Fixing ...

  Ralf

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From: Ralf Baechle <ralf@linux-mips.org>
To: "Kevin D. Kissell" <KevinK@mips.com>
Cc: S C <theansweriz42@hotmail.com>, linux-mips@linux-mips.org
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On Mon, Jul 12, 2004 at 05:16:31PM +0200, Kevin D. Kissell wrote:

> A truly safe and general I-cache flush routine should itself run uncached,
> but a cursory glance at the linux-mips.org sources makes me think
> that we do not take that precaution by default - the flush_icache_range
> pointer looks to be set to the address of r4k_flush_icache_range()
> function, rather than its (uncacheable) alias in kseg1.  Is this something
> that's fixed in a linker script, or are we just living dangerously?

That's a new restriction in MIPS32 v2.0 and you're right, we're not trying
to deal with it yet except for the TX49xx.

  Ralf

From collin_no_spam_for_me@xorotude.com Tue Jul 13 08:52:25 2004
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Subject: Help with MOP network boot install on DECstation 5000/240
Date: Tue, 13 Jul 2004 15:49:30 +0800
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Hi Guys,

I'm trying to install linux-mips on a DECsation 5000/240 I have in my
posession. It has the 5.1b rom so tftp boot is apparently out.

I've setup mopd on a linux (i386) box here and I'm getting the following on
my DECstation:

>>boot 3/mop

???
? PC:  0xa0010aa4<vtr=UTLBM>
? CR:  0x8000200c<BD,CE=0,IP6,EXC=TLBS>
? SR:  0x30080000<CU1,CU0,CM,IPL=8>
? VA:  0x1000
? ER: 0xe7d43000<VALID,CPU,WRITE,ADR=1F50C000>
? CK: 0xef00ffe2<VLDHI,CHKHI=6F,SYNHI=0,VLDLO,CHKLO=7F,SNGLO,SYNLO=62>
>>


In /var/log/messages I'm seeing:

Jul 13 15:44:36 phoenix mopd[10437]: 8:0:2b:2a:fe:c0 (1) Do you have
08002b2afec0? (Yes)
Jul 13 15:44:36 phoenix mopd[10437]: 8:0:2b:2a:fe:c0 Send me 08002b2afec0


and using moptrace I get the following:

Dst          : ab:0:0:1:0:0      MOP Dump/Load Multicast
Src          : 8:0:2b:2a:fe:c0
Proto        : 6001 MOP Dump/Load
Length       : 000b (11)
Code         :   08 Request program
Device Type  :   76 MNE '3MIN (KN02-BA)'
Format       :   01
Program Type :   02 Operating System
Software     :   00 ''
Processor    :   00 System Processor
DL Buff Size : 041c (1052)


Dst          : ab:0:0:2:0:0      MOP Remote Console Multicast
Src          : 8:0:2b:2a:fe:c0
Proto        : 6002 MOP Remote Console
Length       : 001c (28)
Code         :   07 System ID
Reserved     :   00
Receipt Nbr  : 0000
Hardware Addr: 8:0:2b:2a:fe:c0
Maint Version: 3.0.0
Maint Funcion: 004b ( Loop Dump MLdr DLC )
Comm Device  :   76 MNE '3MIN (KN02-BA)'


Dst          : 0:80:ad:72:e3:6f
Src          : 8:0:2b:2a:fe:c0
Proto        : 6001 MOP Dump/Load
Length       : 000b (11)
Code         :   08 Request program
Device Type  :   76 MNE '3MIN (KN02-BA)'
Format       :   01
Program Type :   02 Operating System
Software     :   00 ''
Processor    :   00 System Processor
DL Buff Size : 041c (1052)


Dst          : 0:80:ad:72:e3:6f
Src          : 8:0:2b:2a:fe:c0
Proto        : 6001 MOP Dump/Load
Length       : 0002 (2)
Code         :   0a Request memory load
Load Number  :   01
Error        :   00 (no error)


Dst          : 0:80:ad:72:e3:6f
Src          : 8:0:2b:2a:fe:c0
Proto        : 6001 MOP Dump/Load
Length       : 0002 (2)
Code         :   0a Request memory load
Load Number  :   02
Error        :   00 (no error)


Dst          : 0:80:ad:72:e3:6f
Src          : 8:0:2b:2a:fe:c0
Proto        : 6001 MOP Dump/Load
Length       : 0002 (2)
Code         :   0a Request memory load
Load Number  :   03
Error        :   00 (no error)

I've tried with both the ecoff and the elf kernels (2.4.18) listed on
Karel's web pages.

I was wondering if anyone on the list has had any success installing via MOP
onto a DECstation 5000/240 and would be able to offer me any assistance.

Cheers,

Collin Baillie


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Subject: Re: Help with MOP network boot install on DECstation 5000/240
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On Tue, 2004-07-13 15:49:30 +0800, Collin Baillie <collin_no_spam_for_me@xo=
rotude.com>
wrote in message <000701c468ae$141c3e50$0a9913ac@swift>:

[Thanks for *not* hijacking threads]

> I'm trying to install linux-mips on a DECsation 5000/240 I have in my
> posession. It has the 5.1b rom so tftp boot is apparently out.
>=20
> I've setup mopd on a linux (i386) box here and I'm getting the following =
on
> my DECstation:
>=20
> >>boot 3/mop
[...]
> I've tried with both the ecoff and the elf kernels (2.4.18) listed on
> Karel's web pages.

So it seems to try to get a file some times and gives up on it.

> I was wondering if anyone on the list has had any success installing via =
MOP
> onto a DECstation 5000/240 and would be able to offer me any assistance.

Maybe you'd try Debian's install image?

By the way, which mopd are you using? There are several of them around,
some quite unuseable...

MfG, JBG

--=20
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From safiudeen@hotmail.com Tue Jul 13 09:23:08 2004
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From: "safiudeen Ts" <safiudeen@hotmail.com>
To: linux-mips@linux-mips.org
Subject: Jtag spec. and the firmware for Au1100
Date: Tue, 13 Jul 2004 08:23:01 +0000
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How can we copy the kernel image to target board (processor au1100  )?
if we want to use JTAG where can I get the jatg schemetic detailes and the 
firmware for Red Hat linux 9
please any one can help me in this regards

than you
safi

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From safiudeen@hotmail.com Tue Jul 13 09:25:10 2004
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From: "safiudeen Ts" <safiudeen@hotmail.com>
To: linux-mips@linux-mips.org, ecartis@linux-mips.org
Subject: Jtag spec. and firmware for au1100
Date: Tue, 13 Jul 2004 08:25:03 +0000
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can  anyone help me to get Jtag spec . and the firware for au1100 prcessor 
based target.

_________________________________________________________________
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From wd@denx.de Tue Jul 13 09:32:05 2004
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To: "safiudeen Ts" <safiudeen@hotmail.com>
Cc: linux-mips@linux-mips.org
From: Wolfgang Denk <wd@denx.de>
Subject: Re: Jtag spec. and the firmware for Au1100 
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In message <BAY15-F33CIq1eE3VsX00049230@hotmail.com> you wrote:
> How can we copy the kernel image to target board (processor au1100  )?
> if we want to use JTAG where can I get the jatg schemetic detailes and the 
> firmware for Red Hat linux 9

You don't need any special information about the JTAG interface  (and
you  will  find that it is very difficult to get and under strict NDA
if at all). All you need is a JTAG debugger which understands how  to
deal  with  this interface, for example the Abatron BDI2000 (which is
just great especially for Linux).

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
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Subject: Re: Jtag spec. and the firmware for Au1100
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Normally you could use a boatloader like Yamon or uboot to load something
from a tftp-server or serial conenction on the board. If there isn't any 
bootloader
on the board you have to flash one on your board. This should normally 
be provided
with the board (which one do you have?).

Ejtag: The pin specification for ejtag should be in the board 
documentation, normally
it's quite easy to build an adapter to connect it to ejtag hardware like 
the bdi2000 or similar.

firmware: So you mean a kernel and maybe a rootfile-system? Didn't came 
anything with the board?
Depending on the HW-components on the board you may require your own 
kernel which
you can build from the sources on Linux-mips.org, try at first a default 
configuration for the Au1100.

Tiemo

safiudeen Ts wrote:

> How can we copy the kernel image to target board (processor au1100  )?
> if we want to use JTAG where can I get the jatg schemetic detailes and 
> the firmware for Red Hat linux 9
> please any one can help me in this regards
>
> than you
> safi
>
> _________________________________________________________________
> Protect your PC - get McAfee.com VirusScan Online 
> http://clinic.mcafee.com/clinic/ibuy/campaign.asp?cid=3963
>
>
>


From safiudeen@hotmail.com Tue Jul 13 10:04:31 2004
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Subject: Re: Jtag spec. and the firmware for Au1100
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Is there any software tool that can used to transfer kernel image to db1100 
board with the following cofigartion ?
Db1100's jtag connected a linux pc's lpt port through a 5v to 3.3v converter

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From daff_vadi@hotmail.com Tue Jul 13 14:01:08 2004
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From: "Vadivelan Mani" <daff_vadi@hotmail.com>
To: linux-mips@linux-mips.org
Subject: pci_alloc_consistent() usage 
Date: Tue, 13 Jul 2004 18:31:01 +0530
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hi,

   I'm writing a wireless driver which requires 8 transmit and 8 receive 
buffers each of size 3KB approx.

These buffers should be in dma capable space.

I've allocated them using pci_alloc_consistent().

I've allocated 128KBytes just to make more space. I've got few doubts.

   1. Can pci_alloc_consistent() be used to allocate memory upto 128KBytes?

If this is not possible, how much can it allocate?



2.)   I would also like to know the exact use of this allocated space to 
transmit or receive a packet.

During transmission i do the following. Plz correct me if i'm wrong because 
i'm new to driver writing.

The device has a register which should be loaded with the transmit buffers 
starting address.

I copy the packet coming from the Kernel in the form of sk_buff structure 
into one of the transmit buffers that i've allocated using memcpy().
And i set the register in the device to initiate transmission of the packet.

Where does the dma transfer concept come in this?
There is no mention of the direction of data transfer in 
pci_alloc_consistent().

I also assumed that allocating buffer in dma capable space was itself enough 
to start dma transfers.

Since i do not have the device now i'm not able to test the code. But i 
would like to write the code before i get the device.

Kindly help me in this.

thanking u in advance.

regards,
vadi.

_________________________________________________________________
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From KevinK@mips.com Tue Jul 13 16:38:18 2004
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Subject: Re: Strange, strange occurence
Date: Tue, 13 Jul 2004 17:31:42 +0200
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> > A truly safe and general I-cache flush routine should itself run uncached,
> > but a cursory glance at the linux-mips.org sources makes me think
> > that we do not take that precaution by default - the flush_icache_range
> > pointer looks to be set to the address of r4k_flush_icache_range()
> > function, rather than its (uncacheable) alias in kseg1.  Is this something
> > that's fixed in a linker script, or are we just living dangerously?
> 
> That's a new restriction in MIPS32 v2.0 and you're right, we're not trying
> to deal with it yet except for the TX49xx.

I'm pretty sure that restriction is not new to MIPS32 v2.0.  In any
case, there are pre-MIPS32/MIPS64 chips in current mass production
and use, under Linux among other OSes, which specify in their user
manuals that one should not invalidate the Icache line from which one
is currently executing.  The clause about unpredictable behavior in
that case went into the MIPS32 spec because it was known that such
parts existed, and we wanted to make it as easy as possible for such 
designs to be made compliant

Invalidating the entire Icache with a routine executing out of the Icache
is a Bad Idea, and will almost certainly cause problems some of the time
on some MIPS processors.  Reasonable people could disagree on whether
we want to handle that in the generic code, or create a variant icache flush 
routine which gets plugged in only for those parts that really need it.

            Regards,

            Kevin K.


From ralf@linux-mips.org Tue Jul 13 20:30:53 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: Vadivelan Mani <daff_vadi@hotmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: pci_alloc_consistent() usage
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On Tue, Jul 13, 2004 at 06:31:01PM +0530, Vadivelan Mani wrote:

>   I'm writing a wireless driver which requires 8 transmit and 8 receive 
> buffers each of size 3KB approx.

I hope this device isn't really as simplistic as you make it sound ...

> These buffers should be in dma capable space.
> 
> I've allocated them using pci_alloc_consistent().
> 
> I've allocated 128KBytes just to make more space. I've got few doubts.
> 
>   1. Can pci_alloc_consistent() be used to allocate memory upto 128KBytes?

Yes.  For MIPS MAX_ORDER defaults to 11 so you even do alloc_page (which
is the underlying allocator of pci_alloc_consistent) upto 2^11 page that
is 8MB.  Downside - memory allocation is making such large allocations
unreliable; the more unreliable the larger the allocation.  In general
try to stick to allocations of order 0 that is PAGE_SIZE which atm is
4k on MIPS.  They're ok for permanent allocations such as rx/tx rings
which only happen rarely.

> 2.)   I would also like to know the exact use of this allocated space to 
> transmit or receive a packet.

pci_alloc_consistent() is meant to be used for permanent allocations
such as rx/tx rings.  It's not suitable for allocating skbufs; there are
other mechanisms available for that.

> During transmission i do the following. Plz correct me if i'm wrong because 
> i'm new to driver writing.
> 
> The device has a register which should be loaded with the transmit buffers 
> starting address.
> 
> I copy the packet coming from the Kernel in the form of sk_buff structure 
> into one of the transmit buffers that i've allocated using memcpy().

That's usually an idea only for very small packets.  pci_alloc_consistent
allocates uncached memory on a system withour hardware coherency so this
copy operation would be very slow.  In any case you should experiment to
find the breakeven point.

For larger packets you should use pci_map_single() in the start_xmit()
method of the driver, then pci_unmap_single() later when cleaning that is
typically in an interrupt handler.  Reception of packets would work
fairly similar.

> And i set the register in the device to initiate transmission of the packet.
> 
> Where does the dma transfer concept come in this?
> There is no mention of the direction of data transfer in 
> pci_alloc_consistent().

pci_alloc_consistent will allocate consistent memory that is it's suitable
for transfers in both directions.  On the typical MIPS processor which
doesn't maintain coherency in hardware this means it will return
uncached memory.  Obviously that will work for any direction of transfer.
But: uncached memory is slow - so avoid copying packets there.

> I also assumed that allocating buffer in dma capable space was itself 
> enough to start dma transfers.

No.  DMA capable space means some memory that can be accessed somehow by
a DMA engine.  You still have to tell the device to start the operation.

> Since i do not have the device now i'm not able to test the code. But i 
> would like to write the code before i get the device.

  Ralf

From collin@xorotude.com Wed Jul 14 07:58:42 2004
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Subject: Re: Help with MOP network boot install on DECstation 5000/240
Date: Wed, 14 Jul 2004 14:57:52 +0800
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> [Thanks for *not* hijacking threads]

Sorry *blush*

> So it seems to try to get a file some times and gives up on it.

Oh.. I think it asks for the file, but the mopd server is not sending it. I
am only guessing though.

> Maybe you'd try Debian's install image?

Maybe, but on a _shared_ 31.2k dialup link, it takes a while to download...
and other people tend to get upset... I am using jigdo to get the 4 - 6 ISO
images.. if there's a better (smaller / faster to download) method, I'd love
to hear about it. I really would like to get to know Debian as I'm a
Slackware man and have had to use RedHat at work.. Debian would be another
nice addition to my Linux skillset.

> By the way, which mopd are you using? There are several of them around,
> some quite unuseable...

Umm.. 2.5.3. I downloaded one from linux-mips.org, and applied all the
patches in the order listed in the spec file, but it doesn't compile. So I
compiled another 2.5.3 (79k as opposed to the 48k tgz file I got from
linux-mips.org) and it compiles and responds, but still no file transfer. (I
am compiling/running on i386 arch, so I am wondering if all those patches
are necessary...)

I've read that MOP images usually have some special header in them (NetBSD
website) and someone mentioned that mopd-linux will fudge those headers if
the kernel doesn't have them... or something...

I am perservering with it, and will eventually get there... but for now, I
just thought someone might have more of a clue than I do.

Thanks,

Collin Baillie


From maksik@gmx.co.uk Wed Jul 14 09:42:19 2004
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From: Max Zaitsev <maksik@gmx.co.uk>
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To: linux-mips@linux-mips.org
Subject: is there *any* way to boot IP32 from hard drive ?
Date: Wed, 14 Jul 2004 10:42:18 +0200
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Hi List,

I've asked the very same question here before, but got no answer. Probably, 
the experts, who might have known the answer just overlooked it... (sorry 
guys for addressing some of you directly, but I'm really in trouble). The 
thing is that I desperately need to get the O2 to boot from its HDD, it's all 
installed and supposed to be used as a standalone box.

I'm using kernel 2.6.6 with minimal patches from Ilya and as to be expected it 
does not boot from the volume header. Arcboot seems to be the way to go, but 
I'm not able to compile the bootable arcboot.IP32 image. When I've tried to 
self-compile it with gcc 3.3.3 the image size was over 500K and it did not do 
anything at all. Self-compilation with gcc 3.4 fails during linking. In a 
mean time I've extracted the binary arcboot.IP32 image from the debian 
package and this one at least does something: it loads the kernel into memory 
(goes very slow), recognises a 64-bit executable and even starts it... But 
immediately after the kernel crashes. Any idea why it could be happening? In 
some other thread, Ilya have mentioned, that he has a "highly hacked" version 
of arcboot. Is it available anywhere? Or are other other solutions?

Thanks in advance,
Max

From macro@linux-mips.org Wed Jul 14 10:54:30 2004
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On Wed, 14 Jul 2004, Collin Baillie wrote:

> > So it seems to try to get a file some times and gives up on it.
> 
> Oh.. I think it asks for the file, but the mopd server is not sending it. I
> am only guessing though.

 It looks so.  You may try to verify with `tcpdump', too.

> > By the way, which mopd are you using? There are several of them around,
> > some quite unuseable...
> 
> Umm.. 2.5.3. I downloaded one from linux-mips.org, and applied all the
> patches in the order listed in the spec file, but it doesn't compile. So I

 Hmm, there's no mopd at linux-mips.org.  Do you refer to one at my site,
i.e. "ftp://ftp.ds2.pg.gda.pl/pub/macro/"?  If so, then please report
compiler errors to me.

> compiled another 2.5.3 (79k as opposed to the 48k tgz file I got from
> linux-mips.org) and it compiles and responds, but still no file transfer. (I
> am compiling/running on i386 arch, so I am wondering if all those patches
> are necessary...)

 They are.  They are not processor-dependent.

> I've read that MOP images usually have some special header in them (NetBSD
> website) and someone mentioned that mopd-linux will fudge those headers if
> the kernel doesn't have them... or something...

 You've been misled.  The MOP protocol sends raw data annotated with
addresses.  It's up to the MOP server to obtain both of them.  For example
they can be retrieved from ordinary ELF images.

> I am perservering with it, and will eventually get there... but for now, I
> just thought someone might have more of a clue than I do.

 Try running `mopchk <your-image-file>' to check if it's interpreted 
correctly.

  Maciej

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On Tue, 13 Jul 2004, Kevin D. Kissell wrote:

> > That's a new restriction in MIPS32 v2.0 and you're right, we're not trying
> > to deal with it yet except for the TX49xx.
> 
> I'm pretty sure that restriction is not new to MIPS32 v2.0.  In any

 The restriction was apparently added in revision 1.00 of the MIPS32
architecture vol.II document.  I don't have that revision -- I have
versions 0.95 and 2.00 only -- without looking at the revision history in
2.00 I'd expect the original MIPS32 spec not to enforce such a
restriction, either.

> case, there are pre-MIPS32/MIPS64 chips in current mass production
> and use, under Linux among other OSes, which specify in their user
> manuals that one should not invalidate the Icache line from which one
> is currently executing.  The clause about unpredictable behavior in
> that case went into the MIPS32 spec because it was known that such
> parts existed, and we wanted to make it as easy as possible for such 
> designs to be made compliant

 Ugh, although I can imagine valid arguments for such a decision.

> Invalidating the entire Icache with a routine executing out of the Icache
> is a Bad Idea, and will almost certainly cause problems some of the time
> on some MIPS processors.  Reasonable people could disagree on whether
> we want to handle that in the generic code, or create a variant icache flush 
> routine which gets plugged in only for those parts that really need it.

 As executing code from an uncached space is terribly slow, there are at
least two points of optimization:

1. The Icache invalidation handler should run cached on processors known
to handle it gracefully.

2. For others, as you suggest, it should attempt to figure out whether its
code may invalidate itself and run uncached then, perhaps for the
problematic lines only.

  Maciej

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On Wed, 2004-07-14 14:57:52 +0800, Collin Baillie <collin@xorotude.com>
wrote in message <000e01c4696f$f65cf4f0$0a9913ac@swift>:
> > [Thanks for *not* hijacking threads]
> > Maybe you'd try Debian's install image?
>=20
> Maybe, but on a _shared_ 31.2k dialup link, it takes a while to download.=
=2E.
> and other people tend to get upset... I am using jigdo to get the 4 - 6 I=
SO

It's only a couple of megabytes, not a number of CD images.

> I've read that MOP images usually have some special header in them (NetBSD
> website) and someone mentioned that mopd-linux will fudge those headers if
> the kernel doesn't have them... or something...

Right, eg. Maciej's MOPD does that.

MfG, JBG

--=20
   Jan-Benedict Glaw       jbglaw@lug-owl.de    . +49-172-7608481
   "Eine Freie Meinung in  einem Freien Kopf    | Gegen Zensur | Gegen Krieg
    fuer einen Freien Staat voll Freier B=FCrger" | im Internet! |   im Ira=
k!
   ret =3D do_actions((curr | FREE_SPEECH) & ~(NEW_COPYRIGHT_LAW | DRM | TC=
PA));

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On Wed, 2004-07-14 11:54:23 +0200, Maciej W. Rozycki <macro@linux-mips.org>
wrote in message <Pine.LNX.4.55.0407141058480.4513@jurand.ds.pg.gda.pl>:
>  Hmm, there's no mopd at linux-mips.org.  Do you refer to one at my site,
> i.e. "ftp://ftp.ds2.pg.gda.pl/pub/macro/"?  If so, then please report
> compiler errors to me.

While we are at it. I'll have to re-verify that, but my mopd is loosing
file descriptors if you ^A-F your box during a load.

MfG, JBG

--=20
   Jan-Benedict Glaw       jbglaw@lug-owl.de    . +49-172-7608481
   "Eine Freie Meinung in  einem Freien Kopf    | Gegen Zensur | Gegen Krieg
    fuer einen Freien Staat voll Freier B=FCrger" | im Internet! |   im Ira=
k!
   ret =3D do_actions((curr | FREE_SPEECH) & ~(NEW_COPYRIGHT_LAW | DRM | TC=
PA));

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On Wed, 14 Jul 2004, Jan-Benedict Glaw wrote:

> While we are at it. I'll have to re-verify that, but my mopd is loosing
> file descriptors if you ^A-F your box during a load.

 Hmm, while I get what you mean, what is "^A-F" specifically?

 Anyway, this may be true -- probably the server is still waiting for
following requests to come.  A timeout might be a good thing to add.  
Unfortunately I don't have time to work on mopd ATM.  It would be good to
do a serious rewrite and I plan to do that in the future.  No established 
plan, though.

 Another problem which is already known is mopd dying when one of
interfaces it's listening on goes down.

  Maciej

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On Wed, 2004-07-14 14:51:35 +0200, Maciej W. Rozycki <macro@linux-mips.org>
wrote in message <Pine.LNX.4.55.0407141446440.27072@jurand.ds.pg.gda.pl>:
> On Wed, 14 Jul 2004, Jan-Benedict Glaw wrote:
> > While we are at it. I'll have to re-verify that, but my mopd is loosing
> > file descriptors if you ^A-F your box during a load.
>=20
>  Hmm, while I get what you mean, what is "^A-F" specifically?

Sending a break from minicom :)   That is, I just ask the MOP client to
stop loading.

>  Anyway, this may be true -- probably the server is still waiting for
> following requests to come.  A timeout might be a good thing to add. =20
> Unfortunately I don't have time to work on mopd ATM.  It would be good to
> do a serious rewrite and I plan to do that in the future.  No established=
=20
> plan, though.

Eventually I'll re-get all the sources and compile again. Adding a
timeout shouldn't be all that hard. It should be a matter of extending
the "connection" table by "last packet's recv/send time" and check this
table entry upon each new request.

>  Another problem which is already known is mopd dying when one of
> interfaces it's listening on goes down.

Haven't seen that, but my interfaces tend to not go down (at least not
until the whole machine goes down...).

MfG, JBG

--=20
   Jan-Benedict Glaw       jbglaw@lug-owl.de    . +49-172-7608481
   "Eine Freie Meinung in  einem Freien Kopf    | Gegen Zensur | Gegen Krieg
    fuer einen Freien Staat voll Freier B=FCrger" | im Internet! |   im Ira=
k!
   ret =3D do_actions((curr | FREE_SPEECH) & ~(NEW_COPYRIGHT_LAW | DRM | TC=
PA));

--LmUdgXdNLPkN/XLh
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Hi!

 Is it possible to use it for the something useful ??
(to compie a kernel 8-))

 As it is known, MS provides eMbedded Visual Tools 3.0
for free download. It contains a free C++ MIPS cross compiler .

evt2002web_min.exe [210485 KB]






========================
C:\...ft eMbedded Tools\EVC\WCE300\BIN>CLMIPS.EXE /help 
Microsoft (R) 32-bit/16-bit C/C++ Optimizing Compiler Version 12.01.8667
for MIPS R-Series
Copyright (C) Microsoft Corp 1984-1999. All rights reserved.

[....]
                             -CODE GENERATION-

/QMRWCE optimize for WinCE (Default)     /QMOb<n> basic block threshold
/QMR3900 optimize for r3900              /QMOu<n> unroll n loop
iterations
/QMR4100 optimize for r4100              /QMFPE[-] FP emulation
(default)
/QMR4200 optimize for r4200              /Gd __cdecl calling convention
/QMR4300 optimize for r4300              /GA optimize for Windows
Application
/QMmips16 code for MIPS16 ASE            /GD optimize for Windows DLL
/QMmips1 MIPS1 ISA                       /Gr __fastcall calling
convention
/QMmips2 MIPS2 ISA (default)             /Gf enable string pooling
/QMNoDivCheck no divide by zero check    /GF enable read-only string
pooling
/QMNoUnalign no LWL,LWR,SWL,SWR          /Gh enable hook function call
/QMNoULoad do not generate LWL,LWR       /GR[-] enable C++ RTTI
/QMNoUStore do not generate SWL,SWR      /Gy separate functions for
linker
/QMOC use old float comparison helpers

[....]


--
-=AV=-


From heinold@physik.tu-cottbus.de Wed Jul 14 15:05:30 2004
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Hi,

look at which prozessors are supported, mainly embbeded devices and why
should it useful for linux.
-- 


Bye Henning

From geert@linux-m68k.org Wed Jul 14 15:10:03 2004
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From: Geert Uytterhoeven <geert@linux-m68k.org>
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On Wed, 14 Jul 2004, Alexander Voropay wrote:
>  Is it possible to use it for the something useful ??
> (to compie a kernel 8-))

If `kernel' stands for `Linux kernel', most probably not.

>  As it is known, MS provides eMbedded Visual Tools 3.0
> for free download. It contains a free C++ MIPS cross compiler .

Whether it's `free' or not, depends on your definition of `free'...

> evt2002web_min.exe [210485 KB]

A filename that ends in `*.exe'.... What's that?

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

From kevink@mips.com Wed Jul 14 16:03:23 2004
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Subject: Re: MS VC++ compiler / MIPS
Date: Wed, 14 Jul 2004 17:07:06 +0200
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If I recall correctly, the MS compiler uses a subltly different
calling convention/ABI than the "o32" gcc conventions assumed
by MIPS Linux, and certainly the assembler directives will be
different from those assumed by the Linux sources.  It *might*
be possible to hack up a MIPS Linux kernel source tree to
build with the MS tool kit, but it would be a lot of work, 
some of it subtle.

            Regards,

            Kevin K.

From dom@mips.com Wed Jul 14 17:35:38 2004
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Ralf Baechle (ralf@linux-mips.org) writes:

> > A truly safe and general I-cache flush routine should itself run
> > uncached... 

It depends what you mean by general, and uncached is not the only
option.  The spec says:

 "The operation of the instruction is UNPREDICTABLE if the cache line
  that contains the CACHE instruction is the target of an
  invalidate..." 

If you use hit-type cache operations in a kernel routine, then you're
safe.  I can't envisage any circumstance in which Linux would try to
invalidate kernel mainline code locations from the I-cache (well, you
might be doing something fabulous with debugging the kernel, but
that's not normal and you'd hardly expect to be able to support such
an activity with standard cache management calls).

So this problem can only arise on index-type I-cache invalidation.  I
claim that a running kernel on a MIPS CPU should only use index-type
invalidation when it is necessary to invalidate the entire I-cache.
(If you use index-type operations for a range which doesn't resolve to
"the whole cache" then that should be fixed).

That implies that a MIPS32-paranoid "invalidate-whole-I-cache" routine
should:

1. Identify which indexes might alias to cache lines 
   containing the routines's own 'cache invalidate' instruction(s),
   and thus hit the problem.  There won't be that many of them.

2. Arrange to skip those indexes when zapping the cache, then do
   something weird to invalidate that handful of lines.  You could 
   do that by running uncached, but you could also do it just by using
   some auxiliary routine which is known to be more than a cache line
   but much less than a whole I-cache span distant, so can't possibly
   alias to the same thing...

This is fiddly, but not terribly difficult and should have a
negligible performance impact.

Does that make sense?  Am I now, having named the solution,
responsible for figuring out a patch (yeuch, I never wanted to be a
kernel programmer again...).

--
Dominic Sweetman
MIPS Technologies

From a.voropay@vmb-service.ru Wed Jul 14 18:31:21 2004
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From: "Alexander Voropay" <a.voropay@vmb-service.ru>
To: "'Kevin D. Kissell'" <kevink@mips.com>, <linux-mips@linux-mips.org>
Subject: RE: MS VC++ compiler / MIPS
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Kevin D. Kissell [mailto:kevink@mips.com] wrote:

>If I recall correctly, the MS compiler uses a subltly different calling
convention/ABI
>than the "o32" gcc conventions assumed by MIPS Linux,

 The ABI is identical if the number of the int arguments <=4
(n1-> $4, n2 -> $5, n3 -> $6, n4 -> $7)
(return value --> $2)
 It should be enought for simply functions.

 Otherwise, the MSVC/MIPS does not use $fp, so stack frame structure
seems different.

 MSVC/MIPS supports 2 calling conventions (/Gd __cdecl calling
convention;
/Gr __fastcall calling convention) but I can't grok a difference.

> and certainly the assembler directives will be different from those
assumed by the Linux sources.

 Yes.

 It sems, it is impossible to build a full Linux toolcain at the MSVC
base. The MS linker
(LINK.EXE) is weak (comparing to `ld` monster) and can produce only COFF
.EXE (a.out)
MIPS executables.

>  It *might* be possible to hack up a MIPS Linux kernel source tree to
build with the MS
>tool kit, but it would be a lot of work,  some of it subtle.

 I have no plans to do it, I'm not a MIPS guru :)

--
-=AV=-


From uhler@mips.com Wed Jul 14 18:49:09 2004
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Date: Wed, 14 Jul 2004 10:45:15 -0700
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Dom's proposed solution is probably the right thing to do.  We've got some
code in MIPS that does exactly this, and I've suggested that we convert this
to provide to the Linux community.

/gmu

---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler@mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043   Mobile: (650)868-6870   Admin: (650)567-5085


> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org 
> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of 
> Dominic Sweetman
> Sent: Wednesday, July 14, 2004 9:35 AM
> To: Ralf Baechle
> Cc: Kevin D. Kissell; S C; linux-mips@linux-mips.org
> Subject: Re: Strange, strange occurence
> 
> 
> 
> Ralf Baechle (ralf@linux-mips.org) writes:
> 
> > > A truly safe and general I-cache flush routine should itself run 
> > > uncached...
> 
> It depends what you mean by general, and uncached is not the 
> only option.  The spec says:
> 
>  "The operation of the instruction is UNPREDICTABLE if the cache line
>   that contains the CACHE instruction is the target of an
>   invalidate..." 
> 
> If you use hit-type cache operations in a kernel routine, 
> then you're safe.  I can't envisage any circumstance in which 
> Linux would try to invalidate kernel mainline code locations 
> from the I-cache (well, you might be doing something fabulous 
> with debugging the kernel, but that's not normal and you'd 
> hardly expect to be able to support such an activity with 
> standard cache management calls).
> 
> So this problem can only arise on index-type I-cache 
> invalidation.  I claim that a running kernel on a MIPS CPU 
> should only use index-type invalidation when it is necessary 
> to invalidate the entire I-cache. (If you use index-type 
> operations for a range which doesn't resolve to "the whole 
> cache" then that should be fixed).
> 
> That implies that a MIPS32-paranoid "invalidate-whole-I-cache" routine
> should:
> 
> 1. Identify which indexes might alias to cache lines 
>    containing the routines's own 'cache invalidate' instruction(s),
>    and thus hit the problem.  There won't be that many of them.
> 
> 2. Arrange to skip those indexes when zapping the cache, then do
>    something weird to invalidate that handful of lines.  You could 
>    do that by running uncached, but you could also do it just by using
>    some auxiliary routine which is known to be more than a cache line
>    but much less than a whole I-cache span distant, so can't possibly
>    alias to the same thing...
> 
> This is fiddly, but not terribly difficult and should have a 
> negligible performance impact.
> 
> Does that make sense?  Am I now, having named the solution, 
> responsible for figuring out a patch (yeuch, I never wanted 
> to be a kernel programmer again...).
> 
> --
> Dominic Sweetman
> MIPS Technologies
> 
> 


From ralf@linux-mips.org Thu Jul 15 01:24:58 2004
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On Wed, Jul 14, 2004 at 09:32:23PM +0400, Alexander Voropay wrote:

>  MSVC/MIPS supports 2 calling conventions (/Gd __cdecl calling
> convention;
> /Gr __fastcall calling convention) but I can't grok a difference.

Probably more argument registers etc.  I'd expect something along the
NABI callign conventions.

> > and certainly the assembler directives will be different from those
> assumed by the Linux sources.
> 
>  Yes.
> 
>  It sems, it is impossible to build a full Linux toolcain at the MSVC
> base. The MS linker
> (LINK.EXE) is weak (comparing to `ld` monster) and can produce only COFF
> .EXE (a.out)
> MIPS executables.

PECOFF, Microsoft's ECOFF variant which basically is ECOFF plus an MSDOS
executable header.  Yes, we all run MSDOS on our MIPS boxes so that's
and important feature ;-)

  Ralf

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On Wed, Jul 14, 2004 at 05:07:06PM +0200, Kevin D. Kissell wrote:

> If I recall correctly, the MS compiler uses a subltly different
> calling convention/ABI than the "o32" gcc conventions assumed
> by MIPS Linux, and certainly the assembler directives will be
> different from those assumed by the Linux sources.  It *might*
> be possible to hack up a MIPS Linux kernel source tree to
> build with the MS tool kit, but it would be a lot of work, 
> some of it subtle.

A few years ago we got SGI's IA-64 kernel to compile with their Pro64
compiler.  Despite the usually rather dramatic superiority of Pro64's
code generation compared to the gcc of that time - half the time to
generate twice as fast application code was common - the huge effort
it took was essentially wasted time to achieve a hard to meassure amount
of extra performance.  Most of the kernel code is well optimized, was
written with being compiled by gcc in mind and performance is more
limited by the hardware and kernel algorithms than by the compiler's
code generation.  So I wouldn't invest any time into trying to get the
kernel working on yet another non-gcc compiler ...

  Ralf

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>>>>> On Wed, 14 Jul 2004 17:35:19 +0100, Dominic Sweetman <dom@mips.com> said:
dom> 2. Arrange to skip those indexes when zapping the cache, then do
dom> something weird to invalidate that handful of lines.  You could
dom> do that by running uncached, but you could also do it just by
dom> using some auxiliary routine which is known to be more than a
dom> cache line but much less than a whole I-cache span distant, so
dom> can't possibly alias to the same thing...

dom> This is fiddly, but not terribly difficult and should have a
dom> negligible performance impact.

Yes.  The cache routines for TX49XX surely do it (2 phase
invalidating).  Please look at tx49_blast_icache32() in c-r4k.c.

---
Atsushi Nemoto

From ralf@linux-mips.org Thu Jul 15 02:53:34 2004
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On Wed, Jul 14, 2004 at 05:35:19PM +0100, Dominic Sweetman wrote:

> If you use hit-type cache operations in a kernel routine, then you're
> safe.  I can't envisage any circumstance in which Linux would try to
> invalidate kernel mainline code locations from the I-cache (well, you
> might be doing something fabulous with debugging the kernel, but
> that's not normal and you'd hardly expect to be able to support such
> an activity with standard cache management calls).
> 
> So this problem can only arise on index-type I-cache invalidation.  I
> claim that a running kernel on a MIPS CPU should only use index-type
> invalidation when it is necessary to invalidate the entire I-cache.
> (If you use index-type operations for a range which doesn't resolve to
> "the whole cache" then that should be fixed).
> 
> That implies that a MIPS32-paranoid "invalidate-whole-I-cache" routine
> should:
> 
> 1. Identify which indexes might alias to cache lines 
>    containing the routines's own 'cache invalidate' instruction(s),
>    and thus hit the problem.  There won't be that many of them.
> 
> 2. Arrange to skip those indexes when zapping the cache, then do
>    something weird to invalidate that handful of lines.  You could 
>    do that by running uncached, but you could also do it just by using
>    some auxiliary routine which is known to be more than a cache line
>    but much less than a whole I-cache span distant, so can't possibly
>    alias to the same thing...
> 
> This is fiddly, but not terribly difficult and should have a
> negligible performance impact.
> 
> Does that make sense?  Am I now, having named the solution,
> responsible for figuring out a patch (yeuch, I never wanted to be a
> kernel programmer again...).

You don't have to :-)  What became a architectural restriction for MIPS32
did already show up earlier as an erratum for the TX49/H2 core.  This is
the solution which we currently have in the kernel code:

#define JUMP_TO_ALIGN(order) \
	__asm__ __volatile__( \
		"b\t1f\n\t" \
		".align\t" #order "\n\t" \
		"1:\n\t" \
		)
#define CACHE32_UNROLL32_ALIGN	JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
#define CACHE32_UNROLL32_ALIGN2	JUMP_TO_ALIGN(11)

static inline void mips32_blast_icache32(void)
{
	unsigned long start = INDEX_BASE;
	unsigned long end = start + current_cpu_data.icache.waysize;
	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
	unsigned long ws_end = current_cpu_data.icache.ways <<
	                       current_cpu_data.icache.waybit;
	unsigned long ws, addr;

	CACHE32_UNROLL32_ALIGN2;
	/* I'm in even chunk.  blast odd chunks */
	for (ws = 0; ws < ws_end; ws += ws_inc) 
		for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 
			cache32_unroll32(addr|ws,Index_Invalidate_I);
	CACHE32_UNROLL32_ALIGN;
	/* I'm in odd chunk.  blast even chunks */
	for (ws = 0; ws < ws_end; ws += ws_inc) 
		for (addr = start; addr < end; addr += 0x400 * 2) 
			cache32_unroll32(addr|ws,Index_Invalidate_I);
}

All it takes is using this for all MIPS32 / MIPS64 or maybe even all
processors and some tuning of constants to make this suitable for
all possible I-cache configurations.

  Ralf

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On Wed, 14 Jul 2004, Jan-Benedict Glaw wrote:

> Eventually I'll re-get all the sources and compile again. Adding a
> timeout shouldn't be all that hard. It should be a matter of extending
> the "connection" table by "last packet's recv/send time" and check this
> table entry upon each new request.

 But you probably have to take resumption into account -- a client may
restart sending requests from the point it stopped.  It may happen after a
link is restored somewhere on the way after a break, for example.  Though
I haven't checked if there's any timeout defined in the MOP spec or
imposed by specific MOP download clients -- perhaps there is.

> >  Another problem which is already known is mopd dying when one of
> > interfaces it's listening on goes down.
> 
> Haven't seen that, but my interfaces tend to not go down (at least not
> until the whole machine goes down...).

 Mine tend to do that after I do `ifconfig <iface> down', which is what I
sometimes do.  I need to remember to restart mopd then.  Perhaps mopd
should monitor interfaces appearing and disappearing in general, taking
the restriction on the command line into account, of course.

  Maciej

From wsonguci@yahoo.com Thu Jul 15 23:22:41 2004
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Date: Thu, 15 Jul 2004 15:22:34 -0700 (PDT)
From: Song Wang <wsonguci@yahoo.com>
Subject: asm-mips/processor.h breaks compiling user applications such as iptables
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Hi, Ralf

I am building the latest iptables-1.2.11 against
linux-mips kernel 2.6.6.

When compiling extensions/libipt_state.c

#mips-linux-uclibc-gcc -s -Os -Wall -Wunused
-I/mipslinux2.6.6/linux/include -Iinclude/
-DIPTABLES_VERSION=\"1.2.11\"  -DNO_SHARED_LIBS=1
-D_INIT=ipt_state_init -c -o extensions/libipt_state.o
extensions/libipt_state.c

I got error

In file included from
/mipslinux2.6.6/linux/include/linux/spinlock.h:16,
                 from
/mipslinux2.6.6/linux/include/asm/atomic.h:21,
                 from
/mipslinux2.6.6/linux/include/linux/netfilter_ipv4/ip_conntrack.h:11,
                 from extensions/libipt_state.c:8:
/mipslinux2.6.6/linux/include/asm/processor.h:146:
error: parse error before "fpureg_t"
/mipslinux2.6.6/linux/include/asm/processor.h:146:
warning: type defaults to `int' in declaration of
`fpureg_t'
/mipslinux2.6.6/linux/include/asm/processor.h:146:
warning: data definition has no type or storage class
/mipslinux2.6.6/linux/include/asm/processor.h:149:
error: parse error before "fpureg_t"
/mipslinux2.6.6/linux/include/asm/processor.h:149:
warning: no semicolon at end of struct or union
/mipslinux2.6.6/linux/include/asm/processor.h:151:
error: parse error before '}' token
/mipslinux2.6.6/linux/include/asm/processor.h:161:
error: parse error before "fpureg_t"
/mipslinux2.6.6/linux/include/asm/processor.h:161:
warning: no semicolon at end of struct or union
/mipslinux2.6.6/linux/include/asm/processor.h:163:
error: parse error before '}' token
/mipslinux2.6.6/linux/include/asm/processor.h:166:
error: field `hard' has incomplete type
/mipslinux2.6.6/linux/include/asm/processor.h:167:
error: field `soft' has incomplete type
make[1]: *** [extensions/libipt_state.o] Error 1


I think the error is due to the line 146

typedef u64 fpureg_t;

The type 'u64' is defined in asm-mips/types.h, but
wrapped by #ifdef __KERNEL__, so when the compiler
compiles the user-level application, it cannot
recognize u64.

-Song





		
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From ralf@linux-mips.org Thu Jul 15 23:56:59 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: Song Wang <wsonguci@yahoo.com>
Cc: linux-mips@linux-mips.org
Subject: Re: asm-mips/processor.h breaks compiling user applications such as iptables
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On Thu, Jul 15, 2004 at 03:22:34PM -0700, Song Wang wrote:

> I think the error is due to the line 146
> 
> typedef u64 fpureg_t;
> 
> The type 'u64' is defined in asm-mips/types.h, but
> wrapped by #ifdef __KERNEL__, so when the compiler
> compiles the user-level application, it cannot
> recognize u64.

Correct.  In general the policy is to avoid the use of kernel header
files in user space and copy it but there are still a few crucial tools
that don't follow this rule of Linus, so try below patch.  It also
removes the __KERNEL__ things left.

Cleaning up the use of kernel header to make them more usable for
userspace is one of the things on the agenda for 2.7.  It'll be alot of
hard and boring work but MIPS will be one of the architectures that will
greatly benefit from this.

  Ralf

Index: include/asm-mips/processor.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/processor.h,v
retrieving revision 1.94
diff -u -r1.94 processor.h
--- include/asm-mips/processor.h	28 Jun 2004 21:04:16 -0000	1.94
+++ include/asm-mips/processor.h	15 Jul 2004 22:42:29 -0000
@@ -143,7 +143,7 @@
 
 #define NUM_FPU_REGS	32
 
-typedef u64 fpureg_t;
+typedef __u64 fpureg_t;
 
 struct mips_fpu_hard_struct {
 	fpureg_t	fpr[NUM_FPU_REGS];
@@ -235,8 +235,6 @@
 	MF_FIXADE, 0, 0 \
 }
 
-#ifdef __KERNEL__
-
 struct task_struct;
 
 /* Free all resources held by a thread. */
@@ -264,8 +262,6 @@
 
 #define cpu_relax()	barrier()
 
-#endif /* __KERNEL__ */
-
 /*
  * Return_address is a replacement for __builtin_return_address(count)
  * which on certain architectures cannot reasonably be implemented in GCC

From wsonguci@yahoo.com Fri Jul 16 03:01:54 2004
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Date: Thu, 15 Jul 2004 19:01:47 -0700 (PDT)
From: Song Wang <wsonguci@yahoo.com>
Subject: Re: asm-mips/processor.h breaks compiling user applications such as iptables
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
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--- Ralf Baechle <ralf@linux-mips.org> wrote:
> On Thu, Jul 15, 2004 at 03:22:34PM -0700, Song Wang
> wrote:
> 
> > I think the error is due to the line 146
> > 
> > typedef u64 fpureg_t;
> > 
> > The type 'u64' is defined in asm-mips/types.h, but
> > wrapped by #ifdef __KERNEL__, so when the compiler
> > compiles the user-level application, it cannot
> > recognize u64.
> 
> Correct.  In general the policy is to avoid the use
> of kernel header
> files in user space and copy it but there are still
> a few crucial tools
> that don't follow this rule of Linus, so try below
> patch.  It also
> removes the __KERNEL__ things left.
> 
> Cleaning up the use of kernel header to make them
> more usable for
> userspace is one of the things on the agenda for
> 2.7.  It'll be alot of
> hard and boring work but MIPS will be one of the
> architectures that will
> greatly benefit from this.
> 
>   Ralf
> 
Hi, Ralf

I tested the patch and it compiles fine now, although
when iptables actually runs on mips32, all the 
tcp/udp port numbers are shown as 0 and IP address
shown as 0.0.0.0. I'll dig more.

Anyway, you made a good point for kernel headers
problem. It's kinda headache.

Similar problem happened to asm-mips/page.h when
including <spaces.h> in 2.6.6, but it seemed that
you already fixed in the latest cvs version.

Thanks.

-Song


		
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From ralf@linux-mips.org Fri Jul 16 13:24:16 2004
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	Fri, 16 Jul 2004 14:24:09 +0200
Date: Fri, 16 Jul 2004 14:24:09 +0200
From: Ralf Baechle <ralf@linux-mips.org>
To: Dominic Sweetman <dom@mips.com>
Cc: "Kevin D. Kissell" <KevinK@mips.com>,
	S C <theansweriz42@hotmail.com>, linux-mips@linux-mips.org
Subject: Re: Strange, strange occurence
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On Wed, Jul 14, 2004 at 05:35:19PM +0100, Dominic Sweetman wrote:

> This is fiddly, but not terribly difficult and should have a
> negligible performance impact.
> 
> Does that make sense?  Am I now, having named the solution,
> responsible for figuring out a patch (yeuch, I never wanted to be a
> kernel programmer again...).

No and yes - but here is a simpler solution.  Below patch solves the
problem and adds just 32 bytes of code but removes the special case for
TX49/H2 entirely.

  Ralf

 arch/mips/mm/c-r4k.c        |   59 -------------------------------------------- include/asm-mips/r4kcache.h |   18 ++++++++-----
 include/asm-mips/war.h      |   14 ----------
 3 files changed, 13 insertions(+), 78 deletions(-)


Index: arch/mips/mm/c-r4k.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.88
diff -u -r1.88 c-r4k.c
--- arch/mips/mm/c-r4k.c	16 Jul 2004 12:06:13 -0000	1.88
+++ arch/mips/mm/c-r4k.c	16 Jul 2004 12:17:05 -0000
@@ -96,16 +96,6 @@
 		r4k_blast_dcache = blast_dcache32;
 }
 
-/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
-#define JUMP_TO_ALIGN(order) \
-	__asm__ __volatile__( \
-		"b\t1f\n\t" \
-		".align\t" #order "\n\t" \
-		"1:\n\t" \
-		)
-#define CACHE32_UNROLL32_ALIGN	JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
-#define CACHE32_UNROLL32_ALIGN2	JUMP_TO_ALIGN(11)
-
 static inline void blast_r4600_v1_icache32(void)
 {
 	unsigned long flags;
@@ -115,27 +105,6 @@
 	local_irq_restore(flags);
 }
 
-static inline void tx49_blast_icache32(void)
-{
-	unsigned long start = INDEX_BASE;
-	unsigned long end = start + current_cpu_data.icache.waysize;
-	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
-	unsigned long ws_end = current_cpu_data.icache.ways <<
-	                       current_cpu_data.icache.waybit;
-	unsigned long ws, addr;
-
-	CACHE32_UNROLL32_ALIGN2;
-	/* I'm in even chunk.  blast odd chunks */
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 
-			cache32_unroll32(addr|ws,Index_Invalidate_I);
-	CACHE32_UNROLL32_ALIGN;
-	/* I'm in odd chunk.  blast even chunks */
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x400 * 2) 
-			cache32_unroll32(addr|ws,Index_Invalidate_I);
-}
-
 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 {
 	unsigned long flags;
@@ -145,27 +114,6 @@
 	local_irq_restore(flags);
 }
 
-static inline void tx49_blast_icache32_page_indexed(unsigned long page)
-{
-	unsigned long start = page;
-	unsigned long end = start + PAGE_SIZE;
-	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
-	unsigned long ws_end = current_cpu_data.icache.ways <<
-	                       current_cpu_data.icache.waybit;
-	unsigned long ws, addr;
-
-	CACHE32_UNROLL32_ALIGN2;
-	/* I'm in even chunk.  blast odd chunks */
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 
-			cache32_unroll32(addr|ws,Index_Invalidate_I);
-	CACHE32_UNROLL32_ALIGN;
-	/* I'm in odd chunk.  blast even chunks */
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x400 * 2) 
-			cache32_unroll32(addr|ws,Index_Invalidate_I);
-}
-
 static void (* r4k_blast_icache_page)(unsigned long addr);
 
 static inline void r4k_blast_icache_page_setup(void)
@@ -190,10 +138,7 @@
 	if (ic_lsize == 16)
 		r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 	else if (ic_lsize == 32) {
-		if (TX49XX_ICACHE_INDEX_INV_WAR)
-			r4k_blast_icache_page_indexed =
-				tx49_blast_icache32_page_indexed;
-		else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
+		if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 			r4k_blast_icache_page_indexed =
 				blast_icache32_r4600_v1_page_indexed;
 		else
@@ -214,8 +159,6 @@
 	else if (ic_lsize == 32) {
 		if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 			r4k_blast_icache = blast_r4600_v1_icache32;
-		else if (TX49XX_ICACHE_INDEX_INV_WAR)
-			r4k_blast_icache = tx49_blast_icache32;
 		else
 			r4k_blast_icache = blast_icache32;
 	} else if (ic_lsize == 64)
Index: include/asm-mips/r4kcache.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/r4kcache.h,v
retrieving revision 1.22
diff -u -r1.22 r4kcache.h
--- include/asm-mips/r4kcache.h	5 Jan 2004 01:56:01 -0000	1.22
+++ include/asm-mips/r4kcache.h	16 Jul 2004 12:17:05 -0000
@@ -192,7 +192,7 @@
 
 static inline void blast_icache16(void)
 {
-	unsigned long start = INDEX_BASE;
+	unsigned long start = (unsigned long) &&body + 0x100;
 	unsigned long end = start + current_cpu_data.icache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 	unsigned long ws_end = current_cpu_data.icache.ways <<
@@ -200,8 +200,10 @@
 	unsigned long ws, addr;
 
 	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x200) 
+		for (addr = start; addr < end; addr += 0x200) {
+body:
 			cache16_unroll32(addr|ws,Index_Invalidate_I);
+		}
 }
 
 static inline void blast_icache16_page(unsigned long page)
@@ -335,7 +337,7 @@
 
 static inline void blast_icache32(void)
 {
-	unsigned long start = INDEX_BASE;
+	unsigned long start = (unsigned long) &&body + 0x200;
 	unsigned long end = start + current_cpu_data.icache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 	unsigned long ws_end = current_cpu_data.icache.ways <<
@@ -343,8 +345,10 @@
 	unsigned long ws, addr;
 
 	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x400) 
+		for (addr = start; addr < end; addr += 0x400)  {
+body:
 			cache32_unroll32(addr|ws,Index_Invalidate_I);
+		}
 }
 
 static inline void blast_icache32_page(unsigned long page)
@@ -439,7 +443,7 @@
 
 static inline void blast_icache64(void)
 {
-	unsigned long start = INDEX_BASE;
+	unsigned long start = (unsigned long) &&body + 0x400;
 	unsigned long end = start + current_cpu_data.icache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 	unsigned long ws_end = current_cpu_data.icache.ways <<
@@ -447,8 +451,10 @@
 	unsigned long ws, addr;
 
 	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x800) 
+		for (addr = start; addr < end; addr += 0x800) {
+body:
 			cache64_unroll32(addr|ws,Index_Invalidate_I);
+		}
 }
 
 static inline void blast_icache64_page(unsigned long page)
Index: include/asm-mips/war.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/war.h,v
retrieving revision 1.18
diff -u -r1.18 war.h
--- include/asm-mips/war.h	5 Mar 2004 02:47:19 -0000	1.18
+++ include/asm-mips/war.h	16 Jul 2004 12:17:05 -0000
@@ -158,17 +158,6 @@
 #endif
 
 /*
- * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
- * the line which this instruction itself exists, the following
- * operation is not guaranteed."
- *
- * Workaround: do two phase flushing for Index_Invalidate_I
- */
-#ifdef CONFIG_CPU_TX49XX
-#define TX49XX_ICACHE_INDEX_INV_WAR 1
-#endif
-
-/*
  * On the RM9000 there is a problem which makes the CreateDirtyExclusive
  * cache operation unusable on SMP systems.
  */
@@ -203,9 +192,6 @@
 #ifndef MIPS_CACHE_SYNC_WAR
 #define MIPS_CACHE_SYNC_WAR		0
 #endif
-#ifndef TX49XX_ICACHE_INDEX_INV_WAR
-#define TX49XX_ICACHE_INDEX_INV_WAR	0
-#endif
 #ifndef RM9000_CDEX_SMP_WAR
 #define RM9000_CDEX_SMP_WAR		0
 #endif

From collin@xorotude.com Fri Jul 16 15:41:44 2004
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From: "Collin Baillie" <collin@xorotude.com>
To: "Jan-Benedict Glaw" <jbglaw@lug-owl.de>
Cc: linux-mips@linux-mips.org
References: <BAY2-F21njXXBARdkfw0003b0c8@hotmail.com> <20040710100412.GA23624@linux-mips.org> <00ba01c46823$3729b200$0deca8c0@Ulysses> <20040713003317.GA26715@linux-mips.org> <000701c468ae$141c3e50$0a9913ac@swift> <20040713080320.GC18841@lug-owl.de> <000e01c4696f$f65cf4f0$0a9913ac@swift> <20040714124318.GQ2019@lug-owl.de>
Subject: Re: Help with MOP network boot install on DECstation 5000/240
Date: Fri, 16 Jul 2004 22:41:01 +0800
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> > > Maybe you'd try Debian's install image?
> > Maybe, but on a _shared_ 31.2k dialup link, it takes a while to
download...
> It's only a couple of megabytes, not a number of CD images.

Ok, I found a 4.5MB boot.img file which is supposed to be the netboot debian
installer for r3k-kn03 mipsel. mopd doesn't seem to like it's a.out-ness.
mopchk gives (I named it DEBIAN.SYS for the purpose of mop booting):

Checking: DEBIAN.SYS
Some failure in GetAOutFileInfo

Does mopd work with a.out files? I read somewhere it doesn't. Is this the
install image you speak of? There doesn't seem to be a cd-rom version. I
really have difficulties with Debian's site. Any help you guys could offer
me would be appreciated.

Cheers,

Collin


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From: Jan-Benedict Glaw <jbglaw@lug-owl.de>
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Subject: Re: Help with MOP network boot install on DECstation 5000/240
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On Fri, 2004-07-16 22:41:01 +0800, Collin Baillie <collin@xorotude.com>
wrote in message <000c01c46b42$fd6f9b60$0a9913ac@swift>:
> > > > Maybe you'd try Debian's install image?
> > > Maybe, but on a _shared_ 31.2k dialup link, it takes a while to
> download...
> > It's only a couple of megabytes, not a number of CD images.
>=20
> Ok, I found a 4.5MB boot.img file which is supposed to be the netboot deb=
ian
> installer for r3k-kn03 mipsel. mopd doesn't seem to like it's a.out-ness.
> mopchk gives (I named it DEBIAN.SYS for the purpose of mop booting):
>=20
> Checking: DEBIAN.SYS
> Some failure in GetAOutFileInfo
>=20
> Does mopd work with a.out files? I read somewhere it doesn't. Is this the

Depends on your mopd:) There are several mopds around...

> install image you speak of? There doesn't seem to be a cd-rom version. I

Most probably.

> really have difficulties with Debian's site. Any help you guys could offer
> me would be appreciated.

Use a proper mopd like that one from Maciej (he replied earlier in this
thread, containing an URL for it.

MfG, JBG

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From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Collin Baillie <collin@xorotude.com>
Cc: Jan-Benedict Glaw <jbglaw@lug-owl.de>, linux-mips@linux-mips.org
Subject: Re: Help with MOP network boot install on DECstation 5000/240
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On Fri, 16 Jul 2004, Collin Baillie wrote:

> Ok, I found a 4.5MB boot.img file which is supposed to be the netboot debian
> installer for r3k-kn03 mipsel. mopd doesn't seem to like it's a.out-ness.
> mopchk gives (I named it DEBIAN.SYS for the purpose of mop booting):
> 
> Checking: DEBIAN.SYS
> Some failure in GetAOutFileInfo
> 
> Does mopd work with a.out files? I read somewhere it doesn't. Is this the
> install image you speak of? There doesn't seem to be a cd-rom version. I
> really have difficulties with Debian's site. Any help you guys could offer
> me would be appreciated.

 This is supposedly an ECOFF image for booting with TFTP.  If you can't 
get the ELF image it was converted from, you may try converting it back to 
ELF like this:

$ mipsel-linux-objcopy -O elf32-tradlittlemips boot.img DEBIAN.SYS

I have never used that, though, so I can't say if it works.  Actually
objcopy from more or less current binutils emits a bogus warning when 
executing the above command.

  Maciej

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On Fri, 16 Jul 2004, Jan-Benedict Glaw wrote:

> > Does mopd work with a.out files? I read somewhere it doesn't. Is this the
> 
> Depends on your mopd:) There are several mopds around...

 I don't think any version supports MIPS ECOFF.  COFF and ECOFF are nasty
formats defined differently for different processors, so generic support,
similar to one for ELF, is impossible.  Just don't use ECOFF unless you
absolutely have to.

  Maciej

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>>>>> On Fri, 16 Jul 2004 14:24:09 +0200, Ralf Baechle <ralf@linux-mips.org> said:

ralf> No and yes - but here is a simpler solution.  Below patch solves
ralf> the problem and adds just 32 bytes of code but removes the
ralf> special case for TX49/H2 entirely.

Hmm... Does this patch really solves the problem?

Here is a disassemble list of blast_icache32 (gcc 3.3.3).  The
comments on CACHE instructions are indices of cachelines which the
instruction invalidates.  (for 4 way 16KB cache --- 4KB waysize).

80039ca0 <blast_icache32>:
80039ca0:       3c048038        lui     a0,0x8038
80039ca4:       8c849e2c        lw      a0,-25044(a0)
80039ca8:       3c028038        lui     v0,0x8038
80039cac:       94429e22        lhu     v0,-25054(v0)
80039cb0:       3c038038        lui     v1,0x8038
80039cb4:       8c639e28        lw      v1,-25048(v1)
80039cb8:       00824004        sllv    t0,v0,a0
80039cbc:       24020001        li      v0,1
80039cc0:       3c018004        lui     at,0x8004
80039cc4:       24219ef4        addiu   at,at,-24844	# 80039ef4
80039cc8:       00231821        addu    v1,at,v1
80039ccc:       00823804        sllv    a3,v0,a0
80039cd0:       11000031        beqz    t0,80039d98 <blast_icache32+0xf8>
80039cd4:       00002821        move    a1,zero
80039cd8:       3c028004        lui     v0,0x8004
80039cdc:       24429ef4        addiu   v0,v0,-24844	# 80039ef4
80039ce0:       0043302b        sltu    a2,v0,v1
80039ce4:       3c048004        lui     a0,0x8004
80039ce8:       24849ef4        addiu   a0,a0,-24844	# 80039ef4
80039cec:       50c00027        beqzl   a2,80039d8c <blast_icache32+0xec>
80039cf0:       00a72821        addu    a1,a1,a3
80039cf4:       00851025        or      v0,a0,a1
80039cf8:       bc400000        cache   0x0,0(v0)	# ee0 2e0 6e0 ae0
80039cfc:       bc400020        cache   0x0,32(v0)	# f00 300 700 b00
80039d00:       bc400040        cache   0x0,64(v0)
80039d04:       bc400060        cache   0x0,96(v0)
80039d08:       bc400080        cache   0x0,128(v0)
80039d0c:       bc4000a0        cache   0x0,160(v0)
80039d10:       bc4000c0        cache   0x0,192(v0)
80039d14:       bc4000e0        cache   0x0,224(v0)
80039d18:       bc400100        cache   0x0,256(v0)
80039d1c:       bc400120        cache   0x0,288(v0)	# 000 400 800 c00
80039d20:       bc400140        cache   0x0,320(v0)
80039d24:       bc400160        cache   0x0,352(v0)
80039d28:       bc400180        cache   0x0,384(v0)
80039d2c:       bc4001a0        cache   0x0,416(v0)
80039d30:       bc4001c0        cache   0x0,448(v0)
80039d34:       bc4001e0        cache   0x0,480(v0)
80039d38:       bc400200        cache   0x0,512(v0)
80039d3c:       bc400220        cache   0x0,544(v0)	# 100 500 900 d00
80039d40:       bc400240        cache   0x0,576(v0)	# 120 520 920 d20
80039d44:       bc400260        cache   0x0,608(v0)	# 140 540 940 d40 !!!
80039d48:       bc400280        cache   0x0,640(v0)
80039d4c:       bc4002a0        cache   0x0,672(v0)
80039d50:       bc4002c0        cache   0x0,704(v0)
80039d54:       bc4002e0        cache   0x0,736(v0)
80039d58:       bc400300        cache   0x0,768(v0)
80039d5c:       bc400320        cache   0x0,800(v0)	# 200 600 a00 e00
80039d60:       bc400340        cache   0x0,832(v0)
80039d64:       bc400360        cache   0x0,864(v0)
80039d68:       bc400380        cache   0x0,896(v0)
80039d6c:       bc4003a0        cache   0x0,928(v0)
80039d70:       bc4003c0        cache   0x0,960(v0)
80039d74:       bc4003e0        cache   0x0,992(v0)
80039d78:       24840400        addiu   a0,a0,1024
80039d7c:       0083102b        sltu    v0,a0,v1
80039d80:       1440ffdd        bnez    v0,80039cf8 <blast_icache32+0x58>
80039d84:       00851025        or      v0,a0,a1
80039d88:       00a72821        addu    a1,a1,a3
80039d8c:       00a8102b        sltu    v0,a1,t0
80039d90:       1440ffd4        bnez    v0,80039ce4 <blast_icache32+0x44>
80039d94:       00000000        nop
80039d98:       03e00008        jr      ra
80039d9c:       00000000        nop


The target address of the first CACHE instruction is 0x80039ef4.  It
invalidates index 0xee0 line.  The CACHE instruction on 0x80039d44
invalidates index 0xd40 line which may contains the
instruction... Ouch!!!

I suppose "two-phase invalidating" must be required to solve this
problem.

---
Atsushi Nemoto

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To: linux-mips@linux-mips.org
Subject: Re: Help with MOP network boot install on DECstation 5000/240
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References: <BAY2-F21njXXBARdkfw0003b0c8@hotmail.com> <20040710100412.GA23624@linux-mips.org> <00ba01c46823$3729b200$0deca8c0@Ulysses> <20040713003317.GA26715@linux-mips.org> <000701c468ae$141c3e50$0a9913ac@swift> <20040713080320.GC18841@lug-owl.de> <000e01c4696f$f65cf4f0$0a9913ac@swift> <20040714124318.GQ2019@lug-owl.de> <000c01c46b42$fd6f9b60$0a9913ac@swift> <Pine.LNX.4.55.0407161644440.6227@jurand.ds.pg.gda.pl>
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Maciej W. Rozycki wrote:
[snip]
>  This is supposedly an ECOFF image for booting with TFTP.  If you can't 
> get the ELF image it was converted from, you may try converting it back to 
> ELF like this:

It isn't converted ELF but the output of the t-rex utility, which combines
ECOFF header, ELF stub, kernel and ramdisk into one file.


Thiemo

From dom@mips.com Fri Jul 16 17:50:39 2004
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Date: Fri, 16 Jul 2004 17:50:25 +0100
To: linux-mips@linux-mips.org
Subject: Linux kernel engineer job at MIPS Technologies, Cambridge
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I hope you'll excuse us putting this out once on this list.

MIPS Technologies needs a Linux kernel engineer to work in Cambridge,
UK.  We could use you right now!

This engineer will work in a tight-knit team exploiting the
multithreading capacities for MIPS synthesizable cores.

We're a small team, and the successful candidate will get to share in
the everyday, difficult work: maintaining the Linux kernel, testing
toolchains, and debugging new hardware.

This position requires a knowledgeable, experienced software engineer
with significant Linux kernel experience.

You should have a track record of contribution to Linux code,
experience with coding device drivers, strong knowledge of C, and an
understanding of microprocessors at the machine level.

A degree-level qualification is desirable but not specifically
required. 

This position is open to E.U. citizens; however, a relocation package
is not provided. To apply for this position, email resume to
mailto:johnrob@mips.com or mailto:getajob@mips.com. MIPS is an equal
opportunity employer.

-- 
Dominic Sweetman, 
MIPS Technologies (UK)
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone: +44 1223 706205 / fax: +44 1223 706250 / swbrd: +44 1223 706200
http://www.mips.com


From macro@linux-mips.org Fri Jul 16 17:51:32 2004
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On Fri, 16 Jul 2004, Thiemo Seufer wrote:

> >  This is supposedly an ECOFF image for booting with TFTP.  If you can't 
> > get the ELF image it was converted from, you may try converting it back to 
> > ELF like this:
> 
> It isn't converted ELF but the output of the t-rex utility, which combines
> ECOFF header, ELF stub, kernel and ramdisk into one file.

 I stand corrected.  The image should still work if converted to ELF and
then loaded, though, shouldn't it?

  Maciej

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Subject: libpcap.a
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Hello,

Can somebody share libpcap.a for MIPS platform. Please email me or give me a link to download. 

Thank You

Tejas Kokje
Graduate Student (Computer Science)
University of Southern California
URL : http://www-scf.usc.edu/~kokje
Registered Linux User #: 337673

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Maciej W. Rozycki wrote:
> On Fri, 16 Jul 2004, Thiemo Seufer wrote:
> 
> > >  This is supposedly an ECOFF image for booting with TFTP.  If you can't 
> > > get the ELF image it was converted from, you may try converting it back to 
> > > ELF like this:
> > 
> > It isn't converted ELF but the output of the t-rex utility, which combines
> > ECOFF header, ELF stub, kernel and ramdisk into one file.
> 
>  I stand corrected.  The image should still work if converted to ELF and
> then loaded, though, shouldn't it?

At least I don't see a reason for it to break. I've never tried to
convert it to ELF, though, and binutils support for format conversion
generally isn't as reliable as it should be.


Thiemo

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From: Wolfgang Denk <wd@denx.de>
Subject: Re: libpcap.a 
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In message <20040716185420.D3CA6398199@ws5-1.us4.outblaze.com> you wrote:
> 
> Can somebody share libpcap.a for MIPS platform. Please email me or give me a link to download. 

LE or BE? Compatible with which version of GLIBC?

[http://www.denx.de/ELDK.html ??]

Best regards,

Wolfgang Denk

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From kokje@linuxmail.org Fri Jul 16 20:35:34 2004
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Sorry completely missed out those points.

I want libpcap.a for Little Endian (mipsel). I am writing a small sniffer utility for Linksys WRT54GS router.
glibc version on the router is 2.2.3.


Thanks



----- Original Message -----
From: Wolfgang Denk <wd@denx.de>
Date: Fri, 16 Jul 2004 21:29:24 +0200
To: "Tejas Kokje" <kokje@linuxmail.org>
Subject: Re: libpcap.a 

> In message <20040716185420.D3CA6398199@ws5-1.us4.outblaze.com> you wrote:
> > 
> > Can somebody share libpcap.a for MIPS platform. Please email me or give me a link to download. 
> 
> LE or BE? Compatible with which version of GLIBC?
> 
> [http://www.denx.de/ELDK.html ??]
> 
> Best regards,
> 
> Wolfgang Denk
> 
> -- 
> Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
> Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
> There is only one way to console a widow.  But remember the risk.
>                                                    -- Robert Heinlein



Tejas Kokje
Graduate Student (Computer Science)
University of Southern California
URL : http://www-scf.usc.edu/~kokje
Registered Linux User #: 337673

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From macro@linux-mips.org Mon Jul 19 15:22:03 2004
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: binutils@sources.redhat.com, cgd@broadcom.com
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On Mon, 28 Jun 2004 cgd@broadcom.com wrote:

> personally, i'd make the comment on the 'break' testcase in mips32.s a bit
> clearer and more explicit.  e.g. "for a while, break for mips32 
> took a 20 bit code.  But that was incompatible and caused problems, so
> now it's back to the old 10 bit code, or two comma-separated 10 bit codes."

 Here is an update, including your suggested comment changes as well as an
additional test case to assure single-argument "break" instructions have
the code placed correctly (this has led to an address shift enlarging the
patch significantly, unfortunately).  The gas testsuite has been verified
to pass after the change.

opcodes/:
2004-07-19  Maciej W. Rozycki  <macro@linux-mips.org>

	* mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
	ISA-specific "break" encoding.

gas/testsuite/:
2004-07-19  Maciej W. Rozycki  <macro@linux-mips.org>

	* gas/mips/mips32.s: Adjust for the unified "break" syntax.  Add 
	another "break" case.  Update the comment accordingly.
	* gas/mips/set-arch.s: Likewise.
	* gas/mips/mips32.d: Adjust for the new output.
	* gas/mips/set-arch.d: Likewise.

 OK to apply?

  Maciej

binutils-2.15.91-20040715-mips-break20.patch
diff -up --recursive --new-file binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/mips32.d binutils-2.15.91-20040715/gas/testsuite/gas/mips/mips32.d
--- binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/mips32.d	2003-05-08 03:25:35.000000000 +0000
+++ binutils-2.15.91-20040715/gas/testsuite/gas/mips/mips32.d	2004-07-18 19:10:00.000000000 +0000
@@ -48,8 +48,9 @@ Disassembly of section .text:
 0+0098 <[^>]*> 4359e260 	wait	0x56789
 0+009c <[^>]*> 0000000d 	break
 0+00a0 <[^>]*> 0000000d 	break
-0+00a4 <[^>]*> 0048d14d 	break	0x12345
-0+00a8 <[^>]*> 7000003f 	sdbbp
+0+00a4 <[^>]*> 0345000d 	break	0x345
+0+00a8 <[^>]*> 0048d14d 	break	0x48,0x345
 0+00ac <[^>]*> 7000003f 	sdbbp
-0+00b0 <[^>]*> 7159e27f 	sdbbp	0x56789
+0+00b0 <[^>]*> 7000003f 	sdbbp
+0+00b4 <[^>]*> 7159e27f 	sdbbp	0x56789
 	...
diff -up --recursive --new-file binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/mips32.s binutils-2.15.91-20040715/gas/testsuite/gas/mips/mips32.s
--- binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/mips32.s	2002-09-05 03:25:40.000000000 +0000
+++ binutils-2.15.91-20040715/gas/testsuite/gas/mips/mips32.s	2004-07-18 19:30:04.000000000 +0000
@@ -58,11 +58,17 @@ text_label:
       wait    0                       # disassembles without code
       wait    0x56789
 
-      # Instructions in previous ISAs or CPUs which are now slightly
-      # different.
+      # For a while break for the mips32 ISA interpreted a single argument
+      # as a 20-bit code, placing it in the opcode differently to
+      # traditional ISAs.  This turned out to cause problems, so it has
+      # been removed.  This test is to assure consistent interpretation.
       break
       break   0                       # disassembles without code
-      break   0x12345
+      break   0x345
+      break   0x48,0x345              # this still specifies a 20-bit code
+
+      # Instructions in previous ISAs or CPUs which are now slightly
+      # different.
       sdbbp
       sdbbp   0                       # disassembles without code
       sdbbp   0x56789
diff -up --recursive --new-file binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/set-arch.d binutils-2.15.91-20040715/gas/testsuite/gas/mips/set-arch.d
--- binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/set-arch.d	2003-10-01 03:25:36.000000000 +0000
+++ binutils-2.15.91-20040715/gas/testsuite/gas/mips/set-arch.d	2004-07-18 21:41:02.000000000 +0000
@@ -160,207 +160,208 @@ Disassembly of section \.text:
 00000260 <[^>]*> 4359e260 	wait	0x56789
 00000264 <[^>]*> 0000000d 	break
 00000268 <[^>]*> 0000000d 	break
-0000026c <[^>]*> 0048d14d 	break	0x12345
-00000270 <[^>]*> 7000003f 	sdbbp
+0000026c <[^>]*> 0345000d 	break	0x345
+00000270 <[^>]*> 0048d14d 	break	0x48,0x345
 00000274 <[^>]*> 7000003f 	sdbbp
-00000278 <[^>]*> 7159e27f 	sdbbp	0x56789
-0000027c <[^>]*> 000000c0 	sll	zero,zero,0x3
-00000280 <[^>]*> 7ca43980 	0x7ca43980
-00000284 <[^>]*> 7ca46984 	0x7ca46984
-00000288 <[^>]*> 0100fc09 	0x100fc09
-0000028c <[^>]*> 0120a409 	0x120a409
-00000290 <[^>]*> 01000408 	0x1000408
-00000294 <[^>]*> 7c0a003b 	0x7c0a003b
-00000298 <[^>]*> 7c0b083b 	0x7c0b083b
-0000029c <[^>]*> 7c0c103b 	0x7c0c103b
-000002a0 <[^>]*> 7c0d183b 	0x7c0d183b
-000002a4 <[^>]*> 7c0e203b 	0x7c0e203b
-000002a8 <[^>]*> 7c0f283b 	0x7c0f283b
-000002ac <[^>]*> 002acf02 	0x2acf02
-000002b0 <[^>]*> 002ac902 	0x2ac902
-000002b4 <[^>]*> 0004c823 	negu	t9,a0
-000002b8 <[^>]*> 032ac846 	0x32ac846
-000002bc <[^>]*> 008ac846 	0x8ac846
+00000278 <[^>]*> 7000003f 	sdbbp
+0000027c <[^>]*> 7159e27f 	sdbbp	0x56789
+00000280 <[^>]*> 000000c0 	sll	zero,zero,0x3
+00000284 <[^>]*> 7ca43980 	0x7ca43980
+00000288 <[^>]*> 7ca46984 	0x7ca46984
+0000028c <[^>]*> 0100fc09 	0x100fc09
+00000290 <[^>]*> 0120a409 	0x120a409
+00000294 <[^>]*> 01000408 	0x1000408
+00000298 <[^>]*> 7c0a003b 	0x7c0a003b
+0000029c <[^>]*> 7c0b083b 	0x7c0b083b
+000002a0 <[^>]*> 7c0c103b 	0x7c0c103b
+000002a4 <[^>]*> 7c0d183b 	0x7c0d183b
+000002a8 <[^>]*> 7c0e203b 	0x7c0e203b
+000002ac <[^>]*> 7c0f283b 	0x7c0f283b
+000002b0 <[^>]*> 002acf02 	0x2acf02
+000002b4 <[^>]*> 002ac902 	0x2ac902
+000002b8 <[^>]*> 0004c823 	negu	t9,a0
+000002bc <[^>]*> 032ac846 	0x32ac846
 000002c0 <[^>]*> 008ac846 	0x8ac846
-000002c4 <[^>]*> 7c073c20 	0x7c073c20
-000002c8 <[^>]*> 7c0a4420 	0x7c0a4420
-000002cc <[^>]*> 7c073e20 	0x7c073e20
-000002d0 <[^>]*> 7c0a4620 	0x7c0a4620
-000002d4 <[^>]*> 055f5555 	0x55f5555
-000002d8 <[^>]*> 7c0738a0 	0x7c0738a0
-000002dc <[^>]*> 7c0a40a0 	0x7c0a40a0
-000002e0 <[^>]*> 41606000 	0x41606000
+000002c4 <[^>]*> 008ac846 	0x8ac846
+000002c8 <[^>]*> 7c073c20 	0x7c073c20
+000002cc <[^>]*> 7c0a4420 	0x7c0a4420
+000002d0 <[^>]*> 7c073e20 	0x7c073e20
+000002d4 <[^>]*> 7c0a4620 	0x7c0a4620
+000002d8 <[^>]*> 055f5555 	0x55f5555
+000002dc <[^>]*> 7c0738a0 	0x7c0738a0
+000002e0 <[^>]*> 7c0a40a0 	0x7c0a40a0
 000002e4 <[^>]*> 41606000 	0x41606000
-000002e8 <[^>]*> 416a6000 	0x416a6000
-000002ec <[^>]*> 41606020 	0x41606020
+000002e8 <[^>]*> 41606000 	0x41606000
+000002ec <[^>]*> 416a6000 	0x416a6000
 000002f0 <[^>]*> 41606020 	0x41606020
-000002f4 <[^>]*> 416a6020 	0x416a6020
-000002f8 <[^>]*> 41595000 	0x41595000
-000002fc <[^>]*> 41d95000 	0x41d95000
-00000300 <[^>]*> 44710000 	0x44710000
-00000304 <[^>]*> 44f10000 	0x44f10000
-00000308 <[^>]*> 48715555 	0x48715555
-0000030c <[^>]*> 48f15555 	0x48f15555
-00000310 <[^>]*> 70410825 	dclo	at,v0
-00000314 <[^>]*> 70831824 	dclz	v1,a0
-00000318 <[^>]*> 48232000 	dmfc2	v1,\$4
-0000031c <[^>]*> 48242800 	dmfc2	a0,\$5
-00000320 <[^>]*> 48253007 	dmfc2	a1,\$6,7
-00000324 <[^>]*> 48a63800 	dmtc2	a2,\$7
-00000328 <[^>]*> 48a74000 	dmtc2	a3,\$8
-0000032c <[^>]*> 48a84807 	dmtc2	t0,\$9,7
-00000330 <[^>]*> 00850029 	0x850029
-00000334 <[^>]*> 00a60028 	0xa60028
-00000338 <[^>]*> 00002012 	mflo	a0
-0000033c <[^>]*> 00a62029 	0xa62029
-00000340 <[^>]*> 00a62229 	0xa62229
-00000344 <[^>]*> 00a62629 	0xa62629
-00000348 <[^>]*> 00a62269 	0xa62269
-0000034c <[^>]*> 00a62669 	0xa62669
-00000350 <[^>]*> 00a62429 	0xa62429
-00000354 <[^>]*> 00a62069 	0xa62069
-00000358 <[^>]*> 00a62469 	0xa62469
-0000035c <[^>]*> 00002012 	mflo	a0
-00000360 <[^>]*> 00a62028 	0xa62028
-00000364 <[^>]*> 00a62228 	0xa62228
-00000368 <[^>]*> 00a62628 	0xa62628
-0000036c <[^>]*> 00a62268 	0xa62268
-00000370 <[^>]*> 00a62668 	0xa62668
-00000374 <[^>]*> 00a62428 	0xa62428
-00000378 <[^>]*> 00a62068 	0xa62068
-0000037c <[^>]*> 00a62468 	0xa62468
-00000380 <[^>]*> 00a62059 	0xa62059
-00000384 <[^>]*> 00a62258 	0xa62258
-00000388 <[^>]*> 00a62259 	0xa62259
-0000038c <[^>]*> 00a620d8 	0xa620d8
-00000390 <[^>]*> 00a620d9 	0xa620d9
-00000394 <[^>]*> 00a622d8 	0xa622d8
-00000398 <[^>]*> 00a622d9 	0xa622d9
-0000039c <[^>]*> 00a62158 	0xa62158
-000003a0 <[^>]*> 00a62159 	0xa62159
-000003a4 <[^>]*> 00a62358 	0xa62358
-000003a8 <[^>]*> 00a62359 	0xa62359
-000003ac <[^>]*> 00a621d8 	0xa621d8
-000003b0 <[^>]*> 00a621d9 	0xa621d9
-000003b4 <[^>]*> 00a623d8 	0xa623d8
-000003b8 <[^>]*> 00a623d9 	0xa623d9
-000003bc <[^>]*> 00252642 	0x252642
-000003c0 <[^>]*> 00c52046 	0xc52046
-000003c4 <[^>]*> 0025267a 	0x25267a
-000003c8 <[^>]*> 0025267e 	0x25267e
+000002f4 <[^>]*> 41606020 	0x41606020
+000002f8 <[^>]*> 416a6020 	0x416a6020
+000002fc <[^>]*> 41595000 	0x41595000
+00000300 <[^>]*> 41d95000 	0x41d95000
+00000304 <[^>]*> 44710000 	0x44710000
+00000308 <[^>]*> 44f10000 	0x44f10000
+0000030c <[^>]*> 48715555 	0x48715555
+00000310 <[^>]*> 48f15555 	0x48f15555
+00000314 <[^>]*> 70410825 	dclo	at,v0
+00000318 <[^>]*> 70831824 	dclz	v1,a0
+0000031c <[^>]*> 48232000 	dmfc2	v1,\$4
+00000320 <[^>]*> 48242800 	dmfc2	a0,\$5
+00000324 <[^>]*> 48253007 	dmfc2	a1,\$6,7
+00000328 <[^>]*> 48a63800 	dmtc2	a2,\$7
+0000032c <[^>]*> 48a74000 	dmtc2	a3,\$8
+00000330 <[^>]*> 48a84807 	dmtc2	t0,\$9,7
+00000334 <[^>]*> 00850029 	0x850029
+00000338 <[^>]*> 00a60028 	0xa60028
+0000033c <[^>]*> 00002012 	mflo	a0
+00000340 <[^>]*> 00a62029 	0xa62029
+00000344 <[^>]*> 00a62229 	0xa62229
+00000348 <[^>]*> 00a62629 	0xa62629
+0000034c <[^>]*> 00a62269 	0xa62269
+00000350 <[^>]*> 00a62669 	0xa62669
+00000354 <[^>]*> 00a62429 	0xa62429
+00000358 <[^>]*> 00a62069 	0xa62069
+0000035c <[^>]*> 00a62469 	0xa62469
+00000360 <[^>]*> 00002012 	mflo	a0
+00000364 <[^>]*> 00a62028 	0xa62028
+00000368 <[^>]*> 00a62228 	0xa62228
+0000036c <[^>]*> 00a62628 	0xa62628
+00000370 <[^>]*> 00a62268 	0xa62268
+00000374 <[^>]*> 00a62668 	0xa62668
+00000378 <[^>]*> 00a62428 	0xa62428
+0000037c <[^>]*> 00a62068 	0xa62068
+00000380 <[^>]*> 00a62468 	0xa62468
+00000384 <[^>]*> 00a62059 	0xa62059
+00000388 <[^>]*> 00a62258 	0xa62258
+0000038c <[^>]*> 00a62259 	0xa62259
+00000390 <[^>]*> 00a620d8 	0xa620d8
+00000394 <[^>]*> 00a620d9 	0xa620d9
+00000398 <[^>]*> 00a622d8 	0xa622d8
+0000039c <[^>]*> 00a622d9 	0xa622d9
+000003a0 <[^>]*> 00a62158 	0xa62158
+000003a4 <[^>]*> 00a62159 	0xa62159
+000003a8 <[^>]*> 00a62358 	0xa62358
+000003ac <[^>]*> 00a62359 	0xa62359
+000003b0 <[^>]*> 00a621d8 	0xa621d8
+000003b4 <[^>]*> 00a621d9 	0xa621d9
+000003b8 <[^>]*> 00a623d8 	0xa623d8
+000003bc <[^>]*> 00a623d9 	0xa623d9
+000003c0 <[^>]*> 00252642 	0x252642
+000003c4 <[^>]*> 00c52046 	0xc52046
+000003c8 <[^>]*> 0025267a 	0x25267a
 000003cc <[^>]*> 0025267e 	0x25267e
-000003d0 <[^>]*> 00c52056 	0xc52056
-000003d4 <[^>]*> 7000003f 	sdbbp
-000003d8 <[^>]*> 7000003e 	0x7000003e
-000003dc <[^>]*> 7003183d 	0x7003183d
-000003e0 <[^>]*> 7083183d 	0x7083183d
-000003e4 <[^>]*> 4004c803 	mfc0	a0,c0_perfcnt,3
-000003e8 <[^>]*> 4004c802 	mfc0	a0,c0_perfcnt,2
-000003ec <[^>]*> 4084c803 	mtc0	a0,c0_perfcnt,3
-000003f0 <[^>]*> 4084c802 	mtc0	a0,c0_perfcnt,2
-000003f4 <[^>]*> 4ac4100b 	c2	0xc4100b
-000003f8 <[^>]*> 4886208b 	0x4886208b
-000003fc <[^>]*> 4bcf218b 	c2	0x1cf218b
-00000400 <[^>]*> 4bdf310b 	c2	0x1df310b
-00000404 <[^>]*> 4ac4100c 	c2	0xc4100c
-00000408 <[^>]*> 4886208c 	0x4886208c
-0000040c <[^>]*> 4bcf218c 	c2	0x1cf218c
-00000410 <[^>]*> 4bdf310c 	c2	0x1df310c
-00000414 <[^>]*> 4ac20001 	c2	0xc20001
-00000418 <[^>]*> 48862001 	mtc2	a2,\$4,1
-0000041c <[^>]*> 4bcf3001 	c2	0x1cf3001
-00000420 <[^>]*> 4bdf2001 	c2	0x1df2001
-00000424 <[^>]*> 4ac20005 	c2	0xc20005
-00000428 <[^>]*> 48862005 	mtc2	a2,\$4,5
-0000042c <[^>]*> 4bcf3005 	c2	0x1cf3005
-00000430 <[^>]*> 4bdf2005 	c2	0x1df2005
-00000434 <[^>]*> 4ac20004 	c2	0xc20004
-00000438 <[^>]*> 48862004 	mtc2	a2,\$4,4
-0000043c <[^>]*> 4bcf3004 	c2	0x1cf3004
-00000440 <[^>]*> 4bdf2004 	c2	0x1df2004
-00000444 <[^>]*> 4ac41007 	c2	0xc41007
-00000448 <[^>]*> 48862087 	0x48862087
-0000044c <[^>]*> 4bcf2187 	c2	0x1cf2187
-00000450 <[^>]*> 4bdf3107 	c2	0x1df3107
-00000454 <[^>]*> 4ac41006 	c2	0xc41006
-00000458 <[^>]*> 48862086 	0x48862086
-0000045c <[^>]*> 4bcf2186 	c2	0x1cf2186
-00000460 <[^>]*> 4bdf3106 	c2	0x1df3106
-00000464 <[^>]*> 4ac41030 	c2	0xc41030
-00000468 <[^>]*> 488620b0 	0x488620b0
-0000046c <[^>]*> 4bcf21b0 	c2	0x1cf21b0
-00000470 <[^>]*> 4bdf3130 	c2	0x1df3130
-00000474 <[^>]*> 4ac20033 	c2	0xc20033
-00000478 <[^>]*> 48862033 	0x48862033
-0000047c <[^>]*> 4bcf3033 	c2	0x1cf3033
-00000480 <[^>]*> 4bdf2033 	c2	0x1df2033
-00000484 <[^>]*> 4ac20433 	c2	0xc20433
-00000488 <[^>]*> 48862433 	0x48862433
-0000048c <[^>]*> 4bcf3433 	c2	0x1cf3433
-00000490 <[^>]*> 4bdf2433 	c2	0x1df2433
-00000494 <[^>]*> 4ac20032 	c2	0xc20032
-00000498 <[^>]*> 48862032 	0x48862032
-0000049c <[^>]*> 4bcf3032 	c2	0x1cf3032
-000004a0 <[^>]*> 4bdf2032 	c2	0x1df2032
-000004a4 <[^>]*> 4ac20432 	c2	0xc20432
-000004a8 <[^>]*> 48862432 	0x48862432
-000004ac <[^>]*> 4bcf3432 	c2	0x1cf3432
-000004b0 <[^>]*> 4bdf2432 	c2	0x1df2432
-000004b4 <[^>]*> 4ac4100f 	c2	0xc4100f
-000004b8 <[^>]*> 4886208f 	0x4886208f
-000004bc <[^>]*> 4bcf218f 	c2	0x1cf218f
-000004c0 <[^>]*> 4bdf310f 	c2	0x1df310f
-000004c4 <[^>]*> 4ac4100e 	c2	0xc4100e
-000004c8 <[^>]*> 4886208e 	0x4886208e
-000004cc <[^>]*> 4bcf218e 	c2	0x1cf218e
-000004d0 <[^>]*> 4bdf310e 	c2	0x1df310e
-000004d4 <[^>]*> 4ac41002 	c2	0xc41002
-000004d8 <[^>]*> 48862082 	0x48862082
-000004dc <[^>]*> 4bcf2182 	c2	0x1cf2182
-000004e0 <[^>]*> 4bdf3102 	c2	0x1df3102
-000004e4 <[^>]*> 4ac41003 	c2	0xc41003
-000004e8 <[^>]*> 48862083 	0x48862083
-000004ec <[^>]*> 4bcf2183 	c2	0x1cf2183
-000004f0 <[^>]*> 4bdf3103 	c2	0x1df3103
-000004f4 <[^>]*> 4ac4100a 	c2	0xc4100a
-000004f8 <[^>]*> 4886208a 	0x4886208a
-000004fc <[^>]*> 4bcf218a 	c2	0x1cf218a
-00000500 <[^>]*> 4bdf310a 	c2	0x1df310a
-00000504 <[^>]*> 4ac4100d 	c2	0xc4100d
-00000508 <[^>]*> 4886208d 	0x4886208d
-0000050c <[^>]*> 4bcf218d 	c2	0x1cf218d
-00000510 <[^>]*> 4bdf310d 	c2	0x1df310d
-00000514 <[^>]*> 48a41018 	0x48a41018
-00000518 <[^>]*> 4984101f 	0x4984101f
-0000051c <[^>]*> 49c4101f 	0x49c4101f
-00000520 <[^>]*> 4904101f 	0x4904101f
-00000524 <[^>]*> 4944101f 	0x4944101f
-00000528 <[^>]*> 48c62090 	0x48c62090
-0000052c <[^>]*> 4bce3110 	c2	0x1ce3110
-00000530 <[^>]*> 48c62092 	0x48c62092
-00000534 <[^>]*> 4bce3112 	c2	0x1ce3112
-00000538 <[^>]*> 4bcd00a0 	c2	0x1cd00a0
-0000053c <[^>]*> 4a0000bf 	c2	0xbf
-00000540 <[^>]*> 480000bf 	0x480000bf
-00000544 <[^>]*> 490000bf 	bc2f	00000844 <[^>]*>
-00000548 <[^>]*> 4a00103e 	c2	0x103e
-0000054c <[^>]*> 4804103e 	0x4804103e
-00000550 <[^>]*> 00c52046 	0xc52046
-00000554 <[^>]*> 00252442 	0x252442
-00000558 <[^>]*> 00c52056 	0xc52056
-0000055c <[^>]*> 0025207e 	0x25207e
-00000560 <[^>]*> 002520ba 	0x2520ba
-00000564 <[^>]*> 4ca4200f 	prefx	0x4,a0\(a1\)
-00000568 <[^>]*> 42000020 	wait
+000003d0 <[^>]*> 0025267e 	0x25267e
+000003d4 <[^>]*> 00c52056 	0xc52056
+000003d8 <[^>]*> 7000003f 	sdbbp
+000003dc <[^>]*> 7000003e 	0x7000003e
+000003e0 <[^>]*> 7003183d 	0x7003183d
+000003e4 <[^>]*> 7083183d 	0x7083183d
+000003e8 <[^>]*> 4004c803 	mfc0	a0,c0_perfcnt,3
+000003ec <[^>]*> 4004c802 	mfc0	a0,c0_perfcnt,2
+000003f0 <[^>]*> 4084c803 	mtc0	a0,c0_perfcnt,3
+000003f4 <[^>]*> 4084c802 	mtc0	a0,c0_perfcnt,2
+000003f8 <[^>]*> 4ac4100b 	c2	0xc4100b
+000003fc <[^>]*> 4886208b 	0x4886208b
+00000400 <[^>]*> 4bcf218b 	c2	0x1cf218b
+00000404 <[^>]*> 4bdf310b 	c2	0x1df310b
+00000408 <[^>]*> 4ac4100c 	c2	0xc4100c
+0000040c <[^>]*> 4886208c 	0x4886208c
+00000410 <[^>]*> 4bcf218c 	c2	0x1cf218c
+00000414 <[^>]*> 4bdf310c 	c2	0x1df310c
+00000418 <[^>]*> 4ac20001 	c2	0xc20001
+0000041c <[^>]*> 48862001 	mtc2	a2,\$4,1
+00000420 <[^>]*> 4bcf3001 	c2	0x1cf3001
+00000424 <[^>]*> 4bdf2001 	c2	0x1df2001
+00000428 <[^>]*> 4ac20005 	c2	0xc20005
+0000042c <[^>]*> 48862005 	mtc2	a2,\$4,5
+00000430 <[^>]*> 4bcf3005 	c2	0x1cf3005
+00000434 <[^>]*> 4bdf2005 	c2	0x1df2005
+00000438 <[^>]*> 4ac20004 	c2	0xc20004
+0000043c <[^>]*> 48862004 	mtc2	a2,\$4,4
+00000440 <[^>]*> 4bcf3004 	c2	0x1cf3004
+00000444 <[^>]*> 4bdf2004 	c2	0x1df2004
+00000448 <[^>]*> 4ac41007 	c2	0xc41007
+0000044c <[^>]*> 48862087 	0x48862087
+00000450 <[^>]*> 4bcf2187 	c2	0x1cf2187
+00000454 <[^>]*> 4bdf3107 	c2	0x1df3107
+00000458 <[^>]*> 4ac41006 	c2	0xc41006
+0000045c <[^>]*> 48862086 	0x48862086
+00000460 <[^>]*> 4bcf2186 	c2	0x1cf2186
+00000464 <[^>]*> 4bdf3106 	c2	0x1df3106
+00000468 <[^>]*> 4ac41030 	c2	0xc41030
+0000046c <[^>]*> 488620b0 	0x488620b0
+00000470 <[^>]*> 4bcf21b0 	c2	0x1cf21b0
+00000474 <[^>]*> 4bdf3130 	c2	0x1df3130
+00000478 <[^>]*> 4ac20033 	c2	0xc20033
+0000047c <[^>]*> 48862033 	0x48862033
+00000480 <[^>]*> 4bcf3033 	c2	0x1cf3033
+00000484 <[^>]*> 4bdf2033 	c2	0x1df2033
+00000488 <[^>]*> 4ac20433 	c2	0xc20433
+0000048c <[^>]*> 48862433 	0x48862433
+00000490 <[^>]*> 4bcf3433 	c2	0x1cf3433
+00000494 <[^>]*> 4bdf2433 	c2	0x1df2433
+00000498 <[^>]*> 4ac20032 	c2	0xc20032
+0000049c <[^>]*> 48862032 	0x48862032
+000004a0 <[^>]*> 4bcf3032 	c2	0x1cf3032
+000004a4 <[^>]*> 4bdf2032 	c2	0x1df2032
+000004a8 <[^>]*> 4ac20432 	c2	0xc20432
+000004ac <[^>]*> 48862432 	0x48862432
+000004b0 <[^>]*> 4bcf3432 	c2	0x1cf3432
+000004b4 <[^>]*> 4bdf2432 	c2	0x1df2432
+000004b8 <[^>]*> 4ac4100f 	c2	0xc4100f
+000004bc <[^>]*> 4886208f 	0x4886208f
+000004c0 <[^>]*> 4bcf218f 	c2	0x1cf218f
+000004c4 <[^>]*> 4bdf310f 	c2	0x1df310f
+000004c8 <[^>]*> 4ac4100e 	c2	0xc4100e
+000004cc <[^>]*> 4886208e 	0x4886208e
+000004d0 <[^>]*> 4bcf218e 	c2	0x1cf218e
+000004d4 <[^>]*> 4bdf310e 	c2	0x1df310e
+000004d8 <[^>]*> 4ac41002 	c2	0xc41002
+000004dc <[^>]*> 48862082 	0x48862082
+000004e0 <[^>]*> 4bcf2182 	c2	0x1cf2182
+000004e4 <[^>]*> 4bdf3102 	c2	0x1df3102
+000004e8 <[^>]*> 4ac41003 	c2	0xc41003
+000004ec <[^>]*> 48862083 	0x48862083
+000004f0 <[^>]*> 4bcf2183 	c2	0x1cf2183
+000004f4 <[^>]*> 4bdf3103 	c2	0x1df3103
+000004f8 <[^>]*> 4ac4100a 	c2	0xc4100a
+000004fc <[^>]*> 4886208a 	0x4886208a
+00000500 <[^>]*> 4bcf218a 	c2	0x1cf218a
+00000504 <[^>]*> 4bdf310a 	c2	0x1df310a
+00000508 <[^>]*> 4ac4100d 	c2	0xc4100d
+0000050c <[^>]*> 4886208d 	0x4886208d
+00000510 <[^>]*> 4bcf218d 	c2	0x1cf218d
+00000514 <[^>]*> 4bdf310d 	c2	0x1df310d
+00000518 <[^>]*> 48a41018 	0x48a41018
+0000051c <[^>]*> 4984101f 	0x4984101f
+00000520 <[^>]*> 49c4101f 	0x49c4101f
+00000524 <[^>]*> 4904101f 	0x4904101f
+00000528 <[^>]*> 4944101f 	0x4944101f
+0000052c <[^>]*> 48c62090 	0x48c62090
+00000530 <[^>]*> 4bce3110 	c2	0x1ce3110
+00000534 <[^>]*> 48c62092 	0x48c62092
+00000538 <[^>]*> 4bce3112 	c2	0x1ce3112
+0000053c <[^>]*> 4bcd00a0 	c2	0x1cd00a0
+00000540 <[^>]*> 4a0000bf 	c2	0xbf
+00000544 <[^>]*> 480000bf 	0x480000bf
+00000548 <[^>]*> 490000bf 	bc2f	00000848 <[^>]*>
+0000054c <[^>]*> 4a00103e 	c2	0x103e
+00000550 <[^>]*> 4804103e 	0x4804103e
+00000554 <[^>]*> 00c52046 	0xc52046
+00000558 <[^>]*> 00252442 	0x252442
+0000055c <[^>]*> 00c52056 	0xc52056
+00000560 <[^>]*> 0025207e 	0x25207e
+00000564 <[^>]*> 002520ba 	0x2520ba
+00000568 <[^>]*> 4ca4200f 	prefx	0x4,a0\(a1\)
 0000056c <[^>]*> 42000020 	wait
-00000570 <[^>]*> 4359e260 	wait	0x56789
-00000574 <[^>]*> 00000040 	ssnop
-00000578 <[^>]*> 70831821 	clo	v1,a0
-0000057c <[^>]*> 70831825 	dclo	v1,a0
-00000580 <[^>]*> 70831820 	clz	v1,a0
-00000584 <[^>]*> 70831824 	dclz	v1,a0
-00000588 <[^>]*> 4c440005 	luxc1	\$f0,a0\(v0\)
-0000058c <[^>]*> 4c44100d 	suxc1	\$f2,a0\(v0\)
-00000590 <[^>]*> 42000008 	tlbp
-00000594 <[^>]*> 42000001 	tlbr
+00000570 <[^>]*> 42000020 	wait
+00000574 <[^>]*> 4359e260 	wait	0x56789
+00000578 <[^>]*> 00000040 	ssnop
+0000057c <[^>]*> 70831821 	clo	v1,a0
+00000580 <[^>]*> 70831825 	dclo	v1,a0
+00000584 <[^>]*> 70831820 	clz	v1,a0
+00000588 <[^>]*> 70831824 	dclz	v1,a0
+0000058c <[^>]*> 4c440005 	luxc1	\$f0,a0\(v0\)
+00000590 <[^>]*> 4c44100d 	suxc1	\$f2,a0\(v0\)
+00000594 <[^>]*> 42000008 	tlbp
+00000598 <[^>]*> 42000001 	tlbr
 	\.\.\.
diff -up --recursive --new-file binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/set-arch.s binutils-2.15.91-20040715/gas/testsuite/gas/mips/set-arch.s
--- binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/set-arch.s	2003-06-29 19:41:33.000000000 +0000
+++ binutils-2.15.91-20040715/gas/testsuite/gas/mips/set-arch.s	2004-07-18 19:21:55.000000000 +0000
@@ -200,11 +200,17 @@ text_label:	
 	wait    0                       # disassembles without code
 	wait    0x56789
 
-	# Instructions in previous ISAs or CPUs which are now slightly
-	# different.
+	# For a while break for the mips32 ISA interpreted a single argument
+	# as a 20-bit code, placing it in the opcode differently to
+	# traditional ISAs.  This turned out to cause problems, so it has
+	# been removed.  This test is to assure consistent interpretation.
 	break
 	break   0                       # disassembles without code
-	break   0x12345
+	break	0x345
+	break	0x48,0x345		# this still specifies a 20-bit code
+
+	# Instructions in previous ISAs or CPUs which are now slightly
+	# different.
 	sdbbp
 	sdbbp   0                       # disassembles without code
 	sdbbp   0x56789
diff -up --recursive --new-file binutils-2.15.91-20040715.macro/opcodes/mips-opc.c binutils-2.15.91-20040715/opcodes/mips-opc.c
--- binutils-2.15.91-20040715.macro/opcodes/mips-opc.c	2003-11-19 04:25:23.000000000 +0000
+++ binutils-2.15.91-20040715/opcodes/mips-opc.c	2004-06-26 12:42:46.000000000 +0000
@@ -274,7 +274,6 @@ const struct mips_opcode mips_builtin_op
 {"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 		I2|T3	},
 {"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		I2|T3	},
 {"break",   "",		0x0000000d, 0xffffffff,	TRAP,			I1	},
-{"break",   "B",        0x0000000d, 0xfc00003f, TRAP,           	I32     },
 {"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,			I1	},
 {"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,			I1	},
 {"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},

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At Mon, 19 Jul 2004 14:22:29 +0000 (UTC), "Maciej W. Rozycki" wrote:
> (this has led to an address shift enlarging the
> patch significantly, unfortunately).

maybe add nops to pad, instead?


cgd


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From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Richard Sandiford <rsandifo@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>, gcc-patches@gcc.gnu.org,
	linux-mips@linux-mips.org
Subject: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bit targets
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Hello Richard,

 Your change to gcc 3.5:

2004-05-17  Richard Sandiford  <rsandifo@redhat.com>

	* config/mips/mips.h (MASK_DEBUG_G, TARGET_DEBUG_G_MODE): Delete.
	(TARGET_SWITCHES): Remove debugg.
	* config/mips/mips.md (adddi3, ashldi3, ashrdi3, lshrdi3): Only handle
	TARGET_64BIT.
	(subdi3): Replace the define_expand with a define_insn, the latter
	renamed from subdi3_internal_3.
	(negdi2): Likewise negdi2_internal_2.
	(adddi3_internal_[12], subdi3_internal, ashldi3_internal{,2,3})
	(ashrdi3_internal{,2,3}, lshrdi3_internal{,2,3}): Remove patterns
	and associated define_splits.
	(adddi3_internal): Renamed from adddi3_internal_3.
	(ashldi3_internal): Likewise ashldi3_internal4.
	(ashrdi3_internal): Likewise ashrdi3_internal4.
	(lshrdi3_internal): Likewise lshrdi3_internal4.

breaks 32-bit Linux builds.  Linux relies on simple operations
(addition/subtraction and shifts) on "long long" variables being
implemented inline without a call to libgcc, which isn't linked in.  
After your change Linux has unresolved references to external __ashldi3(),
__ashrdi3() and __lshrdi3() functions at the final link.

 Here is a complete revert of the relevant changes that works for me, but
please feel free to provide a replacement.  Either way, please make
ashldi3, ashrdi3 and lshrdi3 available for 32-bit targets again.

2004-07-19  Maciej W. Rozycki  <macro@linux-mips.org>

	* config/mips/mips.md (ashldi3, ashrdi3, lshrdi3): Handle 
	!TARGET_64BIT again, partially reverting the change from 
	2004-05-17.
	(ashldi3_internal{,2,3}, ashrdi3_internal{,2,3}, 
	lshrdi3_internal{,2,3}): Restore patterns and associated 
	define_splits.
	(ashldi3_internal4): Rename from ashldi3_internal.
	(ashrdi3_internal4): Likewise ashrdi3_internal.
	(lshrdi3_internal4): Likewise lshrdi3_internal.

  Maciej

gcc-3.5.0-20040714-mips-xshxdi32.patch
diff -up --recursive --new-file gcc-3.5.0-20040714.macro/gcc/config/mips/mips.md gcc-3.5.0-20040714/gcc/config/mips/mips.md
--- gcc-3.5.0-20040714.macro/gcc/config/mips/mips.md	2004-07-13 04:59:54.000000000 +0000
+++ gcc-3.5.0-20040714/gcc/config/mips/mips.md	2004-07-17 19:00:14.000000000 +0000
@@ -4997,37 +4997,213 @@ dsrl\t%3,%3,1\n\
   { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
 
 (define_expand "ashldi3"
-  [(set (match_operand:DI 0 "register_operand")
-	(ashift:DI (match_operand:DI 1 "register_operand")
-		   (match_operand:SI 2 "arith_operand")))]
-  "TARGET_64BIT"
+  [(parallel [(set (match_operand:DI 0 "register_operand")
+		   (ashift:DI (match_operand:DI 1 "register_operand")
+			      (match_operand:SI 2 "arith_operand")))
+	      (clobber (match_dup  3))])]
+  "TARGET_64BIT || !TARGET_MIPS16"
 {
-  /* On the mips16, a shift of more than 8 is a four byte
-     instruction, so, for a shift between 8 and 16, it is just as
-     fast to do two shifts of 8 or less.  If there is a lot of
-     shifting going on, we may win in CSE.  Otherwise combine will
-     put the shifts back together again.  This can be called by
-     function_arg, so we must be careful not to allocate a new
-     register if we've reached the reload pass.  */
-  if (TARGET_MIPS16
-      && optimize
-      && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 8
-      && INTVAL (operands[2]) <= 16
-      && ! reload_in_progress
-      && ! reload_completed)
+  if (TARGET_64BIT)
     {
-      rtx temp = gen_reg_rtx (DImode);
+      /* On the mips16, a shift of more than 8 is a four byte
+	 instruction, so, for a shift between 8 and 16, it is just as
+	 fast to do two shifts of 8 or less.  If there is a lot of
+	 shifting going on, we may win in CSE.  Otherwise combine will
+	 put the shifts back together again.  This can be called by
+	 function_arg, so we must be careful not to allocate a new
+	 register if we've reached the reload pass.  */
+      if (TARGET_MIPS16
+	  && optimize
+	  && GET_CODE (operands[2]) == CONST_INT
+	  && INTVAL (operands[2]) > 8
+	  && INTVAL (operands[2]) <= 16
+	  && ! reload_in_progress
+	  && ! reload_completed)
+	{
+	  rtx temp = gen_reg_rtx (DImode);
 
-      emit_insn (gen_ashldi3_internal (temp, operands[1], GEN_INT (8)));
-      emit_insn (gen_ashldi3_internal (operands[0], temp,
-				       GEN_INT (INTVAL (operands[2]) - 8)));
+	  emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
+	  emit_insn (gen_ashldi3_internal4 (operands[0], temp,
+					    GEN_INT (INTVAL (operands[2]) - 8)));
+	  DONE;
+	}
+
+      emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
+					operands[2]));
       DONE;
     }
+
+  operands[3] = gen_reg_rtx (SImode);
 })
 
 
 (define_insn "ashldi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=&d")
+	(ashift:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16"
+  "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+sll\t%M0,%L1,%2\;\
+%(b\t3f\;\
+move\t%L0,%.%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+sll\t%M0,%M1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+srl\t%3,%L1,%3\;\
+or\t%M0,%M0,%3\n\
+%~2:\;\
+sll\t%L0,%L1,%2\n\
+%~3:"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"48")])
+
+
+(define_insn "ashldi3_internal2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashift:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 32) != 0"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+  return "sll\t%M0,%L1,%2\;move\t%L0,%.";
+}
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"8")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(ashift:DI (match_operand:DI 1 "register_operand")
+		   (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 0) (const_int 0))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(ashift:DI (match_operand:DI 1 "register_operand")
+		   (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 4) (const_int 0))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_insn "ashldi3_internal3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashift:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+{
+  int amount = INTVAL (operands[2]);
+
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+
+  return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
+}
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"16")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(ashift:DI (match_operand:DI 1 "register_operand")
+		   (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 4)
+	(ashift:SI (subreg:SI (match_dup 1) 4)
+		   (match_dup 2)))
+
+   (set (match_dup 3)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 4)
+	(ior:SI (subreg:SI (match_dup 0) 4)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ashift:SI (subreg:SI (match_dup 1) 0)
+		   (match_dup 2)))]
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+})
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(ashift:DI (match_operand:DI 1 "register_operand")
+		   (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0)
+	(ashift:SI (subreg:SI (match_dup 1) 0)
+		   (match_dup 2)))
+
+   (set (match_dup 3)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 4)
+		     (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ior:SI (subreg:SI (match_dup 0) 0)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 4)
+	(ashift:SI (subreg:SI (match_dup 1) 4)
+		   (match_dup 2)))]
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+})
+
+
+(define_insn "ashldi3_internal4"
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(ashift:DI (match_operand:DI 1 "register_operand" "d")
 		   (match_operand:SI 2 "arith_operand" "dI")))]
@@ -5157,33 +5333,208 @@ dsrl\t%3,%3,1\n\
   { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
 
 (define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "register_operand")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand")
-		     (match_operand:SI 2 "arith_operand")))]
-  "TARGET_64BIT"
+  [(parallel [(set (match_operand:DI 0 "register_operand")
+		   (ashiftrt:DI (match_operand:DI 1 "register_operand")
+				(match_operand:SI 2 "arith_operand")))
+	      (clobber (match_dup  3))])]
+  "TARGET_64BIT || !TARGET_MIPS16"
 {
-  /* On the mips16, a shift of more than 8 is a four byte
-     instruction, so, for a shift between 8 and 16, it is just as
-     fast to do two shifts of 8 or less.  If there is a lot of
-     shifting going on, we may win in CSE.  Otherwise combine will
-     put the shifts back together again.  */
-  if (TARGET_MIPS16
-      && optimize
-      && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 8
-      && INTVAL (operands[2]) <= 16)
+  if (TARGET_64BIT)
     {
-      rtx temp = gen_reg_rtx (DImode);
+      /* On the mips16, a shift of more than 8 is a four byte
+	 instruction, so, for a shift between 8 and 16, it is just as
+	 fast to do two shifts of 8 or less.  If there is a lot of
+	 shifting going on, we may win in CSE.  Otherwise combine will
+	 put the shifts back together again.  */
+      if (TARGET_MIPS16
+	  && optimize
+	  && GET_CODE (operands[2]) == CONST_INT
+	  && INTVAL (operands[2]) > 8
+	  && INTVAL (operands[2]) <= 16)
+	{
+	  rtx temp = gen_reg_rtx (DImode);
+
+	  emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
+	  emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
+					    GEN_INT (INTVAL (operands[2]) - 8)));
+	  DONE;
+	}
 
-      emit_insn (gen_ashrdi3_internal (temp, operands[1], GEN_INT (8)));
-      emit_insn (gen_ashrdi3_internal (operands[0], temp,
-				       GEN_INT (INTVAL (operands[2]) - 8)));
+      emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
+					operands[2]));
       DONE;
     }
+
+  operands[3] = gen_reg_rtx (SImode);
 })
 
 
 (define_insn "ashrdi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=&d")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16"
+  "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+sra\t%L0,%M1,%2\;\
+%(b\t3f\;\
+sra\t%M0,%M1,31%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+srl\t%L0,%L1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+sll\t%3,%M1,%3\;\
+or\t%L0,%L0,%3\n\
+%~2:\;\
+sra\t%M0,%M1,%2\n\
+%~3:"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"48")])
+
+
+(define_insn "ashrdi3_internal2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && (INTVAL (operands[2]) & 32) != 0"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+  return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31";
+}
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"8")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand")
+		     (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand")
+		     (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_insn "ashrdi3_internal3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+{
+  int amount = INTVAL (operands[2]);
+
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+
+  return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2";
+}
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"16")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand")
+		     (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 2)))
+
+   (set (match_dup 3)
+	(ashift:SI (subreg:SI (match_dup 1) 4)
+		   (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ior:SI (subreg:SI (match_dup 0) 0)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 4)
+	(ashiftrt:SI (subreg:SI (match_dup 1) 4)
+		     (match_dup 2)))]
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+})
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand")
+		     (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 4)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 4)
+		     (match_dup 2)))
+
+   (set (match_dup 3)
+	(ashift:SI (subreg:SI (match_dup 1) 0)
+		   (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 4)
+	(ior:SI (subreg:SI (match_dup 0) 4)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ashiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 2)))]
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+})
+
+
+(define_insn "ashrdi3_internal4"
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
 		     (match_operand:SI 2 "arith_operand" "dI")))]
@@ -5332,33 +5683,209 @@ dsrl\t%3,%3,1\n\
    (set_attr "length"	"16")])
 
 (define_expand "lshrdi3"
-  [(set (match_operand:DI 0 "register_operand")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand")
-		     (match_operand:SI 2 "arith_operand")))]
-  "TARGET_64BIT"
+  [(parallel [(set (match_operand:DI 0 "register_operand")
+		   (lshiftrt:DI (match_operand:DI 1 "register_operand")
+				(match_operand:SI 2 "arith_operand")))
+	      (clobber (match_dup  3))])]
+  "TARGET_64BIT || !TARGET_MIPS16"
 {
-  /* On the mips16, a shift of more than 8 is a four byte
-     instruction, so, for a shift between 8 and 16, it is just as
-     fast to do two shifts of 8 or less.  If there is a lot of
-     shifting going on, we may win in CSE.  Otherwise combine will
-     put the shifts back together again.  */
-  if (TARGET_MIPS16
-      && optimize
-      && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 8
-      && INTVAL (operands[2]) <= 16)
+  if (TARGET_64BIT)
     {
-      rtx temp = gen_reg_rtx (DImode);
+      /* On the mips16, a shift of more than 8 is a four byte
+	 instruction, so, for a shift between 8 and 16, it is just as
+	 fast to do two shifts of 8 or less.  If there is a lot of
+	 shifting going on, we may win in CSE.  Otherwise combine will
+	 put the shifts back together again.  */
+      if (TARGET_MIPS16
+	  && optimize
+	  && GET_CODE (operands[2]) == CONST_INT
+	  && INTVAL (operands[2]) > 8
+	  && INTVAL (operands[2]) <= 16)
+	{
+	  rtx temp = gen_reg_rtx (DImode);
 
-      emit_insn (gen_lshrdi3_internal (temp, operands[1], GEN_INT (8)));
-      emit_insn (gen_lshrdi3_internal (operands[0], temp,
-				       GEN_INT (INTVAL (operands[2]) - 8)));
+	  emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
+	  emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
+					    GEN_INT (INTVAL (operands[2]) - 8)));
+	  DONE;
+	}
+
+      emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
+					operands[2]));
       DONE;
     }
+
+  operands[3] = gen_reg_rtx (SImode);
 })
 
 
 (define_insn "lshrdi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=&d")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16"
+  "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+srl\t%L0,%M1,%2\;\
+%(b\t3f\;\
+move\t%M0,%.%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+srl\t%L0,%L1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+sll\t%3,%M1,%3\;\
+or\t%L0,%L0,%3\n\
+%~2:\;\
+srl\t%M0,%M1,%2\n\
+%~3:"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"48")])
+
+
+(define_insn "lshrdi3_internal2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 32) != 0"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+  return "srl\t%L0,%M1,%2\;move\t%M0,%.";
+}
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"8")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand")
+		     (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 4) (const_int 0))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand")
+		     (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 0) (const_int 0))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_insn "lshrdi3_internal3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+{
+  int amount = INTVAL (operands[2]);
+
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+
+  return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2";
+}
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"16")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand")
+		     (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 2)))
+
+   (set (match_dup 3)
+	(ashift:SI (subreg:SI (match_dup 1) 4)
+		   (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ior:SI (subreg:SI (match_dup 0) 0)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 4)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 4)
+		     (match_dup 2)))]
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+})
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand")
+		     (match_operand:SI 2 "small_int")))
+   (clobber (match_operand:SI 3 "register_operand"))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 4)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 4)
+		     (match_dup 2)))
+
+   (set (match_dup 3)
+	(ashift:SI (subreg:SI (match_dup 1) 0)
+		   (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 4)
+	(ior:SI (subreg:SI (match_dup 0) 4)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 2)))]
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
+})
+
+
+(define_insn "lshrdi3_internal4"
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
 		     (match_operand:SI 2 "arith_operand" "dI")))]

From macro@linux-mips.org Mon Jul 19 16:42:49 2004
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Date: Mon, 19 Jul 2004 17:42:42 +0200 (CEST)
From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: cgd@broadcom.com
Cc: binutils@sources.redhat.com, ddaney@avtrex.com,
	linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	Richard Sandiford <rsandifo@redhat.com>
Subject: Re: [Patch]  / 0 should send SIGFPE not SIGTRAP...
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On Mon, 19 Jul 2004 cgd@broadcom.com wrote:

> At Mon, 19 Jul 2004 14:22:29 +0000 (UTC), "Maciej W. Rozycki" wrote:
> > (this has led to an address shift enlarging the
> > patch significantly, unfortunately).
> 
> maybe add nops to pad, instead?

 Well, addresses have been shifted down, so you'd have to remove 
something.  I suppose the break tests could be moved to the end of file, 
but I fail to see an advantage.  Test cases that embed addresses in output 
patterns are doomed to suffer from such changes.

  Maciej

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From: martin.nichols@oxinst.co.uk
To: linux-mips@linux-mips.org
Subject: Link errors
Date: Mon, 19 Jul 2004 16:48:04 +0100
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Hi All,

I'm new to MIPs architecture and Linux so apologies in advance!

I'm trying to build an application to run on the Au1100.
I have a crosscompiler setup (gcc 3.2) and can build a 'hello world' that
runs on the target.
When I try building a more serious application using Kdevelop - with the
appropriate settings
for the crosstools - I get lots of errors like this:
assert.o(.text+0x1cc): relocation truncated to fit: R_MIPS_GOT16
__assert_program_name
/opt/crosstool/mipsel-unknown-linux-gnu/gcc-3.2.3-glibc-2.2.3/mipsel-unknown
-linux-gnu/lib/libc.a(dcigettext.o): In function `_nl_find_msg':
dcigettext.o(.text+0x153c): relocation truncated to fit: R_MIPS_CALL16
_nl_load_domain
/opt/crosstool/mipsel-unknown-linux-gnu/gcc-3.2.3-glibc-2.2.3/mipsel-unknown
-linux-gnu/lib/libc.a(finddomain.o): In function `_nl_find_domain':

Could someone tell me what I'm doing wrong please.

Thanks,

Martin.

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From ddaney@avtrex.com Mon Jul 19 17:47:57 2004
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martin.nichols@oxinst.co.uk wrote:
> Hi All,
> 
> I'm new to MIPs architecture and Linux so apologies in advance!
> 
> I'm trying to build an application to run on the Au1100.
> I have a crosscompiler setup (gcc 3.2) and can build a 'hello world' that
> runs on the target.
> When I try building a more serious application using Kdevelop - with the
> appropriate settings
> for the crosstools - I get lots of errors like this:
> assert.o(.text+0x1cc): relocation truncated to fit: R_MIPS_GOT16
> __assert_program_name
> /opt/crosstool/mipsel-unknown-linux-gnu/gcc-3.2.3-glibc-2.2.3/mipsel-unknown
> -linux-gnu/lib/libc.a(dcigettext.o): In function `_nl_find_msg':
> dcigettext.o(.text+0x153c): relocation truncated to fit: R_MIPS_CALL16
> _nl_load_domain
> /opt/crosstool/mipsel-unknown-linux-gnu/gcc-3.2.3-glibc-2.2.3/mipsel-unknown
> -linux-gnu/lib/libc.a(finddomain.o): In function `_nl_find_domain':
> 
> Could someone tell me what I'm doing wrong please.
> 
This is the got overflow problem.

Later versions of binutils have multi-got support (2.15 for example),
which under most circumstances will fix the problem.

If you have extreamly large compilation units you might have to use a
32bit got index.  In GCC3.4 and later this is done with the -mxgot
option.  With eariler versions of GCC you have to pass -xgot to the
assembler (-Wa,-xgot IIRC).

David Daney.


From rsandifo@redhat.com Mon Jul 19 17:59:15 2004
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Subject: Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bit
 targets
References: <Pine.LNX.4.55.0407191648451.3667@jurand.ds.pg.gda.pl>
From: Richard Sandiford <rsandifo@redhat.com>
Date: Mon, 19 Jul 2004 17:59:11 +0100
In-Reply-To: <Pine.LNX.4.55.0407191648451.3667@jurand.ds.pg.gda.pl> (Maciej
 W. Rozycki's message of "Mon, 19 Jul 2004 17:35:00 +0200 (CEST)")
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"Maciej W. Rozycki" <macro@linux-mips.org> writes:
> Linux relies on simple operations (addition/subtraction and shifts) on
> "long long" variables being implemented inline without a call to
> libgcc, which isn't linked in.

Sorry, but I don't think this is a reasonable expection for 64-bit
shifts on 32-bit targets.  If linux insists on not using libgcc,
it should provide:

> After your change Linux has unresolved references to external __ashldi3(),
> __ashrdi3() and __lshrdi3() functions at the final link.

...these functions itself.

Richard

From dje@watson.ibm.com Mon Jul 19 18:33:16 2004
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Subject: Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bittargets
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Date: Mon, 19 Jul 2004 13:32:51 -0400
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>>>>> Richard Sandiford writes:

> Sorry, but I don't think this is a reasonable expection for 64-bit
> shifts on 32-bit targets.  If linux insists on not using libgcc,
> it should provide:

	Other targets provide those DImode operations.

	Part of the mission of GCC is to support GNU and GNU/Linux.

David

From macro@linux-mips.org Mon Jul 19 18:33:40 2004
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Richard Sandiford <rsandifo@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>, gcc-patches@gcc.gnu.org,
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On Mon, 19 Jul 2004, Richard Sandiford wrote:

> > Linux relies on simple operations (addition/subtraction and shifts) on
> > "long long" variables being implemented inline without a call to
> > libgcc, which isn't linked in.
> 
> Sorry, but I don't think this is a reasonable expection for 64-bit
> shifts on 32-bit targets.  If linux insists on not using libgcc,

 See e.g: "http://www.ussg.iu.edu/hypermail/linux/kernel/0009.2/0655.html"  
for a rationale behind that.

> it should provide:
> 
> > After your change Linux has unresolved references to external __ashldi3(),
> > __ashrdi3() and __lshrdi3() functions at the final link.
> 
> ...these functions itself.

 Well, other targets, like the i386 (which didn't even have a 64-bit
variation till recently), do not force Linux to go through such
contortions.  I can't see a reason why MIPS should be different -- it's
not any harder to implement shifts for this processor than for an average
other platform.  Anyway, the patch works for me and it has been published
so that others can use it, thus I have no incentive to do anything else,
sorry.

  Maciej

From rsandifo@redhat.com Mon Jul 19 18:37:11 2004
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Subject: Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bit
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From: Richard Sandiford <rsandifo@redhat.com>
Date: Mon, 19 Jul 2004 18:37:08 +0100
In-Reply-To: <Pine.LNX.4.55.0407191907300.3667@jurand.ds.pg.gda.pl> (Maciej
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"Maciej W. Rozycki" <macro@linux-mips.org> writes:
>  Well, other targets, like the i386 (which didn't even have a 64-bit
> variation till recently), do not force Linux to go through such
> contortions.

But arm targets (for instance) don't provide inline 64-bit shifts,
do they?  I don't think there's anything special in the MIPS ISA
that makes them easier for MIPS than they are for ARM.

Richard

From havner@pld-linux.org Mon Jul 19 20:00:45 2004
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From: havner <havner@pld-linux.org>
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Subject: DECstation 5000/20
Date: Mon, 19 Jul 2004 21:02:14 +0200
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-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

What's the recommended kernel for this machine?
I've only managed to boot 2.4.17 from debian and 2.4.18
http://www.xs4all.nl/~vhouten/mipsel/vmlinux-2.4.18-decR3k.ecoff.tgz
Unfortunately both of them freezes system (RH7.1/RH7.3) f.e. when trying to 
cat /proc/cpuinfo. No oops, no message on serial, just hard freeze.
using rpm also likes to freeze this machine. I've tried co cross compile 
kernel from cvs at linux-mips.org, but it stop at boot time just after 
setting high precission timer. vanila kernel (2.6.7) ends with kernel panic.
cross tools used:

1. the newest versions from:
ftp://ftp.linux-mips.org/pub/linux/mips/crossdev/i386-linux/mipsel-linux

2. self compiled:
$ mipsel-pld-linux-gcc -v
Reading specs from /usr/lib/gcc-lib/mipsel-pld-linux/3.3.4/specs
Configured with: ../configure --prefix=/usr --infodir=/usr/share/info 
- --mandir=/usr/share/man --bindir=/usr/bin --libdir=/usr/lib 
- --libexecdir=/usr/lib --includedir=/usr/mipsel-pld-linux/include 
- --disable-shared --disable-threads --enable-languages=c --with-gnu-as 
- --with-gnu-ld --with-system-zlib --with-multilib --without-x 
- --build=athlon-pld-linux --host=athlon-pld-linux --target=mipsel-pld-linux
Thread model: single
gcc version 3.3.4
$ mipsel-pld-linux-ld -v 
GNU ld version 2.15.91.0.1 20040527

The same effect on both.
I cannot find any patches for decstation on the net
Are there any more mips kernel repositories over the net?

I've got this machine two days ago and I'm trying to make small PLD port 
there.
I would be gratefull for any help.

- -- 
Regards       Havner                          http://livecd.pld-linux.org
GG: 2846839                             jid,mail: havner(at)pld-linux.org
          "We live as we dream, alone"   - Joseph Conrad
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To: "Maciej W. Rozycki" <macro@linux-mips.org>
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References: <Pine.LNX.4.55.0407191648451.3667@jurand.ds.pg.gda.pl> <87hds49bmo.fsf@redhat.com> <Pine.LNX.4.55.0407191907300.3667@jurand.ds.pg.gda.pl>
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On Mon, Jul 19, 2004 at 07:33:14PM +0200, Maciej W. Rozycki wrote:
>  Well, other targets, like the i386 (which didn't even have a 64-bit
> variation till recently)...

Except that 80386 has 64-bit shifts in hardware.

And in rebuttal to the "does not make linux jump through hoops"
argument, see arch/*/lib/ for arm, h8300, m68k, sparc, v850.



r~

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-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

log from building -r linux_2_4 (linux module from linux-mips.org)
cross development tools as described in my previous post in point 2.

http://ep09.pld-linux.org/~havner/log.gz
http://ep09.pld-linux.org/~havner/.config

- -- 
Regards       Havner                          http://livecd.pld-linux.org
GG: 2846839                             jid,mail: havner(at)pld-linux.org
          "We live as we dream, alone"   - Joseph Conrad
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From ica2_ts@csv.ica.uni-stuttgart.de Tue Jul 20 00:24:53 2004
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Date: Tue, 20 Jul 2004 01:24:49 +0200
To: havner <havner@pld-linux.org>
Cc: linux-mips@linux-mips.org
Subject: Re: DECstation 5000/20
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havner wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> What's the recommended kernel for this machine?
> I've only managed to boot 2.4.17 from debian and 2.4.18
> http://www.xs4all.nl/~vhouten/mipsel/vmlinux-2.4.18-decR3k.ecoff.tgz

This is very old.

> Unfortunately both of them freezes system (RH7.1/RH7.3) f.e. when trying to 
> cat /proc/cpuinfo. No oops, no message on serial, just hard freeze.

Fixed in newer 2.4 kernels from linux-mips.org.

> using rpm also likes to freeze this machine. I've tried co cross compile 
> kernel from cvs at linux-mips.org, but it stop at boot time just after 
> setting high precission timer. vanila kernel (2.6.7) ends with kernel panic.

linux-mips.org CVS, -r linux_2_4, should work for serial console. Debian
has a r3k-kn02 kernel package for mipsel which is supposed to work as
well.


Thiemo

From ica2_ts@csv.ica.uni-stuttgart.de Tue Jul 20 00:29:15 2004
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Maciej W. Rozycki wrote:
[snip]
> opcodes/:
> 2004-07-19  Maciej W. Rozycki  <macro@linux-mips.org>
> 
> 	* mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
> 	ISA-specific "break" encoding.
> 
> gas/testsuite/:
> 2004-07-19  Maciej W. Rozycki  <macro@linux-mips.org>
> 
> 	* gas/mips/mips32.s: Adjust for the unified "break" syntax.  Add 
> 	another "break" case.  Update the comment accordingly.
> 	* gas/mips/set-arch.s: Likewise.
> 	* gas/mips/mips32.d: Adjust for the new output.
> 	* gas/mips/set-arch.d: Likewise.
> 
>  OK to apply?

Ok.


Thiemo

From havner@pld-linux.org Tue Jul 20 01:00:37 2004
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On Tuesday 20 July 2004 01:24, Thiemo Seufer wrote:
> > Unfortunately both of them freezes system (RH7.1/RH7.3) f.e. when trying
> > to cat /proc/cpuinfo. No oops, no message on serial, just hard freeze.
>
> Fixed in newer 2.4 kernels from linux-mips.org.
I've already found, but it doesn't build (my previous post)

> linux-mips.org CVS, -r linux_2_4, should work for serial console. Debian
> has a r3k-kn02 kernel package for mipsel which is supposed to work as
> well.
The only debian image I've managed to find was 2.4.17 and it freezes the same
way like 2.4.18 quoted previously :-(


- -- 
Regards       Havner                          http://livecd.pld-linux.org
GG: 2846839                             jid,mail: havner(at)pld-linux.org
          "We live as we dream, alone"   - Joseph Conrad
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From tbm@cyrius.com Tue Jul 20 01:09:27 2004
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Subject: Re: DECstation 5000/20
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* havner <havner@pld-linux.org> [2004-07-20 02:02]:
> The only debian image I've managed to find was 2.4.17 and it freezes the same
> way like 2.4.18 quoted previously :-(

http://ftp.debian.org/debian/pool/main/k/kernel-patch-2.4.26-mips/kernel-image-2.4.26-r3k-kn02_2.4.26-0.040505.1_mipsel.deb

-- 
Martin Michlmayr
tbm@cyrius.com

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On Tuesday 20 July 2004 02:09, Martin Michlmayr wrote:
> * havner <havner@pld-linux.org> [2004-07-20 02:02]:
> > The only debian image I've managed to find was 2.4.17 and it freezes the
> > same way like 2.4.18 quoted previously :-(
>
> http://ftp.debian.org/debian/pool/main/k/kernel-patch-2.4.26-mips/kernel-im
>age-2.4.26-r3k-kn02_2.4.26-0.040505.1_mipsel.deb

Thank's. I wasn't looking in packages, but around boot images. It seems thay 
have outdated files there.

- -- 
Regards       Havner                          http://livecd.pld-linux.org
GG: 2846839                             jid,mail: havner(at)pld-linux.org
          "We live as we dream, alone"   - Joseph Conrad
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On Tuesday 20 July 2004 02:09, you wrote:
> * havner <havner@pld-linux.org> [2004-07-20 02:02]:
> > The only debian image I've managed to find was 2.4.17 and it freezes the
> > same way like 2.4.18 quoted previously :-(
>
> http://ftp.debian.org/debian/pool/main/k/kernel-patch-2.4.26-mips/kernel-im
>age-2.4.26-r3k-kn02_2.4.26-0.040505.1_mipsel.deb

It almost works properly. I get oopses all the time (mainly with modules 
operations, but not only). Maybe to old modutils and rest of the system. I'll 
check it tommorrow. Thank for help. I must have a look at debian patches too.

- -- 
Regards       Havner                          http://livecd.pld-linux.org
GG: 2846839                             jid,mail: havner(at)pld-linux.org
          "We live as we dream, alone"   - Joseph Conrad
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From: "Alexander Voropay" <a.voropay@vmb-service.ru>
To: "'Ralf Baechle'" <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Subject: RE: Howto run Linux on ACER PICA 61
Date: Tue, 20 Jul 2004 18:15:04 +0400
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Hi!

>Linux has code for this system but it's suffering from severe bitrot.
>I still have the documents here so I could help you a bit if you were
willing to
>resurrect the kernel - which should be relativly easy, also due to the
>system's similarity to another, somewhat better supported system,
>the Olivetti M700-10.

  I'm trying to cross-compile a kernel from the linux-mips CVS.

  Unfortunately, the build script does not provide a selection for the
SCSI driver for the ACER PICA  (/linux/drivers/scsi/NCR53C9x.h ??)
and SONIC DP83932 Ethernet controller.


--
-=AV=-


From martin.nichols@oxinst.co.uk Tue Jul 20 15:45:23 2004
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From: martin.nichols@oxinst.co.uk
To: ddaney@avtrex.com
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Subject: RE: Link errors
Date: Tue, 20 Jul 2004 15:47:58 +0100
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David,

Many thanks.
I should have Googled first ;)

Best regards,

Martin Nichols.

> -----Original Message-----
> From:	David Daney [SMTP:ddaney@avtrex.com]
> Sent:	19 July 2004 17:44
> To:	martin.nichols@oxinst.co.uk
> Cc:	linux-mips@linux-mips.org
> Subject:	Re: Link errors
> 
> martin.nichols@oxinst.co.uk wrote:
> > Hi All,
> > 
> > I'm new to MIPs architecture and Linux so apologies in advance!
> > 
> > I'm trying to build an application to run on the Au1100.
> > I have a crosscompiler setup (gcc 3.2) and can build a 'hello world'
> that
> > runs on the target.
> > When I try building a more serious application using Kdevelop - with the
> > appropriate settings
> > for the crosstools - I get lots of errors like this:
> > assert.o(.text+0x1cc): relocation truncated to fit: R_MIPS_GOT16
> > __assert_program_name
> >
> /opt/crosstool/mipsel-unknown-linux-gnu/gcc-3.2.3-glibc-2.2.3/mipsel-unkno
> wn
> > -linux-gnu/lib/libc.a(dcigettext.o): In function `_nl_find_msg':
> > dcigettext.o(.text+0x153c): relocation truncated to fit: R_MIPS_CALL16
> > _nl_load_domain
> >
> /opt/crosstool/mipsel-unknown-linux-gnu/gcc-3.2.3-glibc-2.2.3/mipsel-unkno
> wn
> > -linux-gnu/lib/libc.a(finddomain.o): In function `_nl_find_domain':
> > 
> > Could someone tell me what I'm doing wrong please.
> > 
> This is the got overflow problem.
> 
> Later versions of binutils have multi-got support (2.15 for example),
> which under most circumstances will fix the problem.
> 
> If you have extreamly large compilation units you might have to use a
> 32bit got index.  In GCC3.4 and later this is done with the -mxgot
> option.  With eariler versions of GCC you have to pass -xgot to the
> assembler (-Wa,-xgot IIRC).
> 
> David Daney.
> 
> 
> +++ Virus-scanned by Messagelabs for Oxford Instruments +++
> 
 ###  OXFORD INSTRUMENTS   http://www.oxford-instruments.com/  ### 

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From deepfire@elvees.com Tue Jul 20 16:01:28 2004
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From: Samium Gromoff <deepfire@elvees.com>
To: maksik@gmx.co.uk
Subject: Re: is there *any* way to boot IP32 from hard drive ?
Date: Tue, 20 Jul 2004 18:01:54 +0400
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> Hi List,
>
> I've asked the very same question here before, but got no answer. Probably, 
> the experts, who might have known the answer just overlooked it... (sorry 
> guys for addressing some of you directly, but I'm really in trouble). The 
> thing is that I desperately need to get the O2 to boot from its HDD, it'sall 
> installed and supposed to be used as a standalone box.

First -- you`re right to use the arcboot image from debian -- that`s how i got
it working.

Second -- not all kernels will run successfully, indeed -- the one i used was
the glaurung 2.6.1 kernel from:

	http://www.linux-mips.org/~glaurung/

This is the only kernel which worked for me so far, and it is not without it`s
share of flaws, namely -- RTC, framebuffer, the AD-based sound chip and mouse
all having issues. Also it hangs (at times) =)

Hope this helps.

regards, Samium Gromoff

From a.voropay@vmb-service.ru Tue Jul 20 16:58:44 2004
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To: "'Ralf Baechle'" <ralf@linux-mips.org>
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Subject: RE: Howto run Linux on ACER PICA 61
Date: Tue, 20 Jul 2004 19:59:52 +0400
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Hi!

>  Unfortunately, the build script does not provide a selection for the
SCSI driver for
>the ACER PICA 

 It seems, this is a typo in Kconfigs... The JAZZ machine name is a
"MACH_JAZZ",
not a  "MIPS_JAZZ"


[root@monitor linux]# find . -name "Kconfig" | xargs grep MIPS_JAZZ
./drivers/net/Kconfig:config MIPS_JAZZ_SONIC
./drivers/net/Kconfig:  depends on NET_ETHERNET && MIPS_JAZZ
./drivers/scsi/Kconfig: depends on MIPS_JAZZ && SCSI
./linux/drivers/net/Kconfig:config MIPS_JAZZ_SONIC
./linux/drivers/net/Kconfig:    depends on NET_ETHERNET && MIPS_JAZZ
./linux/drivers/scsi/Kconfig:   depends on MIPS_JAZZ && SCSI


--
-=AV=-




From wgowcher@yahoo.com Tue Jul 20 17:23:55 2004
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Date: Tue, 20 Jul 2004 09:23:49 -0700 (PDT)
From: Wayne Gowcher <wgowcher@yahoo.com>
Subject: Should pci driver probe behind a cardbus bridge at boot up ?
To: linux-mips@linux-mips.org
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I am having a problem with a Ti cardbus chip and yenta
on the 2.6.4 mips kernel whereby when yenta tries to
configure the cardbus chip, it finds all the resources
busy ( because they have already been allocated in the
pci driver ) and so starts allocating new ones.

Here's the output of the PCI driver

PCI: Bus 1, cardbus bridge: 0000:00:0c.0
  IO window: 00001000-00001fff
  IO window: 00002000-00002fff
  PREFETCH window: 40000000-41ffffff
  MEM window: 42000000-43ffffff
PCI: Bus 5, cardbus bridge: 0000:00:0c.1
  IO window: 00003000-00003fff
  IO window: 00004000-00004fff
  PREFETCH window: 44000000-45ffffff
  MEM window: 46000000-47ffffff

and here's what yenta reports:

Yenta: CardBus bridge found at 0000:00:0c.0
[0000:0000]
yenta 0000:00:0c.0: Preassigned resource 1 busy,
reconfiguring...
Yenta: CardBus bridge found at 0000:00:0c.1
[0000:0000]


When I run the same 2.6.4 kernel compiled for x86 on a
x86 laptop, the x86 kernel finds the bar 0 registers
of the cardbus chip and adds them to it's resource
space, but probes no further. So that later when yenta
probes the cardbus chip, it can allocate the resources
without conflict.

I also found the following comment in
drivers/pci/probe.c pci_scan_bridge :

 * If it's a bridge, configure it and scan the bus
behind it.
 * For CardBus bridges, we don't scan behind as the
devices will
 * be handled by the bridge driver itself.

But the code does scan behind teh cardbus bridge and
add resources to iomem_resources and ioport_resources.

So as I wrote in my title, does anyone know if :

the pci driver should probe behind a cardbus bridge at
boot up or if it should be left to the yenta cardbus ?


	
		
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From wsonguci@yahoo.com Wed Jul 21 01:04:03 2004
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Date: Tue, 20 Jul 2004 17:03:56 -0700 (PDT)
From: Song Wang <wsonguci@yahoo.com>
Subject: Should #ifdef __KERNEL__ be added before #include <spaces.h> in asm-mips/addrspace.h ?
To: Ralf Baechle <ralf@linux-mips.org>
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Hi, Ralf

Should #ifdef _KERNEL__ be added before #include
<spaces.h> in asm-mips/addrspace.h?

I think the reason is the same as when you added
the #ifdef __KERNEL__ before #include <spaces.h>
for asm-mips/page.h.

-Song


	
		
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From taoyong2002cncq@yahoo.com.cn Wed Jul 21 04:04:36 2004
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Reply-To: taoyong2002cncq@yahoo.com.cn
To: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>
Subject: about the uMon
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Hi linux-mips@linux-mips.org,
    
       We use the CSB350 (CPU is A1100) and use the uMon ,too.  There are some questions after our zImage is tftped to the RAM. the reason may be the file format of the zImage.
Would you please tell us your zImage is an ELF file or other file format?


[root@server tftpboot]# file zImage
zImage: ELF 32-bit LSB MIPS-I executable, MIPS, version 1 (SYSV), statically linked, not stripped


uMON>tfs ls
 Name                        Size   Location   Flags  Info
 boot                          52  0xbf953f4c  e      
 hello                       8938  0xbf95632c  e      
 monrc                        322  0xbf953d1c  e      envsetup
 netcfg                       322  0xbf9539dc  e      envsetup
 zImage                    347336  0xbf8fecac  e      
 zImage2                   685692  0xbf9ffd5c  e      

Total: 6 items listed (1042662 bytes).
uMON>tfs run zImage
Command not found: .ELF..
Terminating script 'zImage' at line 1
uMON>
uMON>
uMON>tfs cp zImage 0xa0300000
uMON>dm 0xa0300000
a0300000: 7f 45 4c 46 01 01 01 00   00 00 00 00 00 00 00 00   .ELF............
a0300010: 02 00 08 00 01 00 00 00   00 00 00 81 34 00 00 00   ............4...
a0300020: 90 38 05 00 01 01 00 00   34 00 20 00 03 00 28 00   .8......4. ...(.
a0300030: 0b 00 08 00 00 00 00 70   00 60 00 00 00 60 00 81   .......p.`...`..
a0300040: 00 60 00 81 18 00 00 00   18 00 00 00 04 00 00 00   .`..............
a0300050: 04 00 00 00 01 00 00 00   00 10 00 00 00 00 00 81   ................
a0300060: 00 00 00 81 70 4b 00 00   70 4b 00 00 05 00 00 00   ....pK..pK......
a0300070: 00 10 00 00 01 00 00 00   00 60 00 00 00 60 00 81   .........`...`.. 
       





Best regards,

> Yong Tao 
> Insitute of Manufacture Engineering of Chongqing University,
> Chongqing,
> China 
> 400030
> tel:(+8623)65111224-108
>     (+86)13752931429





From ppopov@mvista.com Wed Jul 21 04:20:55 2004
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Subject: Re: about the uMon
From: Pete Popov <ppopov@mvista.com>
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On Tue, 2004-07-20 at 20:04, taoyong wrote:
> Hi linux-mips@linux-mips.org,
>     
>        We use the CSB350 (CPU is A1100) and use the uMon ,too.  There are some questions after our zImage is tftped to the RAM. the reason may be the file format of the zImage.
> Would you please tell us your zImage is an ELF file or other file format?

The zboot patch in my directory creates two images: an image ready to be
programmed in flash, and an image that can be downloaded to RAM instead.
The first is an srec image that yamon understands (it understands the
flash addresses and programs the file in flash). The latter is a binary
image.

Pete

> 
> [root@server tftpboot]# file zImage
> zImage: ELF 32-bit LSB MIPS-I executable, MIPS, version 1 (SYSV), statically linked, not stripped
> 
> 
> uMON>tfs ls
>  Name                        Size   Location   Flags  Info
>  boot                          52  0xbf953f4c  e      
>  hello                       8938  0xbf95632c  e      
>  monrc                        322  0xbf953d1c  e      envsetup
>  netcfg                       322  0xbf9539dc  e      envsetup
>  zImage                    347336  0xbf8fecac  e      
>  zImage2                   685692  0xbf9ffd5c  e      
> 
> Total: 6 items listed (1042662 bytes).
> uMON>tfs run zImage
> Command not found: .ELF..
> Terminating script 'zImage' at line 1
> uMON>
> uMON>
> uMON>tfs cp zImage 0xa0300000
> uMON>dm 0xa0300000
> a0300000: 7f 45 4c 46 01 01 01 00   00 00 00 00 00 00 00 00   .ELF............
> a0300010: 02 00 08 00 01 00 00 00   00 00 00 81 34 00 00 00   ............4...
> a0300020: 90 38 05 00 01 01 00 00   34 00 20 00 03 00 28 00   .8......4. ...(.
> a0300030: 0b 00 08 00 00 00 00 70   00 60 00 00 00 60 00 81   .......p.`...`..
> a0300040: 00 60 00 81 18 00 00 00   18 00 00 00 04 00 00 00   .`..............
> a0300050: 04 00 00 00 01 00 00 00   00 10 00 00 00 00 00 81   ................
> a0300060: 00 00 00 81 70 4b 00 00   70 4b 00 00 05 00 00 00   ....pK..pK......
> a0300070: 00 10 00 00 01 00 00 00   00 60 00 00 00 60 00 81   .........`...`.. 
>        
> 
> 
> 
> 
> 
> Best regards,
> 
> > Yong Tao 
> > Insitute of Manufacture Engineering of Chongqing University,
> > Chongqing,
> > China 
> > 400030
> > tel:(+8623)65111224-108
> >     (+86)13752931429
> 
> 
> 
> 
> 


From mrv@tusur.ru Wed Jul 21 05:38:33 2004
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From: "Roman Mashak" <mrv@tusur.ru>
To: <linux-mips@linux-mips.org>
Subject: YAMON compiling
Date: Wed, 21 Jul 2004 13:37:52 +0900
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Hello!

After installing  SDE toolkit onto Linux box I tried to compile the
YAMON bootloader source code (version of YAMON is 2.00). Few errors arised:

../arch/include/mips.h: Assembler messages:
../arch/include/mips.h:397: Warning: rest of line ignored; first ignored
character is `/'
../arch/include/mips.h:398: Warning: rest of line ignored; first ignored
character is `/'
../arch/include/mips.h:399: Warning: rest of line ignored; first ignored
character is `/'
../arch/include/pb1000.h:1: Warning: rest of line ignored; first ignored
character is `/'
../arch/include/pb1000.h:3: Warning: rest of line ignored; first ignored
character is `/'
../arch/include/pb1000.h:406: Warning: rest of line ignored; first ignored
character is `/'
./../init/reset/reset.S:98: Warning: rest of line ignored; first ignored
character is `/'
./../init/reset/reset.S:99: Warning: rest of line ignored; first ignored
character is `/'
../arch/init/reset_db1550.S:641: Warning: rest of line ignored; first
ignored character is `/'
../arch/init/reset_db1550.S:739: Error: absolute expression required `li'
../arch/init/reset_db1550.S:783: Error: absolute expression required `li'
../arch/init/reset_db1550.S:821: Error: absolute expression required `li'
make: *** [reset.o] Error1

The lines in mips.h that arise these warnings are the following:

// #define AU1000 0x00030100
//#define AU1000 0x01030200
//#define AU1000_2_1 0x00030200

It seems it doesn't understand the comment syntax.

    I have installed the version 5.03.06-LITE of SDE. Following is the code
extract around which error occures:

#define t1 $9
#define mem_sdconfiga  0x0840
#define MEM_SDCONFIGA_DDR   0x9030060A
#define MEM_SDREFCFG_D_DDR  MEM_SDCONFIGA_DDR

li      t1, MEM_SDREFCFG_D_DDR
sw      t1, mem_sdconfiga(t0)
sync

Compiler thinks  'li t1, MEM_SDREFCFG_D_DDR'  is 'bad expression',  may be
it guesses MEM_SDREFCFG_D_DDR is not defined correctly?

Thank you for every help in advance!

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru

From mrv@tusur.ru Wed Jul 21 06:17:50 2004
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From: "Roman Mashak" <mrv@tusur.ru>
To: <linux-mips@linux-mips.org>
Subject: simple assembler program
Date: Wed, 21 Jul 2004 14:17:14 +0900
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Hello!

    I tried to compile simple assembler program:

#define a 1
#define b 2

.ent main
.global main
main:
        li $3, a
        li $2, b
        addu $4, $2, $3
.end main

I use SDE-lite kit version 5.03.06 and compile with sde-as:
#sde-as test.S -o testtest.S: Assembler messages:
test.S:9: Error: absolute expression required `li'
test.S:10: Error: absolute expression required `li'

When I eliminate #define and use just 'li $3, 1' and so on - everything is
compiled correctly. Where is my problem?

Thanks in advance!

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru


From jbglaw@dvmwest.gt.owl.de Wed Jul 21 07:56:47 2004
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Subject: Re: simple assembler program
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On Wed, 2004-07-21 14:17:14 +0900, Roman Mashak <mrv@tusur.ru>
wrote in message <002701c46ee1$feeb7fc0$cc20bdd3@roman>:

> #define a 1
> #define b 2
>=20
> .ent main
> .global main
> main:
>         li $3, a
>         li $2, b
>         addu $4, $2, $3
> .end main
>=20
> I use SDE-lite kit version 5.03.06 and compile with sde-as:
> #sde-as test.S -o testtest.S: Assembler messages:
> test.S:9: Error: absolute expression required `li'
> test.S:10: Error: absolute expression required `li'
>=20
> When I eliminate #define and use just 'li $3, 1' and so on - everything is
> compiled correctly. Where is my problem?

Assembler sources aren't commonly fed through a preprocessor, so your
assembler just ignores the comments (your defines) and uses "a" and "b"
as-is.

MfG, JBG

--=20
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From chris@mips.com Wed Jul 21 11:53:06 2004
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Subject: Re: YAMON compiling
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--------------090900020700050409020205
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Roman Mashak wrote:
> Hello!
> 
> After installing  SDE toolkit onto Linux box I tried to compile the 
> YAMON bootloader source code (version of YAMON is 2.00). Few errors
> arised:
...
> The lines in mips.h that arise these warnings are the following:
> 
> // #define AU1000 0x00030100
> //#define AU1000 0x01030200
> //#define AU1000_2_1 0x00030200
> 

   The original MIPS assembler used '#' as a comment character.  Using 
an ANSI style C preprocessor where preprocessor directives do not need 
to be at the beginning of the line can can cause problems with files 
using this type of comment.  For this reason sde-gcc tells the 
preprocessor to run in "traditional" mode which disables various ANSI 
features.  In particular, the preprocessor in traditional mode does not 
accept '//' style comments.

> #define t1 $9
> #define mem_sdconfiga  0x0840
> #define MEM_SDCONFIGA_DDR   0x9030060A
> #define MEM_SDREFCFG_D_DDR  MEM_SDCONFIGA_DDR
>
> li      t1, MEM_SDREFCFG_D_DDR
> sw      t1, mem_sdconfiga(t0)
> sync
> 
> Compiler thinks  'li t1, MEM_SDREFCFG_D_DDR'  is 'bad expression',  may be
> it guesses MEM_SDREFCFG_D_DDR is not defined correctly?


   If the '#define' was not at the beginning of the line the 
preprocessor in traditional mode will ignore them and the assembler 
would end up treating these lines as comments which would cause this error.

   I've attached a patch that works on a MIPS release of the YAMON-2.00 
sources to override the preprocessor mode for assembler files. See if it 
helps...

	Chris

-- 
Chris Dearman          The Fruit Farm, Ely Road    voice +44 1223 706206
MIPS Technologies (UK) Chittering, Cambs, CB5 9PH  fax   +44 1223 706250

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--- bin/makefile.orig	Tue Jul 20 19:49:19 2004
+++ bin/makefile	Tue Jul 20 19:49:49 2004
@@ -288,7 +288,7 @@
 # SDE toolchain does not allow a construct like ".bss", it requires
 # .section bss instead.
 ifeq ($(TOOLCHAIN),sde)
-CC_OPTS_A = $(CC_OPTS) -D_ASSEMBLER_ -D_SDE_
+CC_OPTS_A = $(CC_OPTS) -D_ASSEMBLER_ -D_SDE_ -fno-traditional-cpp
 else
 CC_OPTS_A = $(CC_OPTS) -D_ASSEMBLER_
 endif

--------------090900020700050409020205--

From srinivasjt@esntechnologies.co.in Wed Jul 21 13:54:55 2004
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Subject: Error :Nomatch found in TLB ?????
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Dear All,
I am very new to this group.
I tried to load my .serc file into my Db1500 SDB. The steps that I followed are,

1) I wrote a filein C(Linux).
2) I generated an object file using gcc.
3) By using objcopy I converted my obj file into srec file.
4) Then I tried to download my srec file into Db1500 SDB in Yamon using tftp.

then I got error as,

Error: No match in TLB for mapped address  : Address = 0x00000000

Why I am getting this error ?. Is any error there in my procedure..?

Thanks in Advance.

Regards,
Srinivas JT

From macro@linux-mips.org Wed Jul 21 14:44:11 2004
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
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On Wed, 21 Jul 2004, Jan-Benedict Glaw wrote:

> > #sde-as test.S -o testtest.S: Assembler messages:
> > test.S:9: Error: absolute expression required `li'
> > test.S:10: Error: absolute expression required `li'
> > 
> > When I eliminate #define and use just 'li $3, 1' and so on - everything is
> > compiled correctly. Where is my problem?
> 
> Assembler sources aren't commonly fed through a preprocessor, so your
> assembler just ignores the comments (your defines) and uses "a" and "b"
> as-is.

 However, they would be, based on the file name suffix, which is .S for
assembly to be preprocessed or .s for one not to, if fed to the assembler
via the gcc driver.

  Maciej

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Date: Wed, 21 Jul 2004 16:44:06 +0200 (MEST)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Srinivas JT." <srinivasjt@esntechnologies.co.in>
cc: Linux/MIPS Development <linux-mips@linux-mips.org>
Subject: Re: Error :Nomatch found in TLB ?????
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On Wed, 21 Jul 2004, Srinivas JT. wrote:
> I tried to load my .serc file into my Db1500 SDB. The steps that I followed are,
>
> 1) I wrote a filein C(Linux).
> 2) I generated an object file using gcc.

Using the plain `gcc' command, I guess?

> 3) By using objcopy I converted my obj file into srec file.
> 4) Then I tried to download my srec file into Db1500 SDB in Yamon using tftp.
>
> then I got error as,
>
> Error: No match in TLB for mapped address  : Address = 0x00000000
>
> Why I am getting this error ?. Is any error there in my procedure..?

By default gcc creates ELF files for a virtual memory OS. Hence the load
address (0x00000000) is virtual as well.

You have to explicitly tell the linker to create an image to be loaded at a
specific address, cfr. arch/mips/kernel/vmlinux.lds.S.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

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Srinivas JT. wrote:

>Dear All,
>I am very new to this group.
>I tried to load my .serc file into my Db1500 SDB. The steps that I followed are,
>
>1) I wrote a filein C(Linux).
>2) I generated an object file using gcc.
>3) By using objcopy I converted my obj file into srec file.
>4) Then I tried to download my srec file into Db1500 SDB in Yamon using tftp.
>
>then I got error as,
>
>Error: No match in TLB for mapped address  : Address = 0x00000000
>
>Why I am getting this error ?. Is any error there in my procedure..?
>  
>

Link your image to kseg0, not a virtual addresses like 0. The kernel, 
for example, is linked at kseg0 so the srec addresses are at 0x80100000. 
Since not tlbs are required for kseg0, yamon does not have problems 
loading into that region.

Pete

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Date: Wed, 21 Jul 2004 11:57:43 -0700
From: Jun Sun <jsun@mvista.com>
To: Wayne Gowcher <wgowcher@yahoo.com>
Cc: linux-mips@linux-mips.org, jsun@mvista.com
Subject: Re: Should pci driver probe behind a cardbus bridge at boot up ?
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On Tue, Jul 20, 2004 at 09:23:49AM -0700, Wayne Gowcher wrote:
> I am having a problem with a Ti cardbus chip and yenta
> on the 2.6.4 mips kernel whereby when yenta tries to
> configure the cardbus chip, it finds all the resources
> busy ( because they have already been allocated in the
> pci driver ) and so starts allocating new ones.
> 
> Here's the output of the PCI driver
> 
> PCI: Bus 1, cardbus bridge: 0000:00:0c.0
>   IO window: 00001000-00001fff
>   IO window: 00002000-00002fff
>   PREFETCH window: 40000000-41ffffff
>   MEM window: 42000000-43ffffff
> PCI: Bus 5, cardbus bridge: 0000:00:0c.1
>   IO window: 00003000-00003fff
>   IO window: 00004000-00004fff
>   PREFETCH window: 44000000-45ffffff
>   MEM window: 46000000-47ffffff
> 
> and here's what yenta reports:
> 
> Yenta: CardBus bridge found at 0000:00:0c.0
> [0000:0000]
> yenta 0000:00:0c.0: Preassigned resource 1 busy,
> reconfiguring...
> Yenta: CardBus bridge found at 0000:00:0c.1
> [0000:0000]
> 
> 
> When I run the same 2.6.4 kernel compiled for x86 on a
> x86 laptop, the x86 kernel finds the bar 0 registers
> of the cardbus chip and adds them to it's resource
> space, but probes no further. So that later when yenta
> probes the cardbus chip, it can allocate the resources
> without conflict.
> 
> I also found the following comment in
> drivers/pci/probe.c pci_scan_bridge :
> 
>  * If it's a bridge, configure it and scan the bus
> behind it.
>  * For CardBus bridges, we don't scan behind as the
> devices will
>  * be handled by the bridge driver itself.
> 
> But the code does scan behind teh cardbus bridge and
> add resources to iomem_resources and ioport_resources.
> 
> So as I wrote in my title, does anyone know if :
> 
> the pci driver should probe behind a cardbus bridge at
> boot up or if it should be left to the yenta cardbus ?
>

It should not - me think anyway.

Maybe you can tell us _why_, given the same code, i386 does
not scan behind yenta.

Jun

From taoyong2002cncq@yahoo.com.cn Thu Jul 22 02:50:26 2004
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Subject: boot "hell world " and linux on CSB350
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Hi linux-mips,
    
       We have AMD PB1000 and openpda platform and the hardhat linux keranl. csb350 is a new board,and we want to port the hardhat kernal to the csb350. But after we download the "hello world" ,which is comopiled with the mips-elf-gcc,to the ram 0xa0300000,then "call 0xa0300000",we got "Returned: -2147239488 (0x8003b9c0)" . we tftped the kernal image to the RAM 0xa0300000,then call it ,got the same result "Returned: -2147239488 (0x8003b9c0)" or it stopped there.



uMON>tftp 192.168.100.251 get /tftpboot/hello.bin 0xa0300000
Retrieving /tftpboot/hello.bin from 192.168.100.251...TFTP transfer complete.
 1504 bytes
uMON>call 0xa0300000
Returned: -2147239488 (0x8003b9c0)
uMON>dm 0xa0300000
a0300000: 14 a0 1d 3c 00 ff bd 27   11 a0 1c 3c d0 85 9c 27   ...<...'...<...'
a0300010: 04 00 bf af 54 01 04 0c   00 00 00 00 00 00 00 00   ....T...........
a0300020: 04 00 bf 8f 08 00 e0 03   00 00 00 00 00 00 00 00   ................
a0300030: 08 00 e0 03 00 00 00 00   00 00 00 00 00 00 00 00   ................
a0300040: 21 40 00 00 05 00 a0 14   21 48 80 00 30 00 02 24   !@......!H..0..$
a0300050: 00 00 22 a1 08 00 e0 03   01 00 02 24 1b 00 a6 00   .."........$....
a0300060: 12 28 00 00 21 20 28 01   10 10 00 00 01 00 c0 50   .(..! (........P
a0300070: 0d 00 07 00 21 10 e2 00   00 00 43 90 01 00 08 25   ....!.....C....%

uMON>tftp 192.168.100.251 get /tftpboot/vmlinux.bin 0xa0600000
Retrieving /tftpboot/vmlinux.bin from 192.168.100.251...TFTP transfer complete.
 1548288 bytes
uMON>call 0xa0600000
Returned: -2147239488 (0x8003b9c0)

uMON>tftp 192.168.100.251 get /tftpboot/vmlinux.bin 0xa0300000
Retrieving /tftpboot/vmlinux.bin from 192.168.100.251...TFTP transfer complete.
 1548288 bytes
uMON>dm 0xa0300000                                            
a0300000: 00 00 00 00 00 00 00 00   00 00 00 00 00 00 00 00   ................
a0300010: 00 00 00 00 00 00 00 00   00 00 00 00 00 00 00 00   ................
a0300020: 00 00 00 00 00 00 00 00   00 00 00 00 00 00 00 00   ................
a0300030: 00 00 00 00 00 00 00 00   00 00 00 00 00 00 00 00   ................
a0300040: 00 00 00 00 00 00 00 00   00 00 00 00 00 00 00 00   ................
a0300050: 00 00 00 00 00 00 00 00   00 00 00 00 00 00 00 00   ................
a0300060: 00 00 00 00 00 00 00 00   00 00 00 00 00 00 00 00   ................
a0300070: 00 00 00 00 00 00 00 00   00 00 00 00 00 00 00 00   ................
uMON>call 0xa0300000
 
it stopped here and we have to reset the csb350. what's the reason?








Best regards,

> Yong Tao 
> Insitute of Manufacture Engineering of Chongqing University,
> Chongqing,
> China 
> 400030
> tel:(+8623)65111224-108
>     (+86)13752931429





From Ralf.Ackermann@KOM.tu-darmstadt.de Thu Jul 22 16:55:59 2004
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Subject: Q: (cross)compiling for the Meshcube  (fwd)
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Hello,

I'm trying to (cross)compile some more modules/applications for the 
meshcube - but failed so far.

I installed (on an i386 system):
	binutils-mipsel-linux-2.13.2.1-3.i386.rpm
	gcc-mipsel-linux-2.95.4-1.i386.rpm
(from ftp://ftp.linux-mips.org/pub/linux/mips/crossdev/)

Making a hello world program fails with:
	mipsel-linux-gcc hello.c -o hello
	/usr/mipsel-linux/bin/ld: cannot open crt1.o: No such file or directory
	collect2: ld returned 1 exit status

My questions:
 - Are there any specific hints for the cross-compile environment
	(or: "What are you using ... and would therefore suggest ?)
 - Is there any chance to use a native gcc on the cube itself?
	(could this e.g. been done by chrooting into a (which?)
	existing MIPS Linux distribution that is mounted via NFS)

Any hints are highly appreciated (I have worked with crosscompile/native 
environments for ARM so far, but these are my first experiences in the 
MIPS world).

regards
 Ralf
 
---------------------------------------------------------------
Dr. Ralf Ackermann            _         rac@KOM.tu-darmstadt.de
Multimedia Communications |/ | | |\/|           Merckstrasse 25
                          |\ |_| |  |  64283 Darmstadt, Germany
Tel.: (+49) 6151 16-6138                Fax: (+49) 6151 16-6152
---------------------------------------------------------------
             http://www.kom.tu-darmstadt.de/~rac
---------------------------------------------------------------

From ratin@koperasw.com Thu Jul 22 17:15:01 2004
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Subject: RE: (cross)compiling for the Meshcube  (fwd)
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You don't mention installing libc for the platform. You will need libraries
for the MIPS(el) target to be present in the cross-compile path.
Try ftp://ftp.linux-mips.org/pub/linux/mips/glibc/mipsel-linux/

On doing Native build, if your platform supports tftp loading of boot kernel
(or if it has a boot kernel which you can pass parameter to), load the
kernel with nfsroot="IP-Address-of-server:/path" ip=ip-address-of-target

This requires an NFS image to be kept somewhere reachable by your target.
There is a tarball of RH7.1(mipsel) NFS dump at MIPS ftp for which worked
for my MALTA.

I did (sometime) ago produce NFS image of RH7.3 for my MALTA board. I can
upload it if you can tell me a location where to put it.

-----Original Message-----
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Ralf Ackermann
Sent: Thursday, July 22, 2004 8:56 AM
To: linux-mips@linux-mips.org
Cc: Ralf Ackermann
Subject: Q: (cross)compiling for the Meshcube (fwd)


Hello,

I'm trying to (cross)compile some more modules/applications for the 
meshcube - but failed so far.

I installed (on an i386 system):
	binutils-mipsel-linux-2.13.2.1-3.i386.rpm
	gcc-mipsel-linux-2.95.4-1.i386.rpm
(from ftp://ftp.linux-mips.org/pub/linux/mips/crossdev/)

Making a hello world program fails with:
	mipsel-linux-gcc hello.c -o hello
	/usr/mipsel-linux/bin/ld: cannot open crt1.o: No such file or
directory
	collect2: ld returned 1 exit status

My questions:
 - Are there any specific hints for the cross-compile environment
	(or: "What are you using ... and would therefore suggest ?)
 - Is there any chance to use a native gcc on the cube itself?
	(could this e.g. been done by chrooting into a (which?)
	existing MIPS Linux distribution that is mounted via NFS)

Any hints are highly appreciated (I have worked with crosscompile/native 
environments for ARM so far, but these are my first experiences in the 
MIPS world).

regards
 Ralf
 
---------------------------------------------------------------
Dr. Ralf Ackermann            _         rac@KOM.tu-darmstadt.de
Multimedia Communications |/ | | |\/|           Merckstrasse 25
                          |\ |_| |  |  64283 Darmstadt, Germany
Tel.: (+49) 6151 16-6138                Fax: (+49) 6151 16-6152
---------------------------------------------------------------
             http://www.kom.tu-darmstadt.de/~rac
---------------------------------------------------------------






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Ralf Ackermann wrote:
[snip]
>  - Is there any chance to use a native gcc on the cube itself?
> 	(could this e.g. been done by chrooting into a (which?)
> 	existing MIPS Linux distribution that is mounted via NFS)

Native compiles should work. AFAIK the Meshcube uses a customized
debian, most likely a testing/unstable mix. If you have a debian system
around, you can install the "debootstrap" package there and use it to
create a mips chroot, configure it, export it to the Meshcube, and
install the "build-essential" package there. This gives you the usual
native debian development environment.


Thiemo

From wgowcher@yahoo.com Thu Jul 22 17:53:00 2004
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From: Wayne Gowcher <wgowcher@yahoo.com>
Subject: Re: Should pci driver probe behind a cardbus bridge at boot up ?
To: Jun Sun <jsun@mvista.com>
Cc: linux-mips@linux-mips.org, jsun@mvista.com
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> > So as I wrote in my title, does anyone know if :
> > 
> > the pci driver should probe behind a cardbus
> bridge at
> > boot up or if it should be left to the yenta
> cardbus ?
> >
> 
> It should not - me think anyway.
> 
> Maybe you can tell us _why_, given the same code,
> i386 does
> not scan behind yenta.
> 
> Jun

I believe for x86 targets, the PC bios has already
scanned and programmed the memory / io  bar registers
of the PCI devices. So for an x86 target linux merely
reads the bar registers - it does not try to reprogram
them, and so does not go behind the cardbus bridge.

For mips and any other architecture which does not
have a bios to set up the pci bus like this, linux has
to scan and allocate io and memory, but as it is doing
so it is adding those resources to it's resource list.
- Effectively reserving those io / memory regions.
Then when yenta comes along, it also scans the cardbus
and tries to REALLOCATE the same resources, but finds
the pci probed resources, returns the "busy" and so
then tries to reallocate the already allocated
resources to a new memory region. 
Unfortunately in my case ( and I would like to know if
this true for other people's platforms ), when yenta
does this it seems to corrupt the proc/iomem and
proc/ioport list such that if I do "cat /proc/xx" on
either of these the kernel throws an oops. 

Can anyone else do a cat /proc/iomem or ioports with
yenta configured and a cardbus chip on board ?? 
If yes then I have a problem with my setup, if not
then I suspect the code.


		
__________________________________
Do you Yahoo!?
Yahoo! Mail Address AutoComplete - You start. We finish.
http://promotions.yahoo.com/new_mail 

From jack.villarosa@adtxsystems.com Fri Jul 23 02:52:46 2004
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Hi everyone!

Has anyone tried to boot a rbhma4500 board (tx4938 uprocessor) before? I
tried to read the reference board's manuals but couldn't find anything
linux-related. What i have already tried was to:
     1. Write NAND IPL control information (FORMAT: srec) to sram
     2. Write vmlinux.srec to sram
     3. Use NAND Writer to burn the data to NAND Flash.
     4. Changed board settings to boot starting from NAND IPL.
With these steps, neither an error nor success messages appeard. The board
just hung. Im having a hard time looking for sources on the net; thus, this
mail.

Thank you very much!

-=-=-=-=-=-=-=-$B%8%c%C%/(B=-=-=-=-=-=-=-=-
||  John Alexis S. Villarosa            Jack        ||
-  Dev 1                       Microcode          -
||  ADTX Systems, Incorporated, HQ            ||
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-



From kommu@hotmail.com Fri Jul 23 08:49:21 2004
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Can a 32-bit mips kernel access beyond KSEG0 contiguously? I have a Sibyte 
1250 with 1 Gig RAM, but only 256 MB is located at phyical 0x0. The rest is 
all located at 0x8000_0000. Does that mean the kernel can access only 256 
meg contiguously? Do I need to enabled CONFIG_HIGHMEM to even reach the 
remaining RAM? It appears Highmem gives me only a 4 meg window at a time. 
Can't I set up a page mapping into KSEG2 for the rest of the memory? KSEG2 
seems to be unused from what I read.

Since the user space has a 2 Gig address space, it should be able to access 
it, right? Does the kernel allocate from the whole 1 Gig when the process 
issues a malloc()?

thanks!
Srini

_________________________________________________________________
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From bruno.randolf@4g-systems.biz Fri Jul 23 11:43:16 2004
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Subject: Re: Q: (cross)compiling for the Meshcube  (fwd)
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-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

hi!

we use crosstool from http://www.kegel.com/crosstool/ to create a cross 
toolchain. it is also part of our build system, we have at 
http://www.meshcube.org/ in the CVS. if you check it out, you can cd into the 
build/ directory and "make toolchain". the cross prefix is then 
mipsel-mtx-linux-gnu-.

greetings,
bruno



On Thursday 22 July 2004 17:56, Ralf Ackermann wrote:
> Hello,
>
> I'm trying to (cross)compile some more modules/applications for the
> meshcube - but failed so far.
>
> I installed (on an i386 system):
> 	binutils-mipsel-linux-2.13.2.1-3.i386.rpm
> 	gcc-mipsel-linux-2.95.4-1.i386.rpm
> (from ftp://ftp.linux-mips.org/pub/linux/mips/crossdev/)
>
> Making a hello world program fails with:
> 	mipsel-linux-gcc hello.c -o hello
> 	/usr/mipsel-linux/bin/ld: cannot open crt1.o: No such file or directory
> 	collect2: ld returned 1 exit status
>
> My questions:
>  - Are there any specific hints for the cross-compile environment
> 	(or: "What are you using ... and would therefore suggest ?)
>  - Is there any chance to use a native gcc on the cube itself?
> 	(could this e.g. been done by chrooting into a (which?)
> 	existing MIPS Linux distribution that is mounted via NFS)
>
> Any hints are highly appreciated (I have worked with crosscompile/native
> environments for ARM so far, but these are my first experiences in the
> MIPS world).
>
> regards
>  Ralf
>
> ---------------------------------------------------------------
> Dr. Ralf Ackermann            _         rac@KOM.tu-darmstadt.de
> Multimedia Communications |/ | | |\/|           Merckstrasse 25
>
>                           |\ |_| |  |  64283 Darmstadt, Germany
>
> Tel.: (+49) 6151 16-6138                Fax: (+49) 6151 16-6152
> ---------------------------------------------------------------
>              http://www.kom.tu-darmstadt.de/~rac
> ---------------------------------------------------------------
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From macro@linux-mips.org Fri Jul 23 12:51:39 2004
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
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On Fri, 23 Jul 2004, Srinivas Kommu wrote:

> Can a 32-bit mips kernel access beyond KSEG0 contiguously? I have a Sibyte 
> 1250 with 1 Gig RAM, but only 256 MB is located at phyical 0x0. The rest is 
> all located at 0x8000_0000. Does that mean the kernel can access only 256 
> meg contiguously? Do I need to enabled CONFIG_HIGHMEM to even reach the 
> remaining RAM? It appears Highmem gives me only a 4 meg window at a time. 

 The BCM1250A is a 64-bit processor.  What's the problem with using 64-bit
Linux avoiding the hassle altogether?

> Can't I set up a page mapping into KSEG2 for the rest of the memory? KSEG2 
> seems to be unused from what I read.

 KSEG2 is used for modules.

  Maciej

From macro@linux-mips.org Fri Jul 23 15:41:38 2004
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
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On Mon, 19 Jul 2004, Richard Henderson wrote:

> >  Well, other targets, like the i386 (which didn't even have a 64-bit
> > variation till recently)...
> 
> Except that 80386 has 64-bit shifts in hardware.

 Indeed -- I tend to forget of these two, sigh...

> And in rebuttal to the "does not make linux jump through hoops"
> argument, see arch/*/lib/ for arm, h8300, m68k, sparc, v850.

 OK -- but then is there any way to convince gcc to embed a "static
inline" version of these functions instead of emitting a call?  Sometimes
putting these eight (or nine for ashrdi3) instructions inline would be a
performance win.

  Maciej

From macro@linux-mips.org Fri Jul 23 18:29:19 2004
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To: linux-mips@linux-mips.org
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Hello,

 To anyone interested: the "ftp://ftp.ds2.pg.gda.pl/pub/macro/" site is
being retired and will be shut down soon.  The contents have been copied
to another system, located at: "ftp://ftp3.ds.pg.gda.pl/people/macro/".

 My <macro@ds2.pg.gda.pl> address is going to stop working, too.  Please 
use <macro@linux-mips.org> to contact me in the future.

  Maciej

From ralf@linux-mips.org Fri Jul 23 21:25:44 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Srinivas Kommu <kommu@hotmail.com>, linux-mips@linux-mips.org
Subject: Re: mips32 kernel memory mapping
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On Fri, Jul 23, 2004 at 01:51:34PM +0200, Maciej W. Rozycki wrote:

> > Can a 32-bit mips kernel access beyond KSEG0 contiguously? I have a Sibyte 
> > 1250 with 1 Gig RAM, but only 256 MB is located at phyical 0x0. The rest is 
> > all located at 0x8000_0000. Does that mean the kernel can access only 256 
> > meg contiguously? Do I need to enabled CONFIG_HIGHMEM to even reach the 
> > remaining RAM? It appears Highmem gives me only a 4 meg window at a time. 
> 
>  The BCM1250A is a 64-bit processor.  What's the problem with using 64-bit
> Linux avoiding the hassle altogether?

There is a general perception among Linux users that 64-bit is new an
not really needed which in part I blame on the bs Intel is spreading to
hide the fact that for a long time they simply had no 64-bit roadmap at
all.

> > Can't I set up a page mapping into KSEG2 for the rest of the memory? KSEG2 
> > seems to be unused from what I read.
> 
>  KSEG2 is used for modules.

There are still improvments to be made for BCM1250 support.  Somebody
thought scattering the first 1GB of memory through the lowest 4GB of
physical address space like a three year old his toys over the floor
was a good thing ...  The resulting holes in the memory map are wasting
significant amounts of memory for unused memory; the worst case number
that is reached for 64-bit kernel on a system with > 1GB of RAM is 96MB!
                                                                                
> > Can't I set up a page mapping into KSEG2 for the rest of the memory? KSEG2
> > seems to be unused from what I read.
>
>  KSEG2 is used for modules.
                                                                                
Right.  A part of KSEG2 could be used for mapping more low-memory but
that's only really an interesting option for 32-bit processors and would
only raise the theoretical limit from 512MB (256 on BCM1250) to somewhat
less than 1.5GB (BCM1250: 1.25GB) at the cost of address space for
vmalloc & ioremap.  It's a pretty pointless exercise when there are
still terabytes of unmapped 64-bit address space available.
                                                                                
  Ralf

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On Fri, Jul 23, 2004 at 04:41:35PM +0200, Maciej W. Rozycki wrote:
>  OK -- but then is there any way to convince gcc to embed a "static
> inline" version of these functions instead of emitting a call?

No.

> Sometimes putting these eight (or nine for ashrdi3) instructions
> inline would be a performance win.

Sometimes, maybe.  I suspect you'll find that in general it's
nothing but bloat.


r~

From geert@linux-m68k.org Fri Jul 23 21:34:38 2004
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On Fri, 23 Jul 2004, Ralf Baechle wrote:
> There are still improvments to be made for BCM1250 support.  Somebody
> thought scattering the first 1GB of memory through the lowest 4GB of
> physical address space like a three year old his toys over the floor
> was a good thing ...  The resulting holes in the memory map are wasting
> significant amounts of memory for unused memory; the worst case number
> that is reached for 64-bit kernel on a system with > 1GB of RAM is 96MB!

Perhaps you want to start using virtually mapped zones, like m68k?

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

From ralf@linux-mips.org Fri Jul 23 22:12:39 2004
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On Fri, Jul 23, 2004 at 01:27:03PM -0700, Richard Henderson wrote:

> > Sometimes putting these eight (or nine for ashrdi3) instructions
> > inline would be a performance win.
> 
> Sometimes, maybe.  I suspect you'll find that in general it's
> nothing but bloat.

With a bit of hand waiving because haven't done benchmarks I guess Richard
might be right.  The subroutine calling overhead on modern processors is
rather low and smaller code means better cache hit rates ...

  Ralf

From ralf@linux-mips.org Sat Jul 24 01:32:55 2004
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On Fri, Jul 23, 2004 at 10:34:35PM +0200, Geert Uytterhoeven wrote:

> On Fri, 23 Jul 2004, Ralf Baechle wrote:
> > There are still improvments to be made for BCM1250 support.  Somebody
> > thought scattering the first 1GB of memory through the lowest 4GB of
> > physical address space like a three year old his toys over the floor
> > was a good thing ...  The resulting holes in the memory map are wasting
> > significant amounts of memory for unused memory; the worst case number
> > that is reached for 64-bit kernel on a system with > 1GB of RAM is 96MB!
> 
> Perhaps you want to start using virtually mapped zones, like m68k?

We could do that, yes.  In the cases that would gain most such as the
BCM1250 it'd not be possible though - there simply is not enough virtual
address space left in KSEG2/3.

  Ralf

From sskowron@ET.PUT.Poznan.PL Sun Jul 25 19:59:32 2004
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Date: Sun, 25 Jul 2004 20:59:29 +0200 (MET DST)
From: Stanislaw Skowronek <sskowron@ET.PUT.Poznan.PL>
To: linux-mips@linux-mips.org
Subject: Octane news
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Hello all.

After a long delay I can finally announce something important about Octane
Linux. We are a little nearer to having accelerated graphics support on
IP30.

I managed to set the card into 24-bit RGB pixel format.
I can draw accelerated lines.
I can draw arbitrary accelerated Gouraud-shaded (or not) triangles.
I can draw accelerated characters and bitmaps.

I can't read anything from the frame buffer.
I can't effectively draw pixmaps.
I can't change video mode (however, I'm working on it).
I can't take advantage of the GE11 Geometry Engines, so all triangle
setups and transforms are performed in software.

If anyone has *any* information that might be helpful in achieving the
mentioned goals (especially the GE11 support), please help me.

Thanks for your attention,

Stanislaw Skowronek

--<=>--
  "You're not as old as the trees, not as young as the leaves.
   Not as free as the breeze, not as open as the seas."



From thomas.koeller@baslerweb.com Mon Jul 26 11:35:45 2004
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From: Thomas Koeller <thomas.koeller@baslerweb.com>
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To: linux-mips@linux-mips.org
Subject: [PATCH] Fix gcc-3.4.x compilation
Date: Mon, 26 Jul 2004 12:37:09 +0200
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Hi,

compilation of the kernel with a 3.4.x compiler does not
work, because that compiler does no longer recognize
the 'accum' register pair specifier. This can easily be
fixed (patch attached). Since the meaning of 'accum'
used to be 'hi' and 'lo', all its uses were clearly
redundant.


--- linux-mips/arch/mips/kernel/time.c	2004-07-26 12:15:25.302897080 +0200
+++ linux-mips-work/arch/mips/kernel/time.c	2004-07-15 14:52:18.000000000 +0200
@@ -278,7 +278,7 @@
 	__asm__("multu	%1,%2"
 		: "=h" (res)
 		: "r" (count), "r" (sll32_usecs_per_cycle)
-		: "lo", "accum");
+		: "lo");
 
 	/*
 	 * Due to possible jiffies inconsistencies, we need to check
@@ -333,7 +333,7 @@
 	__asm__("multu  %1,%2"
 		: "=h" (res)
 		: "r" (count), "r" (quotient)
-		: "lo", "accum");
+		: "lo");
 
 	/*
 	 * Due to possible jiffies inconsistencies, we need to check
@@ -375,7 +375,7 @@
 				: "r" (timerhi), "m" (timerlo),
 				  "r" (tmp), "r" (USECS_PER_JIFFY),
 				  "r" (USECS_PER_JIFFY_FRAC)
-				: "hi", "lo", "accum");
+				: "hi", "lo");
 			cached_quotient = quotient;
 		}
 	}
@@ -389,7 +389,7 @@
 	__asm__("multu	%1,%2"
 		: "=h" (res)
 		: "r" (count), "r" (quotient)
-		: "lo", "accum");
+		: "lo");
 
 	/*
 	 * Due to possible jiffies inconsistencies, we need to check


-- 
--------------------------------------------------

Thomas Koeller, Software Development
Basler Vision Technologies

thomas dot koeller at baslerweb dot com
http://www.baslerweb.com

==============================

From macro@linux-mips.org Mon Jul 26 12:23:44 2004
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Srinivas Kommu <kommu@hotmail.com>, linux-mips@linux-mips.org
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On Fri, 23 Jul 2004, Ralf Baechle wrote:

> There is a general perception among Linux users that 64-bit is new an
> not really needed which in part I blame on the bs Intel is spreading to
> hide the fact that for a long time they simply had no 64-bit roadmap at
> all.

 Huh?  How's Intel's policy related to 64-bit Linux?  Especially for other
processors, like MIPS.

 Linux has supported 64-bit operation since ~1995 and around 1998 when I
had an opportunity to use it on DEC Alpha, it (2.0.x) was already stable
enough for regular use.  That is the generic core and the Alpha bits, of
course -- the maturity of other processor support may vary, but for MIPS
it's not worse than the 32-bit support.

> There are still improvments to be made for BCM1250 support.  Somebody
> thought scattering the first 1GB of memory through the lowest 4GB of
> physical address space like a three year old his toys over the floor
> was a good thing ...  The resulting holes in the memory map are wasting
> significant amounts of memory for unused memory; the worst case number
> that is reached for 64-bit kernel on a system with > 1GB of RAM is 96MB!

 Well, there are some resons given in the manual.  Anyway, memory seems to
be remappable to 0x100000000 in the DRAM controller.  Still we probably
have to keep low 256MB mapped and registered within Linux at 0 for bounce
buffers for broken PCI hardware ("hidden" mapping for exception handlers 
and kernel segments would be easier).

 With only 256MB installed in my system it would be tough for me to code
anything interesting, though.  Perhaps another time.

  Maciej

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On Fri, 23 Jul 2004, Ralf Baechle wrote:

> With a bit of hand waiving because haven't done benchmarks I guess Richard
> might be right.  The subroutine calling overhead on modern processors is
> rather low and smaller code means better cache hit rates ...

 Well, I just worry the call may itself include at least the same number
of instructions as the callee if inlined.  There would be no way for it to
be faster.

 That may happen for a leaf function -- the call itself, plus $ra
saving/restoration is already four instructions.  Now it's sufficient for
two statics to be needed to preserve temporaries across such a call and
the size of the caller is already the same.  With three statics, you lose
even for a non-leaf function.  That's for a function containing a single
call to such a shift -- if there are more, then you may win (but is it
common?).

 So not only it may not be faster, but the resulting code may be bigger as
well.  That said, the current GCC's implementation of these operations is
not exactly optimal for current MIPS processors.  That's trivial to deal
with in Linux, but would it be possible to pick a different implementation
from libgcc based on the "-march=" setting, too?

  Maciej

From toch@dfpost.ru Mon Jul 26 17:15:57 2004
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Hello!
I have some problem with assembling my program.

Here is a string from source:
*//*/ jal             sdram_memory_test/

in .lst file I got:

/101 00c8 7600000C              jal             sdram_memory_test/

Looking for sdram_memory_test below....

/295 01d8 0000083C              la      ADDR, _etext            /* Start 
addr of test *//

Hm...

Upload test2.bin in 0xbfc00000 on flash. Starting. Debugging....

Everything goes fine but when become time to jump on sdram_memory_test 
it jumps at 0xb00001d8
but I think it must jump to 0xbfc001d8 where real sdram_test is.

Where is the problem?

Dmitriy




From thomas.koeller@baslerweb.com Tue Jul 27 09:56:30 2004
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From: Thomas Koeller <thomas.koeller@baslerweb.com>
Organization: Basler AG
To: linux-mips@linux-mips.org
Subject: ABI question
Date: Tue, 27 Jul 2004 10:57:52 +0200
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Hi,

for 2.6 kernels, arch/mips/Makefile contains the following lines:

ifdef CONFIG_MIPS64
gcc-abi			= 64
gas-abi			= 32
tool-prefix		= $(64bit-tool-prefix)
UTS_MACHINE		:= mips64
endif

Is it intentional that gcc-abi and gas-abi are different? This
results in '-Wa,-32' appearing on gcc's command line, causing
the asembler to complain:

Error: -mgp64 used with a 32-bit ABI

If I change gas-abi to 64, this error goes away.

tk
-- 
--------------------------------------------------

Thomas Koeller, Software Development
Basler Vision Technologies

thomas dot koeller at baslerweb dot com
http://www.baslerweb.com

==============================

From rsandifo@redhat.com Tue Jul 27 10:46:25 2004
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Date: Tue, 27 Jul 2004 10:46:20 +0100
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Thomas Koeller <thomas.koeller@baslerweb.com> writes:
> Since the meaning of 'accum' used to be 'hi' and 'lo', all its uses
> were clearly redundant.

For the record, that isn't quite true.  GCC internally treated
"accum" as an entirely separate register (which is why it became
such a headache).  In theory, if you have an instruction that
clobbers lo and hi, but doesn't clobber "accum", gcc might think
that a value in "accum" will still be valid.

Richard

From macro@linux-mips.org Tue Jul 27 14:05:05 2004
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
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On Tue, 27 Jul 2004, Thomas Koeller wrote:

> for 2.6 kernels, arch/mips/Makefile contains the following lines:
> 
> ifdef CONFIG_MIPS64
> gcc-abi			= 64
> gas-abi			= 32
> tool-prefix		= $(64bit-tool-prefix)
> UTS_MACHINE		:= mips64
> endif
> 
> Is it intentional that gcc-abi and gas-abi are different? This

 It is -- some people want to use 32-bit pointers within Linux, to 
conserve memory.  It seems to work with older tools, but I've never tried 
that.

> results in '-Wa,-32' appearing on gcc's command line, causing
> the asembler to complain:
> 
> Error: -mgp64 used with a 32-bit ABI
> 
> If I change gas-abi to 64, this error goes away.

 You may run `make "gas-abi=64" <whatever>' as a workaround.  I'm going to 
make it selectable in the configuration one day.

  Maciej

From nickiecoor@evanfarmercc.every1.net Wed Jul 28 16:13:30 2004
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^fotoluz~afhøstningen_indicizzati.

eur^`ope'-an m'`e^ds & 0v~^e_rnig~`ht d~~e`,liver




bigamister^  http://www.bestplace4meds.com/track.asp?cg=hot&c=info






-----Original Message-----
From: Beula Fields [mailto:lq@hno.com] 
To: russel wings; conrad henriquez 
Sent: Saturday, September, 2004 6:49 AM
Subject: 2004 health watch

kunu meginjardir brisingi
Should further research be conducted to assess combination versus
monotherapy? Novel  lactams should not be compared with older generation 
lactams or penicillins combined with aminoglycosides  The reason for further
trials assessing the addition of an aminglycoside to a  lactam seems dubious
as well  
How come you're here?'trills from my tonsils. 'We're friends of Bruce and
Sophie Robinson and he invited us.We loved Withnail.If you're interested
I've written a script called LA Story that has a part you might wanna do.if
it happens.Prabably a year from now.Depending.Not the lead role.Wrote that
for myself.'He's doing that ironic dumb act I know from his records and
tapes.Voice and all.
entricar11zarpa10nectarino,mamancona frijo`n.



From hjl@lucon.org Wed Jul 28 17:19:54 2004
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	Ralf Baechle <ralf@linux-mips.org>,
	Linas Vepstas <linas@linas.org>
Subject: The Linux binutils 2.15.91.0.2 is released
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This is the beta release of binutils 2.15.91.0.2 for Linux, which is
based on binutils 2004 0727 in CVS on sources.redhat.com plus various
changes. It is purely for Linux.

Please report any bugs related to binutils 2.15.91.0.2 to hjl@lucon.org

and

http://www.sourceware.org/bugzilla/

If you don't use

# rpmbuild -ta binutils-xx.xx.xx.xx.xx.tar.bz2

to compile the Linux binutils, please read patches/README in source
tree to apply Linux patches if there are any.

Changes from binutils 2.15.91.0.1:

1. Update from binutils 2004 0727.
2. Fix the x86_64 linker to prevent non-PIC code in shared library.
3. Fix the ia64 linker to warn the relotable files which can't be
relaxed.
4. Fix the comdat group support. Allow mix single-member comdat group
with linkonce section.
5. Added --add-needed/--no-add-needed options to linker.
6. Fix the SHF_LINK_ORDER support.
7. Fix the ia64 assembler for multiple sections with the same name and
SHT_IA_64_UNWIND sections.
8. Fix the ia64 assembler for merge section and relaxation.

Changes from binutils 2.15.90.0.3:

1. Update from binutils 2004 0527.
2. Fix -x auto option in the ia64 assembler.
3. Add the AR check in the ia64 assembler.
4. Fix the section group support.
5. Add a new -z relro linker option.
6. Fix an exception section placement bug in linker.
7. Add .serialize.data and .serialize.instruction to the ia64
assembler.

Changes from binutils 2.15.90.0.2:

1. Update from binutils 2004 0415.
2. Fix the linker for weak undefined symbol handling.
3. Fix the ELF/Sparc and ELF/Sparc64 linker for statically linking PIC
code.

Changes from binutils 2.15.90.0.1.1:

1. Update from binutils 2004 0412.
2. Add --as-needed/--no-as-needed to linker.
3. Fix -z defs in linker.
4. Always reserve the memory for ia64 dynamic linker.
5. Fix a race condition in ia64 lazy binding.

Changes from binutils 2.15.90.0.1:

1. Fixed an ia64 assembler bug.
2. Install the assembler man page.

Changes from binutils 2.14.90.0.8:

1. Update from binutils 2004 0303.
2. Fixed linker for undefined symbols with non-default visibility.
3. Sped up linker weakdef symbol handling.
4. Fixed mixing ELF32 and ELF64 object files in archive.
5. Added ia64 linker brl optimization.
6. Fixed ia64 linker to disallow invalid dynamic relocations.
7. Fixed DT_TEXTREL handling in ia64 linker.
8. Fixed alignment handling in ia64 assembler.
9. Improved ia64 assembler unwind table handling. 

Changes from binutils 2.14.90.0.7:

1. Update from binutils 2004 0114.
2. Fixed an ia64 assembler unwind table bug. 
3. Better handle IPF linker relaxation overflow.
4. Fixed misc PPC bugs.

Changes from binutils 2.14.90.0.6:

1. Update from binutils 2003 1029.
2. Allow type changes for undefined symbols.
3. Fix EH frame optimization.
4. Fix the check for undefined versioned symbol with wildcard.
5. Support generating code for Itanium.
6. Detect and warn bad symbol index.
7. Update IPF assemebler DV check.

Changes from binutils 2.14.90.0.5:

1. Update from binutils 2003 0820.
2. No longer use section names for ELF section types nor flags.
3. Fix some ELF/IA64 linker bugs.
4. Fix some ELF/ppc bugs.
5. Add archive support to readelf.

Changes from binutils 2.14.90.0.4.1:

1. Update from binutils 2003 0722.
2. Fix an ELF/mips linker bug.
3. Fix an ELF/hpppa linker bug.
4. Fix an ELF/ia64 assembler bug.
5. Fix a linkonce support with C++ debug.
6. A new working C++ demangler.
7. Various alpha, mips, ia64, ... bug fixes.
8. Support for the current gcc and glibc.

Changes from binutils 2.14.90.0.4:
 
1. Fix an ia64 assembler hint@pause bug.
2. Support Intel Prescott New Instructions.

Changes from binutils 2.14.90.0.3:

1. Work around the brain dead libtool.

Changes from binutils 2.14.90.0.2:

1. Update from binutils 2003 0523.
2. Fix 2 ELF visibility bugs.
3. Fix ELF/ppc linker bugs.

Changes from binutils 2.14.90.0.1:

1. Update from binutils 2003 0515.
2. Fix various ELF visibility bugs.
3. Fix some ia64 linker bugs.
4. Add more IAS compatibilities to ia64 assembler.

Changes from binutils 2.13.90.0.20:

1. Update from binutils 2003 0505.
2. Fix various ELF visibility bugs.
3. Fix some ia64 linker bugs.
4. Fix some ia64 assembler bugs.
5. Add some IAS compatibilities to ia64 assembler.
6. Fix ELF common symbol alignment.
7. Fix ELF weak symbol handling.

Changes from binutils 2.13.90.0.18:

1. Update from binutils 2003 0319.
2. Fix an ia64 linker brl relaxation bug.
3. Fix some ELF/ppc linker bugs.

Changes from binutils 2.13.90.0.16:

1. Update from binutils 2003 0121.
2. Fix an ia64 gas bug.
3. Fix some TLS bugs.
4. Fix some ELF/ppc bugs.
5. Fix an ELF/m68k bug.

2. Include /usr/bin/c++filt.
Changes from binutils 2.13.90.0.14:

1. Update from binutils 2002 1126.
2. Include /usr/bin/c++filt.
3. Fix "ld -r" with execption handling.

Changes from binutils 2.13.90.0.10:

1. Update from binutils 2002 1114.
2. Fix ELF/alpha bugs.
3. Fix an ELF/i386 assembler bug.

Changes from binutils 2.13.90.0.4:

1. Update from binutils 2002 1010.
2. More ELF/PPC linker bug fixes.
3. Fix an ELF/alpha linker bug.
4. Fix an ELF/sparc linker bug to support Solaris.
5. More TLS updates.

Changes from binutils 2.13.90.0.3:

1. Update from binutils 2002 0814.
2. Fix symbol versioning bugs for gcc 3.2.
3. Fix mips gas.

Changes from binutils 2.13.90.0.2:

1. Update from binutils 2002 0809.
2. Fix a mips gas compatibility bug.
3. Fix an x86 TLS bfd bug.
4. Fix an x86 PIC gas bug.
5. Improve symbol versioning support.

The file list:

1. binutils-2.15.91.0.2.tar.bz2. Source code.
2. binutils-2.15.91.0.1-2.15.91.0.2.diff.bz2. Patch against the
   previous beta source code.
3. binutils-2.15.91.0.2-1.i386.rpm. IA-32 binary RPM for RedHat EL 3.
4. binutils-2.15.91.0.2-1.ia64.rpm. IA-64 binary RPM for RedHat EL 3.
5. binutils-2.15.91.0.2-1.x86_64.rpm. X64_64 binary RPM for RedHat EL 3.

There is no separate source rpm. You can do

# rpmbuild -ta binutils-2.15.91.0.2.tar.bz2

to create both binary and source rpms.

The primary sites for the beta Linux binutils are:

1. http://www.kernel.org/pub/linux/devel/binutils/

Thanks.


H.J. Lu
hjl@lucon.org
07/28/2004

From Ralf.Ackermann@KOM.tu-darmstadt.de Wed Jul 28 19:32:56 2004
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Subject: [meshcube-dev] Q: 2.6 kernel anybody? (fwd)
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Hello,

has anybody made experiences in running a 2.6.x kernel on the Meshcube?
Where to look at / start with for that purpose?

(The main reason for my question is the potential support for a MiniPCI 
ATI rage VGA card in 2.6.x - as mentioned on the list before, 2.6.x takes 
care of the initialization that is the BIOS's work on x86 platforms).

best regards
 Ralf

---------------------------------------------------------------
Dr. Ralf Ackermann            _         rac@KOM.tu-darmstadt.de
Multimedia Communications |/ | | |\/|           Merckstrasse 25
                          |\ |_| |  |  64283 Darmstadt, Germany
Tel.: (+49) 6151 16-6138                Fax: (+49) 6151 16-6152
---------------------------------------------------------------
             http://www.kom.tu-darmstadt.de/~rac
---------------------------------------------------------------

_______________________________________________
dev-list mailing list
dev-list@meshcube.org
https://meshcube.org/cgi-bin/mailman/listinfo/dev-list

From greg.roelofs@philips.com Wed Jul 28 20:52:44 2004
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From: greg.roelofs@philips.com
To: <linux-mips@linux-mips.org>
Subject: apparent math-emu hang on movf instruction
Date: Wed, 28 Jul 2004 12:54:04 -0700
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I hope this isn't a FAQ or a complete newbie oversight, but I haven't
found any mention of a similar problem in the FAQs or in the last 18
months' archives of this list.

I have some floating-point code that hangs, apparently on a movf
instruction, with CPU usage pegged at 99%.  It's interruptible, but
that's the best that can be said about it.

The C code in question is a simple comparison of an integer array
element with a floating-point constant (0.0, in fact).  When (cross-)
compiled with either gcc 3.3.4 or 3.3.1 and -O1 (or -O2) and -mtune=r4600
-mips32, it generates the movf instruction.  Compiled either without
optimization or without the r4600/mips32 options, it generates a branch
instead; that version works.  My attempts so far to create a simplified
test case have not succeeded; it seems to be slightly tricky to get GCC
to emit this instruction.  (I'm not an expert in either GCC, the Linux
kernel, or MIPS hardware, btw, so apologies if I'm completely off-track
here.)

The kernel is question is a 2.4.20 derivative (MontaVista Linux 3.1),
and the processor is a Philips PR4450:  MIPS32 core, no floating-point,
some minor extensions and timing differences in a few instructions.
We're using the kernel's FP emulation rather than GCC's soft-float,
and my working assumption at this point is that it's a problem with
the emulation, since movf is described as "move conditional on floating-
point false."

	Q1:  Is that a correct assumption?

I've just started looking at the kernel's emulation code, and one thing
that pops out immediately is that there's no mention of movf anywhere
in arch/mips/math-emu, though cp1emu.c does cover movc, movn, movz, and
plain mov (at least, their .fmt variants).  Nor does the latest(?) CVS
version (http://www.linux-mips.org/cvsweb/linux/arch/mips/math-emu/
cp1emu.c?rev=1.32&content-type=text/x-cvsweb-markup).  On the other hand,
they also don't mention bc1t, "branch on FP true"--which works--so I'm
probably not on the right track here.

	Q2:  Am I?  I would have expected an unemulated instruction to
	     throw an illegal instruction exception or cause an oops or
	     something, not to spin indefinitely.

	Q3:  Any suggestions for what to test/look at/do next?

(Of course, it's also possible that it's a hardware problem of some sort,
although it doesn't feel that way to me.  Then again, I don't trust such
feelings very far...)

Here's the C code that fails:

	if (a[m][n] != 0.0)
	    i++;

Here's its assembler output ($f20 was previously loaded with zero via
"mtc1 $0,$f20", and $16 contains the pointer a[m]):

        l.s     $f2,0($16)      # $f2 = a[m][n]  (32-bit)
        lw      $3,24($sp)      # $3 = i
        cvt.d.w $f0,$f2         # FP: convert int32 ($f2) to double ($f0)
        c.eq.d  $f0,$f20        # FP: conditional:  $f0 == $f20 ?
        addu    $2,$3,1         # add unsigned:  $2 = i + 1
        la      $4,$LC32        # "DEBUG:  checking ..." (later printf)
        movf    $3,$2,$fcc0     # move if FP false (fcc0 = 0):  $3 = $2 = i+1
        sw      $3,24($sp)      # i = $3 (store on stack)
	 ... [printf stuff, etc.]

Thanks for any help/suggestions,
-- 
Greg Roelofs            `Name an animal that's small and fuzzy.' `Mold.'
Philips Semiconductors   greg.roelofs@philips.com


From rsandifo@redhat.com Thu Jul 29 07:54:55 2004
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Subject: Re: apparent math-emu hang on movf instruction
References: <OFFE4A0198.56A3A2A2-ON88256EDF.006D0D9F@philips.com>
From: Richard Sandiford <rsandifo@redhat.com>
Date: Thu, 29 Jul 2004 07:54:50 +0100
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 roelofs's message of "Wed, 28 Jul 2004 12:54:04 -0700")
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greg.roelofs@philips.com writes:
> I've just started looking at the kernel's emulation code, and one thing
> that pops out immediately is that there's no mention of movf anywhere
> in arch/mips/math-emu, though cp1emu.c does cover movc, movn, movz, and
> plain mov (at least, their .fmt variants).

"movc" covers both movf and movt (bit 16 says which).

But yes, it does look like an emulation bug.  It seems that the code
to handle GPR conditional moves (in cop1Emulate) was copied from the
code to handle FPR moves (in fpu_emu).  The cop1Emulate() code reads:

		if (((ctx->fcr31 & cond) != 0) != ((MIPSInst_RT(ir) & 1) != 0))
			return 0;
		xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)];

"return 0" was fine in fpu_emu(), but not here, since it skips the
all-important:

	/* we did it !! */
	xcp->cp0_epc = VA_TO_REG(contpc);
	xcp->cp0_cause &= ~CAUSEF_BD;
	return 0;

So we'd reenter the exception handler on exit.

Does the patch below (against 2.6) fix things?  Only the first hunk
is needed to fix the bug, the rest is just there for consistency.

Richard


Index: arch/mips/math-emu/cp1emu.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/math-emu/cp1emu.c,v
retrieving revision 1.32
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.32 cp1emu.c
--- arch/mips/math-emu/cp1emu.c	19 Jan 2004 16:25:21 -0000	1.32
+++ arch/mips/math-emu/cp1emu.c	29 Jul 2004 06:42:53 -0000
@@ -528,9 +528,8 @@ static int cop1Emulate(struct pt_regs *x
 		if (MIPSInst_FUNC(ir) != movc_op)
 			return SIGILL;
 		cond = fpucondbit[MIPSInst_RT(ir) >> 2];
-		if (((ctx->fcr31 & cond) != 0) != ((MIPSInst_RT(ir) & 1) != 0))
-			return 0;
-		xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)];
+		if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
+			xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)];
 		break;
 #endif
 
@@ -850,20 +849,17 @@ static int fpu_emu(struct pt_regs *xcp, 
 #if __mips >= 4
 		case fmovc_op:
 			cond = fpucondbit[MIPSInst_FT(ir) >> 2];
-			if (((ctx->fcr31 & cond) != 0) !=
+			if (((ctx->fcr31 & cond) != 0) ==
 				((MIPSInst_FT(ir) & 1) != 0))
-				return 0;
-			SPFROMREG(rv.s, MIPSInst_FS(ir));
+				SPFROMREG(rv.s, MIPSInst_FS(ir));
 			break;
 		case fmovz_op:
-			if (xcp->regs[MIPSInst_FT(ir)] != 0)
-				return 0;
-			SPFROMREG(rv.s, MIPSInst_FS(ir));
+			if (xcp->regs[MIPSInst_FT(ir)] == 0)
+				SPFROMREG(rv.s, MIPSInst_FS(ir));
 			break;
 		case fmovn_op:
-			if (xcp->regs[MIPSInst_FT(ir)] == 0)
-				return 0;
-			SPFROMREG(rv.s, MIPSInst_FS(ir));
+			if (xcp->regs[MIPSInst_FT(ir)] != 0)
+				SPFROMREG(rv.s, MIPSInst_FS(ir));
 			break;
 #endif
 		case fabs_op:
@@ -1040,20 +1036,17 @@ static int fpu_emu(struct pt_regs *xcp, 
 #if __mips >= 4
 		case fmovc_op:
 			cond = fpucondbit[MIPSInst_FT(ir) >> 2];
-			if (((ctx->fcr31 & cond) != 0) !=
+			if (((ctx->fcr31 & cond) != 0) ==
 				((MIPSInst_FT(ir) & 1) != 0))
-				return 0;
-			DPFROMREG(rv.d, MIPSInst_FS(ir));
+				DPFROMREG(rv.d, MIPSInst_FS(ir));
 			break;
 		case fmovz_op:
-			if (xcp->regs[MIPSInst_FT(ir)] != 0)
-				return 0;
-			DPFROMREG(rv.d, MIPSInst_FS(ir));
+			if (xcp->regs[MIPSInst_FT(ir)] == 0)
+				DPFROMREG(rv.d, MIPSInst_FS(ir));
 			break;
 		case fmovn_op:
-			if (xcp->regs[MIPSInst_FT(ir)] == 0)
-				return 0;
-			DPFROMREG(rv.d, MIPSInst_FS(ir));
+			if (xcp->regs[MIPSInst_FT(ir)] != 0)
+				DPFROMREG(rv.d, MIPSInst_FS(ir));
 			break;
 #endif
 		case fabs_op:

From rsandifo@redhat.com Thu Jul 29 08:01:27 2004
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To: greg.roelofs@philips.com
Cc: <linux-mips@linux-mips.org>
Subject: Re: apparent math-emu hang on movf instruction
References: <OFFE4A0198.56A3A2A2-ON88256EDF.006D0D9F@philips.com>
	<876587uwud.fsf@redhat.com>
From: Richard Sandiford <rsandifo@redhat.com>
Date: Thu, 29 Jul 2004 08:01:24 +0100
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 "Thu, 29 Jul 2004 07:54:50 +0100")
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Richard Sandiford <rsandifo@redhat.com> writes:
> Does the patch below (against 2.6) fix things?  Only the first hunk
> is needed to fix the bug, the rest is just there for consistency.

Oops!  Serves me right for dabbling in new code.  Only the first
hunk is correct.

Richard


Index: arch/mips/math-emu/cp1emu.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/math-emu/cp1emu.c,v
retrieving revision 1.32
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.32 cp1emu.c
--- arch/mips/math-emu/cp1emu.c	19 Jan 2004 16:25:21 -0000	1.32
+++ arch/mips/math-emu/cp1emu.c	29 Jul 2004 06:42:53 -0000
@@ -528,9 +528,8 @@ static int cop1Emulate(struct pt_regs *x
 		if (MIPSInst_FUNC(ir) != movc_op)
 			return SIGILL;
 		cond = fpucondbit[MIPSInst_RT(ir) >> 2];
-		if (((ctx->fcr31 & cond) != 0) != ((MIPSInst_RT(ir) & 1) != 0))
-			return 0;
-		xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)];
+		if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
+			xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)];
 		break;
 #endif
 

From yuasa@hh.iij4u.or.jp Thu Jul 29 17:01:19 2004
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Date: Fri, 30 Jul 2004 01:01:12 +0900
From: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: yuasa@hh.iij4u.or.jp, linux-mips <linux-mips@linux-mips.org>
Subject: [PATCH] vr41xx: remove obsolete flag
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Hi Ralf,

This patch removes an obsolete flag in serial driver. 

Please apply this patch to v2.6 CVS tree.

Yoichi

diff -urN -X dontdiff linux-orig/arch/mips/vr41xx/common/serial.c linux/arch/mips/vr41xx/common/serial.c
--- linux-orig/arch/mips/vr41xx/common/serial.c	Thu Jul 22 00:29:06 2004
+++ linux/arch/mips/vr41xx/common/serial.c	Thu Jul 29 00:49:32 2004
@@ -160,7 +160,7 @@
 	port.line = vr41xx_serial_ports;
 	port.uartclk = DSIU_BASE_BAUD * 16;
 	port.irq = DSIU_IRQ;
-	port.flags = UPF_RESOURCES | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
+	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.mapbase = DSIU_BASE;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;

From greg.roelofs@philips.com Thu Jul 29 22:52:25 2004
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From: greg.roelofs@philips.com
To: <rsandifo@redhat.com>
Subject: Re: apparent math-emu hang on movf instruction
Cc: <linux-mips@linux-mips.org>
Date: Thu, 29 Jul 2004 14:53:46 -0700
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Richard Sandiford <rsandifo@redhat.com> wrote...

>> Does the patch below (against 2.6) fix things?  Only the first hunk
>> is needed to fix the bug, the rest is just there for consistency.

> Oops!  Serves me right for dabbling in new code.  Only the first
> hunk is correct.

Yup, that does it!  Many thanks.  The only thing I had to change for
2.4.x was the name of the "fcr31" soft-struct member; it's "sr" in
older kernels:

> +		if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
		           ^^^^^ sr
> +			xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)];

(Ralf renamed things on 20030720, according to the cvsweb.)

Thanks again,
-- 
Greg Roelofs            `Name an animal that's small and fuzzy.' `Mold.'
Philips Semiconductors   greg.roelofs@philips.com


From xuhaoz@neonetech.com Fri Jul 30 09:09:25 2004
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From macro@linux-mips.org Fri Jul 30 10:48:35 2004
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Richard Sandiford <rsandifo@redhat.com>
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Subject: Re: apparent math-emu hang on movf instruction
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On Thu, 29 Jul 2004, Richard Sandiford wrote:

> Oops!  Serves me right for dabbling in new code.  Only the first
> hunk is correct.

 Thanks Richard for working on this.  I've verified your patch on my
system and as it is obviously correct, I've applied it with a trivial
formatting change to our CVS, both to the head and to the 2.4 branch; with
appropriate literal name changes for the latter.

  Maciej

From xuhaoz@neonetech.com Fri Jul 30 11:11:18 2004
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From giles67@yahoo.com Fri Jul 30 22:08:46 2004
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From: G H <giles67@yahoo.com>
Subject: Re: Strange, strange occurence
To: linux-mips@linux-mips.org
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Is the suggested patch below going to be added to CVS or is considered too experimental to add ?
 
>No and yes - but here is a simpler solution.  Below patch solves the
>problem and adds just 32 bytes of code but removes the special case for
>TX49/H2 entirely.

>  Ralf

> arch/mips/mm/c-r4k.c        |   59 
>-------------------------------------------- include/asm-mips/r4kcache.h |   18 
>++++++++-----
> include/asm-mips/war.h      |   14 ----------
> 3 files changed, 13 insertions(+), 78 deletions(-)
>
>
>Index: arch/mips/mm/c-r4k.c
>===================================================================
>RCS file: /home/cvs/linux/arch/mips/mm/c-r4k.c,v
>retrieving revision 1.88
>diff -u -r1.88 c-r4k.c
>--- arch/mips/mm/c-r4k.c        16 Jul 2004 12:06:13 -0000      1.88
>+++ arch/mips/mm/c-r4k.c        16 Jul 2004 12:17:05 -0000
>@@ -96,16 +96,6 @@
>                r4k_blast_dcache = blast_dcache32;
> }


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<DIV>Is the suggested patch below going to be added to CVS or is considered too experimental to add ?</DIV>
<DIV>&nbsp;</DIV>
<DIV>&gt;No and yes - but here is a simpler solution.&nbsp; Below patch solves the<BR>&gt;problem and adds just 32 bytes of code but removes the special case for<BR>&gt;TX49/H2 entirely.<BR><BR>&gt;&nbsp; Ralf<BR><BR>&gt; arch/mips/mm/c-r4k.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp; 59 <BR>&gt;-------------------------------------------- include/asm-mips/r4kcache.h |&nbsp;&nbsp; 18 <BR>&gt;++++++++-----<BR>&gt; include/asm-mips/war.h&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp; 14 ----------<BR>&gt; 3 files changed, 13 insertions(+), 78 deletions(-)<BR>&gt;<BR>&gt;<BR>&gt;Index: arch/mips/mm/c-r4k.c<BR>&gt;===================================================================<BR>&gt;RCS file: /home/cvs/linux/arch/mips/mm/c-r4k.c,v<BR>&gt;retrieving revision 1.88<BR>&gt;diff -u -r1.88 c-r4k.c<BR>&gt;--- arch/mips/mm/c-r4k.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 16 Jul 2004 12:06:13 -0000&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1.88<BR>&gt;+++
 arch/mips/mm/c-r4k.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 16 Jul 2004 12:17:05 -0000<BR>&gt;@@ -96,16 +96,6 @@<BR>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; r4k_blast_dcache = blast_dcache32;<BR>&gt; }<BR></DIV><p>__________________________________________________<br>Do You Yahoo!?<br>Tired of spam?  Yahoo! Mail has the best spam protection around <br>http://mail.yahoo.com 
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From ralf@linux-mips.org Sat Jul 31 06:09:04 2004
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From: Ralf Baechle <ralf@linux-mips.org>
To: G H <giles67@yahoo.com>
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Subject: Re: Strange, strange occurence
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On Fri, Jul 30, 2004 at 02:06:39PM -0700, G H wrote:

> Is the suggested patch below going to be added to CVS or is considered too experimental to add ?

No, that patch is simply wrong.

I'll implement a new one but being on a trip through the Silicon Valley
right now that's a little hard to do from here.

  Ralf

From ralf@linux-mips.org Sat Jul 31 10:25:20 2004
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Date: Sat, 31 Jul 2004 11:25:05 +0200
From: Ralf Baechle <ralf@linux-mips.org>
To: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
Cc: linux-mips <linux-mips@linux-mips.org>
Subject: Re: [PATCH] vr41xx: remove obsolete flag
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On Fri, Jul 30, 2004 at 01:01:12AM +0900, Yoichi Yuasa wrote:

> This patch removes an obsolete flag in serial driver. 
> 
> Please apply this patch to v2.6 CVS tree.

Applied,

  Ralf

From xuhaoz@neonetech.com Sat Jul 31 14:39:31 2004
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hello:
can uclinux run on the mipsR3000 ?, 
_________________________________________
zhang xuhao
ICQ#: 116926669
More ways to contact me: http://wwp.icq.com/116926669
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