Subject: port on exotic board.

From: moreau francis <[email-masked]>
Date: Tue, 21 Dec 2004 09:53:07 +0100 (CET)

Hi,

Well, I'm still trying to port Linux on my "exotic"
board...
I hope you don't mind if I ask a couple of questions,
which may be stupid for you but usefull at my level. 
If you think that linux-mips mailing list is not 
intended for these kind of questions, tell me !

So here I am:

I've mapped kernel code and kernel data in different
memories in order to save precious SDRAM memory.

Code    0xC0000000    0x30000000     16Mo    FLASH
Data    0xC1000000    0x20000000      8Mo    SDRAM

When running the kernel at the very begining, I
encounter different issues:

In "tlb_init" function, cp0 WIRED register is set to
zero, therefore the call to "local_flush_tlb_all" 
flush all TLB entries which were mapping my kernel
in the 3 first entries. Why is this necessary ?  

In different part of the kernel it is assumed that the
kernel start at physical addr 0. For instance in
"init_bootmem" fonction, argument start is set to 0.
Or the way to calculate a page frame index in mem_map
array. Why this assumption ?

Why does "mem_map" need to store page frames for
kernel
code ? Are these pages going be used when the Linux is
running ?

I noticed CPHYSADDR macro. This macro only works if
PAGE_OFFSET is equal to 0x80000000. Why does this 
macro exist ? Why not using __pa macro ?

Thanks for your answers.

   Francis.

		
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---

From: Jun Sun <[email-masked]>
Date: Tue, 21 Dec 2004 17:27:15 -0800

Since nobody else is replying I am giving it a shot.  Hope it helps.

> in the 3 first entries. Why is this necessary ?  

Setting WIRED to zero is just part of kernel start-up initialization.

In 2.4 it is done before board setup routine, which allows board
to setup certain wired mapping.

In 2.6 it is done after board setup routine.  You are screwed. :) I think
this needs to be fixed.  A couple of boards should be broken because of this.

> array. Why this assumption ?

Because all other boards have phys memory starting from 0?  It
simplies code for sure.

> code ? 

mem_map holds kernel page table.  Kernel code is mapped there because
we start from 0 and we need to use the free memory _after_ kernel code
segment.  (I don't think it is very useful for MIPS though, since MIPS uses
a flat 512MB block mapping for kernel virtual address.)

> Are these pages going be used when the Linux is
> running ?

Not much in MIPS case I suppose.

> macro exist ? Why not using __pa macro ?

Don't know much about this one.

BTW, once there was a board whose memory starts from 0x90000000.  It had
similar problems as yours, but I think it ran in the end.  Try to search
the mailing list.

Jun

---

From: "Ilya A. Volynets-Evenbakh" <[email-masked]>
Date: Tue, 21 Dec 2004 18:07:49 -0800

CPHYSADDR gives you physical address from an address that lies in
one of compatibility "unmapped" spaces. "compatibility" in this case refers
to 32bit MIPS view of memory space.

As such, CPHYSADDR macro generally should not be used.

---

From: Manish Lachwani <[email-masked]>
Date: Tue, 21 Dec 2004 21:36:51 -0800 (PST)

Hello !
> be broken because of this.

Well, you can again setup the wired tlb entries later.
For example, in case of Ocelot3 board (setup.c code),
the wired tlb entries are again created in the
time_init function.

void momenco_time_init(void)
{
	setup_wired_tlb_entries();

....

And it is set for the first time in the board setup
function:

static int __init momenco_ocelot_3_setup(void)
{
	unsigned int tmpword;

	board_time_init = momenco_time_init;

	_machine_restart = momenco_ocelot_restart;
	_machine_halt = momenco_ocelot_halt;
	_machine_power_off = momenco_ocelot_power_off;

	/* Wired TLB entries */
	setup_wired_tlb_entries();

....

Maybe you can do the same for this board as well

Thanks
Manish Lachwani

=====
http://www.koffee-break.com

---

From: moreau francis <[email-masked]>
Date: Wed, 22 Dec 2004 10:55:14 +0100 (CET)

> Since nobody else is replying I am giving it a shot.

yes it helps, thanks for replying !

> I think

yes and anyway the default value for WIRED is zero
after a reset.

> > Why this assumption ?
> > 
> 
> Because all other boards have phys memory starting
> from 0?  It simplies code for sure.

Well, a part of the kernel seems to support this
feature but not all, specially mips specific code...
That make me think that it would not so hard to change
it...
I look at arm-arch code, and at the definition of
"page_to_pfn" and it does what I need:
      (((page) - mem_map) + PHYS_PFN_OFFSET)
I can't believe that I'm the first one on mips 
architecture who is trying to run kernel code located
at a physicall address different from 0 !

> Not much in MIPS case I suppose.

If these pages are not used during kernel life, it
could save space to not map kernel code in "mem_map".
PFN 0 could be the first page that map kernel data.

This is specialy true if code starts at 0x20000000.

> Don't know much about this one.

It is a typically mips specific code that prevents
kernel code to start at address different from 0.

> similar problems as yours, but I think it ran in the

I can't find it in mailing list archive :(

   Francis

---

From: moreau francis <[email-masked]>
Date: Wed, 22 Dec 2004 11:00:06 +0100 (CET)

> As such, CPHYSADDR macro generally should not be

Well I still don't understand, why it has been
created...
Why does it should replaced "__pa" in particular time
?

Thanks

   Francis

---

From: moreau francis <[email-masked]>
Date: Wed, 22 Dec 2004 11:04:23 +0100 (CET)

> Maybe you can do the same for this board as well

I don't think so, because at the boot time, before
running the very first lines of linux code, the kernel
must be mapped through the TLB. Used TLB entries
should
never be modified, because linux uses them to run
itself, even at boot time !

   Francis

---

From: Stanislaw Skowronek <[email-masked]>
Date: Wed, 22 Dec 2004 11:35:43 +0100 (MET)

> yes and anyway the default value for WIRED is zero

PROMs *do* have interesting ideas sometimes.

> at a physicall address different from 0 !

Sure you aren't. If you have a 64-bit machine, it's relatively easy in
fact. If your code and data is above 512 MB, you are a little more
screwed, but it still can be done (as evidenced by me), and CPHYSADDR does
not, enter the discussion at all. All you have to do is create a correct
memory map at start.

I don't know about running mapped kernels in 32-bit mode, though. It is a
different thing whatsoever.

Stanislaw Skowronek