From consul.kautuk@gmail.com Wed Jan 4 05:52:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Jan 2012 05:52:59 +0100 (CET) Received: from mail-we0-f177.google.com ([74.125.82.177]:53294 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903546Ab2ADEwy (ORCPT ); Wed, 4 Jan 2012 05:52:54 +0100 Received: by wera10 with SMTP id a10so10792942wer.36 for ; Tue, 03 Jan 2012 20:52:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=B+Hs1D3cBDglGrIUVjtR/d91C5Uedcun7kJFDPEenF4=; b=pb7+iipf79zPMYREc0agwjI4x+Pu0FR+poVp1pXkJ195Gi47LIh8iIWFx5u7AMt6o1 5M2g+cmqz5akFHGGlpeiPqnXEK2Qm4uE6tJSHz9VH+YBx+mrZ00WYhyP53V5rzrdH7hI agA6ZuJExBqjg48Hpin61qex+iYTgIVKPjMvY= MIME-Version: 1.0 Received: by 10.216.134.156 with SMTP id s28mr35993147wei.12.1325652768539; Tue, 03 Jan 2012 20:52:48 -0800 (PST) Received: by 10.181.13.169 with HTTP; Tue, 3 Jan 2012 20:52:48 -0800 (PST) In-Reply-To: References: <1324639362-18220-1-git-send-email-consul.kautuk@gmail.com> Date: Wed, 4 Jan 2012 10:22:48 +0530 Message-ID: Subject: Re: [PATCH 1/1] mips: fault.c: Port OOM changes to do_page_fault From: Kautuk Consul To: Ralf Baechle , Ingo Molnar , Peter Zijlstra Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, "Mohd. Faris" , Kautuk Consul Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32209 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: consul.kautuk@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 231 Lines: 8 > > However, since the generic part of the kernel(mm/filemap.c) now > supports killable and > retryable page fault handling, I thought that this change would be > valid for MIPS too. Did anyone get a chance to review this patch? From m.szyprowski@samsung.com Tue Jan 10 09:42:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jan 2012 09:42:47 +0100 (CET) Received: from mailout3.w1.samsung.com ([210.118.77.13]:46121 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901760Ab2AJIml (ORCPT ); Tue, 10 Jan 2012 09:42:41 +0100 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; charset=us-ascii Received: from euspt1 ([210.118.77.13]) by mailout3.w1.samsung.com (Sun Java(tm) System Messaging Server 6.3-8.04 (built Jul 29 2009; 32bit)) with ESMTP id <0LXK00DLBQUW2Q30@mailout3.w1.samsung.com> for linux-mips@linux-mips.org; Tue, 10 Jan 2012 08:42:32 +0000 (GMT) Received: from linux.samsung.com ([106.116.38.10]) by spt1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LXK003JRQUW88@spt1.w1.samsung.com> for linux-mips@linux-mips.org; Tue, 10 Jan 2012 08:42:32 +0000 (GMT) Received: from AMDC159 (unknown [106.116.37.153]) by linux.samsung.com (Postfix) with ESMTP id BE57D270054; Tue, 10 Jan 2012 09:56:01 +0100 (CET) Date: Tue, 10 Jan 2012 09:42:28 +0100 From: Marek Szyprowski Subject: RE: [PATCH 00/14] DMA-mapping framework redesign preparation In-reply-to: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com> To: Marek Szyprowski , linux-kernel@vger.kernel.org Cc: 'Benjamin Herrenschmidt' , 'Thomas Gleixner' , 'Andrew Morton' , 'Arnd Bergmann' , 'Stephen Rothwell' , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, 'Jonathan Corbet' , 'Kyungmin Park' , Andrzej Pietrasiewicz Message-id: <012501cccf73$c90246a0$5b06d3e0$%szyprowski@samsung.com> Organization: SPRC X-Mailer: Microsoft Office Outlook 12.0 Content-language: pl Thread-index: AczBbk0Kypq1Ioj9R1+ZJPNin88RbgOBU+nw References: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com> X-archive-position: 32210 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.szyprowski@samsung.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1867 Lines: 58 Hello, To help everyone in testing and adapting our patches for his hardware platform I've rebased our patches onto the latest v3.2 Linux kernel and prepared a few GIT branches in our public repository. These branches contain our memory management related patches posted in the following threads: "[PATCHv18 0/11] Contiguous Memory Allocator": http://www.spinics.net/lists/linux-mm/msg28125.html later called CMAv18, "[PATCH 00/14] DMA-mapping framework redesign preparation": http://www.spinics.net/lists/linux-sh/msg09777.html and "[PATCH 0/8 v4] ARM: DMA-mapping framework redesign": http://www.spinics.net/lists/arm-kernel/msg151147.html with the following update: http://www.spinics.net/lists/arm-kernel/msg154889.html later called DMAv5. These branches are available in our public GIT repository: git://git.infradead.org/users/kmpark/linux-samsung http://git.infradead.org/users/kmpark/linux-samsung/ The following branches are available: 1) 3.2-cma-v18 Vanilla Linux v3.2 with fixed CMA v18 patches (first patch replaced with the one from v17 to fix SMP issues, see the respective thread). 2) 3.2-dma-v5 Vanilla Linux v3.2 + iommu/next (IOMMU maintainer's patches) branch with DMA-preparation and DMA-mapping framework redesign patches. 3) 3.2-cma-v18-dma-v5 Previous two branches merged together (DMA-mapping on top of CMA) 4) 3.2-cma-v18-dma-v5-exynos Previous branch rebased on top of iommu/next + kgene/for-next (Samsung SoC platform maintainer's patches) with new Exynos4 IOMMU driver by KyongHo Cho and relevant glue code. 5) 3.2-dma-v5-exynos Branch from point 2 rebased on top of iommu/next + kgene/for-next (Samsung SoC maintainer's patches) with new Exynos4 IOMMU driver by KyongHo Cho and relevant glue code. I hope everyone will find a branch that suits his needs. :) Best regards -- Marek Szyprowski Samsung Poland R&D Center From yuasa@linux-mips.org Tue Jan 10 13:12:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jan 2012 13:12:49 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:52168 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903839Ab2AJMMo (ORCPT ); Tue, 10 Jan 2012 13:12:44 +0100 Received: by iakk12 with SMTP id k12so988318iak.36 for ; Tue, 10 Jan 2012 04:12:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; bh=ok7Vv6d+zRqIDWyiguyX5JQ0C7RgNfC/O+dbkFS1IOU=; b=jsH+k3Oc+H3FArushv//VnTt67FGOH5fslLlUk6a2hpwyjmZ6oD81TrtWeEof+a91K Sl+zHVe+QyASN6ejXprArYV/JH9JWuhSEkIBGTS9HPTYyKyuomc+mXJHNIAgNMpaiUHx rx+zq3pycVI1tY52zcWHIbLzqd7AY5TNMXj7k= Received: by 10.50.47.136 with SMTP id d8mr2218361ign.21.1326197557858; Tue, 10 Jan 2012 04:12:37 -0800 (PST) Received: from sdk (UQ1-221-170-12-50.tky.mesh.ad.jp. [221.170.12.50]) by mx.google.com with ESMTPS id 36sm262564794ibc.6.2012.01.10.04.12.34 (version=SSLv3 cipher=OTHER); Tue, 10 Jan 2012 04:12:36 -0800 (PST) Date: Tue, 10 Jan 2012 21:11:56 +0900 From: Yoichi Yuasa To: Greg Kroah-Hartman Cc: Kay Sievers , Ralf Baechle , yuasa@linux-mips.org, linux-mips Subject: [PATCH] MIPS: txx9 7segled fix struct device has no member Message-Id: <20120110211156.31e27cae.yuasa@linux-mips.org> X-Mailer: Sylpheed 3.1.1 (GTK+ 2.22.0; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 32211 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 831 Lines: 25 arch/mips/txx9/generic/7segled.c: In function 'tx_7segled_init_sysfs': arch/mips/txx9/generic/7segled.c:105:6: error: 'struct device' has no member named 'dev' make[3]: *** [arch/mips/txx9/generic/7segled.o] Error 1 Signed-off-by: Yoichi Yuasa --- arch/mips/txx9/generic/7segled.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/txx9/generic/7segled.c b/arch/mips/txx9/generic/7segled.c index 8e93b21..4642f56 100644 --- a/arch/mips/txx9/generic/7segled.c +++ b/arch/mips/txx9/generic/7segled.c @@ -102,7 +102,7 @@ static int __init tx_7segled_init_sysfs(void) break; } dev->id = i; - dev->dev = &tx_7segled_subsys; + dev->bus = &tx_7segled_subsys; error = device_register(dev); if (!error) { device_create_file(dev, &dev_attr_ascii); -- 1.7.3.4 From khali@linux-fr.org Tue Jan 10 16:04:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jan 2012 16:04:19 +0100 (CET) Received: from zone0.gcu-squad.org ([212.85.147.21]:44186 "EHLO services.gcu-squad.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903848Ab2AJPEP (ORCPT ); Tue, 10 Jan 2012 16:04:15 +0100 Received: from jdelvare.pck.nerim.net ([62.212.121.182] helo=endymion.delvare) by services.gcu-squad.org (GCU Mailer Daemon) with esmtpsa id 1Rke4A-000512-JR (TLSv1:AES128-SHA:128) (envelope-from ) ; Tue, 10 Jan 2012 16:56:50 +0100 Date: Tue, 10 Jan 2012 15:38:34 +0100 From: Jean Delvare To: Matt Turner Cc: linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck , "Maciej W. Rozycki" Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20120110153834.531664db@endymion.delvare> In-Reply-To: <20111031105354.4b888e44@endymion.delvare> References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> <20110903103036.161616a5@endymion.delvare> <20111031105354.4b888e44@endymion.delvare> X-Mailer: Claws Mail 3.7.5 (GTK+ 2.20.1; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 32212 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khali@linux-fr.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 449 Lines: 12 On Mon, 31 Oct 2011 10:53:54 +0100, Jean Delvare wrote: > On Sat, 3 Sep 2011 10:30:36 +0200, Jean Delvare wrote: > > Please address my concerns where you agree and send an updated patch. > > Matt, care to send an updated patch addressing my concerns? Otherwise > it will be lost again. It's been 3 more months. Matt (or anyone else who cares and has access to the hardware), please send an updated patch or I'll have to drop it. -- Jean Delvare From macro@linux-mips.org Tue Jan 10 16:31:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jan 2012 16:31:26 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:50391 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903844Ab2AJPbT (ORCPT ); Tue, 10 Jan 2012 16:31:19 +0100 Date: Tue, 10 Jan 2012 15:31:19 +0000 (GMT) From: "Maciej W. Rozycki" To: Jean Delvare cc: Matt Turner , linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts In-Reply-To: <20120110153834.531664db@endymion.delvare> Message-ID: References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> <20110903103036.161616a5@endymion.delvare> <20111031105354.4b888e44@endymion.delvare> <20120110153834.531664db@endymion.delvare> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32213 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 959 Lines: 22 On Tue, 10 Jan 2012, Jean Delvare wrote: > > > Please address my concerns where you agree and send an updated patch. > > > > Matt, care to send an updated patch addressing my concerns? Otherwise > > it will be lost again. > > It's been 3 more months. Matt (or anyone else who cares and has access > to the hardware), please send an updated patch or I'll have to drop it. Thanks for nagging -- it seems unlikely I'll be able to have a look at it before February. If Matt or anyone else cannot get at it before myself and you have to drop the change, then just do what you have to and drop it. I'll try to resync with the current kernel as soon as I can, recheck my queue of outstanding patches and resend both this change and any other ones I'll consider necessary -- I reckon there were more than just this one. Thanks for your understanding and sorry about my recent lack of activity in this area. All the best in the New Year! :) Maciej From ralf@linux-mips.org Wed Jan 11 15:34:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 15:34:47 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:33872 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1904006Ab2AKOej (ORCPT ); Wed, 11 Jan 2012 15:34:39 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0BEYadl010224; Wed, 11 Jan 2012 15:34:36 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0BEYZxL010222; Wed, 11 Jan 2012 15:34:35 +0100 Date: Wed, 11 Jan 2012 15:34:35 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, David Daney , Hillf Danton Subject: Re: [PATCH] MIPS: Add dummy definitions of HPAGE_SHIFT et al. Message-ID: <20120111143435.GA18077@linux-mips.org> References: <1321990924-14189-1-git-send-email-ddaney.cavm@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1321990924-14189-1-git-send-email-ddaney.cavm@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32214 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 63 Lines: 5 I've folded this fix into the original patch. Thanks, Ralf From blogic@openwrt.org Wed Jan 11 21:44:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:44:57 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47496 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904051Ab2AKUop (ORCPT ); Wed, 11 Jan 2012 21:44:45 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code Date: Wed, 11 Jan 2012 21:44:18 +0100 Message-Id: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32215 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 27046 Lines: 897 Inside the folder arch/mips/lantiq/xway, there were alot of small files with lots of duplicated code. This patch adds a wrapper function for inserting and requesting resources and unifies the small files into one bigger file. This patch makes the xway code consistent with the falcon support added later in this series. Signed-off-by: John Crispin --- arch/mips/include/asm/mach-lantiq/lantiq.h | 21 ++--- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 30 ++++++++ arch/mips/lantiq/clk.c | 25 +------ arch/mips/lantiq/devices.c | 30 ++------ arch/mips/lantiq/devices.h | 4 + arch/mips/lantiq/prom.c | 51 +++++++++++-- arch/mips/lantiq/prom.h | 4 + arch/mips/lantiq/xway/Makefile | 6 +- arch/mips/lantiq/xway/devices.c | 42 ++--------- arch/mips/lantiq/xway/dma.c | 21 +---- arch/mips/lantiq/xway/ebu.c | 52 ------------- arch/mips/lantiq/xway/pmu.c | 69 ----------------- arch/mips/lantiq/xway/prom-ase.c | 9 ++ arch/mips/lantiq/xway/prom-xway.c | 10 +++ arch/mips/lantiq/xway/reset.c | 21 +---- arch/mips/lantiq/xway/setup-ase.c | 19 ----- arch/mips/lantiq/xway/setup-xway.c | 20 ----- arch/mips/lantiq/xway/sysctrl.c | 78 ++++++++++++++++++++ drivers/watchdog/lantiq_wdt.c | 2 +- 19 files changed, 219 insertions(+), 295 deletions(-) delete mode 100644 arch/mips/lantiq/xway/ebu.c delete mode 100644 arch/mips/lantiq/xway/pmu.c delete mode 100644 arch/mips/lantiq/xway/setup-ase.c delete mode 100644 arch/mips/lantiq/xway/setup-xway.c create mode 100644 arch/mips/lantiq/xway/sysctrl.c diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index ce2f029..daaa3f7 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -9,23 +9,16 @@ #define _LANTIQ_H__ #include +#include -/* generic reg access functions */ +/* generic reg access */ #define ltq_r32(reg) __raw_readl(reg) #define ltq_w32(val, reg) __raw_writel(val, reg) -#define ltq_w32_mask(clear, set, reg) \ - ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg) #define ltq_r8(reg) __raw_readb(reg) #define ltq_w8(val, reg) __raw_writeb(val, reg) - -/* register access macros for EBU and CGU */ -#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) -#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) -#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) -#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) - -extern __iomem void *ltq_ebu_membase; -extern __iomem void *ltq_cgu_membase; +static inline void ltq_w32_mask(u32 c, u32 s, volatile void __iomem * r) { + ltq_w32((ltq_r32(r) & ~c) | s, r); +} extern unsigned int ltq_get_cpu_ver(void); extern unsigned int ltq_get_soc_type(void); @@ -51,7 +44,9 @@ extern void ltq_enable_irq(struct irq_data *data); /* find out what caused the last cpu reset */ extern int ltq_reset_cause(void); -#define LTQ_RST_CAUSE_WDTRST 0x20 + +/* helper for requesting and remapping resources */ +extern void __iomem *ltq_remap_resource(struct resource *res); #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 8a3c6be..9ea7043 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -61,6 +61,8 @@ #define LTQ_CGU_BASE_ADDR 0x1F103000 #define LTQ_CGU_SIZE 0x1000 +#define CGU_EPHY 0x10 + /* ICU - interrupt control unit */ #define LTQ_ICU_BASE_ADDR 0x1F880200 #define LTQ_ICU_SIZE 0x100 @@ -97,6 +99,8 @@ #define LTQ_WDT_BASE_ADDR 0x1F8803F0 #define LTQ_WDT_SIZE 0x10 +#define LTQ_RST_CAUSE_WDTRST 0x20 + /* STP - serial to parallel conversion unit */ #define LTQ_STP_BASE_ADDR 0x1E100BB0 #define LTQ_STP_SIZE 0x40 @@ -121,11 +125,37 @@ #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) +extern __iomem void *ltq_ebu_membase; +extern __iomem void *ltq_cgu_membase; + +/* ebu access */ +static inline void ltq_ebu_w32(u32 v, u32 r) { + ltq_w32(v, ltq_ebu_membase + r); +}; +static inline u32 ltq_ebu_r32(u32 r) { + return ltq_r32(ltq_ebu_membase + r); +}; +static inline void ltq_ebu_w32_mask(u32 c, u32 s, u32 r) { + ltq_ebu_w32((ltq_ebu_r32(r) & ~c) | s, r); +} + +/* cgu access */ +static inline void ltq_cgu_w32(u32 v, u32 r) { + ltq_w32(v, ltq_cgu_membase + r); +}; +static inline u32 ltq_cgu_r32(u32 r) { + return ltq_r32(ltq_cgu_membase + r); +}; +static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) { + ltq_cgu_w32((ltq_cgu_r32(r) & ~c) | s, r); +} + /* request a non-gpio and set the PIO config */ extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, unsigned int alt1, unsigned int dir, const char *name); extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); +extern void ltq_cgu_enable(unsigned int clk); static inline int ltq_is_ar9(void) { diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index 412814f..39eef7f 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -22,6 +22,7 @@ #include #include "clk.h" +#include "prom.h" struct clk { const char *name; @@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = { }, }; -static struct resource ltq_cgu_resource = { - .name = "cgu", - .start = LTQ_CGU_BASE_ADDR, - .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -/* remapped clock register range */ -void __iomem *ltq_cgu_membase; - void clk_init(void) { cpu_clk = cpu_clk_generic; @@ -133,21 +124,11 @@ void __init plat_time_init(void) { struct clk *clk; - if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) - panic("Failed to insert cgu memory"); - - if (request_mem_region(ltq_cgu_resource.start, - resource_size(<q_cgu_resource), "cgu") < 0) - panic("Failed to request cgu memory"); + ltq_soc_init(); - ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, - resource_size(<q_cgu_resource)); - if (!ltq_cgu_membase) { - pr_err("Failed to remap cgu memory\n"); - unreachable(); - } clk = clk_get(0, "cpu"); mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); write_c0_compare(read_c0_count()); + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); clk_put(clk); } diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c index de1cb2b..7193d78 100644 --- a/arch/mips/lantiq/devices.c +++ b/arch/mips/lantiq/devices.c @@ -27,12 +27,8 @@ #include "devices.h" /* nor flash */ -static struct resource ltq_nor_resource = { - .name = "nor", - .start = LTQ_FLASH_START, - .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_nor_resource = + MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX); static struct platform_device ltq_nor = { .name = "ltq_nor", @@ -47,12 +43,8 @@ void __init ltq_register_nor(struct physmap_flash_data *data) } /* watchdog */ -static struct resource ltq_wdt_resource = { - .name = "watchdog", - .start = LTQ_WDT_BASE_ADDR, - .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_wdt_resource = + MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE); void __init ltq_register_wdt(void) { @@ -61,24 +53,14 @@ void __init ltq_register_wdt(void) /* asc ports */ static struct resource ltq_asc0_resources[] = { - { - .name = "asc0", - .start = LTQ_ASC0_BASE_ADDR, - .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, + MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE), IRQ_RES(tx, LTQ_ASC_TIR(0)), IRQ_RES(rx, LTQ_ASC_RIR(0)), IRQ_RES(err, LTQ_ASC_EIR(0)), }; static struct resource ltq_asc1_resources[] = { - { - .name = "asc1", - .start = LTQ_ASC1_BASE_ADDR, - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, + MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), IRQ_RES(tx, LTQ_ASC_TIR(1)), IRQ_RES(rx, LTQ_ASC_RIR(1)), IRQ_RES(err, LTQ_ASC_EIR(1)), diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h index 2947bb1..18b65df 100644 --- a/arch/mips/lantiq/devices.h +++ b/arch/mips/lantiq/devices.h @@ -14,6 +14,10 @@ #define IRQ_RES(resname, irq) \ {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} +#define MEM_RES(resname, adr_start, adr_size) \ + { .name = resname, .flags = IORESOURCE_MEM, \ + .start = CPHYSADDR(adr_start), \ + .end = CPHYSADDR(adr_start + adr_size - 1) } extern void ltq_register_nor(struct physmap_flash_data *data); extern void ltq_register_wdt(void); diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index e34fcfd..528e205 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -16,6 +16,10 @@ #include "prom.h" #include "clk.h" +/* access to the ebu needs to be locked between different drivers */ +DEFINE_SPINLOCK(ebu_lock); +EXPORT_SYMBOL_GPL(ebu_lock); + static struct ltq_soc_info soc_info; unsigned int ltq_get_cpu_ver(void) @@ -55,16 +59,51 @@ static void __init prom_init_cmdline(void) } } -void __init prom_init(void) +void __iomem *ltq_remap_resource(struct resource *res) { - struct clk *clk; + __iomem void *ret = NULL; + struct resource *lookup = lookup_resource(&iomem_resource, res->start); + + if (lookup && strcmp(lookup->name, res->name)) { + pr_err("conflicting memory range %s\n", res->name); + return NULL; + } + if (!lookup) { + if (insert_resource(&iomem_resource, res) < 0) { + pr_err("Failed to insert %s memory\n", res->name); + return NULL; + } + } + if (request_mem_region(res->start, + resource_size(res), res->name) < 0) { + pr_err("Failed to request %s memory\n", res->name); + goto err_res; + } + ret = ioremap_nocache(res->start, resource_size(res)); + if (!ret) + goto err_mem; + + pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n", + res->start, res->end, res->name); + return ret; + +err_mem: + panic("Failed to remap %s memory", res->name); + release_mem_region(res->start, resource_size(res)); + +err_res: + release_resource(res); + return NULL; +} +EXPORT_SYMBOL(ltq_remap_resource); + +void __init prom_init(void) +{ ltq_soc_detect(&soc_info); clk_init(); - clk = clk_get(0, "cpu"); - snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", - soc_info.name, soc_info.rev); - clk_put(clk); + snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", + soc_info.name, soc_info.rev_type); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; pr_info("SoC: %s\n", soc_info.sys_type); prom_init_cmdline(); diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h index b4229d9..51dba1b 100644 --- a/arch/mips/lantiq/prom.h +++ b/arch/mips/lantiq/prom.h @@ -9,17 +9,21 @@ #ifndef _LTQ_PROM_H__ #define _LTQ_PROM_H__ +#define LTQ_SYS_REV_LEN 0x10 #define LTQ_SYS_TYPE_LEN 0x100 struct ltq_soc_info { unsigned char *name; unsigned int rev; + unsigned char rev_type[LTQ_SYS_REV_LEN]; + unsigned int srev; unsigned int partnum; unsigned int type; unsigned char sys_type[LTQ_SYS_TYPE_LEN]; }; extern void ltq_soc_detect(struct ltq_soc_info *i); +extern void ltq_soc_init(void); extern void ltq_soc_setup(void); #endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index c517f2e..6678402 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,7 +1,7 @@ -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c index d614aa7..f97e565 100644 --- a/arch/mips/lantiq/xway/devices.c +++ b/arch/mips/lantiq/xway/devices.c @@ -31,22 +31,9 @@ /* gpio */ static struct resource ltq_gpio_resource[] = { - { - .name = "gpio0", - .start = LTQ_GPIO0_BASE_ADDR, - .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "gpio1", - .start = LTQ_GPIO1_BASE_ADDR, - .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "gpio2", - .start = LTQ_GPIO2_BASE_ADDR, - .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - } + MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE), + MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE), + MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE), }; void __init ltq_register_gpio(void) @@ -64,12 +51,8 @@ void __init ltq_register_gpio(void) } /* serial to parallel conversion */ -static struct resource ltq_stp_resource = { - .name = "stp", - .start = LTQ_STP_BASE_ADDR, - .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_stp_resource = + MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE); void __init ltq_register_gpio_stp(void) { @@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void) /* asc ports - amazon se has its own serial mapping */ static struct resource ltq_ase_asc_resources[] = { - { - .name = "asc0", - .start = LTQ_ASC1_BASE_ADDR, - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, + MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), IRQ_RES(tx, LTQ_ASC_ASE_TIR), IRQ_RES(rx, LTQ_ASC_ASE_RIR), IRQ_RES(err, LTQ_ASC_ASE_EIR), @@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void) } /* ethernet */ -static struct resource ltq_etop_resources = { - .name = "etop", - .start = LTQ_ETOP_BASE_ADDR, - .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_etop_resources = + MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE); static struct platform_device ltq_etop = { .name = "ltq_etop", diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index b210e93..6cf883b 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -24,6 +24,8 @@ #include #include +#include "../devices.h" + #define LTQ_DMA_CTRL 0x10 #define LTQ_DMA_CPOLL 0x14 #define LTQ_DMA_CS 0x18 @@ -55,12 +57,8 @@ #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ ltq_dma_membase + (z)) -static struct resource ltq_dma_resource = { - .name = "dma", - .start = LTQ_DMA_BASE_ADDR, - .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_dma_resource = + MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE); static void __iomem *ltq_dma_membase; @@ -220,17 +218,8 @@ ltq_dma_init(void) { int i; - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_dma_resource) < 0) - panic("Failed to insert dma memory"); - - if (request_mem_region(ltq_dma_resource.start, - resource_size(<q_dma_resource), "dma") < 0) - panic("Failed to request dma memory"); - /* remap dma register range */ - ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, - resource_size(<q_dma_resource)); + ltq_dma_membase = ltq_remap_resource(<q_dma_resource); if (!ltq_dma_membase) panic("Failed to remap dma memory"); diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c deleted file mode 100644 index 862e3e8..0000000 --- a/arch/mips/lantiq/xway/ebu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * EBU - the external bus unit attaches PCI, NOR and NAND - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include - -#include - -/* all access to the ebu must be locked */ -DEFINE_SPINLOCK(ebu_lock); -EXPORT_SYMBOL_GPL(ebu_lock); - -static struct resource ltq_ebu_resource = { - .name = "ebu", - .start = LTQ_EBU_BASE_ADDR, - .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -/* remapped base addr of the clock unit and external bus unit */ -void __iomem *ltq_ebu_membase; - -static int __init lantiq_ebu_init(void) -{ - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) - panic("Failed to insert ebu memory"); - - if (request_mem_region(ltq_ebu_resource.start, - resource_size(<q_ebu_resource), "ebu") < 0) - panic("Failed to request ebu memory"); - - /* remap ebu register range */ - ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, - resource_size(<q_ebu_resource)); - if (!ltq_ebu_membase) - panic("Failed to remap ebu memory"); - - /* make sure to unprotect the memory region where flash is located */ - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); - return 0; -} - -postcore_initcall(lantiq_ebu_init); diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c deleted file mode 100644 index fe85361..0000000 --- a/arch/mips/lantiq/xway/pmu.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include - -#include - -/* PMU - the power management unit allows us to turn part of the core - * on and off - */ - -/* the enable / disable registers */ -#define LTQ_PMU_PWDCR 0x1C -#define LTQ_PMU_PWDSR 0x20 - -#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) -#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) - -static struct resource ltq_pmu_resource = { - .name = "pmu", - .start = LTQ_PMU_BASE_ADDR, - .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static void __iomem *ltq_pmu_membase; - -void ltq_pmu_enable(unsigned int module) -{ - int err = 1000000; - - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); - do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); - - if (!err) - panic("activating PMU module failed!"); -} -EXPORT_SYMBOL(ltq_pmu_enable); - -void ltq_pmu_disable(unsigned int module) -{ - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); -} -EXPORT_SYMBOL(ltq_pmu_disable); - -int __init ltq_pmu_init(void) -{ - if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) - panic("Failed to insert pmu memory"); - - if (request_mem_region(ltq_pmu_resource.start, - resource_size(<q_pmu_resource), "pmu") < 0) - panic("Failed to request pmu memory"); - - ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, - resource_size(<q_pmu_resource)); - if (!ltq_pmu_membase) - panic("Failed to remap pmu memory"); - return 0; -} - -core_initcall(ltq_pmu_init); diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c index ae4959a..3f86a3b 100644 --- a/arch/mips/lantiq/xway/prom-ase.c +++ b/arch/mips/lantiq/xway/prom-ase.c @@ -13,6 +13,7 @@ #include +#include "devices.h" #include "../prom.h" #define SOC_AMAZON_SE "Amazon_SE" @@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) { i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); switch (i->partnum) { case SOC_ID_AMAZON_SE: i->name = SOC_AMAZON_SE; @@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) break; } } + +void __init ltq_soc_setup(void) +{ + ltq_register_ase_asc(); + ltq_register_gpio(); + ltq_register_wdt(); +} diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c index 2228133..d823a92 100644 --- a/arch/mips/lantiq/xway/prom-xway.c +++ b/arch/mips/lantiq/xway/prom-xway.c @@ -13,6 +13,7 @@ #include +#include "devices.h" #include "../prom.h" #define SOC_DANUBE "Danube" @@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) { i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); switch (i->partnum) { case SOC_ID_DANUBE1: case SOC_ID_DANUBE2: @@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) break; } } + +void __init ltq_soc_setup(void) +{ + ltq_register_asc(0); + ltq_register_asc(1); + ltq_register_gpio(); + ltq_register_wdt(); +} diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c index 8b66bd8..c705bbf 100644 --- a/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c @@ -15,6 +15,8 @@ #include +#include "../devices.h" + #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) @@ -25,12 +27,8 @@ #define LTQ_RCU_RST_STAT 0x0014 #define LTQ_RCU_STAT_SHIFT 26 -static struct resource ltq_rcu_resource = { - .name = "rcu", - .start = LTQ_RCU_BASE_ADDR, - .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_rcu_resource = + MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE); /* remapped base addr of the reset control unit */ static void __iomem *ltq_rcu_membase; @@ -67,17 +65,8 @@ static void ltq_machine_power_off(void) static int __init mips_reboot_setup(void) { - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) - panic("Failed to insert rcu memory"); - - if (request_mem_region(ltq_rcu_resource.start, - resource_size(<q_rcu_resource), "rcu") < 0) - panic("Failed to request rcu memory"); - /* remap rcu register range */ - ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, - resource_size(<q_rcu_resource)); + ltq_rcu_membase = ltq_remap_resource(<q_rcu_resource); if (!ltq_rcu_membase) panic("Failed to remap rcu memory"); diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c deleted file mode 100644 index f6f3267..0000000 --- a/arch/mips/lantiq/xway/setup-ase.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include - -#include "../prom.h" -#include "devices.h" - -void __init ltq_soc_setup(void) -{ - ltq_register_ase_asc(); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c deleted file mode 100644 index c292f64..0000000 --- a/arch/mips/lantiq/xway/setup-xway.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include - -#include "../prom.h" -#include "devices.h" - -void __init ltq_soc_setup(void) -{ - ltq_register_asc(0); - ltq_register_asc(1); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c new file mode 100644 index 0000000..38c122f --- /dev/null +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -0,0 +1,78 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include + +#include + +#include "../devices.h" + +/* clock control register */ +#define LTQ_CGU_IFCCR 0x0018 + +/* the enable / disable registers */ +#define LTQ_PMU_PWDCR 0x1C +#define LTQ_PMU_PWDSR 0x20 + +#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) +#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) + +static struct resource ltq_cgu_resource = + MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); + +static struct resource ltq_pmu_resource = + MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); + +static struct resource ltq_ebu_resource = + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + +void __iomem *ltq_cgu_membase; +void __iomem *ltq_ebu_membase; +static void __iomem *ltq_pmu_membase; + +void ltq_cgu_enable(unsigned int clk) +{ + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR); +} + +void ltq_pmu_enable(unsigned int module) +{ + int err = 1000000; + + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); + do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); + + if (!err) + panic("activating PMU module failed!"); +} +EXPORT_SYMBOL(ltq_pmu_enable); + +void ltq_pmu_disable(unsigned int module) +{ + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); +} +EXPORT_SYMBOL(ltq_pmu_disable); + +void __init ltq_soc_init(void) +{ + ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource); + if (!ltq_pmu_membase) + panic("Failed to remap pmu memory"); + + ltq_cgu_membase = ltq_remap_resource(<q_cgu_resource); + if (!ltq_cgu_membase) + panic("Failed to remap cgu memory"); + + ltq_ebu_membase = ltq_remap_resource(<q_ebu_resource); + if (!ltq_ebu_membase) + panic("Failed to remap ebu memory"); + + /* make sure to unprotect the memory region where flash is located */ + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); +} diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c index 102aed0..179bf98 100644 --- a/drivers/watchdog/lantiq_wdt.c +++ b/drivers/watchdog/lantiq_wdt.c @@ -16,7 +16,7 @@ #include #include -#include +#include /* Section 3.4 of the datasheet * The password sequence protects the WDT control register from unintended -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:45:19 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47502 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904052Ab2AKUop (ORCPT ); Wed, 11 Jan 2012 21:44:45 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH RESEND 02/17] MIPS: lantiq: change ltq_request_gpio() call signature Date: Wed, 11 Jan 2012 21:44:19 +0100 Message-Id: <1326314674-9899-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32216 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5309 Lines: 147 ltq_request_gpio() was using alt0/1 to multiplex the function of GPIO pins. This was XWAY specific. In order to also accomodate SoCs that require more bits we use a 32bit mask instead. This way the call signature is consistent between XWAY and FALC-ON. Signed-off-by: John Crispin Signed-off-by: Thomas Langer --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +- arch/mips/lantiq/xway/gpio.c | 8 ++-- arch/mips/lantiq/xway/gpio_stp.c | 6 +- arch/mips/pci/pci-lantiq.c | 40 +++++++++---------- 4 files changed, 28 insertions(+), 30 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 9ea7043..a6521ec 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -151,8 +151,8 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) { } /* request a non-gpio and set the PIO config */ -extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, - unsigned int alt1, unsigned int dir, const char *name); +extern int ltq_gpio_request(unsigned int pin, unsigned int mux, + unsigned int dir, const char *name); extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); extern void ltq_cgu_enable(unsigned int clk); diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c index d2fa98f..f204f6c 100644 --- a/arch/mips/lantiq/xway/gpio.c +++ b/arch/mips/lantiq/xway/gpio.c @@ -48,8 +48,8 @@ int irq_to_gpio(unsigned int gpio) } EXPORT_SYMBOL(irq_to_gpio); -int ltq_gpio_request(unsigned int pin, unsigned int alt0, - unsigned int alt1, unsigned int dir, const char *name) +int ltq_gpio_request(unsigned int pin, unsigned int mux, + unsigned int dir, const char *name) { int id = 0; @@ -67,13 +67,13 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0, pin -= PINS_PER_PORT; id++; } - if (alt0) + if (mux & 0x2) ltq_gpio_setbit(ltq_gpio_port[id].membase, LTQ_GPIO_ALTSEL0, pin); else ltq_gpio_clearbit(ltq_gpio_port[id].membase, LTQ_GPIO_ALTSEL0, pin); - if (alt1) + if (mux & 0x1) ltq_gpio_setbit(ltq_gpio_port[id].membase, LTQ_GPIO_ALTSEL1, pin); else diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index ff9991c..2c78660 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -79,9 +79,9 @@ static struct gpio_chip ltq_stp_chip = { static int ltq_stp_hw_init(void) { /* the 3 pins used to control the external stp */ - ltq_gpio_request(4, 1, 0, 1, "stp-st"); - ltq_gpio_request(5, 1, 0, 1, "stp-d"); - ltq_gpio_request(6, 1, 0, 1, "stp-sh"); + ltq_gpio_request(4, 2, 1, "stp-st"); + ltq_gpio_request(5, 2, 1, "stp-d"); + ltq_gpio_request(6, 2, 1, "stp-sh"); /* sane defaults */ ltq_stp_w32(0, LTQ_STP_AR); diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index be1e1af..3bf42c8 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -69,29 +69,28 @@ #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) struct ltq_pci_gpio_map { - int pin; - int alt0; - int alt1; - int dir; + unsigned int pin; + unsigned int mux; + unsigned char dir; char *name; }; /* the pci core can make use of the following gpios */ static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { - { 0, 1, 0, 0, "pci-exin0" }, - { 1, 1, 0, 0, "pci-exin1" }, - { 2, 1, 0, 0, "pci-exin2" }, - { 39, 1, 0, 0, "pci-exin3" }, - { 10, 1, 0, 0, "pci-exin4" }, - { 9, 1, 0, 0, "pci-exin5" }, - { 30, 1, 0, 1, "pci-gnt1" }, - { 23, 1, 0, 1, "pci-gnt2" }, - { 19, 1, 0, 1, "pci-gnt3" }, - { 38, 1, 0, 1, "pci-gnt4" }, - { 29, 1, 0, 0, "pci-req1" }, - { 31, 1, 0, 0, "pci-req2" }, - { 3, 1, 0, 0, "pci-req3" }, - { 37, 1, 0, 0, "pci-req4" }, + { .pin = 0, .mux = 2, .dir = 0, .name = "pci-exin0" }, + { .pin = 1, .mux = 2, .dir = 0, .name = "pci-exin1" }, + { .pin = 2, .mux = 2, .dir = 0, .name = "pci-exin2" }, + { .pin = 39, .mux = 2, .dir = 0, .name = "pci-exin3" }, + { .pin = 10, .mux = 2, .dir = 0, .name = "pci-exin4" }, + { .pin = 9, .mux = 2, .dir = 0, .name = "pci-exin5" }, + { .pin = 30, .mux = 2, .dir = 1, .name = "pci-gnt1" }, + { .pin = 23, .mux = 2, .dir = 1, .name = "pci-gnt2" }, + { .pin = 19, .mux = 2, .dir = 1, .name = "pci-gnt3" }, + { .pin = 38, .mux = 2, .dir = 1, .name = "pci-gnt4" }, + { .pin = 29, .mux = 2, .dir = 0, .name = "pci-req1" }, + { .pin = 31, .mux = 2, .dir = 0, .name = "pci-req2" }, + { .pin = 3, .mux = 2, .dir = 0, .name = "pci-req3" }, + { .pin = 37, .mux = 2, .dir = 0, .name = "pci-req4" }, }; __iomem void *ltq_pci_mapped_cfg; @@ -157,13 +156,12 @@ static void ltq_pci_setup_gpio(int gpio) for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { if (gpio & (1 << i)) { ltq_gpio_request(ltq_pci_gpio_map[i].pin, - ltq_pci_gpio_map[i].alt0, - ltq_pci_gpio_map[i].alt1, + ltq_pci_gpio_map[i].mux, ltq_pci_gpio_map[i].dir, ltq_pci_gpio_map[i].name); } } - ltq_gpio_request(21, 0, 0, 1, "pci-reset"); + ltq_gpio_request(21, 0, 1, "pci-reset"); ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; } -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:45:43 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47507 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904054Ab2AKUoq (ORCPT ); Wed, 11 Jan 2012 21:44:46 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH RESEND 03/17] MIPS: lantiq: make irq.c support the FALC-ON Date: Wed, 11 Jan 2012 21:44:20 +0100 Message-Id: <1326314674-9899-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32217 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2461 Lines: 68 There are minor differences in how irqs work on xway and falcon socs. Xway needs 2 quirks that we need to disable for falcon to also work with this code. * EBU irq does not need to send a special ack to the EBU * The EIU does not exist Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- arch/mips/lantiq/irq.c | 24 +++++++++++++----------- 1 files changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index d673731..3b8cea5 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int module) do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); /* if this is a EBU irq, we need to ack it or get a deadlock */ - if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, LTQ_EBU_PCC_ISTAT); } @@ -259,17 +259,19 @@ void __init arch_init_irq(void) if (!ltq_icu_membase) panic("Failed to remap icu memory"); - if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) - panic("Failed to insert eiu memory"); + if (LTQ_EIU_BASE_ADDR) { + if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) + panic("Failed to insert eiu memory"); - if (request_mem_region(ltq_eiu_resource.start, - resource_size(<q_eiu_resource), "eiu") < 0) - panic("Failed to request eiu memory"); + if (request_mem_region(ltq_eiu_resource.start, + resource_size(<q_eiu_resource), "eiu") < 0) + panic("Failed to request eiu memory"); - ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, + ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, resource_size(<q_eiu_resource)); - if (!ltq_eiu_membase) - panic("Failed to remap eiu memory"); + if (!ltq_eiu_membase) + panic("Failed to remap eiu memory"); + } /* make sure all irqs are turned off by default */ for (i = 0; i < 5; i++) @@ -295,8 +297,8 @@ void __init arch_init_irq(void) for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) - if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || - (i == LTQ_EIU_IR2)) + if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || + (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR) irq_set_chip_and_handler(i, <q_eiu_type, handle_level_irq); /* EIU3-5 only exist on ar9 and vr9 */ -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:46:11 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47513 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904055Ab2AKUor (ORCPT ); Wed, 11 Jan 2012 21:44:47 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH RESEND 04/17] MIPS: lantiq: add basic support for FALC-ON Date: Wed, 11 Jan 2012 21:44:21 +0100 Message-Id: <1326314674-9899-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32218 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35176 Lines: 1096 Adds support for the FALC-ON SoC. This SoC is from the FTTH/GPON SoC family. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- .../include/asm/mach-lantiq/falcon/falcon_irq.h | 268 ++++++++++++++++++++ arch/mips/include/asm/mach-lantiq/falcon/irq.h | 18 ++ .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 152 +++++++++++ arch/mips/include/asm/mach-lantiq/lantiq.h | 1 + arch/mips/lantiq/Kconfig | 4 + arch/mips/lantiq/Makefile | 1 + arch/mips/lantiq/Platform | 1 + arch/mips/lantiq/falcon/Makefile | 1 + arch/mips/lantiq/falcon/clk.c | 44 ++++ arch/mips/lantiq/falcon/devices.c | 87 +++++++ arch/mips/lantiq/falcon/devices.h | 18 ++ arch/mips/lantiq/falcon/prom.c | 93 +++++++ arch/mips/lantiq/falcon/reset.c | 91 +++++++ arch/mips/lantiq/falcon/sysctrl.c | 183 +++++++++++++ 14 files changed, 962 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h create mode 100644 arch/mips/lantiq/falcon/Makefile create mode 100644 arch/mips/lantiq/falcon/clk.c create mode 100644 arch/mips/lantiq/falcon/devices.c create mode 100644 arch/mips/lantiq/falcon/devices.h create mode 100644 arch/mips/lantiq/falcon/prom.c create mode 100644 arch/mips/lantiq/falcon/reset.c create mode 100644 arch/mips/lantiq/falcon/sysctrl.c diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h new file mode 100644 index 0000000..4dc6466 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h @@ -0,0 +1,268 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer + */ + +#ifndef _FALCON_IRQ__ +#define _FALCON_IRQ__ + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define MIPS_CPU_TIMER_IRQ 7 + +/* HOST IF Event Interrupt */ +#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0) +/* HOST IF Mailbox0 Receive Interrupt */ +#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1) +/* HOST IF Mailbox0 Transmit Interrupt */ +#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2) +/* HOST IF Mailbox1 Receive Interrupt */ +#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3) +/* HOST IF Mailbox1 Transmit Interrupt */ +#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4) +/* I2C Last Single Data Transfer Request */ +#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8) +/* I2C Single Data Transfer Request */ +#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9) +/* I2C Last Burst Data Transfer Request */ +#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10) +/* I2C Burst Data Transfer Request */ +#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11) +/* I2C Error Interrupt */ +#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12) +/* I2C Protocol Interrupt */ +#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13) +/* SSC Transmit Interrupt */ +#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14) +/* SSC Receive Interrupt */ +#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15) +/* SSC Error Interrupt */ +#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16) +/* SSC Frame Interrupt */ +#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17) +/* Advanced Encryption Standard Interrupt */ +#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27) +/* Secure Hash Algorithm Interrupt */ +#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28) +/* PCM Receive Interrupt */ +#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29) +/* PCM Transmit Interrupt */ +#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30) +/* PCM Transmit Crash Interrupt */ +#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31) + +/* EBU Serial Flash Command Error */ +#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0) +/* EBU Serial Flash Command Overwrite Error */ +#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1) +/* EBU Serial Flash Busy */ +#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2) +/* External Interrupt from GPIO P0 */ +#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4) +/* External Interrupt from GPIO P1 */ +#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5) +/* External Interrupt from GPIO P2 */ +#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6) +/* External Interrupt from GPIO P3 */ +#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7) +/* External Interrupt from GPIO P4 */ +#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8) +/* 8kHz backup interrupt derived from core-PLL */ +#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10) +/* FSC Timer Interrupt 0 */ +#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11) +/* FSC Timer Interrupt 1 */ +#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12) +/* 8kHz root interrupt derived from GPON interface */ +#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13) +/* Time of Day */ +#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14) +/* PMA Interrupt from IntNode of the 200MHz Domain */ +#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15) +/* PMA Interrupt from IntNode of the TX Clk Domain */ +#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16) +/* PMA Interrupt from IntNode of the RX Clk Domain */ +#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17) +/* SYS1 Interrupt */ +#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20) +/* SYS GPE Interrupt */ +#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21) +/* Watchdog Access Error Interrupt */ +#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24) +/* Watchdog Prewarning Interrupt */ +#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25) +/* SBIU interrupt */ +#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27) +/* FPI Bus Control Unit Interrupt */ +#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29) +/* DDR Controller Interrupt */ +#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30) +/* Crossbar Error Interrupt */ +#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31) + +/* ICTRLL 0 Interrupt */ +#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0) +/* ICTRLL 1 Interrupt */ +#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1) +/* ICTRLL 2 Interrupt */ +#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2) +/* ICTRLL 3 Interrupt */ +#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3) +/* OCTRLL 0 Interrupt */ +#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4) +/* OCTRLL 1 Interrupt */ +#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5) +/* OCTRLL 2 Interrupt */ +#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6) +/* OCTRLL 3 Interrupt */ +#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7) +/* OCTRLG Interrupt */ +#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9) +/* IQM Interrupt */ +#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10) +/* FSQM Interrupt */ +#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11) +/* TMU Interrupt */ +#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12) +/* LINK1 Interrupt */ +#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14) +/* ICTRLC 0 Interrupt */ +#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16) +/* ICTRLC 1 Interrupt */ +#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17) +/* OCTRLC Interrupt */ +#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18) +/* CONFIG Break Interrupt */ +#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19) +/* CONFIG Interrupt */ +#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20) +/* Dispatcher Interrupt */ +#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21) +/* TBM Interrupt */ +#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22) +/* GTC Downstream Interrupt */ +#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29) +/* GTC Upstream Interrupt */ +#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30) +/* EIM Interrupt */ +#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31) + +/* ASC0 Transmit Interrupt */ +#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0) +/* ASC0 Receive Interrupt */ +#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1) +/* ASC0 Error Interrupt */ +#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2) +/* ASC0 Transmit Buffer Interrupt */ +#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3) +/* ASC0 Autobaud Start Interrupt */ +#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4) +/* ASC0 Autobaud Detection Interrupt */ +#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5) +/* ASC1 Modem Status Interrupt */ +#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6) +/* ASC0 Soft Flow Control Interrupt */ +#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7) +/* ASC1 Transmit Interrupt */ +#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8) +/* ASC1 Receive Interrupt */ +#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9) +/* ASC1 Error Interrupt */ +#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10) +/* ASC1 Transmit Buffer Interrupt */ +#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11) +/* ASC1 Autobaud Start Interrupt */ +#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12) +/* ASC1 Autobaud Detection Interrupt */ +#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13) +/* ASC1 Modem Status Interrupt */ +#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14) +/* ASC1 Soft Flow Control Interrupt */ +#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15) +/* GPTC Timer/Counter 1A Interrupt */ +#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16) +/* GPTC Timer/Counter 1B Interrupt */ +#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17) +/* GPTC Timer/Counter 2A Interrupt */ +#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18) +/* GPTC Timer/Counter 2B Interrupt */ +#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19) +/* GPTC Timer/Counter 3A Interrupt */ +#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20) +/* GPTC Timer/Counter 3B Interrupt */ +#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21) +/* DFEV0, Channel 1 Transmit Interrupt */ +#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26) +/* DFEV0, Channel 1 Receive Interrupt */ +#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27) +/* DFEV0, Channel 1 General Purpose Interrupt */ +#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28) +/* DFEV0, Channel 0 Transmit Interrupt */ +#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29) +/* DFEV0, Channel 0 Receive Interrupt */ +#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30) +/* DFEV0, Channel 0 General Purpose Interrupt */ +#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31) + +/* ICTRLL 0 Error */ +#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0) +/* ICTRLL 1 Error */ +#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1) +/* ICTRLL 2 Error */ +#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2) +/* ICTRLL 3 Error */ +#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3) +/* OCTRLL 0 Error */ +#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4) +/* OCTRLL 1 Error */ +#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5) +/* OCTRLL 2 Error */ +#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6) +/* OCTRLL 3 Error */ +#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7) +/* ICTRLG Error */ +#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8) +/* OCTRLG Error */ +#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9) +/* IQM Error */ +#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10) +/* FSQM Error */ +#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11) +/* TMU Error */ +#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12) +/* MPS Status Interrupt #0 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14) +/* MPS Status Interrupt #1 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15) +/* MPS Status Interrupt #2 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16) +/* MPS Status Interrupt #3 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17) +/* MPS Status Interrupt #4 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18) +/* MPS Status Interrupt #5 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19) +/* MPS Status Interrupt #6 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20) +/* MPS Status Interrupt #7 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21) +/* MPS Status Interrupt #8 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22) +/* VPE0 Exception Level Flag Interrupt */ +#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29) +/* VPE0 Error Level Flag Interrupt */ +#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30) +/* VPE0 Performance Monitoring Counter Interrupt */ +#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31) + +#endif /* _FALCON_IRQ__ */ diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h new file mode 100644 index 0000000..2caccd9 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + */ + +#ifndef __FALCON_IRQ_H +#define __FALCON_IRQ_H + +#include + +#define NR_IRQS 328 + +#include_next + +#endif diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h new file mode 100644 index 0000000..22f8774 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -0,0 +1,152 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_FALCON_H__ +#define _LTQ_FALCON_H__ + +#ifdef CONFIG_SOC_FALCON + +#include + +/* Chip IDs */ +#define SOC_ID_FALCON 0x01B8 + +/* SoC Types */ +#define SOC_TYPE_FALCON 0x01 + +/* ASC0/1 - serial port */ +#define LTQ_ASC0_BASE_ADDR 0x1E100C00 +#define LTQ_ASC1_BASE_ADDR 0x1E100B00 +#define LTQ_ASC_SIZE 0x100 + +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) + +/* + * during early_printk no ioremap possible at this early stage + * lets use KSEG1 instead + */ +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) + +/* ICU - interrupt control unit */ +#define LTQ_ICU_BASE_ADDR 0x1F880200 +#define LTQ_ICU_SIZE 0x100 + +/* WDT */ +#define LTQ_WDT_BASE_ADDR 0x1F8803F0 +#define LTQ_WDT_SIZE 0x10 + +#define LTQ_RST_CAUSE_WDTRST 0x0002 + +/* EBU - external bus unit */ +#define LTQ_EBU_BASE_ADDR 0x18000000 +#define LTQ_EBU_SIZE 0x0100 + +#define LTQ_EBU_MODCON 0x000C + +/* GPIO */ +#define LTQ_GPIO0_BASE_ADDR 0x1D810000 +#define LTQ_GPIO0_SIZE 0x0080 +#define LTQ_GPIO1_BASE_ADDR 0x1E800100 +#define LTQ_GPIO1_SIZE 0x0080 +#define LTQ_GPIO2_BASE_ADDR 0x1D810100 +#define LTQ_GPIO2_SIZE 0x0080 +#define LTQ_GPIO3_BASE_ADDR 0x1E800200 +#define LTQ_GPIO3_SIZE 0x0080 +#define LTQ_GPIO4_BASE_ADDR 0x1E800300 +#define LTQ_GPIO4_SIZE 0x0080 +#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000 +#define LTQ_PADCTRL0_SIZE 0x0100 +#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400 +#define LTQ_PADCTRL1_SIZE 0x0100 +#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000 +#define LTQ_PADCTRL2_SIZE 0x0100 +#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500 +#define LTQ_PADCTRL3_SIZE 0x0100 +#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 +#define LTQ_PADCTRL4_SIZE 0x0100 + +/* CHIP ID */ +#define LTQ_STATUS_BASE_ADDR 0x1E802000 + +#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) +#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) +#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) + +/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ +#define LTQ_SYS1_BASE_ADDR 0x1EF00000 +#define LTQ_SYS1_SIZE 0x0100 +#define LTQ_STATUS_BASE_ADDR 0x1E802000 +#define LTQ_STATUS_SIZE 0x0080 +#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000 +#define LTQ_SYS_ETH_SIZE 0x0100 +#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000 +#define LTQ_SYS_GPE_SIZE 0x0100 + +#define SYSCTL_SYS1 0 +#define SYSCTL_SYSETH 1 +#define SYSCTL_SYSGPE 2 + +/* Activation Status Register */ +#define ACTS_ASC1_ACT 0x00000800 +#define ACTS_P0 0x00010000 +#define ACTS_P1 0x00010000 +#define ACTS_P2 0x00020000 +#define ACTS_P3 0x00020000 +#define ACTS_P4 0x00040000 +#define ACTS_PADCTRL0 0x00100000 +#define ACTS_PADCTRL1 0x00100000 +#define ACTS_PADCTRL2 0x00200000 +#define ACTS_PADCTRL3 0x00200000 +#define ACTS_PADCTRL4 0x00400000 + +extern void ltq_sysctl_activate(int module, unsigned int mask); +extern void ltq_sysctl_deactivate(int module, unsigned int mask); +extern void ltq_sysctl_clken(int module, unsigned int mask); +extern void ltq_sysctl_clkdis(int module, unsigned int mask); +extern void ltq_sysctl_reboot(int module, unsigned int mask); +extern int ltq_gpe_is_activated(unsigned int mask); + +/* global register ranges */ +extern void __iomem *ltq_ebu_membase; +extern void __iomem *ltq_sys1_membase; +static inline void ltq_ebu_w32(u32 v, u32 r) { + ltq_w32(v, ltq_ebu_membase + r); +}; +static inline u32 ltq_ebu_r32(u32 r) { + return ltq_r32(ltq_ebu_membase + r); +}; +static inline void ltq_ebu_w32_mask(u32 c, u32 s, u32 r) { + ltq_ebu_w32((ltq_ebu_r32(r) & ~c) | s, r); +} +static inline void ltq_sys1_w32(u32 v, u32 r) { + ltq_w32(v, ltq_sys1_membase + r); +}; +static inline u32 ltq_sys1_r32(u32 r) { + return ltq_r32(ltq_sys1_membase + r); +}; +static inline void ltq_sys1_w32_mask(u32 c, u32 s, u32 r) { + ltq_sys1_w32((ltq_sys1_r32(r) & ~c) | s, r); +} + +/* gpio_request wrapper to help configure the pin */ +extern int ltq_gpio_request(unsigned int pin, unsigned int mux, + unsigned int dir, const char *name); +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); + +/* to keep the irq code generic we need to define these to 0 as falcon + has no EIU/EBU */ +#define LTQ_EIU_BASE_ADDR 0 +#define LTQ_EBU_PCC_ISTAT 0 + +#define ltq_is_ar9() 0 +#define ltq_is_vr9() 0 + +#endif /* CONFIG_SOC_FALCON */ +#endif /* _LTQ_XWAY_H__ */ diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index daaa3f7..1a09f29 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -26,6 +26,7 @@ extern unsigned int ltq_get_soc_type(void); /* clock speeds */ #define CLOCK_60M 60000000 #define CLOCK_83M 83333333 +#define CLOCK_100M 100000000 #define CLOCK_111M 111111111 #define CLOCK_133M 133333333 #define CLOCK_167M 166666667 diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 3fccf21..cb6b39f 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -16,8 +16,12 @@ config SOC_XWAY bool "XWAY" select SOC_TYPE_XWAY select HW_HAS_PCI + +config SOC_FALCON + bool "FALCON" endchoice source "arch/mips/lantiq/xway/Kconfig" +source "arch/mips/lantiq/falcon/Kconfig" endif diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index e5dae0e..7e9c69e 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devices.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ +obj-$(CONFIG_SOC_FALCON) += falcon/ diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform index f3dff05..b3ec498 100644 --- a/arch/mips/lantiq/Platform +++ b/arch/mips/lantiq/Platform @@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/ cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq load-$(CONFIG_LANTIQ) = 0xffffffff80002000 cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway +cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile new file mode 100644 index 0000000..e9c7455 --- /dev/null +++ b/arch/mips/lantiq/falcon/Makefile @@ -0,0 +1 @@ +obj-y := clk.o prom.o reset.o sysctrl.o devices.o diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c new file mode 100644 index 0000000..afe1b52 --- /dev/null +++ b/arch/mips/lantiq/falcon/clk.c @@ -0,0 +1,44 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include + +#include + +#include "devices.h" + +/* CPU0 Clock Control Register */ +#define LTQ_SYS1_CPU0CC 0x0040 +/* clock divider bit */ +#define LTQ_CPU0CC_CPUDIV 0x0001 + +unsigned int +ltq_get_io_region_clock(void) +{ + return CLOCK_200M; +} +EXPORT_SYMBOL(ltq_get_io_region_clock); + +unsigned int +ltq_get_cpu_hz(void) +{ + if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) + return CLOCK_200M; + else + return CLOCK_400M; +} +EXPORT_SYMBOL(ltq_get_cpu_hz); + +unsigned int +ltq_get_fpi_hz(void) +{ + return CLOCK_100M; +} +EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c new file mode 100644 index 0000000..c4606f2 --- /dev/null +++ b/arch/mips/lantiq/falcon/devices.c @@ -0,0 +1,87 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include + +#include + +#include "devices.h" + +/* nand flash */ +/* address lines used for NAND control signals */ +#define NAND_ADDR_ALE 0x10000 +#define NAND_ADDR_CLE 0x20000 +/* Ready/Busy Status */ +#define MODCON_STS 0x0002 +/* Ready/Busy Status Edge */ +#define MODCON_STSEDGE 0x0004 + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static int +falcon_nand_ready(struct mtd_info *mtd) +{ + u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON); + + return (((modcon & (MODCON_STS | MODCON_STSEDGE)) == + (MODCON_STS | MODCON_STSEDGE))); +} + +static void +falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE); + + if (ctrl & NAND_CLE) + nandaddr |= NAND_ADDR_CLE; + if (ctrl & NAND_ALE) + nandaddr |= NAND_ADDR_ALE; + + this->IO_ADDR_W = (void __iomem *) nandaddr; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static struct platform_nand_data falcon_flash_nand_data = { + .chip = { + .nr_chips = 1, + .chip_delay = 25, + .part_probe_types = part_probes, + }, + .ctrl = { + .cmd_ctrl = falcon_hwcontrol, + .dev_ready = falcon_nand_ready, + } +}; + +static struct resource ltq_nand_res = + MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX); + +static struct platform_device ltq_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = <q_nand_res, + .dev = { + .platform_data = &falcon_flash_nand_data, + }, +}; + +void __init +falcon_register_nand(void) +{ + platform_device_register(<q_flash_nand); +} diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h new file mode 100644 index 0000000..e802a7c --- /dev/null +++ b/arch/mips/lantiq/falcon/devices.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#ifndef _FALCON_DEVICES_H__ +#define _FALCON_DEVICES_H__ + +#include "../devices.h" + +extern void falcon_register_nand(void); + +#endif diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c new file mode 100644 index 0000000..b50d6f9 --- /dev/null +++ b/arch/mips/lantiq/falcon/prom.c @@ -0,0 +1,93 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include + +#include "devices.h" + +#include "../prom.h" + +#define SOC_FALCON "Falcon" +#define SOC_FALCON_D "Falcon-D" +#define SOC_FALCON_V "Falcon-V" +#define SOC_FALCON_M "Falcon-M" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFF000 +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 +#define SREV_SHIFT 22 +#define SREV_MASK 0x03C00000 +#define TYPE_SHIFT 26 +#define TYPE_MASK 0x3C000000 + +#define MUXC_SIF_RX_PIN 112 +#define MUXC_SIF_TX_PIN 113 + +/* this parameter allows us enable/disable asc1 via commandline */ +static int register_asc1; +static int __init +ltq_parse_asc1(char *p) +{ + register_asc1 = 1; + return 0; +} +__setup("use_asc1", ltq_parse_asc1); + +void __init +ltq_soc_setup(void) +{ + ltq_register_asc(0); + ltq_register_wdt(); + falcon_register_gpio(); + if (register_asc1) { + ltq_register_asc(1); + if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx")) + pr_err("failed to request asc1-rx"); + if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx")) + pr_err("failed to request asc1-tx"); + ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT); + } +} + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + u32 type; + i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; + i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT); + sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), + i->rev & 0x7, (i->srev & 0x3) + 1); + + switch (i->partnum) { + case SOC_ID_FALCON: + type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT; + switch (type) { + case 0: + i->name = SOC_FALCON_D; + break; + case 1: + i->name = SOC_FALCON_V; + break; + case 2: + i->name = SOC_FALCON_M; + break; + default: + i->name = SOC_FALCON; + break; + } + i->type = SOC_TYPE_FALCON; + break; + + default: + unreachable(); + break; + } +} diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c new file mode 100644 index 0000000..aa7a770 --- /dev/null +++ b/arch/mips/lantiq/falcon/reset.c @@ -0,0 +1,91 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include + +#include + +/* CPU0 Reset Source Register */ +#define LTQ_SYS1_CPU0RS 0x0040 +/* reset cause mask */ +#define LTQ_CPU0RS_MASK 0x0003 + +int +ltq_reset_cause(void) +{ + return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK; +} +EXPORT_SYMBOL_GPL(ltq_reset_cause); + +#define BOOT_REG_BASE (KSEG1 | 0x1F200000) +#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) +#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) +#define BOOT_PW1 0x4C545100 +#define BOOT_PW2 0x0051544C + +#define WDT_REG_BASE (KSEG1 | 0x1F8803F0) +#define WDT_PW1 0x00BE0000 +#define WDT_PW2 0x00DC0000 + +static void +ltq_machine_restart(char *command) +{ + pr_notice("System restart\n"); + local_irq_disable(); + + /* reboot magic */ + ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ + ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ + ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ + + /* watchdog magic */ + ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); + ltq_w32(WDT_PW2 | + (0x3 << 26) | /* PWL */ + (0x2 << 24) | /* CLKDIV */ + (0x1 << 31) | /* enable */ + (1), /* reload */ + (void *)WDT_REG_BASE); + /* + * Dont call unreachable(); here as we need to wait for the watchdog + * to trigger. + */ + do {} while(1); +} + +static void +ltq_machine_halt(void) +{ + pr_notice("System halted.\n"); + local_irq_disable(); + unreachable(); +} + +static void +ltq_machine_power_off(void) +{ + pr_notice("Please turn off the power now.\n"); + local_irq_disable(); + unreachable(); +} + +static int __init +mips_reboot_setup(void) +{ + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c new file mode 100644 index 0000000..905a142 --- /dev/null +++ b/arch/mips/lantiq/falcon/sysctrl.c @@ -0,0 +1,183 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include + +#include + +#include "devices.h" + +/* infrastructure control register */ +#define SYS1_INFRAC 0x00bc +/* Configuration fuses for drivers and pll */ +#define STATUS_CONFIG 0x0040 + +/* GPE frequency selection */ +#define GPPC_OFFSET 24 +#define GPEFREQ_MASK 0x00000C0 +#define GPEFREQ_OFFSET 10 +/* Clock status register */ +#define LTQ_SYSCTL_CLKS 0x0000 +/* Clock enable register */ +#define LTQ_SYSCTL_CLKEN 0x0004 +/* Clock clear register */ +#define LTQ_SYSCTL_CLKCLR 0x0008 +/* Activation Status Register */ +#define LTQ_SYSCTL_ACTS 0x0020 +/* Activation Register */ +#define LTQ_SYSCTL_ACT 0x0024 +/* Deactivation Register */ +#define LTQ_SYSCTL_DEACT 0x0028 +/* reboot Register */ +#define LTQ_SYSCTL_RBT 0x002c + +static struct resource ltq_sysctl_res[] = { + MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), + MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE), + MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE), +}; + +static struct resource ltq_status_res = + MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE); +static struct resource ltq_ebu_res = + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + +static void __iomem *ltq_sysctl[3]; +static void __iomem *ltq_status_membase; +void __iomem *ltq_sys1_membase; +void __iomem *ltq_ebu_membase; + +#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y)) +#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x)) +#define ltq_reg_w32_mask(m, clear, set, reg) \ + ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg) + +#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y)) +#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) + +static inline void +ltq_sysctl_wait(int module, unsigned int mask, + unsigned int test, unsigned int reg) +{ + int err = 1000000; + + do {} while (--err && ((ltq_reg_r32(module, reg) + & mask) != test)); + if (!err) + pr_err("module de/activation failed %d %08X %08X\n", + module, mask, test); +} + +void +ltq_sysctl_activate(int module, unsigned int mask) +{ + if (module > SYSCTL_SYSGPE) + return; + + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); +} +EXPORT_SYMBOL(ltq_sysctl_activate); + +void +ltq_sysctl_deactivate(int module, unsigned int mask) +{ + if (module > SYSCTL_SYSGPE) + return; + + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); + ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT); + ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS); +} +EXPORT_SYMBOL(ltq_sysctl_deactivate); + +void +ltq_sysctl_clken(int module, unsigned int mask) +{ + if (module > SYSCTL_SYSGPE) + return; + + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS); +} +EXPORT_SYMBOL(ltq_sysctl_clken); + +void +ltq_sysctl_clkdis(int module, unsigned int mask) +{ + if (module > SYSCTL_SYSGPE) + return; + + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); + ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS); +} +EXPORT_SYMBOL(ltq_sysctl_clkdis); + +void +ltq_sysctl_reboot(int module, unsigned int mask) +{ + unsigned int act; + + if (module > SYSCTL_SYSGPE) + return; + + act = ltq_reg_r32(module, LTQ_SYSCTL_ACT); + if ((~act & mask) != 0) + ltq_sysctl_activate(module, ~act & mask); + ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT); + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); +} +EXPORT_SYMBOL(ltq_sysctl_reboot); + +/* enable the ONU core */ +static void +ltq_gpe_enable(void) +{ + unsigned int freq; + unsigned int status; + + /* if if the clock is already enabled */ + status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC); + if (status & (1 << (GPPC_OFFSET + 1))) + return; + + if (ltq_status_r32(STATUS_CONFIG) == 0) + freq = 1; /* use 625MHz on unfused chip */ + else + freq = (ltq_status_r32(STATUS_CONFIG) & + GPEFREQ_MASK) >> + GPEFREQ_OFFSET; + + /* apply new frequency */ + ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), + freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); + udelay(1); + + /* enable new frequency */ + ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); + udelay(1); +} + +void __init +ltq_soc_init(void) +{ + int i; + + for (i = 0; i < 3; i++) + ltq_sysctl[i] = ltq_remap_resource(<q_sysctl_res[i]); + + ltq_sys1_membase = ltq_sysctl[0]; + ltq_status_membase = ltq_remap_resource(<q_status_res); + ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); + + ltq_gpe_enable(); +} -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:46:36 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47516 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904056Ab2AKUos (ORCPT ); Wed, 11 Jan 2012 21:44:48 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH RESEND 05/17] MIPS: lantiq: add support for FALC-ON GPIOs Date: Wed, 11 Jan 2012 21:44:22 +0100 Message-Id: <1326314674-9899-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32219 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14467 Lines: 496 FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds the new driver. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- arch/mips/lantiq/falcon/Makefile | 2 +- arch/mips/lantiq/falcon/devices.c | 41 ++++ arch/mips/lantiq/falcon/devices.h | 2 + arch/mips/lantiq/falcon/gpio.c | 399 +++++++++++++++++++++++++++++++++++++ 4 files changed, 443 insertions(+), 1 deletions(-) create mode 100644 arch/mips/lantiq/falcon/gpio.c diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile index e9c7455..de72209 100644 --- a/arch/mips/lantiq/falcon/Makefile +++ b/arch/mips/lantiq/falcon/Makefile @@ -1 +1 @@ -obj-y := clk.o prom.o reset.o sysctrl.o devices.o +obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c index c4606f2..4f47b44 100644 --- a/arch/mips/lantiq/falcon/devices.c +++ b/arch/mips/lantiq/falcon/devices.c @@ -9,6 +9,7 @@ #include #include +#include #include @@ -85,3 +86,43 @@ falcon_register_nand(void) { platform_device_register(<q_flash_nand); } + +/* gpio */ +#define DECLARE_GPIO_RES(port) \ +static struct resource falcon_gpio ## port ## _res[] = { \ + MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \ + LTQ_GPIO ## port ## _SIZE), \ + MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \ + LTQ_PADCTRL ## port ## _SIZE), \ + IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \ +} +DECLARE_GPIO_RES(0); +DECLARE_GPIO_RES(1); +DECLARE_GPIO_RES(2); +DECLARE_GPIO_RES(3); +DECLARE_GPIO_RES(4); + +void __init +falcon_register_gpio(void) +{ + platform_device_register_simple("falcon_gpio", 0, + falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res)); + platform_device_register_simple("falcon_gpio", 1, + falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); + platform_device_register_simple("falcon_gpio", 2, + falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); + ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); + ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 | + ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2); +} + +void __init +falcon_register_gpio_extra(void) +{ + platform_device_register_simple("falcon_gpio", 3, + falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); + platform_device_register_simple("falcon_gpio", 4, + falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); + ltq_sysctl_activate(SYSCTL_SYS1, + ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4); +} diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h index e802a7c..18be8b6 100644 --- a/arch/mips/lantiq/falcon/devices.h +++ b/arch/mips/lantiq/falcon/devices.h @@ -14,5 +14,7 @@ #include "../devices.h" extern void falcon_register_nand(void); +extern void falcon_register_gpio(void); +extern void falcon_register_gpio_extra(void); #endif diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c new file mode 100644 index 0000000..28f8639 --- /dev/null +++ b/arch/mips/lantiq/falcon/gpio.c @@ -0,0 +1,399 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include + +#include + +/* Multiplexer Control Register */ +#define LTQ_PADC_MUX(x) (x * 0x4) +/* Pad Control Availability Register */ +#define LTQ_PADC_AVAIL 0x000000F0 + +/* Data Output Register */ +#define LTQ_GPIO_OUT 0x00000000 +/* Data Input Register */ +#define LTQ_GPIO_IN 0x00000004 +/* Direction Register */ +#define LTQ_GPIO_DIR 0x00000008 +/* External Interrupt Control Register 0 */ +#define LTQ_GPIO_EXINTCR0 0x00000018 +/* External Interrupt Control Register 1 */ +#define LTQ_GPIO_EXINTCR1 0x0000001C +/* IRN Capture Register */ +#define LTQ_GPIO_IRNCR 0x00000020 +/* IRN Interrupt Configuration Register */ +#define LTQ_GPIO_IRNCFG 0x0000002C +/* IRN Interrupt Enable Set Register */ +#define LTQ_GPIO_IRNRNSET 0x00000030 +/* IRN Interrupt Enable Clear Register */ +#define LTQ_GPIO_IRNENCLR 0x00000034 +/* Output Set Register */ +#define LTQ_GPIO_OUTSET 0x00000040 +/* Output Cler Register */ +#define LTQ_GPIO_OUTCLR 0x00000044 +/* Direction Clear Register */ +#define LTQ_GPIO_DIRSET 0x00000048 +/* Direction Set Register */ +#define LTQ_GPIO_DIRCLR 0x0000004C + +/* turn a gpio_chip into a falcon_gpio_port */ +#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip) +/* turn a irq_data into a falcon_gpio_port */ +#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq)) + +#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg) +#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg) +#define ltq_pad_w32_mask(c, clear, set, reg) \ + ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg) + +#define ltq_port_r32(p, reg) ltq_r32(p->port + reg) +#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg) +#define ltq_port_w32_mask(p, clear, set, reg) \ + ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg) + +#define MAX_PORTS 5 +#define PINS_PER_PORT 32 + +struct falcon_gpio_port { + struct gpio_chip gpio_chip; + void __iomem *pad; + void __iomem *port; + unsigned int irq_base; + unsigned int chained_irq; +}; + +static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; + +int gpio_to_irq(unsigned int gpio) +{ + return __gpio_to_irq(gpio); +} +EXPORT_SYMBOL(gpio_to_irq); + +int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) +{ + int port = pin / 100; + int offset = pin % 100; + struct falcon_gpio_port *gpio_port; + + if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS)) + return -EINVAL; + + gpio_port = <q_gpio_port[port]; + ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset)); + + return 0; +} +EXPORT_SYMBOL(ltq_gpio_mux_set); + +int ltq_gpio_request(unsigned int pin, unsigned int mux, + unsigned int dir, const char *name) +{ + int port = pin / 100; + int offset = pin % 100; + + if (offset >= PINS_PER_PORT || port >= MAX_PORTS) + return -EINVAL; + + if (gpio_request(pin, name)) { + pr_err("failed to setup lantiq gpio: %s\n", name); + return -EBUSY; + } + + if (dir) + gpio_direction_output(pin, 1); + else + gpio_direction_input(pin); + + return ltq_gpio_mux_set(pin, mux); +} +EXPORT_SYMBOL(ltq_gpio_request); + +static int +falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR); + + return 0; +} + +static void +falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + if (value) + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET); + else + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR); +} + +static int +falcon_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + falcon_gpio_set(chip, offset, value); + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET); + + return 0; +} + +static int +falcon_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1) + return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1; + else + return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1; +} + +static int +falcon_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { + if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) + return -EBUSY; + /* switch on gpio function */ + ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset)); + return 0; + } + + return -ENODEV; +} + +static void +falcon_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { + if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) + return; + /* switch off gpio function */ + ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset)); + } +} + +static int +falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return ctop(chip)->irq_base + offset; +} + +static void +falcon_gpio_disable_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); +} + +static void +falcon_gpio_enable_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1) + /* switch on gpio function */ + ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset)); + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET); +} + +static void +falcon_gpio_ack_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); +} + +static void +falcon_gpio_mask_and_ack_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); +} + +static struct irq_chip falcon_gpio_irq_chip; +static int +falcon_gpio_irq_type(struct irq_data *d, unsigned int type) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + unsigned int mask = 1 << offset; + + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) + return 0; + + if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) { + /* level triggered */ + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG); + irq_set_chip_and_handler_name(d->irq, + &falcon_gpio_irq_chip, handle_level_irq, "mux"); + } else { + /* edge triggered */ + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG); + irq_set_chip_and_handler_name(d->irq, + &falcon_gpio_irq_chip, handle_simple_irq, "mux"); + } + + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1); + } else { + if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0) + /* positive logic: rising edge, high level */ + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); + else + /* negative logic: falling edge, low level */ + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0); + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1); + } + + return gpio_direction_input(itop(d)->gpio_chip.base + offset); +} + +static void +falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc); + unsigned long irncr; + int offset; + + /* acknowledge interrupt */ + irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR); + ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR); + + desc->irq_data.chip->irq_ack(&desc->irq_data); + + for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio) + generic_handle_irq(gpio_port->irq_base + offset); +} + +static struct irq_chip falcon_gpio_irq_chip = { + .name = "gpio_irq_mux", + .irq_mask = falcon_gpio_disable_irq, + .irq_unmask = falcon_gpio_enable_irq, + .irq_ack = falcon_gpio_ack_irq, + .irq_mask_ack = falcon_gpio_mask_and_ack_irq, + .irq_set_type = falcon_gpio_irq_type, +}; + +static struct irqaction gpio_cascade = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "gpio_cascade", +}; + +static int +falcon_gpio_probe(struct platform_device *pdev) +{ + struct falcon_gpio_port *gpio_port; + int ret, i; + struct resource *gpiores, *padres; + int irq; + + if (pdev->id >= MAX_PORTS) + return -ENODEV; + + gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + padres = platform_get_resource(pdev, IORESOURCE_MEM, 1); + irq = platform_get_irq(pdev, 0); + if (!gpiores || !padres) + return -ENODEV; + + gpio_port = <q_gpio_port[pdev->id]; + gpio_port->gpio_chip.label = "falcon-gpio"; + gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input; + gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output; + gpio_port->gpio_chip.get = falcon_gpio_get; + gpio_port->gpio_chip.set = falcon_gpio_set; + gpio_port->gpio_chip.request = falcon_gpio_request; + gpio_port->gpio_chip.free = falcon_gpio_free; + gpio_port->gpio_chip.base = 100 * pdev->id; + gpio_port->gpio_chip.ngpio = 32; + gpio_port->gpio_chip.dev = &pdev->dev; + + gpio_port->port = ltq_remap_resource(gpiores); + gpio_port->pad = ltq_remap_resource(padres); + + if (!gpio_port->port || !gpio_port->pad) { + dev_err(&pdev->dev, "Could not map io ranges\n"); + ret = -ENOMEM; + goto err; + } + + if (irq > 0) { + /* irq_chip support */ + gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; + gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id); + + for (i = 0; i < 32; i++) { + irq_set_chip_and_handler_name(gpio_port->irq_base + i, + &falcon_gpio_irq_chip, handle_simple_irq, + "mux"); + irq_set_chip_data(gpio_port->irq_base + i, gpio_port); + /* set to negative logic (falling edge, low level) */ + ltq_port_w32_mask(gpio_port, 0, 1 << i, + LTQ_GPIO_EXINTCR0); + } + + gpio_port->chained_irq = irq; + setup_irq(irq, &gpio_cascade); + irq_set_handler_data(irq, gpio_port); + irq_set_chained_handler(irq, falcon_gpio_irq_handler); + } + + ret = gpiochip_add(&gpio_port->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", + pdev->id, ret); + goto err; + } + platform_set_drvdata(pdev, gpio_port); + return ret; + +err: + dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret); + if (gpiores) + release_resource(gpiores); + if (padres) + release_resource(padres); + + if (gpio_port->port) + iounmap(gpio_port->port); + if (gpio_port->pad) + iounmap(gpio_port->pad); + return ret; +} + +static struct platform_driver falcon_gpio_driver = { + .probe = falcon_gpio_probe, + .driver = { + .name = "falcon_gpio", + .owner = THIS_MODULE, + }, +}; + +int __init +falcon_gpio_init(void) +{ + int ret; + + pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n"); + ret = platform_driver_register(&falcon_gpio_driver); + if (ret) + pr_err("falcon_gpio: Error registering platform driver!"); + return ret; +} + +postcore_initcall(falcon_gpio_init); -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:46:58 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47520 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904057Ab2AKUos (ORCPT ); Wed, 11 Jan 2012 21:44:48 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH RESEND 06/17] MIPS: lantiq: add support for the EASY98000 evaluation board Date: Wed, 11 Jan 2012 21:44:23 +0100 Message-Id: <1326314674-9899-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32220 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4693 Lines: 172 This patch adds the machine code for the EASY9800 evaluation board. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- arch/mips/lantiq/falcon/Kconfig | 11 +++ arch/mips/lantiq/falcon/Makefile | 1 + arch/mips/lantiq/falcon/mach-easy98000.c | 110 ++++++++++++++++++++++++++++++ arch/mips/lantiq/machtypes.h | 5 ++ 4 files changed, 127 insertions(+), 0 deletions(-) create mode 100644 arch/mips/lantiq/falcon/Kconfig create mode 100644 arch/mips/lantiq/falcon/mach-easy98000.c diff --git a/arch/mips/lantiq/falcon/Kconfig b/arch/mips/lantiq/falcon/Kconfig new file mode 100644 index 0000000..03e999d --- /dev/null +++ b/arch/mips/lantiq/falcon/Kconfig @@ -0,0 +1,11 @@ +if SOC_FALCON + +menu "MIPS Machine" + +config LANTIQ_MACH_EASY98000 + bool "Easy98000" + default y + +endmenu + +endif diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile index de72209..56b22eb 100644 --- a/arch/mips/lantiq/falcon/Makefile +++ b/arch/mips/lantiq/falcon/Makefile @@ -1 +1,2 @@ obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o +obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o diff --git a/arch/mips/lantiq/falcon/mach-easy98000.c b/arch/mips/lantiq/falcon/mach-easy98000.c new file mode 100644 index 0000000..361b8f0 --- /dev/null +++ b/arch/mips/lantiq/falcon/mach-easy98000.c @@ -0,0 +1,110 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include + +#include "../machtypes.h" + +#include "devices.h" + +static struct mtd_partition easy98000_nor_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x40000, + }, + { + .name = "uboot_env", + .offset = 0x40000, + .size = 0x40000, /* 2 sectors for redundant env. */ + }, + { + .name = "linux", + .offset = 0x80000, + .size = 0xF80000, /* map only 16 MiB */ + }, +}; + +struct physmap_flash_data easy98000_nor_flash_data = { + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), + .parts = easy98000_nor_partitions, +}; + +/* setup gpio based spi bus/device for access to the eeprom on the board */ +#define SPI_GPIO_MRST 102 +#define SPI_GPIO_MTSR 103 +#define SPI_GPIO_CLK 104 +#define SPI_GPIO_CS0 105 +#define SPI_GPIO_CS1 106 +#define SPI_GPIO_BUS_NUM 1 + +static struct spi_gpio_platform_data easy98000_spi_gpio_data = { + .sck = SPI_GPIO_CLK, + .mosi = SPI_GPIO_MTSR, + .miso = SPI_GPIO_MRST, + .num_chipselect = 2, +}; + +static struct platform_device easy98000_spi_gpio_device = { + .name = "spi_gpio", + .id = SPI_GPIO_BUS_NUM, + .dev.platform_data = &easy98000_spi_gpio_data, +}; + +static struct spi_eeprom at25160n = { + .byte_len = 16 * 1024 / 8, + .name = "at25160n", + .page_size = 32, + .flags = EE_ADDR2, +}; + +static struct spi_board_info easy98000_spi_gpio_devices __initdata = { + .modalias = "at25", + .bus_num = SPI_GPIO_BUS_NUM, + .max_speed_hz = 1000 * 1000, + .mode = SPI_MODE_3, + .chip_select = 1, + .controller_data = (void *) SPI_GPIO_CS1, + .platform_data = &at25160n, +}; + +static void __init +easy98000_init_common(void) +{ + spi_register_board_info(&easy98000_spi_gpio_devices, 1); + platform_device_register(&easy98000_spi_gpio_device); +} + +static void __init +easy98000_init(void) +{ + easy98000_init_common(); + ltq_register_nor(&easy98000_nor_flash_data); +} + +static void __init +easy98000nand_init(void) +{ + easy98000_init_common(); + falcon_register_nand(); +} + +MIPS_MACHINE(LANTIQ_MACH_EASY98000, + "EASY98000", + "EASY98000 Eval Board", + easy98000_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND, + "EASY98000NAND", + "EASY98000 Eval Board (NAND Flash)", + easy98000nand_init); diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h index 7e01b8c..dfc6af7 100644 --- a/arch/mips/lantiq/machtypes.h +++ b/arch/mips/lantiq/machtypes.h @@ -15,6 +15,11 @@ enum lantiq_mach_type { LTQ_MACH_GENERIC = 0, LTQ_MACH_EASY50712, /* Danube evaluation board */ LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ + + /* FALCON */ + LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ + LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ + LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ }; #endif -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:47:24 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47522 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904058Ab2AKUot (ORCPT ); Wed, 11 Jan 2012 21:44:49 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH RESEND 07/17] MIPS: lantiq: fix early printk Date: Wed, 11 Jan 2012 21:44:24 +0100 Message-Id: <1326314674-9899-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32221 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2158 Lines: 63 The code was using a 32bit write operations in the early_printk code. This resulted in 3 zero bytes also being written to the serial port. This patch changes the memory access to 8bit. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 6 ++++++ arch/mips/lantiq/early_printk.c | 14 ++++++++------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index a6521ec..c8024e3 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -34,6 +34,12 @@ #define LTQ_ASC1_BASE_ADDR 0x1E100C00 #define LTQ_ASC_SIZE 0x400 +/* + * during early_printk no ioremap is possible + * lets use KSEG1 instead + */ +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) + /* RCU - reset control unit */ #define LTQ_RCU_BASE_ADDR 0x1F203000 #define LTQ_RCU_SIZE 0x1000 diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c index 972e05f..5089075 100644 --- a/arch/mips/lantiq/early_printk.c +++ b/arch/mips/lantiq/early_printk.c @@ -12,11 +12,13 @@ #include #include -/* no ioremap possible at this early stage, lets use KSEG1 instead */ -#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) #define ASC_BUF 1024 -#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) -#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) +#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048)) +#ifdef __BIG_ENDIAN +#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3)) +#else +#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020)) +#endif #define TXMASK 0x3F00 #define TXOFFSET 8 @@ -27,7 +29,7 @@ void prom_putchar(char c) local_irq_save(flags); do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); if (c == '\n') - ltq_w32('\r', LTQ_ASC_TBUF); - ltq_w32(c, LTQ_ASC_TBUF); + ltq_w8('\r', LTQ_ASC_TBUF); + ltq_w8(c, LTQ_ASC_TBUF); local_irq_restore(flags); } -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:47:51 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47525 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904059Ab2AKUou (ORCPT ); Wed, 11 Jan 2012 21:44:50 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH RESEND 08/17] MIPS: lantiq: fix cmdline parsing Date: Wed, 11 Jan 2012 21:44:25 +0100 Message-Id: <1326314674-9899-8-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32222 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 924 Lines: 31 The code tested if the KSEG1 mapped address of argv was != 0. We need to use CPHYSADDR instead to make the conditional actually work. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- arch/mips/lantiq/prom.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 528e205..ee63a33 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -49,10 +49,12 @@ static void __init prom_init_cmdline(void) char **argv = (char **) KSEG1ADDR(fw_arg1); int i; + arcs_cmdline[0] = '\0'; + for (i = 0; i < argc; i++) { - char *p = (char *) KSEG1ADDR(argv[i]); + char *p = (char *) KSEG1ADDR(argv[i]); - if (p && *p) { + if (CPHYSADDR(p) && *p) { strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); } -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:48:15 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47529 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904060Ab2AKUou (ORCPT ); Wed, 11 Jan 2012 21:44:50 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Matti Laakso Subject: [PATCH RESEND 09/17] MIPS: lantiq: fix STP gpio groups Date: Wed, 11 Jan 2012 21:44:26 +0100 Message-Id: <1326314674-9899-9-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32223 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1245 Lines: 37 The STP engine has 3 groups of 8 pins. Only the first was activated by default. This patch activates the 2 missing groups. Signed-off-by: Matti Laakso Signed-off-by: John Crispin --- arch/mips/lantiq/xway/gpio_stp.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index 2c78660..cb6f170 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -35,6 +35,8 @@ #define LTQ_STP_ADSL_SRC (3 << 24) #define LTQ_STP_GROUP0 (1 << 0) +#define LTQ_STP_GROUP1 (1 << 1) +#define LTQ_STP_GROUP2 (1 << 2) #define LTQ_STP_RISING 0 #define LTQ_STP_FALLING (1 << 26) @@ -93,8 +95,9 @@ static int ltq_stp_hw_init(void) /* rising or falling edge */ ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0); - /* per default stp 15-0 are set */ - ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1); + /* enable all three led groups */ + ltq_stp_w32_mask(0, LTQ_STP_GROUP0 | LTQ_STP_GROUP1 | LTQ_STP_GROUP2, + LTQ_STP_CON1); /* stp are update periodically by the FPI bus */ ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1); -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:44:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:48:37 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47532 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904061Ab2AKUov (ORCPT ); Wed, 11 Jan 2012 21:44:51 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Matti Laakso Subject: [PATCH RESEND 10/17] MIPS: lantiq: fix pull gpio up resistors usage Date: Wed, 11 Jan 2012 21:44:27 +0100 Message-Id: <1326314674-9899-10-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32224 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1479 Lines: 43 The register that enables a gpios internal pullups was not used. This patch makes sure the pullups are activated correctly. Signed-off-by: Matti Laakso Signed-off-by: John Crispin --- arch/mips/lantiq/xway/gpio.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c index f204f6c..14ff7c7 100644 --- a/arch/mips/lantiq/xway/gpio.c +++ b/arch/mips/lantiq/xway/gpio.c @@ -21,6 +21,8 @@ #define LTQ_GPIO_ALTSEL0 0x0C #define LTQ_GPIO_ALTSEL1 0x10 #define LTQ_GPIO_OD 0x14 +#define LTQ_GPIO_PUDSEL 0x1C +#define LTQ_GPIO_PUDEN 0x20 #define PINS_PER_PORT 16 #define MAX_PORTS 3 @@ -106,6 +108,8 @@ static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); return 0; } @@ -117,6 +121,8 @@ static int ltq_gpio_direction_output(struct gpio_chip *chip, ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); ltq_gpio_set(chip, offset, value); return 0; -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:49:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:49:09 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47691 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904061Ab2AKUtF (ORCPT ); Wed, 11 Jan 2012 21:49:05 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH RESEND 15/17] NET: MIPS: lantiq: return value of request_irq was not handled gracefully Date: Wed, 11 Jan 2012 21:44:32 +0100 Message-Id: <1326314674-9899-15-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32225 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2043 Lines: 65 The return values of request_irq() were not checked leading to the following error message. drivers/net/ethernet/lantiq_etop.c: In function 'ltq_etop_hw_init': drivers/net/ethernet/lantiq_etop.c:368:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result drivers/net/ethernet/lantiq_etop.c:377:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result Signed-off-by: John Crispin Acked-by: David S. Miller --- drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 9fd6779..659c868 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -312,6 +312,7 @@ ltq_etop_hw_init(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); unsigned int mii_mode = priv->pldata->mii_mode; + int err = 0; int i; ltq_pmu_enable(PMU_PPE); @@ -356,7 +357,7 @@ ltq_etop_hw_init(struct net_device *dev) ltq_dma_init_port(DMA_PORT_ETOP); - for (i = 0; i < MAX_DMA_CHAN; i++) { + for (i = 0; i < MAX_DMA_CHAN && !err; i++) { int irq = LTQ_DMA_ETOP + i; struct ltq_etop_chan *ch = &priv->ch[i]; @@ -364,21 +365,22 @@ ltq_etop_hw_init(struct net_device *dev) if (IS_TX(i)) { ltq_dma_alloc_tx(&ch->dma); - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, + err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); } else if (IS_RX(i)) { ltq_dma_alloc_rx(&ch->dma); for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; ch->dma.desc++) if (ltq_etop_alloc_skb(ch)) - return -ENOMEM; + err = -ENOMEM; ch->dma.desc = 0; - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, + err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); } - ch->dma.irq = irq; + if (!err) + ch->dma.irq = irq; } - return 0; + return err; } static void -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:49:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:49:34 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47693 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904065Ab2AKUtH (ORCPT ); Wed, 11 Jan 2012 21:49:07 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH RESEND 13/17] NET: MIPS: lantiq: make etop ethernet work on ase/ar9 Date: Wed, 11 Jan 2012 21:44:30 +0100 Message-Id: <1326314674-9899-13-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32226 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 13302 Lines: 423 Extend the driver to handle the different DMA channel layout for AR9 and Amazon-SE SoCs. The patch also adds support for the integrated PHY found on Amazon-SE and the gigabit switch found inside the AR9. Signed-off-by: John Crispin Acked-by: David S. Miller --- .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 22 +--- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 10 ++ arch/mips/lantiq/xway/devices.c | 11 +- arch/mips/lantiq/xway/mach-easy50601.c | 5 + drivers/net/ethernet/lantiq_etop.c | 171 ++++++++++++++++++-- 5 files changed, 179 insertions(+), 40 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h index b4465a8..2a8d5ad 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -38,26 +38,8 @@ #define MIPS_CPU_TIMER_IRQ 7 -#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) -#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) -#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) -#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) -#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) -#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) -#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) -#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) -#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) -#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) -#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) -#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) -#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) -#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) -#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) -#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) -#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) -#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) -#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) -#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) +#define LTQ_DMA_ETOP ((ltq_is_ase()) ? \ + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) #define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index c8024e3..763e163 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -82,6 +82,7 @@ #define LTQ_PMU_SIZE 0x1000 #define PMU_DMA 0x0020 +#define PMU_EPHY 0x0080 #define PMU_USB 0x8041 #define PMU_LED 0x0800 #define PMU_GPT 0x1000 @@ -93,6 +94,10 @@ #define LTQ_ETOP_BASE_ADDR 0x1E180000 #define LTQ_ETOP_SIZE 0x40000 +/* GBIT - gigabit switch */ +#define LTQ_GBIT_BASE_ADDR 0x1E108000 +#define LTQ_GBIT_SIZE 0x200 + /* DMA */ #define LTQ_DMA_BASE_ADDR 0x1E104100 #define LTQ_DMA_SIZE 0x800 @@ -163,6 +168,11 @@ extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); extern void ltq_cgu_enable(unsigned int clk); +static inline int ltq_is_ase(void) +{ + return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE); +} + static inline int ltq_is_ar9(void) { return (ltq_get_soc_type() == SOC_TYPE_AR9); diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c index f97e565..eab4644d 100644 --- a/arch/mips/lantiq/xway/devices.c +++ b/arch/mips/lantiq/xway/devices.c @@ -74,18 +74,23 @@ void __init ltq_register_ase_asc(void) } /* ethernet */ -static struct resource ltq_etop_resources = - MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE); +static struct resource ltq_etop_resources[] = { + MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE), + MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE), +}; static struct platform_device ltq_etop = { .name = "ltq_etop", - .resource = <q_etop_resources, + .resource = ltq_etop_resources, .num_resources = 1, }; void __init ltq_register_etop(struct ltq_eth_data *eth) { + /* only register the gphy on socs that have one */ + if (ltq_is_ar9() | ltq_is_vr9()) + ltq_etop.num_resources = 2; if (eth) { ltq_etop.dev.platform_data = eth; platform_device_register(<q_etop); diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c index d5aaf63..16d65e0 100644 --- a/arch/mips/lantiq/xway/mach-easy50601.c +++ b/arch/mips/lantiq/xway/mach-easy50601.c @@ -46,9 +46,14 @@ static struct physmap_flash_data easy50601_flash_data = { .parts = easy50601_partitions, }; +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = -1, /* use EPHY */ +}; + static void __init easy50601_init(void) { ltq_register_nor(&easy50601_flash_data); + ltq_register_etop(<q_eth_data); } MIPS_MACHINE(LTQ_MACH_EASY50601, diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 0b3567a..d3d4931 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -71,10 +71,43 @@ #define ETOP_MII_REVERSE 0xe #define ETOP_PLEN_UNDER 0x40 #define ETOP_CGEN 0x800 - -/* use 2 static channels for TX/RX */ +#define ETOP_CFG_MII0 0x01 + +#define LTQ_GBIT_MDIO_CTL 0xCC +#define LTQ_GBIT_MDIO_DATA 0xd0 +#define LTQ_GBIT_GCTL0 0x68 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c +#define LTQ_GBIT_P0_CTL 0x4 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8 + +#define PMAC_HD_CTL_AS (1 << 19) +#define PMAC_HD_CTL_RXSH (1 << 22) + +/* Switch Enable (0=disable, 1=enable) */ +#define GCTL0_SE 0x80000000 +/* Disable MDIO auto polling (0=disable, 1=enable) */ +#define PX_CTL_DMDIO 0x00400000 + +/* register information for the gbit's MDIO bus */ +#define MDIO_XR9_REQUEST 0x00008000 +#define MDIO_XR9_READ 0x00000800 +#define MDIO_XR9_WRITE 0x00000400 +#define MDIO_XR9_REG_MASK 0x1f +#define MDIO_XR9_ADDR_MASK 0x1f +#define MDIO_XR9_RD_MASK 0xffff +#define MDIO_XR9_REG_OFFSET 0 +#define MDIO_XR9_ADDR_OFFSET 5 +#define MDIO_XR9_WR_OFFSET 16 + +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ +#define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9()) + +/* use 2 static channels for TX/RX + depending on the SoC we need to use different DMA channels for ethernet */ #define LTQ_ETOP_TX_CHANNEL 1 -#define LTQ_ETOP_RX_CHANNEL 6 +#define LTQ_ETOP_RX_CHANNEL ((ltq_is_ase()) ? (5) : \ + ((ltq_has_gbit()) ? (0) : (6))) + #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) @@ -83,9 +116,15 @@ #define ltq_etop_w32_mask(x, y, z) \ ltq_w32_mask(x, y, ltq_etop_membase + (z)) +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) +#define ltq_gbit_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_gbit_membase + (z)) + #define DRV_VERSION "1.0" static void __iomem *ltq_etop_membase; +static void __iomem *ltq_gbit_membase; struct ltq_etop_chan { int idx; @@ -110,6 +149,9 @@ struct ltq_etop_priv { spinlock_t lock; }; +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, + int phy_reg, u16 phy_data); + static int ltq_etop_alloc_skb(struct ltq_etop_chan *ch) { @@ -211,7 +253,7 @@ static irqreturn_t ltq_etop_dma_irq(int irq, void *_priv) { struct ltq_etop_priv *priv = _priv; - int ch = irq - LTQ_DMA_CH0_INT; + int ch = irq - LTQ_DMA_ETOP; napi_schedule(&priv->ch[ch].napi); return IRQ_HANDLED; @@ -244,15 +286,43 @@ ltq_etop_hw_exit(struct net_device *dev) ltq_etop_free_channel(dev, &priv->ch[i]); } +static void +ltq_etop_gbit_init(void) +{ + ltq_pmu_enable(PMU_SWITCH); + + ltq_gpio_request(42, 2, 1, "MDIO"); + ltq_gpio_request(43, 2, 1, "MDC"); + + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); + /** Disable MDIO auto polling mode */ + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); + /* set 1522 packet size */ + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); + /* disable pmac & dmac headers */ + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, + LTQ_GBIT_PMAC_HD_CTL); + /* Due to traffic halt when burst length 8, + replace default IPG value with 0x3B */ + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); +} + static int ltq_etop_hw_init(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned int mii_mode = priv->pldata->mii_mode; int i; ltq_pmu_enable(PMU_PPE); - switch (priv->pldata->mii_mode) { + if (ltq_has_gbit()) { + ltq_etop_gbit_init(); + /* force the etops link to the gbit to MII */ + mii_mode = PHY_INTERFACE_MODE_MII; + } + + switch (mii_mode) { case PHY_INTERFACE_MODE_RMII: ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE, LTQ_ETOP_CFG); @@ -264,6 +334,18 @@ ltq_etop_hw_init(struct net_device *dev) break; default: + if (ltq_is_ase()) { + ltq_pmu_enable(PMU_EPHY); + /* disable external MII */ + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); + /* enable clock for internal PHY */ + ltq_cgu_enable(CGU_EPHY); + /* we need to write this magic to the internal phy to + make it work */ + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); + pr_info("Selected EPHY mode\n"); + break; + } netdev_err(dev, "unknown mii mode %d\n", priv->pldata->mii_mode); return -ENOTSUPP; @@ -275,7 +357,7 @@ ltq_etop_hw_init(struct net_device *dev) ltq_dma_init_port(DMA_PORT_ETOP); for (i = 0; i < MAX_DMA_CHAN; i++) { - int irq = LTQ_DMA_CH0_INT + i; + int irq = LTQ_DMA_ETOP + i; struct ltq_etop_chan *ch = &priv->ch[i]; ch->idx = ch->dma.nr = i; @@ -339,6 +421,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = { }; static int +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, + int phy_reg, u16 phy_data) +{ + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | + (phy_data << MDIO_XR9_WR_OFFSET) | + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); + + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) + ; + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) + ; + return 0; +} + +static int +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) +{ + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); + + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) + ; + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) + ; + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; + return val; +} + +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) { u32 val = MDIO_REQUEST | @@ -379,14 +494,11 @@ ltq_etop_mdio_probe(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); struct phy_device *phydev = NULL; - int phy_addr; - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { - if (priv->mii_bus->phy_map[phy_addr]) { - phydev = priv->mii_bus->phy_map[phy_addr]; - break; - } - } + if (ltq_is_ase()) + phydev = priv->mii_bus->phy_map[8]; + else + phydev = priv->mii_bus->phy_map[0]; if (!phydev) { netdev_err(dev, "no PHY found\n"); @@ -408,6 +520,9 @@ ltq_etop_mdio_probe(struct net_device *dev) | SUPPORTED_Autoneg | SUPPORTED_MII | SUPPORTED_TP); + if (ltq_has_gbit()) + phydev->supported &= SUPPORTED_1000baseT_Half + | SUPPORTED_1000baseT_Full; phydev->advertising = phydev->supported; priv->phydev = phydev; @@ -433,8 +548,13 @@ ltq_etop_mdio_init(struct net_device *dev) } priv->mii_bus->priv = dev; - priv->mii_bus->read = ltq_etop_mdio_rd; - priv->mii_bus->write = ltq_etop_mdio_wr; + if (ltq_has_gbit()) { + priv->mii_bus->read = ltq_etop_mdio_rd_xr9; + priv->mii_bus->write = ltq_etop_mdio_wr_xr9; + } else { + priv->mii_bus->read = ltq_etop_mdio_rd; + priv->mii_bus->write = ltq_etop_mdio_wr; + } priv->mii_bus->name = "ltq_mii"; snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); @@ -524,9 +644,9 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) struct ltq_etop_priv *priv = netdev_priv(dev); struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; - int len; unsigned long flags; u32 byte_offset; + int len; len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; @@ -700,7 +820,7 @@ ltq_etop_probe(struct platform_device *pdev) { struct net_device *dev; struct ltq_etop_priv *priv; - struct resource *res; + struct resource *res, *gbit_res; int err; int i; @@ -728,6 +848,23 @@ ltq_etop_probe(struct platform_device *pdev) goto err_out; } + if (ltq_has_gbit()) { + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!gbit_res) { + dev_err(&pdev->dev, "failed to get gbit resource\n"); + err = -ENOENT; + goto err_out; + } + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, + gbit_res->start, resource_size(gbit_res)); + if (!ltq_gbit_membase) { + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", + pdev->id); + err = -ENOMEM; + goto err_out; + } + } + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); strcpy(dev->name, "eth%d"); dev->netdev_ops = <q_eth_netdev_ops; -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:49:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:49:56 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47695 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904069Ab2AKUtH (ORCPT ); Wed, 11 Jan 2012 21:49:07 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH RESEND 12/17] MAINTAINERS: add entry for Lantiq related files Date: Wed, 11 Jan 2012 21:44:29 +0100 Message-Id: <1326314674-9899-12-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32227 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 844 Lines: 33 Adds new entry to MAINTAINERS file for Lantiq SoC related code. Signed-off-by: John Crispin --- MAINTAINERS | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4475602..caf9d00 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4362,6 +4362,18 @@ S: Supported F: Documentation/mips/ F: arch/mips/ +MIPS/LANTIQ +M: John Crispin +M: Thomas Langer +S: Maintained +F: arch/mips/lantiq/* +F: drivers/i2c/busses/i2c-falcon.c +F: drivers/mtd/maps/lantiq-flash.c +F: drivers/net/ethernet/lantiq_etop.c +F: drivers/spi/spi-falcon.c +F: drivers/tty/serial/lantiq.c +F: drivers/watchdog/lantiq_wdt.c + MISCELLANEOUS MCA-SUPPORT M: James Bottomley S: Maintained -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:49:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:50:21 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47697 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904071Ab2AKUtI (ORCPT ); Wed, 11 Jan 2012 21:49:08 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH RESEND 11/17] MIPS: lantiq: add default configs Date: Wed, 11 Jan 2012 21:44:28 +0100 Message-Id: <1326314674-9899-11-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32228 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7249 Lines: 281 This patch adds the default config for 3 Lantiq SoCs * Danube/AR9 (xway) * Amazon-SE * Falc-ON Signed-off-by: John Crispin --- arch/mips/configs/ase_defconfig | 80 ++++++++++++++++++++++++++++++++++ arch/mips/configs/falcon_defconfig | 83 ++++++++++++++++++++++++++++++++++++ arch/mips/configs/xway_defconfig | 81 +++++++++++++++++++++++++++++++++++ 3 files changed, 244 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/ase_defconfig create mode 100644 arch/mips/configs/falcon_defconfig create mode 100644 arch/mips/configs/xway_defconfig diff --git a/arch/mips/configs/ase_defconfig b/arch/mips/configs/ase_defconfig new file mode 100644 index 0000000..04a6aa5 --- /dev/null +++ b/arch/mips/configs/ase_defconfig @@ -0,0 +1,80 @@ +CONFIG_LANTIQ=y +CONFIG_SOC_AMAZON_SE=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_EXPERIMENTAL=y +CONFIG_DEFAULT_HOSTNAME="amazon_se" +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" +CONFIG_INITRAMFS_ROOT_UID=1000 +CONFIG_INITRAMFS_ROOT_GID=1000 +# CONFIG_RD_GZIP is not set +CONFIG_RD_LZMA=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_LANTIQ=y +CONFIG_MISC_DEVICES=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_LANTIQ_ETOP=y +CONFIG_PHYLIB=y +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_LANTIQ=y +# CONFIG_HW_RANDOM is not set +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_LANTIQ_WDT=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y diff --git a/arch/mips/configs/falcon_defconfig b/arch/mips/configs/falcon_defconfig new file mode 100644 index 0000000..ab8f8e2 --- /dev/null +++ b/arch/mips/configs/falcon_defconfig @@ -0,0 +1,83 @@ +CONFIG_LANTIQ=y +CONFIG_SOC_FALCON=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_EXPERIMENTAL=y +CONFIG_DEFAULT_HOSTNAME="falcon" +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" +CONFIG_INITRAMFS_ROOT_UID=1000 +CONFIG_INITRAMFS_ROOT_GID=1000 +CONFIG_RD_LZMA=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_LANTIQ=y +CONFIG_MTD_M25P80=y +CONFIG_MISC_DEVICES=y +CONFIG_EEPROM_AT24=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_PHYLIB=y +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_LANTIQ=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_FALCON=y +CONFIG_SPI=y +CONFIG_SPI_FALCON=y +CONFIG_GPIO_SYSFS=y +CONFIG_WATCHDOG=y +CONFIG_LANTIQ_WDT=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y diff --git a/arch/mips/configs/xway_defconfig b/arch/mips/configs/xway_defconfig new file mode 100644 index 0000000..461d58d --- /dev/null +++ b/arch/mips/configs/xway_defconfig @@ -0,0 +1,81 @@ +CONFIG_LANTIQ=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_EXPERIMENTAL=y +CONFIG_DEFAULT_HOSTNAME="danube" +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" +CONFIG_INITRAMFS_ROOT_UID=1000 +CONFIG_INITRAMFS_ROOT_GID=1000 +# CONFIG_RD_GZIP is not set +CONFIG_RD_LZMA=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_PCI=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_LANTIQ=y +CONFIG_MISC_DEVICES=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_LANTIQ_ETOP=y +CONFIG_PHYLIB=y +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_LANTIQ=y +# CONFIG_HW_RANDOM is not set +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_LANTIQ_WDT=y +# CONFIG_VGA_ARB is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:49:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:50:46 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47741 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904058Ab2AKUtY (ORCPT ); Wed, 11 Jan 2012 21:49:24 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH RESEND 14/17] NET: MIPS: lantiq: non existing phy was not handled gracefully Date: Wed, 11 Jan 2012 21:44:31 +0100 Message-Id: <1326314674-9899-14-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32229 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1845 Lines: 61 The code blindly assumed that that a PHY device was present causing a BadVA. In addition the driver should not fail to load incase no PHY was found. Instead we print the following line and continue with no attached PHY. etop: mdio probe failed Signed-off-by: John Crispin Acked-by: David S. Miller --- drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index d3d4931..9fd6779 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -612,7 +612,8 @@ ltq_etop_open(struct net_device *dev) ltq_dma_open(&ch->dma); napi_enable(&ch->napi); } - phy_start(priv->phydev); + if (priv->phydev) + phy_start(priv->phydev); netif_tx_start_all_queues(dev); return 0; } @@ -624,7 +625,8 @@ ltq_etop_stop(struct net_device *dev) int i; netif_tx_stop_all_queues(dev); - phy_stop(priv->phydev); + if (priv->phydev) + phy_stop(priv->phydev); for (i = 0; i < MAX_DMA_CHAN; i++) { struct ltq_etop_chan *ch = &priv->ch[i]; @@ -770,9 +772,10 @@ ltq_etop_init(struct net_device *dev) if (err) goto err_netdev; ltq_etop_set_multicast_list(dev); - err = ltq_etop_mdio_init(dev); - if (err) - goto err_netdev; + if (!ltq_etop_mdio_init(dev)) + dev->ethtool_ops = <q_etop_ethtool_ops; + else + pr_warn("etop: mdio probe failed\n");; return 0; err_netdev: @@ -868,7 +871,6 @@ ltq_etop_probe(struct platform_device *pdev) dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); strcpy(dev->name, "eth%d"); dev->netdev_ops = <q_eth_netdev_ops; - dev->ethtool_ops = <q_etop_ethtool_ops; priv = netdev_priv(dev); priv->res = res; priv->pldata = dev_get_platdata(&pdev->dev); -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:49:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:51:12 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47743 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904070Ab2AKUtZ (ORCPT ); Wed, 11 Jan 2012 21:49:25 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Felix Fietkau Subject: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set Date: Wed, 11 Jan 2012 21:44:33 +0100 Message-Id: <1326314674-9899-16-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32230 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1786 Lines: 64 The patch makes the oprofile code use the performance counters irq. This patch is written by Felix Fietkau. Signed-off-by: Felix Fietkau Signed-off-by: John Crispin --- arch/mips/kernel/cevt-r4k.c | 2 +- arch/mips/oprofile/op_model_mipsxx.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 51095dd9..bc702c8 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -84,7 +84,7 @@ out: struct irqaction c0_compare_irqaction = { .handler = c0_compare_interrupt, - .flags = IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED, .name = "timer", }; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..86cf234 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -298,6 +298,11 @@ static void reset_counters(void *arg) } } +static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id) +{ + return mipsxx_perfcount_handler(); +} + static int __init mipsxx_init(void) { int counters; @@ -374,6 +379,10 @@ static int __init mipsxx_init(void) save_perf_irq = perf_irq; perf_irq = mipsxx_perfcount_handler; + if (cp0_perfcount_irq >= 0) + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int, + IRQF_SHARED, "Perfcounter", save_perf_irq); + return 0; } @@ -381,6 +390,9 @@ static void mipsxx_exit(void) { int counters = op_model_mipsxx_ops.num_counters; + if (cp0_perfcount_irq >= 0) + free_irq(cp0_perfcount_irq, save_perf_irq); + counters = counters_per_cpu_to_total(counters); on_each_cpu(reset_counters, (void *)(long)counters, 1); -- 1.7.7.1 From blogic@openwrt.org Wed Jan 11 21:49:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jan 2012 21:51:33 +0100 (CET) Received: from nbd.name ([46.4.11.11]:47745 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904073Ab2AKUtZ (ORCPT ); Wed, 11 Jan 2012 21:49:25 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH RESEND 17/17] MIPS: lantiq: enable oprofile support on lantiq targets Date: Wed, 11 Jan 2012 21:44:34 +0100 Message-Id: <1326314674-9899-17-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> X-archive-position: 32231 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 833 Lines: 33 This patch sets the performance counters irq for Lantiq SoCs. Signed-off-by: John Crispin --- arch/mips/lantiq/irq.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 3b8cea5..6304a80 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -40,6 +40,9 @@ #define MAX_EIU 6 +/* the performance counter */ +#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) + /* irqs generated by device attached to the EBU need to be acked in * a special manner */ @@ -317,6 +320,8 @@ void __init arch_init_irq(void) set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); #endif + + cp0_perfcount_irq = LTQ_PERF_IRQ; } unsigned int __cpuinit get_c0_compare_int(void) -- 1.7.7.1 From sshtylyov@mvista.com Thu Jan 12 12:35:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jan 2012 12:35:15 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:39032 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901164Ab2ALLfH (ORCPT ); Thu, 12 Jan 2012 12:35:07 +0100 Received: by bkty8 with SMTP id y8so1938972bkt.36 for ; Thu, 12 Jan 2012 03:35:01 -0800 (PST) Received: by 10.204.10.72 with SMTP id o8mr963867bko.92.1326368101755; Thu, 12 Jan 2012 03:35:01 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-80-144.pppoe.mtu-net.ru. [91.79.80.144]) by mx.google.com with ESMTPS id cg2sm10087392bkb.12.2012.01.12.03.34.59 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 12 Jan 2012 03:35:00 -0800 (PST) Message-ID: <4F0EC523.7040608@mvista.com> Date: Thu, 12 Jan 2012 15:33:55 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:9.0) Gecko/20111222 Thunderbird/9.0.1 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH RESEND 15/17] NET: MIPS: lantiq: return value of request_irq was not handled gracefully References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-15-git-send-email-blogic@openwrt.org> In-Reply-To: <1326314674-9899-15-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32232 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1760 Lines: 53 Hello. On 12-01-2012 0:44, John Crispin wrote: > The return values of request_irq() were not checked leading to the following > error message. > drivers/net/ethernet/lantiq_etop.c: In function 'ltq_etop_hw_init': > drivers/net/ethernet/lantiq_etop.c:368:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result > drivers/net/ethernet/lantiq_etop.c:377:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result > Signed-off-by: John Crispin > Acked-by: David S. Miller > --- > drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------ > 1 files changed, 8 insertions(+), 6 deletions(-) > diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c > index 9fd6779..659c868 100644 > --- a/drivers/net/ethernet/lantiq_etop.c > +++ b/drivers/net/ethernet/lantiq_etop.c [...] > @@ -364,21 +365,22 @@ ltq_etop_hw_init(struct net_device *dev) > > if (IS_TX(i)) { > ltq_dma_alloc_tx(&ch->dma); > - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, > + err = request_irq(irq, ltq_etop_dma_irq, 0, > "etop_tx", priv); > } else if (IS_RX(i)) { > ltq_dma_alloc_rx(&ch->dma); > for (ch->dma.desc = 0; ch->dma.desc< LTQ_DESC_NUM; > ch->dma.desc++) > if (ltq_etop_alloc_skb(ch)) > - return -ENOMEM; > + err = -ENOMEM; This 'err' will get overwrtitten by subseuent request_irq(). > ch->dma.desc = 0; > - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, > + err = request_irq(irq, ltq_etop_dma_irq, 0, > "etop_rx", priv); > } > - ch->dma.irq = irq; > + if (!err) > + ch->dma.irq = irq; > } > - return 0; > + return err; > } WBR, Sergei From sshtylyov@mvista.com Thu Jan 12 12:38:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jan 2012 12:38:24 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:42296 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901164Ab2ALLiO (ORCPT ); Thu, 12 Jan 2012 12:38:14 +0100 Received: by bkty8 with SMTP id y8so1941641bkt.36 for ; Thu, 12 Jan 2012 03:38:09 -0800 (PST) Received: by 10.204.156.17 with SMTP id u17mr1016317bkw.57.1326368289316; Thu, 12 Jan 2012 03:38:09 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-80-144.pppoe.mtu-net.ru. [91.79.80.144]) by mx.google.com with ESMTPS id t23sm10117116bkv.10.2012.01.12.03.38.08 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 12 Jan 2012 03:38:08 -0800 (PST) Message-ID: <4F0EC5E0.4060700@mvista.com> Date: Thu, 12 Jan 2012 15:37:04 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:9.0) Gecko/20111222 Thunderbird/9.0.1 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, Felix Fietkau Subject: Re: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-16-git-send-email-blogic@openwrt.org> In-Reply-To: <1326314674-9899-16-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32233 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 391 Lines: 16 Hello. On 12-01-2012 0:44, John Crispin wrote: > The patch makes the oprofile code use the performance counters irq. > This patch is written by Felix Fietkau. Perhaps you should have marked it as "From: Felix Fietkau " in the first line of the mail? > Signed-off-by: Felix Fietkau > Signed-off-by: John Crispin WBR, Sergei From sshtylyov@mvista.com Thu Jan 12 15:39:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jan 2012 15:39:42 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:64025 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904102Ab2ALOjf (ORCPT ); Thu, 12 Jan 2012 15:39:35 +0100 Received: by eaaa13 with SMTP id a13so863365eaa.36 for ; Thu, 12 Jan 2012 06:39:29 -0800 (PST) Received: by 10.204.225.71 with SMTP id ir7mr1217089bkb.124.1326379168947; Thu, 12 Jan 2012 06:39:28 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id b9sm11124861bks.6.2012.01.12.06.39.27 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 12 Jan 2012 06:39:28 -0800 (PST) Message-ID: <4F0EFE6E.3080503@mvista.com> Date: Thu, 12 Jan 2012 18:38:22 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:6.0) Gecko/20110812 Thunderbird/6.0 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org, Felix Fietkau Subject: Re: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-16-git-send-email-blogic@openwrt.org> In-Reply-To: <1326314674-9899-16-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32234 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1048 Lines: 38 Hello. On 01/11/2012 11:44 PM, John Crispin wrote: > The patch makes the oprofile code use the performance counters irq. > This patch is written by Felix Fietkau. > Signed-off-by: Felix Fietkau > Signed-off-by: John Crispin > @@ -374,6 +379,10 @@ static int __init mipsxx_init(void) > save_perf_irq = perf_irq; > perf_irq = mipsxx_perfcount_handler; > > + if (cp0_perfcount_irq>= 0) BTW, I just noticed. IRQ0 is not a valid IRQ in Linux, request_irq() should fail when passed 0, so this and following check should be '> 0'. > + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int, > + IRQF_SHARED, "Perfcounter", save_perf_irq); > + > return 0; > } > > @@ -381,6 +390,9 @@ static void mipsxx_exit(void) > { > int counters = op_model_mipsxx_ops.num_counters; > > + if (cp0_perfcount_irq>= 0) > + free_irq(cp0_perfcount_irq, save_perf_irq); > + > counters = counters_per_cpu_to_total(counters); > on_each_cpu(reset_counters, (void *)(long)counters, 1); > WBR, Sergei From guenter.roeck@ericsson.com Thu Jan 12 15:51:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jan 2012 15:51:36 +0100 (CET) Received: from imr3.ericy.com ([198.24.6.13]:46517 "EHLO imr3.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904104Ab2ALOva (ORCPT ); Thu, 12 Jan 2012 15:51:30 +0100 Received: from eusaamw0711.eamcs.ericsson.se ([147.117.20.178]) by imr3.ericy.com (8.13.8/8.13.8) with ESMTP id q0CEp46X021921 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Thu, 12 Jan 2012 08:51:16 -0600 Received: from localhost (147.117.20.214) by eusaamw0711.eamcs.ericsson.se (147.117.20.179) with Microsoft SMTP Server id 8.3.137.0; Thu, 12 Jan 2012 09:51:05 -0500 Date: Thu, 12 Jan 2012 06:49:38 -0800 From: Guenter Roeck To: Sergei Shtylyov CC: John Crispin , Ralf Baechle , "linux-mips@linux-mips.org" , Felix Fietkau Subject: Re: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set Message-ID: <20120112144938.GA17168@ericsson.com> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-16-git-send-email-blogic@openwrt.org> <4F0EFE6E.3080503@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <4F0EFE6E.3080503@mvista.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32235 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1276 Lines: 44 On Thu, Jan 12, 2012 at 10:38:22AM -0500, Sergei Shtylyov wrote: > Hello. > > On 01/11/2012 11:44 PM, John Crispin wrote: > > > The patch makes the oprofile code use the performance counters irq. > > > This patch is written by Felix Fietkau. > > > Signed-off-by: Felix Fietkau > > Signed-off-by: John Crispin > > > @@ -374,6 +379,10 @@ static int __init mipsxx_init(void) > > save_perf_irq = perf_irq; > > perf_irq = mipsxx_perfcount_handler; > > > > + if (cp0_perfcount_irq>= 0) > > BTW, I just noticed. IRQ0 is not a valid IRQ in Linux, request_irq() should > fail when passed 0, so this and following check should be '> 0'. > There is also the little matter of coding style. Watch out for chapter 3. Guenter > > + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int, > > + IRQF_SHARED, "Perfcounter", save_perf_irq); > > + > > return 0; > > } > > > > @@ -381,6 +390,9 @@ static void mipsxx_exit(void) > > { > > int counters = op_model_mipsxx_ops.num_counters; > > > > + if (cp0_perfcount_irq>= 0) > > + free_irq(cp0_perfcount_irq, save_perf_irq); > > + > > counters = counters_per_cpu_to_total(counters); > > on_each_cpu(reset_counters, (void *)(long)counters, 1); > > > > WBR, Sergei > From ralf@linux-mips.org Thu Jan 12 18:02:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jan 2012 18:02:59 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58640 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1901168Ab2ALRCz (ORCPT ); Thu, 12 Jan 2012 18:02:55 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0CH2rcx024077; Thu, 12 Jan 2012 18:02:54 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0CH2pSL024076; Thu, 12 Jan 2012 18:02:51 +0100 Date: Thu, 12 Jan 2012 18:02:51 +0100 From: Ralf Baechle To: Sergei Shtylyov Cc: John Crispin , linux-mips@linux-mips.org, Felix Fietkau Subject: Re: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set Message-ID: <20120112170251.GA21781@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-16-git-send-email-blogic@openwrt.org> <4F0EFE6E.3080503@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4F0EFE6E.3080503@mvista.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32236 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 924 Lines: 24 On Thu, Jan 12, 2012 at 06:38:22PM +0300, Sergei Shtylyov wrote: > >@@ -374,6 +379,10 @@ static int __init mipsxx_init(void) > > save_perf_irq = perf_irq; > > perf_irq = mipsxx_perfcount_handler; > > > >+ if (cp0_perfcount_irq>= 0) > > BTW, I just noticed. IRQ0 is not a valid IRQ in Linux, > request_irq() should fail when passed 0, so this and following check > should be '> 0'. In a normal configuration that is in a discrete processor or in a MIPS core where the performance IRQ is just routed back into the core the lowest sensible value for cp0_perfcount_irq is 2, so there is no immediate problem there. IRQ 0 is ok for static use; dynamic use is problematic. This case is even more problematic because the interrupt might be shared with the timer and the timer interrupt is allocated statically (see cevt-r4k.c) but the performance counter interrupt later allocated dynamically with IRQF_SHARED. Ralf From mattst88@gmail.com Thu Jan 12 22:20:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jan 2012 22:20:21 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:54268 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901167Ab2ALVUR (ORCPT ); Thu, 12 Jan 2012 22:20:17 +0100 Received: by dajx4 with SMTP id x4so2033140daj.36 for ; Thu, 12 Jan 2012 13:20:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=GXQs5YpTFA3aVL2tTdzWSX5RlE2K2d1GMcP6xb/EqGw=; b=Q7wThLpFDGNp3ZeOB/cCT1tYYN9UxK7rXSNyW3+OWxya4uAs9d4Aa6M3tavoLnMPZG 7qlr5vQXN7JcdB8ydJfkgUzKcKJMLKn/G4RAYGaFre7YElAIX/XnBVvdLSzqGoYAOGIJ 3Sis/Jb+ZhI4jEMkIgsNML/zMdPLsmOqVklQc= Received: by 10.68.115.195 with SMTP id jq3mr11568276pbb.34.1326403210267; Thu, 12 Jan 2012 13:20:10 -0800 (PST) MIME-Version: 1.0 Received: by 10.68.48.8 with HTTP; Thu, 12 Jan 2012 13:19:49 -0800 (PST) In-Reply-To: <20120110153834.531664db@endymion.delvare> References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> <20110903103036.161616a5@endymion.delvare> <20111031105354.4b888e44@endymion.delvare> <20120110153834.531664db@endymion.delvare> From: Matt Turner Date: Thu, 12 Jan 2012 16:19:49 -0500 Message-ID: Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts To: Jean Delvare Cc: linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck , "Maciej W. Rozycki" Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32237 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 711 Lines: 20 On Tue, Jan 10, 2012 at 9:38 AM, Jean Delvare wrote: > On Mon, 31 Oct 2011 10:53:54 +0100, Jean Delvare wrote: >> On Sat, 3 Sep 2011 10:30:36 +0200, Jean Delvare wrote: >> > Please address my concerns where you agree and send an updated patch. >> >> Matt, care to send an updated patch addressing my concerns? Otherwise >> it will be lost again. > > It's been 3 more months. Matt (or anyone else who cares and has access > to the hardware), please send an updated patch or I'll have to drop it. > > -- > Jean Delvare I'll fix it up and resend the next time I'm working on the related mips stuff. It's hard to prioritize volunteer work for hardware you and two other people have. :) Matt From ralf@linux-mips.org Fri Jan 13 13:38:02 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jan 2012 13:38:07 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:52402 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903542Ab2AMMiC (ORCPT ); Fri, 13 Jan 2012 13:38:02 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0DCc1vY024389; Fri, 13 Jan 2012 13:38:01 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0DCc1ww024388; Fri, 13 Jan 2012 13:38:01 +0100 Date: Fri, 13 Jan 2012 13:38:01 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code Message-ID: <20120113123800.GA22597@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-1-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32238 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1074 Lines: 39 On Wed, Jan 11, 2012 at 09:44:18PM +0100, John Crispin wrote: > +static inline void ltq_ebu_w32_mask(u32 c, u32 s, u32 r) { > + ltq_ebu_w32((ltq_ebu_r32(r) & ~c) | s, r); > +} > + > +/* cgu access */ > +static inline void ltq_cgu_w32(u32 v, u32 r) { > + ltq_w32(v, ltq_cgu_membase + r); > +}; > +static inline u32 ltq_cgu_r32(u32 r) { > + return ltq_r32(ltq_cgu_membase + r); > +}; > +static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) { > + ltq_cgu_w32((ltq_cgu_r32(r) & ~c) | s, r); > +} Documentation/CodingStyle: [...] However, there is one special case, namely functions: they have the opening brace at the beginning of the next line, thus: int function(int x) { body of function } Heretic people all over the world have claimed that this inconsistency is ... well ... inconsistent, but all right-thinking people know that (a) K&R are _right_ and (b) K&R are right. Besides, functions are special anyway (you can't nest them in C). [...] So this formatting is heretic. Pray 10 CodingStyle to Saint K&R. Ralf From miloody@gmail.com Fri Jan 13 14:36:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jan 2012 14:36:34 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:50590 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901761Ab2AMNg2 (ORCPT ); Fri, 13 Jan 2012 14:36:28 +0100 Received: by ggnl1 with SMTP id l1so1856958ggn.36 for ; Fri, 13 Jan 2012 05:36:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; bh=Wr+ckNT7TjnbyYFFsQ1epf7j71wliFPOAq1y1mh0rzg=; b=S4XQpyM8IhyBa5ckID9wXRnAtywNPtuEF1L+pTF13fcsyg6QmttJQ7QGN7flPsZmC7 W8kUcd8b05Of87JRMxxBuMcgKjgzSi7D5GfnReIuYATiDF9IZeNBv6u5umKoiSE11zCB ruv6QJ7pVXnn3rAxYeC7L1qcUjAQHwz/XIa0I= MIME-Version: 1.0 Received: by 10.50.183.166 with SMTP id en6mr938808igc.7.1326461780740; Fri, 13 Jan 2012 05:36:20 -0800 (PST) Received: by 10.42.244.65 with HTTP; Fri, 13 Jan 2012 05:36:20 -0800 (PST) Date: Fri, 13 Jan 2012 21:36:20 +0800 Message-ID: Subject: Kernel coredump about kblockd deadlock From: loody To: LKML , Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32239 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3214 Lines: 65 Dear all: I use kernel 2.6.35.13 and cpu for mips When I plug in/out usb stick for several times I got following warning messages as I append at the end of mail. is it possible correlate to below issue http://thread.gmane.org/gmane.linux.kernel/1177383/focus=69879 Thanks for your help, INFO: task kblockd/0:10 blocked for more than 120 seconds. "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. kblockd/0 D [87016a78] 802d1e48 0 10 0x00100000 2 11 9 (kernel thread) Stack : 00000001 80107148 8562ed80 800e9098 00000001 00000001 7fffffff 00000000 00000000 7fffffff 87053d38 ffffffff 87053d38 87053d28 872ff00c 802d1e48 00000001 00000009 00000102 80071c80 00005965 0056addf 00005965 00000001 00000000 00000000 7fffffff 80020c64 00000000 00000002 00000000 00000000 7fffffff 802d1ca8 00000000 80024538 00000004 0000000a 00000001 87016a78 ... Call Trace: [<802d1764>] schedule+0x648/0x70c from[<802d1e48>] schedule_timeout+0x30/0x324 [<802d1e48>] schedule_timeout+0x30/0x324 from[<802d1ca8>] wait_for_common+0xf8/0x1c0 [<802d1ca8>] wait_for_common+0xf8/0x1c0 from[<80044400>] __cancel_work_timer+0x188/0x210 [<80044400>] __cancel_work_timer+0x188/0x210 from[<801a48c4>] blk_cleanup_queue+0x18/0x6c [<801a48c4>] blk_cleanup_queue+0x18/0x6c from[<802098f4>] scsi_device_dev_release_usercontext+0x174/0x1e4 [<802098f4>] scsi_device_dev_release_usercontext+0x174/0x1e4 from[<80043aa8>] execute_in_process_context+0x30/0x5c [<80043aa8>] execute_in_process_context+0x30/0x5c from[<801eeda8>] device_release+0x54/0x90 [<801eeda8>] device_release+0x54/0x90 from[<801b0180>] kobject_release+0x70/0xa8 [<801b0180>] kobject_release+0x70/0xa8 from[<801b17bc>] kref_put+0x80/0x98 [<801b17bc>] kref_put+0x80/0x98 from[<80203c04>] scsi_request_fn+0x51c/0x61c [<80203c04>] scsi_request_fn+0x51c/0x61c from[<801a482c>] generic_unplug_device+0x38/0x7c [<801a482c>] generic_unplug_device+0x38/0x7c from[<80043e90>] worker_thread+0x1ec/0x2d4 [<80043e90>] worker_thread+0x1ec/0x2d4 from[<800482c4>] kthread+0x7c/0x84 [<800482c4>] kthread+0x7c/0x84 from[<80007818>] kernel_thread_helper+0x10/0x18 ------------------------------------------------------------------------------------- hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0002 hub 1-0:1.0: port 1, status 0000, change 0001, 12 Mb/s usb 1-1: USB disconnect, address 35 usb 1-1: unregistering device usb 1-1: unregistering interface 1-1:1.0 usb 1-1: usb_disable_device nuking all URBs hub 1-0:1.0: debounce: port 1: total 100ms stable 100ms status 0x0 hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0002 ehci-ehci ehci-ehci.0: GetStatus port 1 status 000803 sig=j CSC CONNECT hub 1-0:1.0: port 1, status 0401, change 0001, 480 Mb/s hub 1-0:1.0: debounce: port 1: total 100ms stable 100ms status 0x401 ehci-ehci ehci-ehci.0: port 1 high speed ehci-ehci ehci-ehci.0: GetStatus port 1 status 00000d sig=se0 PEC PE CONNECT usb 1-1: new high speed USB device using ehci-ehci and address 36 ehci-ehci ehci-ehci.0: port 1 high speed ehci-ehci ehci-ehci.0: GetStatus port 1 status 00000d sig=se0 PEC PE CONNECT usb 1-1: default language 0x0409 usb 1-1: udev 36, busnum 1, minor = 35 .... ..... From marek.vasut@gmail.com Sat Jan 14 01:29:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 14 Jan 2012 01:29:45 +0100 (CET) Received: from mail-ee0-f49.google.com ([74.125.83.49]:48164 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903547Ab2ANA3l (ORCPT ); Sat, 14 Jan 2012 01:29:41 +0100 Received: by eeke50 with SMTP id e50so426847eek.36 for ; Fri, 13 Jan 2012 16:29:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding:message-id; bh=FEj4QKl7xm5Twma6PTvKKY0DbCXgvaATFa/FPaWPq4A=; b=MFwtFBSxVsAPCx2KNraiVazM7Em4s0PoUaElrtcCAsfJSQ4/IwMJQSdviVtB3DGqmR PqIIs/E3H+QE8Bl657c4KMZYqw/zbVpslBiwRavCPjU63ixm82+j65BpkvFRDPsKuoMl d6gViqiF1V7QqQFJCqJ0BKqi+XmMKQAyP/mvc= Received: by 10.213.3.154 with SMTP id 26mr792014ebn.27.1326500975949; Fri, 13 Jan 2012 16:29:35 -0800 (PST) Received: from mashiro.localnet (vasut.kolej.mff.cuni.cz. [78.128.198.52]) by mx.google.com with ESMTPS id b49sm36348334eec.9.2012.01.13.16.29.35 (version=SSLv3 cipher=OTHER); Fri, 13 Jan 2012 16:29:35 -0800 (PST) From: Marek Vasut To: loody Subject: Re: Kernel coredump about kblockd deadlock Date: Sat, 14 Jan 2012 01:29:34 +0100 User-Agent: KMail/1.13.7 (Linux/3.1.0-1-amd64; KDE/4.6.5; x86_64; ; ) Cc: LKML , Linux MIPS Mailing List References: In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <201201140129.34399.marek.vasut@gmail.com> X-archive-position: 32240 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: marek.vasut@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3362 Lines: 73 > Dear all: > I use kernel 2.6.35.13 and cpu for mips Does this happen with anything less ancient ? M > When I plug in/out usb stick for several times I got following warning > messages as I append at the end of mail. > > is it possible correlate to below issue > http://thread.gmane.org/gmane.linux.kernel/1177383/focus=69879 > Thanks for your help, > > > INFO: task kblockd/0:10 blocked for more than 120 seconds. > "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. > kblockd/0 D [87016a78] 802d1e48 0 10 0x00100000 2 > 11 9 (kernel thread) > Stack : 00000001 80107148 8562ed80 800e9098 00000001 00000001 7fffffff > 00000000 00000000 7fffffff 87053d38 ffffffff 87053d38 87053d28 872ff00c > 802d1e48 00000001 00000009 00000102 80071c80 00005965 0056addf 00005965 > 00000001 00000000 00000000 7fffffff 80020c64 00000000 00000002 00000000 > 00000000 7fffffff 802d1ca8 00000000 80024538 00000004 0000000a 00000001 > 87016a78 ... > Call Trace: > [<802d1764>] schedule+0x648/0x70c from[<802d1e48>] > schedule_timeout+0x30/0x324 [<802d1e48>] schedule_timeout+0x30/0x324 > from[<802d1ca8>] > wait_for_common+0xf8/0x1c0 > [<802d1ca8>] wait_for_common+0xf8/0x1c0 from[<80044400>] > __cancel_work_timer+0x188/0x210 > [<80044400>] __cancel_work_timer+0x188/0x210 from[<801a48c4>] > blk_cleanup_queue+0x18/0x6c > [<801a48c4>] blk_cleanup_queue+0x18/0x6c from[<802098f4>] > scsi_device_dev_release_usercontext+0x174/0x1e4 > [<802098f4>] scsi_device_dev_release_usercontext+0x174/0x1e4 > from[<80043aa8>] execute_in_process_context+0x30/0x5c > [<80043aa8>] execute_in_process_context+0x30/0x5c from[<801eeda8>] > device_release+0x54/0x90 > [<801eeda8>] device_release+0x54/0x90 from[<801b0180>] > kobject_release+0x70/0xa8 [<801b0180>] kobject_release+0x70/0xa8 > from[<801b17bc>] kref_put+0x80/0x98 [<801b17bc>] kref_put+0x80/0x98 > from[<80203c04>] scsi_request_fn+0x51c/0x61c [<80203c04>] > scsi_request_fn+0x51c/0x61c from[<801a482c>] > generic_unplug_device+0x38/0x7c > [<801a482c>] generic_unplug_device+0x38/0x7c from[<80043e90>] > worker_thread+0x1ec/0x2d4 > [<80043e90>] worker_thread+0x1ec/0x2d4 from[<800482c4>] kthread+0x7c/0x84 > [<800482c4>] kthread+0x7c/0x84 from[<80007818>] > kernel_thread_helper+0x10/0x18 > > --------------------------------------------------------------------------- > ---------- hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0002 > hub 1-0:1.0: port 1, status 0000, change 0001, 12 Mb/s > usb 1-1: USB disconnect, address 35 > usb 1-1: unregistering device > usb 1-1: unregistering interface 1-1:1.0 > usb 1-1: usb_disable_device nuking all URBs > hub 1-0:1.0: debounce: port 1: total 100ms stable 100ms status 0x0 > hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0002 > ehci-ehci ehci-ehci.0: GetStatus port 1 status 000803 sig=j CSC CONNECT > hub 1-0:1.0: port 1, status 0401, change 0001, 480 Mb/s > hub 1-0:1.0: debounce: port 1: total 100ms stable 100ms status 0x401 > ehci-ehci ehci-ehci.0: port 1 high speed > ehci-ehci ehci-ehci.0: GetStatus port 1 status 00000d sig=se0 PEC PE > CONNECT usb 1-1: new high speed USB device using ehci-ehci and address 36 > ehci-ehci ehci-ehci.0: port 1 high speed > ehci-ehci ehci-ehci.0: GetStatus port 1 status 00000d sig=se0 PEC PE > CONNECT usb 1-1: default language 0x0409 > usb 1-1: udev 36, busnum 1, minor = 35 > .... > ..... From manuel.lauss@googlemail.com Sat Jan 14 10:44:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 14 Jan 2012 10:44:33 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:40129 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903565Ab2ANJo0 (ORCPT ); Sat, 14 Jan 2012 10:44:26 +0100 Received: by eaaa13 with SMTP id a13so501513eaa.36 for ; Sat, 14 Jan 2012 01:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=uMh9epn7EGP3HCkoNv1xKq6TJ60k/EEcIOYJV3qxIWY=; b=LPAO7Dvkr6vBJxiaFPKyTTyCcyXFCFIx0MNbjU6BhkZcXGWiK3SscOwrdk/DF3DkdO tSSlkVPiylyS8QTBys2nHpyEICAWZ1K949fMoOLZGABw+KTrlyBgMSRLEpdIqWGNNPXv 5O7O+pBldO5GfdmAy9T7sdRt/jo2wDYxuf34o= Received: by 10.213.108.145 with SMTP id f17mr1219136ebp.1.1326534261369; Sat, 14 Jan 2012 01:44:21 -0800 (PST) Received: from flagship.roarinelk.net (178-191-3-31.adsl.highway.telekom.at. [178.191.3.31]) by mx.google.com with ESMTPS id x43sm41359382eef.8.2012.01.14.01.44.19 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 14 Jan 2012 01:44:20 -0800 (PST) From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS , Manuel Lauss Subject: [PATCH mips-next] MIPS: Alchemy: update Au1300 inlined GPIO macros Date: Sat, 14 Jan 2012 10:44:15 +0100 Message-Id: <1326534255-20073-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.8.3 X-archive-position: 32241 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1625 Lines: 54 Add a few missing macros for the inlined (!CONFIG_GPIOLIB) GPIO case. Fixes a build failure in the mmc core due to missing gpio_request_one() function: mmc/core/cd-gpio.c: In function 'mmc_cd_gpio_request': mmc/core/cd-gpio.c:43:2: error: implicit declaration of function 'gpio_request_one' [-Werror=implicit-function-declaration] Signed-off-by: Manuel Lauss --- Please fold into patch "MIPS: Alchemy: Au1300-SoC-support" if possible. arch/mips/include/asm/mach-au1x00/gpio-au1300.h | 20 +++++++++++++++++++- 1 files changed, 19 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h index 556e1be..fb9975c 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -11,6 +11,9 @@ #include #include +struct gpio; +struct gpio_chip; + /* with the current GPIC design, up to 128 GPIOs are possible. * The only implementation so far is in the Au1300, which has 75 externally * available GPIOs. @@ -203,7 +206,22 @@ static inline int gpio_request(unsigned int gpio, const char *label) return 0; } -static inline void gpio_free(unsigned int gpio) +static inline int gpio_request_one(unsigned gpio, + unsigned long flags, const char *label) +{ + return 0; +} + +static inline int gpio_request_array(struct gpio *array, size_t num) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +static inline void gpio_free_array(struct gpio *array, size_t num) { } -- 1.7.8.3 From marek.vasut@gmail.com Sun Jan 15 16:07:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Jan 2012 16:07:36 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:44180 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903559Ab2AOPHX (ORCPT ); Sun, 15 Jan 2012 16:07:23 +0100 Received: by eaaa13 with SMTP id a13so813913eaa.36 for ; Sun, 15 Jan 2012 07:07:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding:message-id; bh=CRBBRBtNG4krNYCyQBpUJo09Cz/PdZXU6isUzZP5JpQ=; b=X5nbjkzJJJiwR5wntpTf9EHzcxv3ipE5srDK2YlaP9K1mtoRmZfw7/IEF+bwy7C/BA qKgA7TjXZfs9bzhZtmyAJJULeAc0B5FfV0k4o84KQwOlccv+7ugBk3yWWxrjfO5Lnxow R3QXNt/R6R+oRiRHCfvq7RNUfQonsSiP/D7go= Received: by 10.213.113.208 with SMTP id b16mr927108ebq.55.1326640038346; Sun, 15 Jan 2012 07:07:18 -0800 (PST) Received: from mashiro.localnet (vasut.kolej.mff.cuni.cz. [78.128.198.52]) by mx.google.com with ESMTPS id y12sm59292471eeb.11.2012.01.15.07.07.17 (version=SSLv3 cipher=OTHER); Sun, 15 Jan 2012 07:07:17 -0800 (PST) From: Marek Vasut To: loody Subject: Re: Kernel coredump about kblockd deadlock Date: Sun, 15 Jan 2012 16:07:16 +0100 User-Agent: KMail/1.13.7 (Linux/3.1.0-1-amd64; KDE/4.6.5; x86_64; ; ) Cc: LKML , Linux MIPS Mailing List References: <201201140129.34399.marek.vasut@gmail.com> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <201201151607.16792.marek.vasut@gmail.com> X-archive-position: 32242 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: marek.vasut@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3811 Lines: 83 > hi Marek: > > 2012/1/14 Marek Vasut : > >> Dear all: > >> I use kernel 2.6.35.13 and cpu for mips > > > > Does this happen with anything less ancient ? > > Sorry for my broken English, your "less ancient" mean? ALWAYS keep the MLs in CC. Less ancient == less old. Don't you have a dictionary? > > Thanks for your reply. > > > M > > > >> When I plug in/out usb stick for several times I got following warning > >> messages as I append at the end of mail. > >> > >> is it possible correlate to below issue > >> http://thread.gmane.org/gmane.linux.kernel/1177383/focus=69879 > >> Thanks for your help, > >> > >> > >> INFO: task kblockd/0:10 blocked for more than 120 seconds. > >> "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this > >> message. kblockd/0 D [87016a78] 802d1e48 0 10 0x00100000 > >> 2 11 9 (kernel thread) > >> Stack : 00000001 80107148 8562ed80 800e9098 00000001 00000001 7fffffff > >> 00000000 00000000 7fffffff 87053d38 ffffffff 87053d38 87053d28 872ff00c > >> 802d1e48 00000001 00000009 00000102 80071c80 00005965 0056addf 00005965 > >> 00000001 00000000 00000000 7fffffff 80020c64 00000000 00000002 00000000 > >> 00000000 7fffffff 802d1ca8 00000000 80024538 00000004 0000000a 00000001 > >> 87016a78 ... > >> Call Trace: > >> [<802d1764>] schedule+0x648/0x70c from[<802d1e48>] > >> schedule_timeout+0x30/0x324 [<802d1e48>] schedule_timeout+0x30/0x324 > >> from[<802d1ca8>] > >> wait_for_common+0xf8/0x1c0 > >> [<802d1ca8>] wait_for_common+0xf8/0x1c0 from[<80044400>] > >> __cancel_work_timer+0x188/0x210 > >> [<80044400>] __cancel_work_timer+0x188/0x210 from[<801a48c4>] > >> blk_cleanup_queue+0x18/0x6c > >> [<801a48c4>] blk_cleanup_queue+0x18/0x6c from[<802098f4>] > >> scsi_device_dev_release_usercontext+0x174/0x1e4 > >> [<802098f4>] scsi_device_dev_release_usercontext+0x174/0x1e4 > >> from[<80043aa8>] execute_in_process_context+0x30/0x5c > >> [<80043aa8>] execute_in_process_context+0x30/0x5c from[<801eeda8>] > >> device_release+0x54/0x90 > >> [<801eeda8>] device_release+0x54/0x90 from[<801b0180>] > >> kobject_release+0x70/0xa8 [<801b0180>] kobject_release+0x70/0xa8 > >> from[<801b17bc>] kref_put+0x80/0x98 [<801b17bc>] kref_put+0x80/0x98 > >> from[<80203c04>] scsi_request_fn+0x51c/0x61c [<80203c04>] > >> scsi_request_fn+0x51c/0x61c from[<801a482c>] > >> generic_unplug_device+0x38/0x7c > >> [<801a482c>] generic_unplug_device+0x38/0x7c from[<80043e90>] > >> worker_thread+0x1ec/0x2d4 > >> [<80043e90>] worker_thread+0x1ec/0x2d4 from[<800482c4>] > >> kthread+0x7c/0x84 [<800482c4>] kthread+0x7c/0x84 from[<80007818>] > >> kernel_thread_helper+0x10/0x18 > >> > >> ------------------------------------------------------------------------ > >> --- ---------- hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0002 > >> hub 1-0:1.0: port 1, status 0000, change 0001, 12 Mb/s > >> usb 1-1: USB disconnect, address 35 > >> usb 1-1: unregistering device > >> usb 1-1: unregistering interface 1-1:1.0 > >> usb 1-1: usb_disable_device nuking all URBs > >> hub 1-0:1.0: debounce: port 1: total 100ms stable 100ms status 0x0 > >> hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0002 > >> ehci-ehci ehci-ehci.0: GetStatus port 1 status 000803 sig=j CSC CONNECT > >> hub 1-0:1.0: port 1, status 0401, change 0001, 480 Mb/s > >> hub 1-0:1.0: debounce: port 1: total 100ms stable 100ms status 0x401 > >> ehci-ehci ehci-ehci.0: port 1 high speed > >> ehci-ehci ehci-ehci.0: GetStatus port 1 status 00000d sig=se0 PEC PE > >> CONNECT usb 1-1: new high speed USB device using ehci-ehci and address > >> 36 ehci-ehci ehci-ehci.0: port 1 high speed > >> ehci-ehci ehci-ehci.0: GetStatus port 1 status 00000d sig=se0 PEC PE > >> CONNECT usb 1-1: default language 0x0409 > >> usb 1-1: udev 36, busnum 1, minor = 35 > >> .... > >> ..... From jj@chaosbits.net Sun Jan 15 21:07:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Jan 2012 21:07:44 +0100 (CET) Received: from swampdragon.chaosbits.net ([90.184.90.115]:23661 "EHLO swampdragon.chaosbits.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903568Ab2AOUHh (ORCPT ); Sun, 15 Jan 2012 21:07:37 +0100 Received: by swampdragon.chaosbits.net (Postfix, from userid 1000) id B5C1D9403D; Sun, 15 Jan 2012 21:07:35 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by swampdragon.chaosbits.net (Postfix) with ESMTP id AF0989403B; Sun, 15 Jan 2012 21:07:35 +0100 (CET) Date: Sun, 15 Jan 2012 21:07:35 +0100 (CET) From: Jesper Juhl To: linux-mips@linux-mips.org cc: linux-kernel@vger.kernel.org, Kevin Cernekee , Ralf Baechle , trivial@kernel.org Subject: [PATCH] arch/mips/kernel/smp-bmips.c does not need to include version.h Message-ID: User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32243 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jj@chaosbits.net Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 798 Lines: 30 As 'make versioncheck' nicely points out, arch/mips/kernel/smp-bmips.c has no need to '#include '. This patch removes the unneeded include. Signed-off-by: Jesper Juhl --- arch/mips/kernel/smp-bmips.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 58fe71a..d5e950a 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -8,7 +8,6 @@ * SMP support for BMIPS */ -#include #include #include #include -- 1.7.8.3 -- Jesper Juhl http://www.chaosbits.net/ Don't top-post http://www.catb.org/jargon/html/T/top-post.html Plain text mails only, please. From ralf@linux-mips.org Mon Jan 16 11:04:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 11:04:43 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:34835 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903606Ab2APKEg (ORCPT ); Mon, 16 Jan 2012 11:04:36 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0GA4VOj013436; Mon, 16 Jan 2012 11:04:31 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0GA4TOR013431; Mon, 16 Jan 2012 11:04:29 +0100 Date: Mon, 16 Jan 2012 11:04:29 +0100 From: Ralf Baechle To: Jesper Juhl Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Kevin Cernekee , trivial@kernel.org Subject: Re: [PATCH] arch/mips/kernel/smp-bmips.c does not need to include version.h Message-ID: <20120116100429.GA12838@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32244 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Thanks, applied. Ralf From david@gibson.dropbear.id.au Mon Jan 16 12:52:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 12:52:46 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:53667 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903606Ab2APLwW (ORCPT ); Mon, 16 Jan 2012 12:52:22 +0100 Received: by ozlabs.org (Postfix, from userid 1007) id E0EDF1007D3; Mon, 16 Jan 2012 22:52:17 +1100 (EST) Date: Mon, 16 Jan 2012 19:09:40 +1100 From: David Gibson To: Marek Szyprowski Cc: linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Kyungmin Park , Andrzej Pietrasiewicz Subject: Re: [PATCH 04/14] PowerPC: adapt for dma_map_ops changes Message-ID: <20120116080940.GF4512@truffala.fritz.box> Mail-Followup-To: David Gibson , Marek Szyprowski , linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Kyungmin Park , Andrzej Pietrasiewicz References: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com> <1324643253-3024-5-git-send-email-m.szyprowski@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1324643253-3024-5-git-send-email-m.szyprowski@samsung.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32245 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david@gibson.dropbear.id.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 696 Lines: 19 On Fri, Dec 23, 2011 at 01:27:23PM +0100, Marek Szyprowski wrote: > From: Andrzej Pietrasiewicz > > Adapt core PowerPC architecture code for dma_map_ops changes: replace > alloc/free_coherent with generic alloc/free methods. > > Signed-off-by: Andrzej Pietrasiewicz > Signed-off-by: Marek Szyprowski > Signed-off-by: Kyungmin Park Looks sane. Reviewed-by: David Gibson -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson From david@gibson.dropbear.id.au Mon Jan 16 12:52:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 12:53:28 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:36054 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903605Ab2APLwV (ORCPT ); Mon, 16 Jan 2012 12:52:21 +0100 Received: by ozlabs.org (Postfix, from userid 1007) id DE6651007D2; Mon, 16 Jan 2012 22:52:17 +1100 (EST) Date: Mon, 16 Jan 2012 12:57:10 +1100 From: David Gibson To: Marek Szyprowski Cc: linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Kyungmin Park , Andrzej Pietrasiewicz Subject: Re: [PATCH 01/14] common: dma-mapping: introduce alloc_attrs and free_attrs methods Message-ID: <20120116015710.GD4512@truffala.fritz.box> Mail-Followup-To: David Gibson , Marek Szyprowski , linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Thomas Gleixner , Andrew Morton , Arnd Bergmann , Stephen Rothwell , microblaze-uclinux@itee.uq.edu.au, linux-arch@vger.kernel.org, x86@kernel.org, linux-sh@vger.kernel.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-mips@linux-mips.org, discuss@x86-64.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linaro-mm-sig@lists.linaro.org, Jonathan Corbet , Kyungmin Park , Andrzej Pietrasiewicz References: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com> <1324643253-3024-2-git-send-email-m.szyprowski@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1324643253-3024-2-git-send-email-m.szyprowski@samsung.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32246 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david@gibson.dropbear.id.au Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 957 Lines: 22 On Fri, Dec 23, 2011 at 01:27:20PM +0100, Marek Szyprowski wrote: > Introduce new generic alloc and free methods with attributes argument. > > Existing alloc_coherent and free_coherent can be implemented on top of the > new calls with NULL attributes argument. Later also dma_alloc_non_coherent > can be implemented using DMA_ATTR_NONCOHERENT attribute as well as > dma_alloc_writecombine with separate DMA_ATTR_WRITECOMBINE attribute. > > This way the drivers will get more generic, platform independent way of > allocating dma buffers with specific parameters. > > Signed-off-by: Marek Szyprowski > Signed-off-by: Kyungmin Park Looks sensible to me. Reviewed-by: David Gibson -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson From ralf@linux-mips.org Mon Jan 16 13:44:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 13:44:42 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:54996 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903606Ab2APMoi (ORCPT ); Mon, 16 Jan 2012 13:44:38 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0GCib82005584; Mon, 16 Jan 2012 13:44:37 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0GCiavq005583; Mon, 16 Jan 2012 13:44:36 +0100 Date: Mon, 16 Jan 2012 13:44:36 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH mips-next] MIPS: Alchemy: update Au1300 inlined GPIO macros Message-ID: <20120116124436.GA5349@linux-mips.org> References: <1326534255-20073-1-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326534255-20073-1-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32247 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Thanks, applied. Ralf From ralf@linux-mips.org Mon Jan 16 14:22:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 14:23:03 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:55901 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903606Ab2APNW6 (ORCPT ); Mon, 16 Jan 2012 14:22:58 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0GDMu6k013127; Mon, 16 Jan 2012 14:22:56 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0GDMsjT013122; Mon, 16 Jan 2012 14:22:54 +0100 Date: Mon, 16 Jan 2012 14:22:54 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: Greg Kroah-Hartman , Kay Sievers , linux-mips Subject: Re: [PATCH] MIPS: txx9 7segled fix struct device has no member Message-ID: <20120116132254.GA12896@linux-mips.org> References: <20120110211156.31e27cae.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120110211156.31e27cae.yuasa@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32248 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Thanks, applied. Ralf From ralf@linux-mips.org Mon Jan 16 14:32:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 14:32:22 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47399 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903614Ab2APNcT (ORCPT ); Mon, 16 Jan 2012 14:32:19 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0GDWHs3013612; Mon, 16 Jan 2012 14:32:17 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0GDWH8s013611; Mon, 16 Jan 2012 14:32:17 +0100 Date: Mon, 16 Jan 2012 14:32:17 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH] MIPS: Alchemy: increase minimum timeout for 32kHz timer. Message-ID: <20120116133217.GB12896@linux-mips.org> References: <1324399049-6410-1-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1324399049-6410-1-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32249 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 26 Lines: 3 Applied. Thanks, Ralf From ralf@linux-mips.org Mon Jan 16 16:06:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 16:06:43 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59200 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903627Ab2APPGj (ORCPT ); Mon, 16 Jan 2012 16:06:39 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0GF6bbx016860; Mon, 16 Jan 2012 16:06:37 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0GF6bpR016859; Mon, 16 Jan 2012 16:06:37 +0100 Date: Mon, 16 Jan 2012 16:06:37 +0100 From: Ralf Baechle To: Tony Wu Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] vmlinux.lds.S: remove duplicate _sdata symbol Message-ID: <20120116150637.GC12896@linux-mips.org> References: <20111222145317.GA411@hades> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20111222145317.GA411@hades> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32250 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Thanks, applied. Ralf From ralf@linux-mips.org Mon Jan 16 16:47:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 16:47:11 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:53940 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903627Ab2APPrH (ORCPT ); Mon, 16 Jan 2012 16:47:07 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0GFl3Fn018470; Mon, 16 Jan 2012 16:47:03 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0GFl1bH018464; Mon, 16 Jan 2012 16:47:01 +0100 Date: Mon, 16 Jan 2012 16:47:01 +0100 From: Ralf Baechle To: Kautuk Consul Cc: Ingo Molnar , Peter Zijlstra , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, "Mohd. Faris" Subject: Re: [PATCH 1/1] mips: fault.c: Port OOM changes to do_page_fault Message-ID: <20120116154701.GE12896@linux-mips.org> References: <1324639362-18220-1-git-send-email-consul.kautuk@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1324639362-18220-1-git-send-email-consul.kautuk@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32251 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 97 Lines: 5 On Fri, Dec 23, 2011 at 04:52:42PM +0530, Kautuk Consul wrote: Applied. Thanks Kautuk! Ralf From ralf@linux-mips.org Mon Jan 16 17:25:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 17:25:29 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:50320 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903613Ab2APQZZ (ORCPT ); Mon, 16 Jan 2012 17:25:25 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0GGPMZR020151; Mon, 16 Jan 2012 17:25:22 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0GGPKPF020147; Mon, 16 Jan 2012 17:25:20 +0100 Date: Mon, 16 Jan 2012 17:25:20 +0100 From: Ralf Baechle To: Bjorn Helgaas Cc: Jesse Barnes , linux-pci@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH 2/6] MIPS: PCI: use list_for_each_entry() for bus->devices traversal Message-ID: <20120116162520.GF12896@linux-mips.org> References: <20111216223043.5963.87534.stgit@bhelgaas.mtv.corp.google.com> <20111216223139.5963.51460.stgit@bhelgaas.mtv.corp.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20111216223139.5963.51460.stgit@bhelgaas.mtv.corp.google.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32252 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Thanks, applied. Ralf From blogic@openwrt.org Mon Jan 16 17:44:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 17:44:34 +0100 (CET) Received: from nbd.name ([46.4.11.11]:56218 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903607Ab2APQoX (ORCPT ); Mon, 16 Jan 2012 17:44:23 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 01/17] MIPS: lantiq: reorganize xway code Date: Mon, 16 Jan 2012 17:43:38 +0100 Message-Id: <1326732224-21336-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 X-archive-position: 32253 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 27686 Lines: 931 Inside the folder arch/mips/lantiq/xway, there were alot of small files with lots of duplicated code. This patch adds a wrapper function for inserting and requesting resources and unifies the small files into one bigger file. This patch makes the xway code consistent with the falcon support added later in this series. Signed-off-by: John Crispin --- Changes in V2: * ritually kill printks that notify about reset * fixes code formatting of inline functions arch/mips/include/asm/mach-lantiq/lantiq.h | 22 ++--- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 36 +++++++++ arch/mips/lantiq/clk.c | 25 +------ arch/mips/lantiq/devices.c | 30 ++------ arch/mips/lantiq/devices.h | 4 + arch/mips/lantiq/prom.c | 51 +++++++++++-- arch/mips/lantiq/prom.h | 4 + arch/mips/lantiq/xway/Makefile | 6 +- arch/mips/lantiq/xway/devices.c | 42 ++--------- arch/mips/lantiq/xway/dma.c | 21 +---- arch/mips/lantiq/xway/ebu.c | 52 ------------- arch/mips/lantiq/xway/pmu.c | 69 ----------------- arch/mips/lantiq/xway/prom-ase.c | 9 ++ arch/mips/lantiq/xway/prom-xway.c | 10 +++ arch/mips/lantiq/xway/reset.c | 24 +----- arch/mips/lantiq/xway/setup-ase.c | 19 ----- arch/mips/lantiq/xway/setup-xway.c | 20 ----- arch/mips/lantiq/xway/sysctrl.c | 78 ++++++++++++++++++++ drivers/watchdog/lantiq_wdt.c | 2 +- 19 files changed, 226 insertions(+), 298 deletions(-) delete mode 100644 arch/mips/lantiq/xway/ebu.c delete mode 100644 arch/mips/lantiq/xway/pmu.c delete mode 100644 arch/mips/lantiq/xway/setup-ase.c delete mode 100644 arch/mips/lantiq/xway/setup-xway.c create mode 100644 arch/mips/lantiq/xway/sysctrl.c diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index ce2f029..5bdec4f 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -9,23 +9,17 @@ #define _LANTIQ_H__ #include +#include -/* generic reg access functions */ +/* generic reg access */ #define ltq_r32(reg) __raw_readl(reg) #define ltq_w32(val, reg) __raw_writel(val, reg) -#define ltq_w32_mask(clear, set, reg) \ - ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg) #define ltq_r8(reg) __raw_readb(reg) #define ltq_w8(val, reg) __raw_writeb(val, reg) - -/* register access macros for EBU and CGU */ -#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) -#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) -#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) -#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) - -extern __iomem void *ltq_ebu_membase; -extern __iomem void *ltq_cgu_membase; +static inline void ltq_w32_mask(u32 c, u32 s, volatile void __iomem *r) +{ + ltq_w32((ltq_r32(r) & ~(c)) | (s), r); +} extern unsigned int ltq_get_cpu_ver(void); extern unsigned int ltq_get_soc_type(void); @@ -51,7 +45,9 @@ extern void ltq_enable_irq(struct irq_data *data); /* find out what caused the last cpu reset */ extern int ltq_reset_cause(void); -#define LTQ_RST_CAUSE_WDTRST 0x20 + +/* helper for requesting and remapping resources */ +extern void __iomem *ltq_remap_resource(struct resource *res); #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 8a3c6be..001bf2e 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -61,6 +61,8 @@ #define LTQ_CGU_BASE_ADDR 0x1F103000 #define LTQ_CGU_SIZE 0x1000 +#define CGU_EPHY 0x10 + /* ICU - interrupt control unit */ #define LTQ_ICU_BASE_ADDR 0x1F880200 #define LTQ_ICU_SIZE 0x100 @@ -97,6 +99,8 @@ #define LTQ_WDT_BASE_ADDR 0x1F8803F0 #define LTQ_WDT_SIZE 0x10 +#define LTQ_RST_CAUSE_WDTRST 0x20 + /* STP - serial to parallel conversion unit */ #define LTQ_STP_BASE_ADDR 0x1E100BB0 #define LTQ_STP_SIZE 0x40 @@ -121,11 +125,43 @@ #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) +extern __iomem void *ltq_ebu_membase; +extern __iomem void *ltq_cgu_membase; + +/* ebu access */ +static inline void ltq_ebu_w32(u32 v, u32 r) +{ + ltq_w32(v, ltq_ebu_membase + r); +} +static inline u32 ltq_ebu_r32(u32 r) +{ + return ltq_r32(ltq_ebu_membase + r); +} +static inline void ltq_ebu_w32_mask(u32 c, u32 s, u32 r) +{ + ltq_ebu_w32((ltq_ebu_r32(r) & ~(c)) | (s), r); +} + +/* cgu access */ +static inline void ltq_cgu_w32(u32 v, u32 r) +{ + ltq_w32(v, ltq_cgu_membase + r); +} +static inline u32 ltq_cgu_r32(u32 r) +{ + return ltq_r32(ltq_cgu_membase + r); +} +static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) +{ + ltq_cgu_w32((ltq_cgu_r32(r) & ~(c)) | (s), r); +} + /* request a non-gpio and set the PIO config */ extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, unsigned int alt1, unsigned int dir, const char *name); extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); +extern void ltq_cgu_enable(unsigned int clk); static inline int ltq_is_ar9(void) { diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index 412814f..39eef7f 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -22,6 +22,7 @@ #include #include "clk.h" +#include "prom.h" struct clk { const char *name; @@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = { }, }; -static struct resource ltq_cgu_resource = { - .name = "cgu", - .start = LTQ_CGU_BASE_ADDR, - .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -/* remapped clock register range */ -void __iomem *ltq_cgu_membase; - void clk_init(void) { cpu_clk = cpu_clk_generic; @@ -133,21 +124,11 @@ void __init plat_time_init(void) { struct clk *clk; - if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) - panic("Failed to insert cgu memory"); - - if (request_mem_region(ltq_cgu_resource.start, - resource_size(<q_cgu_resource), "cgu") < 0) - panic("Failed to request cgu memory"); + ltq_soc_init(); - ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, - resource_size(<q_cgu_resource)); - if (!ltq_cgu_membase) { - pr_err("Failed to remap cgu memory\n"); - unreachable(); - } clk = clk_get(0, "cpu"); mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); write_c0_compare(read_c0_count()); + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); clk_put(clk); } diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c index de1cb2b..7193d78 100644 --- a/arch/mips/lantiq/devices.c +++ b/arch/mips/lantiq/devices.c @@ -27,12 +27,8 @@ #include "devices.h" /* nor flash */ -static struct resource ltq_nor_resource = { - .name = "nor", - .start = LTQ_FLASH_START, - .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_nor_resource = + MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX); static struct platform_device ltq_nor = { .name = "ltq_nor", @@ -47,12 +43,8 @@ void __init ltq_register_nor(struct physmap_flash_data *data) } /* watchdog */ -static struct resource ltq_wdt_resource = { - .name = "watchdog", - .start = LTQ_WDT_BASE_ADDR, - .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_wdt_resource = + MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE); void __init ltq_register_wdt(void) { @@ -61,24 +53,14 @@ void __init ltq_register_wdt(void) /* asc ports */ static struct resource ltq_asc0_resources[] = { - { - .name = "asc0", - .start = LTQ_ASC0_BASE_ADDR, - .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, + MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE), IRQ_RES(tx, LTQ_ASC_TIR(0)), IRQ_RES(rx, LTQ_ASC_RIR(0)), IRQ_RES(err, LTQ_ASC_EIR(0)), }; static struct resource ltq_asc1_resources[] = { - { - .name = "asc1", - .start = LTQ_ASC1_BASE_ADDR, - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, + MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), IRQ_RES(tx, LTQ_ASC_TIR(1)), IRQ_RES(rx, LTQ_ASC_RIR(1)), IRQ_RES(err, LTQ_ASC_EIR(1)), diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h index 2947bb1..18b65df 100644 --- a/arch/mips/lantiq/devices.h +++ b/arch/mips/lantiq/devices.h @@ -14,6 +14,10 @@ #define IRQ_RES(resname, irq) \ {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} +#define MEM_RES(resname, adr_start, adr_size) \ + { .name = resname, .flags = IORESOURCE_MEM, \ + .start = CPHYSADDR(adr_start), \ + .end = CPHYSADDR(adr_start + adr_size - 1) } extern void ltq_register_nor(struct physmap_flash_data *data); extern void ltq_register_wdt(void); diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index e34fcfd..528e205 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -16,6 +16,10 @@ #include "prom.h" #include "clk.h" +/* access to the ebu needs to be locked between different drivers */ +DEFINE_SPINLOCK(ebu_lock); +EXPORT_SYMBOL_GPL(ebu_lock); + static struct ltq_soc_info soc_info; unsigned int ltq_get_cpu_ver(void) @@ -55,16 +59,51 @@ static void __init prom_init_cmdline(void) } } -void __init prom_init(void) +void __iomem *ltq_remap_resource(struct resource *res) { - struct clk *clk; + __iomem void *ret = NULL; + struct resource *lookup = lookup_resource(&iomem_resource, res->start); + + if (lookup && strcmp(lookup->name, res->name)) { + pr_err("conflicting memory range %s\n", res->name); + return NULL; + } + if (!lookup) { + if (insert_resource(&iomem_resource, res) < 0) { + pr_err("Failed to insert %s memory\n", res->name); + return NULL; + } + } + if (request_mem_region(res->start, + resource_size(res), res->name) < 0) { + pr_err("Failed to request %s memory\n", res->name); + goto err_res; + } + ret = ioremap_nocache(res->start, resource_size(res)); + if (!ret) + goto err_mem; + + pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n", + res->start, res->end, res->name); + return ret; + +err_mem: + panic("Failed to remap %s memory", res->name); + release_mem_region(res->start, resource_size(res)); + +err_res: + release_resource(res); + return NULL; +} +EXPORT_SYMBOL(ltq_remap_resource); + +void __init prom_init(void) +{ ltq_soc_detect(&soc_info); clk_init(); - clk = clk_get(0, "cpu"); - snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", - soc_info.name, soc_info.rev); - clk_put(clk); + snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", + soc_info.name, soc_info.rev_type); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; pr_info("SoC: %s\n", soc_info.sys_type); prom_init_cmdline(); diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h index b4229d9..51dba1b 100644 --- a/arch/mips/lantiq/prom.h +++ b/arch/mips/lantiq/prom.h @@ -9,17 +9,21 @@ #ifndef _LTQ_PROM_H__ #define _LTQ_PROM_H__ +#define LTQ_SYS_REV_LEN 0x10 #define LTQ_SYS_TYPE_LEN 0x100 struct ltq_soc_info { unsigned char *name; unsigned int rev; + unsigned char rev_type[LTQ_SYS_REV_LEN]; + unsigned int srev; unsigned int partnum; unsigned int type; unsigned char sys_type[LTQ_SYS_TYPE_LEN]; }; extern void ltq_soc_detect(struct ltq_soc_info *i); +extern void ltq_soc_init(void); extern void ltq_soc_setup(void); #endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index c517f2e..6678402 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,7 +1,7 @@ -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c index d614aa7..f97e565 100644 --- a/arch/mips/lantiq/xway/devices.c +++ b/arch/mips/lantiq/xway/devices.c @@ -31,22 +31,9 @@ /* gpio */ static struct resource ltq_gpio_resource[] = { - { - .name = "gpio0", - .start = LTQ_GPIO0_BASE_ADDR, - .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "gpio1", - .start = LTQ_GPIO1_BASE_ADDR, - .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "gpio2", - .start = LTQ_GPIO2_BASE_ADDR, - .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1, - .flags = IORESOURCE_MEM, - } + MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE), + MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE), + MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE), }; void __init ltq_register_gpio(void) @@ -64,12 +51,8 @@ void __init ltq_register_gpio(void) } /* serial to parallel conversion */ -static struct resource ltq_stp_resource = { - .name = "stp", - .start = LTQ_STP_BASE_ADDR, - .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_stp_resource = + MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE); void __init ltq_register_gpio_stp(void) { @@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void) /* asc ports - amazon se has its own serial mapping */ static struct resource ltq_ase_asc_resources[] = { - { - .name = "asc0", - .start = LTQ_ASC1_BASE_ADDR, - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, + MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), IRQ_RES(tx, LTQ_ASC_ASE_TIR), IRQ_RES(rx, LTQ_ASC_ASE_RIR), IRQ_RES(err, LTQ_ASC_ASE_EIR), @@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void) } /* ethernet */ -static struct resource ltq_etop_resources = { - .name = "etop", - .start = LTQ_ETOP_BASE_ADDR, - .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_etop_resources = + MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE); static struct platform_device ltq_etop = { .name = "ltq_etop", diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index b210e93..6cf883b 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -24,6 +24,8 @@ #include #include +#include "../devices.h" + #define LTQ_DMA_CTRL 0x10 #define LTQ_DMA_CPOLL 0x14 #define LTQ_DMA_CS 0x18 @@ -55,12 +57,8 @@ #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ ltq_dma_membase + (z)) -static struct resource ltq_dma_resource = { - .name = "dma", - .start = LTQ_DMA_BASE_ADDR, - .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_dma_resource = + MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE); static void __iomem *ltq_dma_membase; @@ -220,17 +218,8 @@ ltq_dma_init(void) { int i; - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_dma_resource) < 0) - panic("Failed to insert dma memory"); - - if (request_mem_region(ltq_dma_resource.start, - resource_size(<q_dma_resource), "dma") < 0) - panic("Failed to request dma memory"); - /* remap dma register range */ - ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, - resource_size(<q_dma_resource)); + ltq_dma_membase = ltq_remap_resource(<q_dma_resource); if (!ltq_dma_membase) panic("Failed to remap dma memory"); diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c deleted file mode 100644 index 862e3e8..0000000 --- a/arch/mips/lantiq/xway/ebu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * EBU - the external bus unit attaches PCI, NOR and NAND - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include - -#include - -/* all access to the ebu must be locked */ -DEFINE_SPINLOCK(ebu_lock); -EXPORT_SYMBOL_GPL(ebu_lock); - -static struct resource ltq_ebu_resource = { - .name = "ebu", - .start = LTQ_EBU_BASE_ADDR, - .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -/* remapped base addr of the clock unit and external bus unit */ -void __iomem *ltq_ebu_membase; - -static int __init lantiq_ebu_init(void) -{ - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) - panic("Failed to insert ebu memory"); - - if (request_mem_region(ltq_ebu_resource.start, - resource_size(<q_ebu_resource), "ebu") < 0) - panic("Failed to request ebu memory"); - - /* remap ebu register range */ - ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, - resource_size(<q_ebu_resource)); - if (!ltq_ebu_membase) - panic("Failed to remap ebu memory"); - - /* make sure to unprotect the memory region where flash is located */ - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); - return 0; -} - -postcore_initcall(lantiq_ebu_init); diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c deleted file mode 100644 index fe85361..0000000 --- a/arch/mips/lantiq/xway/pmu.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include - -#include - -/* PMU - the power management unit allows us to turn part of the core - * on and off - */ - -/* the enable / disable registers */ -#define LTQ_PMU_PWDCR 0x1C -#define LTQ_PMU_PWDSR 0x20 - -#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) -#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) - -static struct resource ltq_pmu_resource = { - .name = "pmu", - .start = LTQ_PMU_BASE_ADDR, - .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static void __iomem *ltq_pmu_membase; - -void ltq_pmu_enable(unsigned int module) -{ - int err = 1000000; - - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); - do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); - - if (!err) - panic("activating PMU module failed!"); -} -EXPORT_SYMBOL(ltq_pmu_enable); - -void ltq_pmu_disable(unsigned int module) -{ - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); -} -EXPORT_SYMBOL(ltq_pmu_disable); - -int __init ltq_pmu_init(void) -{ - if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) - panic("Failed to insert pmu memory"); - - if (request_mem_region(ltq_pmu_resource.start, - resource_size(<q_pmu_resource), "pmu") < 0) - panic("Failed to request pmu memory"); - - ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, - resource_size(<q_pmu_resource)); - if (!ltq_pmu_membase) - panic("Failed to remap pmu memory"); - return 0; -} - -core_initcall(ltq_pmu_init); diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c index ae4959a..3f86a3b 100644 --- a/arch/mips/lantiq/xway/prom-ase.c +++ b/arch/mips/lantiq/xway/prom-ase.c @@ -13,6 +13,7 @@ #include +#include "devices.h" #include "../prom.h" #define SOC_AMAZON_SE "Amazon_SE" @@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) { i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); switch (i->partnum) { case SOC_ID_AMAZON_SE: i->name = SOC_AMAZON_SE; @@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) break; } } + +void __init ltq_soc_setup(void) +{ + ltq_register_ase_asc(); + ltq_register_gpio(); + ltq_register_wdt(); +} diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c index 2228133..d823a92 100644 --- a/arch/mips/lantiq/xway/prom-xway.c +++ b/arch/mips/lantiq/xway/prom-xway.c @@ -13,6 +13,7 @@ #include +#include "devices.h" #include "../prom.h" #define SOC_DANUBE "Danube" @@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) { i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); switch (i->partnum) { case SOC_ID_DANUBE1: case SOC_ID_DANUBE2: @@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) break; } } + +void __init ltq_soc_setup(void) +{ + ltq_register_asc(0); + ltq_register_asc(1); + ltq_register_gpio(); + ltq_register_wdt(); +} diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c index 8b66bd8..bd0b697 100644 --- a/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c @@ -15,6 +15,8 @@ #include +#include "../devices.h" + #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) @@ -25,12 +27,8 @@ #define LTQ_RCU_RST_STAT 0x0014 #define LTQ_RCU_STAT_SHIFT 26 -static struct resource ltq_rcu_resource = { - .name = "rcu", - .start = LTQ_RCU_BASE_ADDR, - .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource ltq_rcu_resource = + MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE); /* remapped base addr of the reset control unit */ static void __iomem *ltq_rcu_membase; @@ -45,7 +43,6 @@ EXPORT_SYMBOL_GPL(ltq_reset_cause); static void ltq_machine_restart(char *command) { - pr_notice("System restart\n"); local_irq_disable(); ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST); unreachable(); @@ -53,31 +50,20 @@ static void ltq_machine_restart(char *command) static void ltq_machine_halt(void) { - pr_notice("System halted.\n"); local_irq_disable(); unreachable(); } static void ltq_machine_power_off(void) { - pr_notice("Please turn off the power now.\n"); local_irq_disable(); unreachable(); } static int __init mips_reboot_setup(void) { - /* insert and request the memory region */ - if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) - panic("Failed to insert rcu memory"); - - if (request_mem_region(ltq_rcu_resource.start, - resource_size(<q_rcu_resource), "rcu") < 0) - panic("Failed to request rcu memory"); - /* remap rcu register range */ - ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, - resource_size(<q_rcu_resource)); + ltq_rcu_membase = ltq_remap_resource(<q_rcu_resource); if (!ltq_rcu_membase) panic("Failed to remap rcu memory"); diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c deleted file mode 100644 index f6f3267..0000000 --- a/arch/mips/lantiq/xway/setup-ase.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include - -#include "../prom.h" -#include "devices.h" - -void __init ltq_soc_setup(void) -{ - ltq_register_ase_asc(); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c deleted file mode 100644 index c292f64..0000000 --- a/arch/mips/lantiq/xway/setup-xway.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2011 John Crispin - */ - -#include - -#include "../prom.h" -#include "devices.h" - -void __init ltq_soc_setup(void) -{ - ltq_register_asc(0); - ltq_register_asc(1); - ltq_register_gpio(); - ltq_register_wdt(); -} diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c new file mode 100644 index 0000000..38c122f --- /dev/null +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -0,0 +1,78 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include + +#include + +#include "../devices.h" + +/* clock control register */ +#define LTQ_CGU_IFCCR 0x0018 + +/* the enable / disable registers */ +#define LTQ_PMU_PWDCR 0x1C +#define LTQ_PMU_PWDSR 0x20 + +#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) +#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) + +static struct resource ltq_cgu_resource = + MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); + +static struct resource ltq_pmu_resource = + MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); + +static struct resource ltq_ebu_resource = + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + +void __iomem *ltq_cgu_membase; +void __iomem *ltq_ebu_membase; +static void __iomem *ltq_pmu_membase; + +void ltq_cgu_enable(unsigned int clk) +{ + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR); +} + +void ltq_pmu_enable(unsigned int module) +{ + int err = 1000000; + + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); + do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); + + if (!err) + panic("activating PMU module failed!"); +} +EXPORT_SYMBOL(ltq_pmu_enable); + +void ltq_pmu_disable(unsigned int module) +{ + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); +} +EXPORT_SYMBOL(ltq_pmu_disable); + +void __init ltq_soc_init(void) +{ + ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource); + if (!ltq_pmu_membase) + panic("Failed to remap pmu memory"); + + ltq_cgu_membase = ltq_remap_resource(<q_cgu_resource); + if (!ltq_cgu_membase) + panic("Failed to remap cgu memory"); + + ltq_ebu_membase = ltq_remap_resource(<q_ebu_resource); + if (!ltq_ebu_membase) + panic("Failed to remap ebu memory"); + + /* make sure to unprotect the memory region where flash is located */ + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); +} diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c index 102aed0..179bf98 100644 --- a/drivers/watchdog/lantiq_wdt.c +++ b/drivers/watchdog/lantiq_wdt.c @@ -16,7 +16,7 @@ #include #include -#include +#include /* Section 3.4 of the datasheet * The password sequence protects the WDT control register from unintended -- 1.7.7.1 From blogic@openwrt.org Mon Jan 16 17:44:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 17:45:06 +0100 (CET) Received: from nbd.name ([46.4.11.11]:56220 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903613Ab2APQoY (ORCPT ); Mon, 16 Jan 2012 17:44:24 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH V2 04/17] MIPS: lantiq: add basic support for FALC-ON Date: Mon, 16 Jan 2012 17:43:39 +0100 Message-Id: <1326732224-21336-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326732224-21336-1-git-send-email-blogic@openwrt.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> X-archive-position: 32254 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35182 Lines: 1104 Adds support for the FALC-ON SoC. This SoC is from the FTTH/GPON SoC family. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- Changes in V2: * ritually kill printks that notify about reset * fixes code formatting of inline functions .../include/asm/mach-lantiq/falcon/falcon_irq.h | 268 ++++++++++++++++++++ arch/mips/include/asm/mach-lantiq/falcon/irq.h | 18 ++ .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 158 ++++++++++++ arch/mips/include/asm/mach-lantiq/lantiq.h | 1 + arch/mips/lantiq/Kconfig | 4 + arch/mips/lantiq/Makefile | 1 + arch/mips/lantiq/Platform | 1 + arch/mips/lantiq/falcon/Makefile | 1 + arch/mips/lantiq/falcon/clk.c | 44 ++++ arch/mips/lantiq/falcon/devices.c | 87 +++++++ arch/mips/lantiq/falcon/devices.h | 18 ++ arch/mips/lantiq/falcon/prom.c | 93 +++++++ arch/mips/lantiq/falcon/reset.c | 88 +++++++ arch/mips/lantiq/falcon/sysctrl.c | 183 +++++++++++++ 14 files changed, 965 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h create mode 100644 arch/mips/lantiq/falcon/Makefile create mode 100644 arch/mips/lantiq/falcon/clk.c create mode 100644 arch/mips/lantiq/falcon/devices.c create mode 100644 arch/mips/lantiq/falcon/devices.h create mode 100644 arch/mips/lantiq/falcon/prom.c create mode 100644 arch/mips/lantiq/falcon/reset.c create mode 100644 arch/mips/lantiq/falcon/sysctrl.c diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h new file mode 100644 index 0000000..4dc6466 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h @@ -0,0 +1,268 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer + */ + +#ifndef _FALCON_IRQ__ +#define _FALCON_IRQ__ + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define MIPS_CPU_TIMER_IRQ 7 + +/* HOST IF Event Interrupt */ +#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0) +/* HOST IF Mailbox0 Receive Interrupt */ +#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1) +/* HOST IF Mailbox0 Transmit Interrupt */ +#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2) +/* HOST IF Mailbox1 Receive Interrupt */ +#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3) +/* HOST IF Mailbox1 Transmit Interrupt */ +#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4) +/* I2C Last Single Data Transfer Request */ +#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8) +/* I2C Single Data Transfer Request */ +#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9) +/* I2C Last Burst Data Transfer Request */ +#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10) +/* I2C Burst Data Transfer Request */ +#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11) +/* I2C Error Interrupt */ +#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12) +/* I2C Protocol Interrupt */ +#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13) +/* SSC Transmit Interrupt */ +#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14) +/* SSC Receive Interrupt */ +#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15) +/* SSC Error Interrupt */ +#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16) +/* SSC Frame Interrupt */ +#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17) +/* Advanced Encryption Standard Interrupt */ +#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27) +/* Secure Hash Algorithm Interrupt */ +#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28) +/* PCM Receive Interrupt */ +#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29) +/* PCM Transmit Interrupt */ +#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30) +/* PCM Transmit Crash Interrupt */ +#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31) + +/* EBU Serial Flash Command Error */ +#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0) +/* EBU Serial Flash Command Overwrite Error */ +#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1) +/* EBU Serial Flash Busy */ +#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2) +/* External Interrupt from GPIO P0 */ +#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4) +/* External Interrupt from GPIO P1 */ +#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5) +/* External Interrupt from GPIO P2 */ +#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6) +/* External Interrupt from GPIO P3 */ +#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7) +/* External Interrupt from GPIO P4 */ +#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8) +/* 8kHz backup interrupt derived from core-PLL */ +#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10) +/* FSC Timer Interrupt 0 */ +#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11) +/* FSC Timer Interrupt 1 */ +#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12) +/* 8kHz root interrupt derived from GPON interface */ +#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13) +/* Time of Day */ +#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14) +/* PMA Interrupt from IntNode of the 200MHz Domain */ +#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15) +/* PMA Interrupt from IntNode of the TX Clk Domain */ +#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16) +/* PMA Interrupt from IntNode of the RX Clk Domain */ +#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17) +/* SYS1 Interrupt */ +#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20) +/* SYS GPE Interrupt */ +#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21) +/* Watchdog Access Error Interrupt */ +#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24) +/* Watchdog Prewarning Interrupt */ +#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25) +/* SBIU interrupt */ +#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27) +/* FPI Bus Control Unit Interrupt */ +#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29) +/* DDR Controller Interrupt */ +#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30) +/* Crossbar Error Interrupt */ +#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31) + +/* ICTRLL 0 Interrupt */ +#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0) +/* ICTRLL 1 Interrupt */ +#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1) +/* ICTRLL 2 Interrupt */ +#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2) +/* ICTRLL 3 Interrupt */ +#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3) +/* OCTRLL 0 Interrupt */ +#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4) +/* OCTRLL 1 Interrupt */ +#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5) +/* OCTRLL 2 Interrupt */ +#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6) +/* OCTRLL 3 Interrupt */ +#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7) +/* OCTRLG Interrupt */ +#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9) +/* IQM Interrupt */ +#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10) +/* FSQM Interrupt */ +#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11) +/* TMU Interrupt */ +#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12) +/* LINK1 Interrupt */ +#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14) +/* ICTRLC 0 Interrupt */ +#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16) +/* ICTRLC 1 Interrupt */ +#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17) +/* OCTRLC Interrupt */ +#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18) +/* CONFIG Break Interrupt */ +#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19) +/* CONFIG Interrupt */ +#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20) +/* Dispatcher Interrupt */ +#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21) +/* TBM Interrupt */ +#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22) +/* GTC Downstream Interrupt */ +#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29) +/* GTC Upstream Interrupt */ +#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30) +/* EIM Interrupt */ +#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31) + +/* ASC0 Transmit Interrupt */ +#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0) +/* ASC0 Receive Interrupt */ +#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1) +/* ASC0 Error Interrupt */ +#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2) +/* ASC0 Transmit Buffer Interrupt */ +#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3) +/* ASC0 Autobaud Start Interrupt */ +#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4) +/* ASC0 Autobaud Detection Interrupt */ +#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5) +/* ASC1 Modem Status Interrupt */ +#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6) +/* ASC0 Soft Flow Control Interrupt */ +#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7) +/* ASC1 Transmit Interrupt */ +#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8) +/* ASC1 Receive Interrupt */ +#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9) +/* ASC1 Error Interrupt */ +#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10) +/* ASC1 Transmit Buffer Interrupt */ +#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11) +/* ASC1 Autobaud Start Interrupt */ +#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12) +/* ASC1 Autobaud Detection Interrupt */ +#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13) +/* ASC1 Modem Status Interrupt */ +#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14) +/* ASC1 Soft Flow Control Interrupt */ +#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15) +/* GPTC Timer/Counter 1A Interrupt */ +#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16) +/* GPTC Timer/Counter 1B Interrupt */ +#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17) +/* GPTC Timer/Counter 2A Interrupt */ +#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18) +/* GPTC Timer/Counter 2B Interrupt */ +#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19) +/* GPTC Timer/Counter 3A Interrupt */ +#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20) +/* GPTC Timer/Counter 3B Interrupt */ +#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21) +/* DFEV0, Channel 1 Transmit Interrupt */ +#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26) +/* DFEV0, Channel 1 Receive Interrupt */ +#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27) +/* DFEV0, Channel 1 General Purpose Interrupt */ +#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28) +/* DFEV0, Channel 0 Transmit Interrupt */ +#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29) +/* DFEV0, Channel 0 Receive Interrupt */ +#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30) +/* DFEV0, Channel 0 General Purpose Interrupt */ +#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31) + +/* ICTRLL 0 Error */ +#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0) +/* ICTRLL 1 Error */ +#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1) +/* ICTRLL 2 Error */ +#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2) +/* ICTRLL 3 Error */ +#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3) +/* OCTRLL 0 Error */ +#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4) +/* OCTRLL 1 Error */ +#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5) +/* OCTRLL 2 Error */ +#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6) +/* OCTRLL 3 Error */ +#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7) +/* ICTRLG Error */ +#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8) +/* OCTRLG Error */ +#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9) +/* IQM Error */ +#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10) +/* FSQM Error */ +#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11) +/* TMU Error */ +#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12) +/* MPS Status Interrupt #0 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14) +/* MPS Status Interrupt #1 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15) +/* MPS Status Interrupt #2 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16) +/* MPS Status Interrupt #3 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17) +/* MPS Status Interrupt #4 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18) +/* MPS Status Interrupt #5 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19) +/* MPS Status Interrupt #6 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20) +/* MPS Status Interrupt #7 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21) +/* MPS Status Interrupt #8 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22) +/* VPE0 Exception Level Flag Interrupt */ +#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29) +/* VPE0 Error Level Flag Interrupt */ +#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30) +/* VPE0 Performance Monitoring Counter Interrupt */ +#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31) + +#endif /* _FALCON_IRQ__ */ diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h new file mode 100644 index 0000000..2caccd9 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + */ + +#ifndef __FALCON_IRQ_H +#define __FALCON_IRQ_H + +#include + +#define NR_IRQS 328 + +#include_next + +#endif diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h new file mode 100644 index 0000000..8ac509a --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -0,0 +1,158 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_FALCON_H__ +#define _LTQ_FALCON_H__ + +#ifdef CONFIG_SOC_FALCON + +#include + +/* Chip IDs */ +#define SOC_ID_FALCON 0x01B8 + +/* SoC Types */ +#define SOC_TYPE_FALCON 0x01 + +/* ASC0/1 - serial port */ +#define LTQ_ASC0_BASE_ADDR 0x1E100C00 +#define LTQ_ASC1_BASE_ADDR 0x1E100B00 +#define LTQ_ASC_SIZE 0x100 + +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) + +/* + * during early_printk no ioremap possible at this early stage + * lets use KSEG1 instead + */ +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) + +/* ICU - interrupt control unit */ +#define LTQ_ICU_BASE_ADDR 0x1F880200 +#define LTQ_ICU_SIZE 0x100 + +/* WDT */ +#define LTQ_WDT_BASE_ADDR 0x1F8803F0 +#define LTQ_WDT_SIZE 0x10 + +#define LTQ_RST_CAUSE_WDTRST 0x0002 + +/* EBU - external bus unit */ +#define LTQ_EBU_BASE_ADDR 0x18000000 +#define LTQ_EBU_SIZE 0x0100 + +#define LTQ_EBU_MODCON 0x000C + +/* GPIO */ +#define LTQ_GPIO0_BASE_ADDR 0x1D810000 +#define LTQ_GPIO0_SIZE 0x0080 +#define LTQ_GPIO1_BASE_ADDR 0x1E800100 +#define LTQ_GPIO1_SIZE 0x0080 +#define LTQ_GPIO2_BASE_ADDR 0x1D810100 +#define LTQ_GPIO2_SIZE 0x0080 +#define LTQ_GPIO3_BASE_ADDR 0x1E800200 +#define LTQ_GPIO3_SIZE 0x0080 +#define LTQ_GPIO4_BASE_ADDR 0x1E800300 +#define LTQ_GPIO4_SIZE 0x0080 +#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000 +#define LTQ_PADCTRL0_SIZE 0x0100 +#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400 +#define LTQ_PADCTRL1_SIZE 0x0100 +#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000 +#define LTQ_PADCTRL2_SIZE 0x0100 +#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500 +#define LTQ_PADCTRL3_SIZE 0x0100 +#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 +#define LTQ_PADCTRL4_SIZE 0x0100 + +/* CHIP ID */ +#define LTQ_STATUS_BASE_ADDR 0x1E802000 + +#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) +#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) +#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) + +/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ +#define LTQ_SYS1_BASE_ADDR 0x1EF00000 +#define LTQ_SYS1_SIZE 0x0100 +#define LTQ_STATUS_BASE_ADDR 0x1E802000 +#define LTQ_STATUS_SIZE 0x0080 +#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000 +#define LTQ_SYS_ETH_SIZE 0x0100 +#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000 +#define LTQ_SYS_GPE_SIZE 0x0100 + +#define SYSCTL_SYS1 0 +#define SYSCTL_SYSETH 1 +#define SYSCTL_SYSGPE 2 + +/* Activation Status Register */ +#define ACTS_ASC1_ACT 0x00000800 +#define ACTS_P0 0x00010000 +#define ACTS_P1 0x00010000 +#define ACTS_P2 0x00020000 +#define ACTS_P3 0x00020000 +#define ACTS_P4 0x00040000 +#define ACTS_PADCTRL0 0x00100000 +#define ACTS_PADCTRL1 0x00100000 +#define ACTS_PADCTRL2 0x00200000 +#define ACTS_PADCTRL3 0x00200000 +#define ACTS_PADCTRL4 0x00400000 + +extern void ltq_sysctl_activate(int module, unsigned int mask); +extern void ltq_sysctl_deactivate(int module, unsigned int mask); +extern void ltq_sysctl_clken(int module, unsigned int mask); +extern void ltq_sysctl_clkdis(int module, unsigned int mask); +extern void ltq_sysctl_reboot(int module, unsigned int mask); +extern int ltq_gpe_is_activated(unsigned int mask); + +/* global register ranges */ +extern void __iomem *ltq_ebu_membase; +extern void __iomem *ltq_sys1_membase; +static inline void ltq_ebu_w32(u32 v, u32 r) +{ + ltq_w32(v, ltq_ebu_membase + r); +} +static inline u32 ltq_ebu_r32(u32 r) +{ + return ltq_r32(ltq_ebu_membase + r); +} +static inline void ltq_ebu_w32_mask(u32 c, u32 s, u32 r) +{ + ltq_ebu_w32((ltq_ebu_r32(r) & ~(c)) | (s), r); +} +static inline void ltq_sys1_w32(u32 v, u32 r) +{ + ltq_w32(v, ltq_sys1_membase + r); +} +static inline u32 ltq_sys1_r32(u32 r) +{ + return ltq_r32(ltq_sys1_membase + r); +} +static inline void ltq_sys1_w32_mask(u32 c, u32 s, u32 r) +{ + ltq_sys1_w32((ltq_sys1_r32(r) & ~(c)) | (s), r); +} + +/* gpio_request wrapper to help configure the pin */ +extern int ltq_gpio_request(unsigned int pin, unsigned int mux, + unsigned int dir, const char *name); +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); + +/* to keep the irq code generic we need to define these to 0 as falcon + has no EIU/EBU */ +#define LTQ_EIU_BASE_ADDR 0 +#define LTQ_EBU_PCC_ISTAT 0 + +#define ltq_is_ar9() 0 +#define ltq_is_vr9() 0 + +#endif /* CONFIG_SOC_FALCON */ +#endif /* _LTQ_XWAY_H__ */ diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index 5bdec4f..bf05854 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -27,6 +27,7 @@ extern unsigned int ltq_get_soc_type(void); /* clock speeds */ #define CLOCK_60M 60000000 #define CLOCK_83M 83333333 +#define CLOCK_100M 100000000 #define CLOCK_111M 111111111 #define CLOCK_133M 133333333 #define CLOCK_167M 166666667 diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 3fccf21..cb6b39f 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -16,8 +16,12 @@ config SOC_XWAY bool "XWAY" select SOC_TYPE_XWAY select HW_HAS_PCI + +config SOC_FALCON + bool "FALCON" endchoice source "arch/mips/lantiq/xway/Kconfig" +source "arch/mips/lantiq/falcon/Kconfig" endif diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index e5dae0e..7e9c69e 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devices.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ +obj-$(CONFIG_SOC_FALCON) += falcon/ diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform index f3dff05..b3ec498 100644 --- a/arch/mips/lantiq/Platform +++ b/arch/mips/lantiq/Platform @@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/ cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq load-$(CONFIG_LANTIQ) = 0xffffffff80002000 cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway +cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile new file mode 100644 index 0000000..e9c7455 --- /dev/null +++ b/arch/mips/lantiq/falcon/Makefile @@ -0,0 +1 @@ +obj-y := clk.o prom.o reset.o sysctrl.o devices.o diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c new file mode 100644 index 0000000..afe1b52 --- /dev/null +++ b/arch/mips/lantiq/falcon/clk.c @@ -0,0 +1,44 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include + +#include + +#include "devices.h" + +/* CPU0 Clock Control Register */ +#define LTQ_SYS1_CPU0CC 0x0040 +/* clock divider bit */ +#define LTQ_CPU0CC_CPUDIV 0x0001 + +unsigned int +ltq_get_io_region_clock(void) +{ + return CLOCK_200M; +} +EXPORT_SYMBOL(ltq_get_io_region_clock); + +unsigned int +ltq_get_cpu_hz(void) +{ + if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) + return CLOCK_200M; + else + return CLOCK_400M; +} +EXPORT_SYMBOL(ltq_get_cpu_hz); + +unsigned int +ltq_get_fpi_hz(void) +{ + return CLOCK_100M; +} +EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c new file mode 100644 index 0000000..c4606f2 --- /dev/null +++ b/arch/mips/lantiq/falcon/devices.c @@ -0,0 +1,87 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include + +#include + +#include "devices.h" + +/* nand flash */ +/* address lines used for NAND control signals */ +#define NAND_ADDR_ALE 0x10000 +#define NAND_ADDR_CLE 0x20000 +/* Ready/Busy Status */ +#define MODCON_STS 0x0002 +/* Ready/Busy Status Edge */ +#define MODCON_STSEDGE 0x0004 + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static int +falcon_nand_ready(struct mtd_info *mtd) +{ + u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON); + + return (((modcon & (MODCON_STS | MODCON_STSEDGE)) == + (MODCON_STS | MODCON_STSEDGE))); +} + +static void +falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE); + + if (ctrl & NAND_CLE) + nandaddr |= NAND_ADDR_CLE; + if (ctrl & NAND_ALE) + nandaddr |= NAND_ADDR_ALE; + + this->IO_ADDR_W = (void __iomem *) nandaddr; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static struct platform_nand_data falcon_flash_nand_data = { + .chip = { + .nr_chips = 1, + .chip_delay = 25, + .part_probe_types = part_probes, + }, + .ctrl = { + .cmd_ctrl = falcon_hwcontrol, + .dev_ready = falcon_nand_ready, + } +}; + +static struct resource ltq_nand_res = + MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX); + +static struct platform_device ltq_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = <q_nand_res, + .dev = { + .platform_data = &falcon_flash_nand_data, + }, +}; + +void __init +falcon_register_nand(void) +{ + platform_device_register(<q_flash_nand); +} diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h new file mode 100644 index 0000000..e802a7c --- /dev/null +++ b/arch/mips/lantiq/falcon/devices.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#ifndef _FALCON_DEVICES_H__ +#define _FALCON_DEVICES_H__ + +#include "../devices.h" + +extern void falcon_register_nand(void); + +#endif diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c new file mode 100644 index 0000000..b50d6f9 --- /dev/null +++ b/arch/mips/lantiq/falcon/prom.c @@ -0,0 +1,93 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include + +#include "devices.h" + +#include "../prom.h" + +#define SOC_FALCON "Falcon" +#define SOC_FALCON_D "Falcon-D" +#define SOC_FALCON_V "Falcon-V" +#define SOC_FALCON_M "Falcon-M" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFF000 +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 +#define SREV_SHIFT 22 +#define SREV_MASK 0x03C00000 +#define TYPE_SHIFT 26 +#define TYPE_MASK 0x3C000000 + +#define MUXC_SIF_RX_PIN 112 +#define MUXC_SIF_TX_PIN 113 + +/* this parameter allows us enable/disable asc1 via commandline */ +static int register_asc1; +static int __init +ltq_parse_asc1(char *p) +{ + register_asc1 = 1; + return 0; +} +__setup("use_asc1", ltq_parse_asc1); + +void __init +ltq_soc_setup(void) +{ + ltq_register_asc(0); + ltq_register_wdt(); + falcon_register_gpio(); + if (register_asc1) { + ltq_register_asc(1); + if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx")) + pr_err("failed to request asc1-rx"); + if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx")) + pr_err("failed to request asc1-tx"); + ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT); + } +} + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + u32 type; + i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; + i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT); + sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), + i->rev & 0x7, (i->srev & 0x3) + 1); + + switch (i->partnum) { + case SOC_ID_FALCON: + type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT; + switch (type) { + case 0: + i->name = SOC_FALCON_D; + break; + case 1: + i->name = SOC_FALCON_V; + break; + case 2: + i->name = SOC_FALCON_M; + break; + default: + i->name = SOC_FALCON; + break; + } + i->type = SOC_TYPE_FALCON; + break; + + default: + unreachable(); + break; + } +} diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c new file mode 100644 index 0000000..6d829af --- /dev/null +++ b/arch/mips/lantiq/falcon/reset.c @@ -0,0 +1,88 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include + +#include + +/* CPU0 Reset Source Register */ +#define LTQ_SYS1_CPU0RS 0x0040 +/* reset cause mask */ +#define LTQ_CPU0RS_MASK 0x0003 + +int +ltq_reset_cause(void) +{ + return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK; +} +EXPORT_SYMBOL_GPL(ltq_reset_cause); + +#define BOOT_REG_BASE (KSEG1 | 0x1F200000) +#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) +#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) +#define BOOT_PW1 0x4C545100 +#define BOOT_PW2 0x0051544C + +#define WDT_REG_BASE (KSEG1 | 0x1F8803F0) +#define WDT_PW1 0x00BE0000 +#define WDT_PW2 0x00DC0000 + +static void +ltq_machine_restart(char *command) +{ + local_irq_disable(); + + /* reboot magic */ + ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ + ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ + ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ + + /* watchdog magic */ + ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); + ltq_w32(WDT_PW2 | + (0x3 << 26) | /* PWL */ + (0x2 << 24) | /* CLKDIV */ + (0x1 << 31) | /* enable */ + (1), /* reload */ + (void *)WDT_REG_BASE); + /* + * Dont call unreachable(); here as we need to wait for the watchdog + * to trigger. + */ + do {} while (1); +} + +static void +ltq_machine_halt(void) +{ + local_irq_disable(); + unreachable(); +} + +static void +ltq_machine_power_off(void) +{ + local_irq_disable(); + unreachable(); +} + +static int __init +mips_reboot_setup(void) +{ + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c new file mode 100644 index 0000000..905a142 --- /dev/null +++ b/arch/mips/lantiq/falcon/sysctrl.c @@ -0,0 +1,183 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include + +#include + +#include "devices.h" + +/* infrastructure control register */ +#define SYS1_INFRAC 0x00bc +/* Configuration fuses for drivers and pll */ +#define STATUS_CONFIG 0x0040 + +/* GPE frequency selection */ +#define GPPC_OFFSET 24 +#define GPEFREQ_MASK 0x00000C0 +#define GPEFREQ_OFFSET 10 +/* Clock status register */ +#define LTQ_SYSCTL_CLKS 0x0000 +/* Clock enable register */ +#define LTQ_SYSCTL_CLKEN 0x0004 +/* Clock clear register */ +#define LTQ_SYSCTL_CLKCLR 0x0008 +/* Activation Status Register */ +#define LTQ_SYSCTL_ACTS 0x0020 +/* Activation Register */ +#define LTQ_SYSCTL_ACT 0x0024 +/* Deactivation Register */ +#define LTQ_SYSCTL_DEACT 0x0028 +/* reboot Register */ +#define LTQ_SYSCTL_RBT 0x002c + +static struct resource ltq_sysctl_res[] = { + MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), + MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE), + MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE), +}; + +static struct resource ltq_status_res = + MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE); +static struct resource ltq_ebu_res = + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + +static void __iomem *ltq_sysctl[3]; +static void __iomem *ltq_status_membase; +void __iomem *ltq_sys1_membase; +void __iomem *ltq_ebu_membase; + +#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y)) +#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x)) +#define ltq_reg_w32_mask(m, clear, set, reg) \ + ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg) + +#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y)) +#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) + +static inline void +ltq_sysctl_wait(int module, unsigned int mask, + unsigned int test, unsigned int reg) +{ + int err = 1000000; + + do {} while (--err && ((ltq_reg_r32(module, reg) + & mask) != test)); + if (!err) + pr_err("module de/activation failed %d %08X %08X\n", + module, mask, test); +} + +void +ltq_sysctl_activate(int module, unsigned int mask) +{ + if (module > SYSCTL_SYSGPE) + return; + + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); +} +EXPORT_SYMBOL(ltq_sysctl_activate); + +void +ltq_sysctl_deactivate(int module, unsigned int mask) +{ + if (module > SYSCTL_SYSGPE) + return; + + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); + ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT); + ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS); +} +EXPORT_SYMBOL(ltq_sysctl_deactivate); + +void +ltq_sysctl_clken(int module, unsigned int mask) +{ + if (module > SYSCTL_SYSGPE) + return; + + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS); +} +EXPORT_SYMBOL(ltq_sysctl_clken); + +void +ltq_sysctl_clkdis(int module, unsigned int mask) +{ + if (module > SYSCTL_SYSGPE) + return; + + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); + ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS); +} +EXPORT_SYMBOL(ltq_sysctl_clkdis); + +void +ltq_sysctl_reboot(int module, unsigned int mask) +{ + unsigned int act; + + if (module > SYSCTL_SYSGPE) + return; + + act = ltq_reg_r32(module, LTQ_SYSCTL_ACT); + if ((~act & mask) != 0) + ltq_sysctl_activate(module, ~act & mask); + ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT); + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); +} +EXPORT_SYMBOL(ltq_sysctl_reboot); + +/* enable the ONU core */ +static void +ltq_gpe_enable(void) +{ + unsigned int freq; + unsigned int status; + + /* if if the clock is already enabled */ + status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC); + if (status & (1 << (GPPC_OFFSET + 1))) + return; + + if (ltq_status_r32(STATUS_CONFIG) == 0) + freq = 1; /* use 625MHz on unfused chip */ + else + freq = (ltq_status_r32(STATUS_CONFIG) & + GPEFREQ_MASK) >> + GPEFREQ_OFFSET; + + /* apply new frequency */ + ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), + freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); + udelay(1); + + /* enable new frequency */ + ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); + udelay(1); +} + +void __init +ltq_soc_init(void) +{ + int i; + + for (i = 0; i < 3; i++) + ltq_sysctl[i] = ltq_remap_resource(<q_sysctl_res[i]); + + ltq_sys1_membase = ltq_sysctl[0]; + ltq_status_membase = ltq_remap_resource(<q_status_res); + ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); + + ltq_gpe_enable(); +} -- 1.7.7.1 From blogic@openwrt.org Mon Jan 16 17:44:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 17:45:32 +0100 (CET) Received: from nbd.name ([46.4.11.11]:56222 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903621Ab2APQoY (ORCPT ); Mon, 16 Jan 2012 17:44:24 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Thomas Langer Subject: [PATCH V2 05/17] MIPS: lantiq: add support for FALC-ON GPIOs Date: Mon, 16 Jan 2012 17:43:40 +0100 Message-Id: <1326732224-21336-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326732224-21336-1-git-send-email-blogic@openwrt.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> X-archive-position: 32255 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14529 Lines: 500 FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds the new driver. Signed-off-by: Thomas Langer Signed-off-by: John Crispin --- Changes in V2 * fixes parentheses breakage inside a macro arch/mips/lantiq/falcon/Makefile | 2 +- arch/mips/lantiq/falcon/devices.c | 41 ++++ arch/mips/lantiq/falcon/devices.h | 2 + arch/mips/lantiq/falcon/gpio.c | 399 +++++++++++++++++++++++++++++++++++++ 4 files changed, 443 insertions(+), 1 deletions(-) create mode 100644 arch/mips/lantiq/falcon/gpio.c diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile index e9c7455..de72209 100644 --- a/arch/mips/lantiq/falcon/Makefile +++ b/arch/mips/lantiq/falcon/Makefile @@ -1 +1 @@ -obj-y := clk.o prom.o reset.o sysctrl.o devices.o +obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c index c4606f2..4f47b44 100644 --- a/arch/mips/lantiq/falcon/devices.c +++ b/arch/mips/lantiq/falcon/devices.c @@ -9,6 +9,7 @@ #include #include +#include #include @@ -85,3 +86,43 @@ falcon_register_nand(void) { platform_device_register(<q_flash_nand); } + +/* gpio */ +#define DECLARE_GPIO_RES(port) \ +static struct resource falcon_gpio ## port ## _res[] = { \ + MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \ + LTQ_GPIO ## port ## _SIZE), \ + MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \ + LTQ_PADCTRL ## port ## _SIZE), \ + IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \ +} +DECLARE_GPIO_RES(0); +DECLARE_GPIO_RES(1); +DECLARE_GPIO_RES(2); +DECLARE_GPIO_RES(3); +DECLARE_GPIO_RES(4); + +void __init +falcon_register_gpio(void) +{ + platform_device_register_simple("falcon_gpio", 0, + falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res)); + platform_device_register_simple("falcon_gpio", 1, + falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); + platform_device_register_simple("falcon_gpio", 2, + falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); + ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); + ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 | + ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2); +} + +void __init +falcon_register_gpio_extra(void) +{ + platform_device_register_simple("falcon_gpio", 3, + falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); + platform_device_register_simple("falcon_gpio", 4, + falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); + ltq_sysctl_activate(SYSCTL_SYS1, + ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4); +} diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h index e802a7c..18be8b6 100644 --- a/arch/mips/lantiq/falcon/devices.h +++ b/arch/mips/lantiq/falcon/devices.h @@ -14,5 +14,7 @@ #include "../devices.h" extern void falcon_register_nand(void); +extern void falcon_register_gpio(void); +extern void falcon_register_gpio_extra(void); #endif diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c new file mode 100644 index 0000000..3eebd51 --- /dev/null +++ b/arch/mips/lantiq/falcon/gpio.c @@ -0,0 +1,399 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include + +#include + +/* Multiplexer Control Register */ +#define LTQ_PADC_MUX(x) ((x) * 0x4) +/* Pad Control Availability Register */ +#define LTQ_PADC_AVAIL 0x000000F0 + +/* Data Output Register */ +#define LTQ_GPIO_OUT 0x00000000 +/* Data Input Register */ +#define LTQ_GPIO_IN 0x00000004 +/* Direction Register */ +#define LTQ_GPIO_DIR 0x00000008 +/* External Interrupt Control Register 0 */ +#define LTQ_GPIO_EXINTCR0 0x00000018 +/* External Interrupt Control Register 1 */ +#define LTQ_GPIO_EXINTCR1 0x0000001C +/* IRN Capture Register */ +#define LTQ_GPIO_IRNCR 0x00000020 +/* IRN Interrupt Configuration Register */ +#define LTQ_GPIO_IRNCFG 0x0000002C +/* IRN Interrupt Enable Set Register */ +#define LTQ_GPIO_IRNRNSET 0x00000030 +/* IRN Interrupt Enable Clear Register */ +#define LTQ_GPIO_IRNENCLR 0x00000034 +/* Output Set Register */ +#define LTQ_GPIO_OUTSET 0x00000040 +/* Output Cler Register */ +#define LTQ_GPIO_OUTCLR 0x00000044 +/* Direction Clear Register */ +#define LTQ_GPIO_DIRSET 0x00000048 +/* Direction Set Register */ +#define LTQ_GPIO_DIRCLR 0x0000004C + +/* turn a gpio_chip into a falcon_gpio_port */ +#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip) +/* turn a irq_data into a falcon_gpio_port */ +#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq)) + +#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg) +#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg) +#define ltq_pad_w32_mask(c, clear, set, reg) \ + ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg) + +#define ltq_port_r32(p, reg) ltq_r32(p->port + reg) +#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg) +#define ltq_port_w32_mask(p, clear, set, reg) \ + ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg) + +#define MAX_PORTS 5 +#define PINS_PER_PORT 32 + +struct falcon_gpio_port { + struct gpio_chip gpio_chip; + void __iomem *pad; + void __iomem *port; + unsigned int irq_base; + unsigned int chained_irq; +}; + +static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; + +int gpio_to_irq(unsigned int gpio) +{ + return __gpio_to_irq(gpio); +} +EXPORT_SYMBOL(gpio_to_irq); + +int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) +{ + int port = pin / 100; + int offset = pin % 100; + struct falcon_gpio_port *gpio_port; + + if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS)) + return -EINVAL; + + gpio_port = <q_gpio_port[port]; + ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset)); + + return 0; +} +EXPORT_SYMBOL(ltq_gpio_mux_set); + +int ltq_gpio_request(unsigned int pin, unsigned int mux, + unsigned int dir, const char *name) +{ + int port = pin / 100; + int offset = pin % 100; + + if (offset >= PINS_PER_PORT || port >= MAX_PORTS) + return -EINVAL; + + if (gpio_request(pin, name)) { + pr_err("failed to setup lantiq gpio: %s\n", name); + return -EBUSY; + } + + if (dir) + gpio_direction_output(pin, 1); + else + gpio_direction_input(pin); + + return ltq_gpio_mux_set(pin, mux); +} +EXPORT_SYMBOL(ltq_gpio_request); + +static int +falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR); + + return 0; +} + +static void +falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + if (value) + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET); + else + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR); +} + +static int +falcon_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + falcon_gpio_set(chip, offset, value); + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET); + + return 0; +} + +static int +falcon_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1) + return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1; + else + return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1; +} + +static int +falcon_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { + if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) + return -EBUSY; + /* switch on gpio function */ + ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset)); + return 0; + } + + return -ENODEV; +} + +static void +falcon_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { + if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) + return; + /* switch off gpio function */ + ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset)); + } +} + +static int +falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return ctop(chip)->irq_base + offset; +} + +static void +falcon_gpio_disable_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); +} + +static void +falcon_gpio_enable_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1) + /* switch on gpio function */ + ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset)); + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET); +} + +static void +falcon_gpio_ack_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); +} + +static void +falcon_gpio_mask_and_ack_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); +} + +static struct irq_chip falcon_gpio_irq_chip; +static int +falcon_gpio_irq_type(struct irq_data *d, unsigned int type) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + unsigned int mask = 1 << offset; + + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) + return 0; + + if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) { + /* level triggered */ + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG); + irq_set_chip_and_handler_name(d->irq, + &falcon_gpio_irq_chip, handle_level_irq, "mux"); + } else { + /* edge triggered */ + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG); + irq_set_chip_and_handler_name(d->irq, + &falcon_gpio_irq_chip, handle_simple_irq, "mux"); + } + + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1); + } else { + if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0) + /* positive logic: rising edge, high level */ + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); + else + /* negative logic: falling edge, low level */ + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0); + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1); + } + + return gpio_direction_input(itop(d)->gpio_chip.base + offset); +} + +static void +falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc); + unsigned long irncr; + int offset; + + /* acknowledge interrupt */ + irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR); + ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR); + + desc->irq_data.chip->irq_ack(&desc->irq_data); + + for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio) + generic_handle_irq(gpio_port->irq_base + offset); +} + +static struct irq_chip falcon_gpio_irq_chip = { + .name = "gpio_irq_mux", + .irq_mask = falcon_gpio_disable_irq, + .irq_unmask = falcon_gpio_enable_irq, + .irq_ack = falcon_gpio_ack_irq, + .irq_mask_ack = falcon_gpio_mask_and_ack_irq, + .irq_set_type = falcon_gpio_irq_type, +}; + +static struct irqaction gpio_cascade = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "gpio_cascade", +}; + +static int +falcon_gpio_probe(struct platform_device *pdev) +{ + struct falcon_gpio_port *gpio_port; + int ret, i; + struct resource *gpiores, *padres; + int irq; + + if (pdev->id >= MAX_PORTS) + return -ENODEV; + + gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + padres = platform_get_resource(pdev, IORESOURCE_MEM, 1); + irq = platform_get_irq(pdev, 0); + if (!gpiores || !padres) + return -ENODEV; + + gpio_port = <q_gpio_port[pdev->id]; + gpio_port->gpio_chip.label = "falcon-gpio"; + gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input; + gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output; + gpio_port->gpio_chip.get = falcon_gpio_get; + gpio_port->gpio_chip.set = falcon_gpio_set; + gpio_port->gpio_chip.request = falcon_gpio_request; + gpio_port->gpio_chip.free = falcon_gpio_free; + gpio_port->gpio_chip.base = 100 * pdev->id; + gpio_port->gpio_chip.ngpio = 32; + gpio_port->gpio_chip.dev = &pdev->dev; + + gpio_port->port = ltq_remap_resource(gpiores); + gpio_port->pad = ltq_remap_resource(padres); + + if (!gpio_port->port || !gpio_port->pad) { + dev_err(&pdev->dev, "Could not map io ranges\n"); + ret = -ENOMEM; + goto err; + } + + if (irq > 0) { + /* irq_chip support */ + gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; + gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id); + + for (i = 0; i < 32; i++) { + irq_set_chip_and_handler_name(gpio_port->irq_base + i, + &falcon_gpio_irq_chip, handle_simple_irq, + "mux"); + irq_set_chip_data(gpio_port->irq_base + i, gpio_port); + /* set to negative logic (falling edge, low level) */ + ltq_port_w32_mask(gpio_port, 0, 1 << i, + LTQ_GPIO_EXINTCR0); + } + + gpio_port->chained_irq = irq; + setup_irq(irq, &gpio_cascade); + irq_set_handler_data(irq, gpio_port); + irq_set_chained_handler(irq, falcon_gpio_irq_handler); + } + + ret = gpiochip_add(&gpio_port->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", + pdev->id, ret); + goto err; + } + platform_set_drvdata(pdev, gpio_port); + return ret; + +err: + dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret); + if (gpiores) + release_resource(gpiores); + if (padres) + release_resource(padres); + + if (gpio_port->port) + iounmap(gpio_port->port); + if (gpio_port->pad) + iounmap(gpio_port->pad); + return ret; +} + +static struct platform_driver falcon_gpio_driver = { + .probe = falcon_gpio_probe, + .driver = { + .name = "falcon_gpio", + .owner = THIS_MODULE, + }, +}; + +int __init +falcon_gpio_init(void) +{ + int ret; + + pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n"); + ret = platform_driver_register(&falcon_gpio_driver); + if (ret) + pr_err("falcon_gpio: Error registering platform driver!"); + return ret; +} + +postcore_initcall(falcon_gpio_init); -- 1.7.7.1 From blogic@openwrt.org Mon Jan 16 17:44:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 17:45:55 +0100 (CET) Received: from nbd.name ([46.4.11.11]:56227 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903626Ab2APQoY (ORCPT ); Mon, 16 Jan 2012 17:44:24 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 12/17] MAINTAINERS: add entry for Lantiq related files Date: Mon, 16 Jan 2012 17:43:41 +0100 Message-Id: <1326732224-21336-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326732224-21336-1-git-send-email-blogic@openwrt.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> X-archive-position: 32256 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 700 Lines: 31 Adds new entry to MAINTAINERS file for Lantiq SoC related code. Signed-off-by: John Crispin --- Changes in V2 * only add entry for MIPS until all drivers are merged MAINTAINERS | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4475602..99a0a96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4362,6 +4362,12 @@ S: Supported F: Documentation/mips/ F: arch/mips/ +MIPS/LANTIQ +M: John Crispin +M: Thomas Langer +S: Maintained +F: arch/mips/lantiq/* + MISCELLANEOUS MCA-SUPPORT M: James Bottomley S: Maintained -- 1.7.7.1 From blogic@openwrt.org Mon Jan 16 17:44:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 17:46:18 +0100 (CET) Received: from nbd.name ([46.4.11.11]:56228 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903627Ab2APQoY (ORCPT ); Mon, 16 Jan 2012 17:44:24 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 14/17] NET: MIPS: lantiq: non existing phy was not handled gracefully Date: Mon, 16 Jan 2012 17:43:42 +0100 Message-Id: <1326732224-21336-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326732224-21336-1-git-send-email-blogic@openwrt.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> X-archive-position: 32257 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1897 Lines: 65 The code blindly assumed that that a PHY device was present causing a BadVA. In addition the driver should not fail to load incase no PHY was found. Instead we print the following line and continue with no attached PHY. etop: mdio probe failed Signed-off-by: John Crispin Acked-by: David S. Miller --- Changes in V2: * remove superflous ";" in line 778 drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index d3d4931..643faf9 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -612,7 +612,8 @@ ltq_etop_open(struct net_device *dev) ltq_dma_open(&ch->dma); napi_enable(&ch->napi); } - phy_start(priv->phydev); + if (priv->phydev) + phy_start(priv->phydev); netif_tx_start_all_queues(dev); return 0; } @@ -624,7 +625,8 @@ ltq_etop_stop(struct net_device *dev) int i; netif_tx_stop_all_queues(dev); - phy_stop(priv->phydev); + if (priv->phydev) + phy_stop(priv->phydev); for (i = 0; i < MAX_DMA_CHAN; i++) { struct ltq_etop_chan *ch = &priv->ch[i]; @@ -770,9 +772,10 @@ ltq_etop_init(struct net_device *dev) if (err) goto err_netdev; ltq_etop_set_multicast_list(dev); - err = ltq_etop_mdio_init(dev); - if (err) - goto err_netdev; + if (!ltq_etop_mdio_init(dev)) + dev->ethtool_ops = <q_etop_ethtool_ops; + else + pr_warn("etop: mdio probe failed\n"); return 0; err_netdev: @@ -868,7 +871,6 @@ ltq_etop_probe(struct platform_device *pdev) dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); strcpy(dev->name, "eth%d"); dev->netdev_ops = <q_eth_netdev_ops; - dev->ethtool_ops = <q_etop_ethtool_ops; priv = netdev_priv(dev); priv->res = res; priv->pldata = dev_get_platdata(&pdev->dev); -- 1.7.7.1 From blogic@openwrt.org Mon Jan 16 17:44:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 17:46:43 +0100 (CET) Received: from nbd.name ([46.4.11.11]:56230 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903629Ab2APQoZ (ORCPT ); Mon, 16 Jan 2012 17:44:25 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 15/17] NET: MIPS: lantiq: return value of request_irq was not handled gracefully Date: Mon, 16 Jan 2012 17:43:43 +0100 Message-Id: <1326732224-21336-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326732224-21336-1-git-send-email-blogic@openwrt.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> X-archive-position: 32258 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2191 Lines: 72 The return values of request_irq() were not checked leading to the following error message. drivers/net/ethernet/lantiq_etop.c: In function 'ltq_etop_hw_init': drivers/net/ethernet/lantiq_etop.c:368:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result drivers/net/ethernet/lantiq_etop.c:377:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result Signed-off-by: John Crispin Acked-by: David S. Miller --- Changes in V2 * really handle all return codes and not just the last drivers/net/ethernet/lantiq_etop.c | 19 ++++++++++++------- 1 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 643faf9..02fd7cf 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -312,6 +312,7 @@ ltq_etop_hw_init(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); unsigned int mii_mode = priv->pldata->mii_mode; + int err = 0; int i; ltq_pmu_enable(PMU_PPE); @@ -356,7 +357,7 @@ ltq_etop_hw_init(struct net_device *dev) ltq_dma_init_port(DMA_PORT_ETOP); - for (i = 0; i < MAX_DMA_CHAN; i++) { + for (i = 0; i < MAX_DMA_CHAN && !err; i++) { int irq = LTQ_DMA_ETOP + i; struct ltq_etop_chan *ch = &priv->ch[i]; @@ -364,21 +365,25 @@ ltq_etop_hw_init(struct net_device *dev) if (IS_TX(i)) { ltq_dma_alloc_tx(&ch->dma); - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, + err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); } else if (IS_RX(i)) { ltq_dma_alloc_rx(&ch->dma); for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; ch->dma.desc++) - if (ltq_etop_alloc_skb(ch)) - return -ENOMEM; + if (ltq_etop_alloc_skb(ch)) { + err = -ENOMEM; + goto err_out; + } ch->dma.desc = 0; - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, + err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); } - ch->dma.irq = irq; + if (!err) + ch->dma.irq = irq; } - return 0; +err_out: + return err; } static void -- 1.7.7.1 From blogic@openwrt.org Mon Jan 16 17:44:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jan 2012 17:47:06 +0100 (CET) Received: from nbd.name ([46.4.11.11]:56232 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903631Ab2APQoZ (ORCPT ); Mon, 16 Jan 2012 17:44:25 +0100 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin , Felix Fietkau Subject: [PATCH V2 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set Date: Mon, 16 Jan 2012 17:43:44 +0100 Message-Id: <1326732224-21336-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.7.1 In-Reply-To: <1326732224-21336-1-git-send-email-blogic@openwrt.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> X-archive-position: 32259 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1857 Lines: 68 The patch makes the oprofile code use the performance counters irq. Signed-off-by: Felix Fietkau Signed-off-by: John Crispin --- Based on a patch made by Felix Changes in V2 * fixes code formatting * 0 is not an IRQ use "> 0" and not ">= 0" arch/mips/kernel/cevt-r4k.c | 2 +- arch/mips/oprofile/op_model_mipsxx.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 51095dd9..bc702c8 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -84,7 +84,7 @@ out: struct irqaction c0_compare_irqaction = { .handler = c0_compare_interrupt, - .flags = IRQF_PERCPU | IRQF_TIMER, + .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED, .name = "timer", }; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..ed35a16 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -298,6 +298,11 @@ static void reset_counters(void *arg) } } +static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id) +{ + return mipsxx_perfcount_handler(); +} + static int __init mipsxx_init(void) { int counters; @@ -374,6 +379,10 @@ static int __init mipsxx_init(void) save_perf_irq = perf_irq; perf_irq = mipsxx_perfcount_handler; + if (cp0_perfcount_irq > 0) + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int, + IRQF_SHARED, "Perfcounter", save_perf_irq); + return 0; } @@ -381,6 +390,9 @@ static void mipsxx_exit(void) { int counters = op_model_mipsxx_ops.num_counters; + if (cp0_perfcount_irq > 0) + free_irq(cp0_perfcount_irq, save_perf_irq); + counters = counters_per_cpu_to_total(counters); on_each_cpu(reset_counters, (void *)(long)counters, 1); -- 1.7.7.1 From keguang.zhang@gmail.com Tue Jan 17 06:13:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 06:13:30 +0100 (CET) Received: from mail-tul01m020-f177.google.com ([209.85.214.177]:40805 "EHLO mail-tul01m020-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903605Ab2AQFNW (ORCPT ); Tue, 17 Jan 2012 06:13:22 +0100 Received: by obcuz6 with SMTP id uz6so3069952obc.36 for ; Mon, 16 Jan 2012 21:13:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=QpvhlNJEe2itqFTXV9WmI4TVR5qiFsWyoMASyVBgo68=; b=jqQTJm+siEICD05rx7WTeQ57rGRnwLjGkmWPrX9fvlojhQrEwT7xhBmkNFLHZPNSSE zu7f2v1ODDCMra4aMNv5P6kSRoZtDQEMJXbODeC5O/R6aAr1cW6IRt1y35xJEj/DIm2M vEy9JwhXjSwkwMiKVvQxUtURs/fcDWTbaOPag= Received: by 10.50.156.130 with SMTP id we2mr15798791igb.10.1326777195997; Mon, 16 Jan 2012 21:13:15 -0800 (PST) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id lu10sm36937638igc.0.2012.01.16.21.13.07 (version=SSLv3 cipher=OTHER); Mon, 16 Jan 2012 21:13:14 -0800 (PST) From: Kelvin Cheung To: ralf@linux-mips.org, linux-mips@linux-mips.org, stern@rowland.harvard.edu, linux-usb@vger.kernel.org Cc: gregkh@suse.de, zhzhl555@gmail.com, peppe.cavallaro@st.com, wuzhangjin@gmail.com, linux-kernel@vger.kernel.org, Kelvin Cheung Subject: [PATCH V6 0/5] MIPS: Add support for Loongson1B Date: Tue, 17 Jan 2012 13:12:35 +0800 Message-Id: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 X-archive-position: 32260 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3936 Lines: 80 These patches add support for Loongson1B. Changelog: V6: Add USB support for Loongson1B. V5: Add IS_ENABLED() macro for platform devices. V4: Split the RTC patch, and merge the arch/mips parts into patch 2/4. Use 'KSEG1ADDR' instead of 'ioremap()' in registers definitions. V3: Add RTC support for Loongson1B. V2: Add Ethernet support for Loongson1B. V1: Add basic support for Loongson1B. ---------------- Kelvin Cheung (5): MIPS: Add CPU support for Loongson1B MIPS: Add board support for Loongson1B MIPS: Add Makefile and Kconfig for Loongson1B USB: Add EHCI bus glue for Loongson1x SoCs MIPS: Add defconfig for Loongson1B arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 31 ++++ arch/mips/configs/ls1b_defconfig | 104 +++++++++++++ arch/mips/include/asm/cpu.h | 3 +- arch/mips/include/asm/mach-loongson1/irq.h | 68 +++++++++ arch/mips/include/asm/mach-loongson1/loongson1.h | 44 ++++++ arch/mips/include/asm/mach-loongson1/platform.h | 23 +++ arch/mips/include/asm/mach-loongson1/prom.h | 24 +++ arch/mips/include/asm/mach-loongson1/regs-clk.h | 33 ++++ arch/mips/include/asm/mach-loongson1/regs-wdt.h | 22 +++ arch/mips/include/asm/mach-loongson1/war.h | 25 +++ arch/mips/include/asm/module.h | 2 + arch/mips/kernel/cpu-probe.c | 15 ++ arch/mips/kernel/perf_event_mipsxx.c | 6 + arch/mips/kernel/traps.c | 1 + arch/mips/loongson1/Kconfig | 21 +++ arch/mips/loongson1/Makefile | 11 ++ arch/mips/loongson1/Platform | 7 + arch/mips/loongson1/common/Makefile | 5 + arch/mips/loongson1/common/clock.c | 165 +++++++++++++++++++++ arch/mips/loongson1/common/irq.c | 146 +++++++++++++++++++ arch/mips/loongson1/common/platform.c | 130 +++++++++++++++++ arch/mips/loongson1/common/prom.c | 87 +++++++++++ arch/mips/loongson1/common/reset.c | 45 ++++++ arch/mips/loongson1/common/setup.c | 29 ++++ arch/mips/loongson1/ls1b/Makefile | 5 + arch/mips/loongson1/ls1b/board.c | 39 +++++ arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 4 + drivers/usb/Kconfig | 1 + drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-ls1x.c | 170 ++++++++++++++++++++++ 32 files changed, 1272 insertions(+), 1 deletions(-) create mode 100644 arch/mips/configs/ls1b_defconfig create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h create mode 100644 arch/mips/include/asm/mach-loongson1/war.h create mode 100644 arch/mips/loongson1/Kconfig create mode 100644 arch/mips/loongson1/Makefile create mode 100644 arch/mips/loongson1/Platform create mode 100644 arch/mips/loongson1/common/Makefile create mode 100644 arch/mips/loongson1/common/clock.c create mode 100644 arch/mips/loongson1/common/irq.c create mode 100644 arch/mips/loongson1/common/platform.c create mode 100644 arch/mips/loongson1/common/prom.c create mode 100644 arch/mips/loongson1/common/reset.c create mode 100644 arch/mips/loongson1/common/setup.c create mode 100644 arch/mips/loongson1/ls1b/Makefile create mode 100644 arch/mips/loongson1/ls1b/board.c create mode 100644 drivers/usb/host/ehci-ls1x.c From keguang.zhang@gmail.com Tue Jan 17 06:13:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 06:13:53 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:41663 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903607Ab2AQFNa (ORCPT ); Tue, 17 Jan 2012 06:13:30 +0100 Received: by iaek3 with SMTP id k3so595800iae.36 for ; Mon, 16 Jan 2012 21:13:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=i+TicSe9HOt5rkS3uPCQnimznRGQMjaYCFLDWCwXI4U=; b=sIp4C4qTpqDQPetTKWQMNZ7aJLG7tf7xHS2oWSUtDB7n4vCU4mXYq8b8m6FkzHAOmU r6SL5tuYsqUYkLRYrLxftv1w+CQn8qgo/nHW4KV7Q8V9zCGQpQMykn9Mgkr4uqxZ014U WYbZt7fHlMz0eZGJeFjitxEPsTV0qjxTc4Ofs= Received: by 10.50.168.70 with SMTP id zu6mr13231608igb.1.1326777203581; Mon, 16 Jan 2012 21:13:23 -0800 (PST) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id lu10sm36937638igc.0.2012.01.16.21.13.16 (version=SSLv3 cipher=OTHER); Mon, 16 Jan 2012 21:13:22 -0800 (PST) From: Kelvin Cheung To: ralf@linux-mips.org, linux-mips@linux-mips.org, stern@rowland.harvard.edu, linux-usb@vger.kernel.org Cc: gregkh@suse.de, zhzhl555@gmail.com, peppe.cavallaro@st.com, wuzhangjin@gmail.com, linux-kernel@vger.kernel.org, Kelvin Cheung Subject: [PATCH V6 1/5] MIPS: Add CPU support for Loongson1B Date: Tue, 17 Jan 2012 13:12:36 +0800 Message-Id: <1326777160-9930-2-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> References: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 32261 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4772 Lines: 150 This patch adds CPU support for Loongson1B. Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), which implements the MIPS32 release 2 instruction set. Signed-off-by: Kelvin Cheung --- arch/mips/include/asm/cpu.h | 3 ++- arch/mips/include/asm/module.h | 2 ++ arch/mips/kernel/cpu-probe.c | 15 +++++++++++++++ arch/mips/kernel/perf_event_mipsxx.c | 6 ++++++ arch/mips/kernel/traps.c | 1 + arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 4 ++++ 7 files changed, 31 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 5f95a4b..975f372 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -191,6 +191,7 @@ #define PRID_REV_34K_V1_0_2 0x0022 #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 +#define PRID_REV_LOONGSON1B 0x0020 /* * Older processors used to encode processor version and revision in two @@ -253,7 +254,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, - CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, + CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, /* * MIPS64 class processors diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index bc01a02..b53d642 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -116,6 +116,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "SB1 " #elif defined CONFIG_CPU_LOONGSON2 #define MODULE_PROC_FAMILY "LOONGSON2 " +#elif defined CONFIG_CPU_LOONGSON1 +#define MODULE_PROC_FAMILY "LOONGSON1 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " #elif defined CONFIG_CPU_XLR diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 664bc13..98d4235 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -37,6 +37,8 @@ void (*cpu_wait)(void); EXPORT_SYMBOL(cpu_wait); +static void __cpuinit decode_configs(struct cpuinfo_mips *c); + static void r3081_wait(void) { unsigned long cfg = read_c0_conf(); @@ -191,6 +193,7 @@ void __init check_wait(void) case CPU_CAVIUM_OCTEON2: case CPU_JZRISC: case CPU_XLR: + case CPU_LOONGSON1: cpu_wait = r4k_wait; break; @@ -636,6 +639,18 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) MIPS_CPU_32FPR; c->tlbsize = 64; break; + case PRID_IMP_LOONGSON1: + decode_configs(c); + + c->cputype = CPU_LOONGSON1; + + switch (c->processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON1B: + __cpu_name[cpu] = "Loongson 1B"; + break; + } + + break; } } diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index e5ad09a..e316b0e 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1062,6 +1062,12 @@ init_hw_perf_events(void) mipsxxcore_pmu.irq = irq; mipspmu = &mipsxxcore_pmu; break; + case CPU_LOONGSON1: + mipsxxcore_pmu.name = "mips/loongson1"; + mipsxxcore_pmu.num_counters = counters; + mipsxxcore_pmu.irq = irq; + mipspmu = &mipsxxcore_pmu; + break; default: pr_cont("Either hardware does not support performance " "counters, or not yet implemented.\n"); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 01eff7e..cd55823 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1241,6 +1241,7 @@ static inline void parity_protection_init(void) break; case CPU_5KC: + case CPU_LOONGSON1: write_c0_ecc(0x80000000); back_to_back_c0_hazard(); /* Set the PE bit (bit 31) in the c0_errctl register. */ diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index d1f2d4c..99216f0 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -89,6 +89,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_R10000: case CPU_R12000: case CPU_R14000: + case CPU_LOONGSON1: lmodel = &op_model_mipsxx_ops; break; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..03be670 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -365,6 +365,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/sb1"; break; + case CPU_LOONGSON1: + op_model_mipsxx_ops.cpu_type = "mips/loongson1"; + break; + default: printk(KERN_ERR "Profiling unsupported for this CPU\n"); -- 1.7.1 From keguang.zhang@gmail.com Tue Jan 17 06:13:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 06:14:23 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:41663 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903611Ab2AQFNd (ORCPT ); Tue, 17 Jan 2012 06:13:33 +0100 Received: by mail-iy0-f177.google.com with SMTP id k3so595800iae.36 for ; Mon, 16 Jan 2012 21:13:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=fF2AqBO4vDwgG441zCChzINbsLnKB5Qc8X499FjATZs=; b=DVrZSs8ATccI7fkeYQosFGybNqqTsJ4xHgqbMFM+gIwYwuRzu39MvwIozO833wYADk yA+5SfzWw++CpjpjHpPRRWKR76UNv6psXED8E3fW0POuFvFYHm2BUkLBpuSRe4/LjQ// vZwZFImHa6bnt1mBMneZRaqXU6OxMQ1syeb5U= Received: by 10.50.222.193 with SMTP id qo1mr15855268igc.22.1326777212748; Mon, 16 Jan 2012 21:13:32 -0800 (PST) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id lu10sm36937638igc.0.2012.01.16.21.13.24 (version=SSLv3 cipher=OTHER); Mon, 16 Jan 2012 21:13:31 -0800 (PST) From: Kelvin Cheung To: ralf@linux-mips.org, linux-mips@linux-mips.org, stern@rowland.harvard.edu, linux-usb@vger.kernel.org Cc: gregkh@suse.de, zhzhl555@gmail.com, peppe.cavallaro@st.com, wuzhangjin@gmail.com, linux-kernel@vger.kernel.org, Kelvin Cheung Subject: [PATCH V6 2/5] MIPS: Add board support for Loongson1B Date: Tue, 17 Jan 2012 13:12:37 +0800 Message-Id: <1326777160-9930-3-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> References: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 32262 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 27639 Lines: 1011 This patch adds basic platform devices for Loongson1B, including serial port, ethernet, usb, rtc and interrupt handler. Loongson1B UART is compatible with NS16550A. Loongson1B GMAC is built around Synopsys IP Core. Use normal descriptor instead of enhanced descriptor. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung --- arch/mips/include/asm/mach-loongson1/irq.h | 68 +++++++++ arch/mips/include/asm/mach-loongson1/loongson1.h | 44 ++++++ arch/mips/include/asm/mach-loongson1/platform.h | 23 +++ arch/mips/include/asm/mach-loongson1/prom.h | 24 +++ arch/mips/include/asm/mach-loongson1/regs-clk.h | 33 +++++ arch/mips/include/asm/mach-loongson1/regs-wdt.h | 22 +++ arch/mips/include/asm/mach-loongson1/war.h | 25 ++++ arch/mips/loongson1/common/clock.c | 165 ++++++++++++++++++++++ arch/mips/loongson1/common/irq.c | 146 +++++++++++++++++++ arch/mips/loongson1/common/platform.c | 130 +++++++++++++++++ arch/mips/loongson1/common/prom.c | 87 ++++++++++++ arch/mips/loongson1/common/reset.c | 45 ++++++ arch/mips/loongson1/common/setup.c | 29 ++++ arch/mips/loongson1/ls1b/board.c | 39 +++++ 14 files changed, 880 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h create mode 100644 arch/mips/include/asm/mach-loongson1/war.h create mode 100644 arch/mips/loongson1/common/clock.c create mode 100644 arch/mips/loongson1/common/irq.c create mode 100644 arch/mips/loongson1/common/platform.c create mode 100644 arch/mips/loongson1/common/prom.c create mode 100644 arch/mips/loongson1/common/reset.c create mode 100644 arch/mips/loongson1/common/setup.c create mode 100644 arch/mips/loongson1/ls1b/board.c diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h new file mode 100644 index 0000000..762bd2b --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/irq.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * IRQ mappings for Loongson1. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_IRQ_H +#define __ASM_MACH_LOONGSON1_IRQ_H + +/* + * CPU core Interrupt Numbers + */ +#define MIPS_CPU_IRQ_BASE 0 +#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) +#define SOFTINT0_IRQ MIPS_CPU_IRQ(0) +#define SOFTINT1_IRQ MIPS_CPU_IRQ(1) +#define INT0_IRQ MIPS_CPU_IRQ(2) +#define INT1_IRQ MIPS_CPU_IRQ(3) +#define INT2_IRQ MIPS_CPU_IRQ(4) +#define INT3_IRQ MIPS_CPU_IRQ(5) +#define INT4_IRQ MIPS_CPU_IRQ(6) +#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ + +/* + * INT0~3 Interrupt Numbers + */ +#define LS1X_IRQ_BASE 8 +#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) + +#define LS1X_UART0_IRQ LS1X_IRQ(0, 2) +#define LS1X_UART1_IRQ LS1X_IRQ(0, 3) +#define LS1X_UART2_IRQ LS1X_IRQ(0, 4) +#define LS1X_UART3_IRQ LS1X_IRQ(0, 5) +#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) +#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) +#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) +#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) +#define LS1X_AC97_IRQ LS1X_IRQ(0, 10) +#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) +#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) +#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) +#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) +#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) +#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) +#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) +#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) +#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) +#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) +#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) +#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) +#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) +#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) +#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) + +#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) +#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) +#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) +#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) + +#define NR_IRQS LS1X_GMAC1_IRQ + +#endif /* __ASM_MACH_LOONGSON1_IRQ_H */ diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h new file mode 100644 index 0000000..0440627 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/loongson1.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Register mappings for Loongson1. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H +#define __ASM_MACH_LOONGSON1_LOONGSON1_H + +#define DEFAULT_MEMSIZE 256 /* If no memsize provided */ + +/* Loongson1 Register Bases */ +#define LS1X_INTC_BASE 0x1fd01040 +#define LS1X_EHCI_BASE 0x1fe00000 +#define LS1X_OHCI_BASE 0x1fe08000 +#define LS1X_GMAC0_BASE 0x1fe10000 +#define LS1X_GMAC1_BASE 0x1fe20000 + +#define LS1X_UART0_BASE 0x1fe40000 +#define LS1X_UART1_BASE 0x1fe44000 +#define LS1X_UART2_BASE 0x1fe48000 +#define LS1X_UART3_BASE 0x1fe4c000 +#define LS1X_CAN0_BASE 0x1fe50000 +#define LS1X_CAN1_BASE 0x1fe54000 +#define LS1X_I2C0_BASE 0x1fe58000 +#define LS1X_I2C1_BASE 0x1fe68000 +#define LS1X_I2C2_BASE 0x1fe70000 +#define LS1X_PWM_BASE 0x1fe5c000 +#define LS1X_WDT_BASE 0x1fe5c060 +#define LS1X_RTC_BASE 0x1fe64000 +#define LS1X_AC97_BASE 0x1fe74000 +#define LS1X_NAND_BASE 0x1fe78000 +#define LS1X_CLK_BASE 0x1fe78030 + +#include +#include + +#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */ diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h new file mode 100644 index 0000000..2f17161 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/platform.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H +#define __ASM_MACH_LOONGSON1_PLATFORM_H + +#include + +extern struct platform_device ls1x_uart_device; +extern struct platform_device ls1x_eth0_device; +extern struct platform_device ls1x_ehci_device; +extern struct platform_device ls1x_rtc_device; + +void ls1x_serial_setup(void); + +#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h new file mode 100644 index 0000000..b871dc4 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/prom.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_PROM_H +#define __ASM_MACH_LOONGSON1_PROM_H + +#include +#include +#include + +/* environment arguments from bootloader */ +extern unsigned long memsize, highmemsize; + +/* loongson-specific command line, env and memory initialization */ +extern char *prom_getenv(char *name); +extern void __init prom_init_cmdline(void); + +#endif /* __ASM_MACH_LOONGSON1_PROM_H */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h new file mode 100644 index 0000000..5b9635a --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Loongson1 Clock Register Definitions. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H +#define __ASM_MACH_LOONGSON1_REGS_CLK_H + +#define LS1X_CLK_REG(x) \ + ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x))) + +#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) +#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) + +/* Clock PLL Divisor Register Bits */ +#define DIV_DC_EN (0x1 << 31) +#define DIV_DC (0x1f << 26) +#define DIV_CPU_EN (0x1 << 25) +#define DIV_CPU (0x1f << 20) +#define DIV_DDR_EN (0x1 << 19) +#define DIV_DDR (0x1f << 14) + +#define DIV_DC_SHIFT 26 +#define DIV_CPU_SHIFT 20 +#define DIV_DDR_SHIFT 14 + +#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h new file mode 100644 index 0000000..d339fe7 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Loongson1 Watchdog register definitions. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H +#define __ASM_MACH_LOONGSON1_REGS_WDT_H + +#define LS1X_WDT_REG(x) \ + ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x))) + +#define LS1X_WDT_EN LS1X_WDT_REG(0x0) +#define LS1X_WDT_SET LS1X_WDT_REG(0x4) +#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8) + +#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */ diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h new file mode 100644 index 0000000..e3680a8 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_LOONGSON1_WAR_H +#define __ASM_MACH_LOONGSON1_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_LOONGSON1_WAR_H */ diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c new file mode 100644 index 0000000..2d98fb0 --- /dev/null +++ b/arch/mips/loongson1/common/clock.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +struct clk *clk_get(struct device *dev, const char *name) +{ + struct clk *c; + struct clk *ret = NULL; + + mutex_lock(&clocks_mutex); + list_for_each_entry(c, &clocks, node) { + if (!strcmp(c->name, name)) { + ret = c; + break; + } + } + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL(clk_get); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +static void pll_clk_init(struct clk *clk) +{ + u32 pll; + + pll = __raw_readl(LS1X_CLK_PLL_FREQ); + clk->rate = (12 + (pll & 0x3f)) * 33 / 2 + + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2; + clk->rate *= 1000000; +} + +static void cpu_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU; + clk->rate = pll / (ctrl >> DIV_CPU_SHIFT); +} + +static void ddr_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR; + clk->rate = pll / (ctrl >> DIV_DDR_SHIFT); +} + +static void dc_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC; + clk->rate = pll / (ctrl >> DIV_DC_SHIFT); +} + +static struct clk_ops pll_clk_ops = { + .init = pll_clk_init, +}; + +static struct clk_ops cpu_clk_ops = { + .init = cpu_clk_init, +}; + +static struct clk_ops ddr_clk_ops = { + .init = ddr_clk_init, +}; + +static struct clk_ops dc_clk_ops = { + .init = dc_clk_init, +}; + +static struct clk pll_clk = { + .name = "pll", + .ops = &pll_clk_ops, +}; + +static struct clk cpu_clk = { + .name = "cpu", + .parent = &pll_clk, + .ops = &cpu_clk_ops, +}; + +static struct clk ddr_clk = { + .name = "ddr", + .parent = &pll_clk, + .ops = &ddr_clk_ops, +}; + +static struct clk dc_clk = { + .name = "dc", + .parent = &pll_clk, + .ops = &dc_clk_ops, +}; + +int clk_register(struct clk *clk) +{ + mutex_lock(&clocks_mutex); + list_add(&clk->node, &clocks); + if (clk->ops->init) + clk->ops->init(clk); + mutex_unlock(&clocks_mutex); + + return 0; +} +EXPORT_SYMBOL(clk_register); + +static struct clk *ls1x_clks[] = { + &pll_clk, + &cpu_clk, + &ddr_clk, + &dc_clk, +}; + +int __init ls1x_clock_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++) + clk_register(ls1x_clks[i]); + + return 0; +} + +void __init plat_time_init(void) +{ + struct clk *clk; + + /* Initialize LS1X clocks */ + ls1x_clock_init(); + + /* setup mips r4k timer */ + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get dc clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; +} diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/irq.c new file mode 100644 index 0000000..5465baf --- /dev/null +++ b/arch/mips/loongson1/common/irq.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include +#include + +#define LS1X_INTC_REG(n, x) \ + ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x))) + +#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0) +#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4) +#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8) +#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc) +#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10) +#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14) + +static void ls1x_irq_ack(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) + | (1 << bit), LS1X_INTC_INTCLR(n)); +} + +static void ls1x_irq_mask(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + & ~(1 << bit), LS1X_INTC_INTIEN(n)); +} + +static void ls1x_irq_mask_ack(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + & ~(1 << bit), LS1X_INTC_INTIEN(n)); + __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) + | (1 << bit), LS1X_INTC_INTCLR(n)); +} + +static void ls1x_irq_unmask(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + | (1 << bit), LS1X_INTC_INTIEN(n)); +} + +static struct irq_chip ls1x_irq_chip = { + .name = "LS1X-INTC", + .irq_ack = ls1x_irq_ack, + .irq_mask = ls1x_irq_mask, + .irq_mask_ack = ls1x_irq_mask_ack, + .irq_unmask = ls1x_irq_unmask, +}; + +static void ls1x_irq_dispatch(int n) +{ + u32 int_status, irq; + + /* Get pending sources, masked by current enables */ + int_status = __raw_readl(LS1X_INTC_INTISR(n)) & + __raw_readl(LS1X_INTC_INTIEN(n)); + + if (int_status) { + irq = LS1X_IRQ(n, __ffs(int_status)); + do_IRQ(irq); + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending; + + pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) + do_IRQ(TIMER_IRQ); + else if (pending & CAUSEF_IP2) + ls1x_irq_dispatch(0); /* INT0 */ + else if (pending & CAUSEF_IP3) + ls1x_irq_dispatch(1); /* INT1 */ + else if (pending & CAUSEF_IP4) + ls1x_irq_dispatch(2); /* INT2 */ + else if (pending & CAUSEF_IP5) + ls1x_irq_dispatch(3); /* INT3 */ + else if (pending & CAUSEF_IP6) + ls1x_irq_dispatch(4); /* INT4 */ + else + spurious_interrupt(); + +} + +struct irqaction cascade_irqaction = { + .handler = no_action, + .name = "cascade", + .flags = IRQF_NO_THREAD, +}; + +static void __init ls1x_irq_init(int base) +{ + int n; + + /* Disable interrupts and clear pending, + * setup all IRQs as high level triggered + */ + for (n = 0; n < 4; n++) { + __raw_writel(0x0, LS1X_INTC_INTIEN(n)); + __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n)); + __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n)); + __raw_writel(0x0, LS1X_INTC_INTEDGE(n)); + } + + + for (n = base; n < NR_IRQS; n++) { + irq_set_chip_and_handler(n, &ls1x_irq_chip, + handle_level_irq); + } + + setup_irq(INT0_IRQ, &cascade_irqaction); + setup_irq(INT1_IRQ, &cascade_irqaction); + setup_irq(INT2_IRQ, &cascade_irqaction); + setup_irq(INT3_IRQ, &cascade_irqaction); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + ls1x_irq_init(LS1X_IRQ_BASE); +} diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/common/platform.c new file mode 100644 index 0000000..d928af5 --- /dev/null +++ b/arch/mips/loongson1/common/platform.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LS1X_UART(_id) \ + { \ + .mapbase = LS1X_UART ## _id ## _BASE, \ + .irq = LS1X_UART ## _id ## _IRQ, \ + .iotype = UPIO_MEM, \ + .flags = UPF_IOREMAP | UPF_FIXED_TYPE, \ + .type = PORT_16550A, \ + } + +static struct plat_serial8250_port ls1x_serial8250_port[] = { + LS1X_UART(0), + LS1X_UART(1), + LS1X_UART(2), + LS1X_UART(3), + {}, +}; + +struct platform_device ls1x_uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = ls1x_serial8250_port, + }, +}; + +void __init ls1x_serial_setup(void) +{ + struct clk *clk; + struct plat_serial8250_port *p; + + clk = clk_get(NULL, "dc"); + if (IS_ERR(clk)) + panic("unable to get dc clock, err=%ld", PTR_ERR(clk)); + + for (p = ls1x_serial8250_port; p->flags != 0; ++p) + p->uartclk = clk_get_rate(clk); +} + +/* Synopsys Ethernet GMAC */ +#if IS_ENABLED(CONFIG_STMMAC_ETH) +static struct resource ls1x_eth0_resources[] = { + [0] = { + .start = LS1X_GMAC0_BASE, + .end = LS1X_GMAC0_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "macirq", + .start = LS1X_GMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = { + .bus_id = 0, + .phy_mask = 0, +}; + +static struct plat_stmmacenet_data ls1x_eth_data = { + .bus_id = 0, + .phy_addr = -1, + .mdio_bus_data = &ls1x_mdio_bus_data, + .pbl = 32, + .has_gmac = 1, + .tx_coe = 1, +}; + +struct platform_device ls1x_eth0_device = { + .name = "stmmaceth", + .id = 0, + .num_resources = ARRAY_SIZE(ls1x_eth0_resources), + .resource = ls1x_eth0_resources, + .dev = { + .platform_data = &ls1x_eth_data, + }, +}; +#endif + +/* EHCI */ +#if IS_ENABLED(CONFIG_USB_EHCI_HCD) +static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32); + +static struct resource ls1x_ehci_resources[] = { + [0] = { + .start = LS1X_EHCI_BASE, + .end = LS1X_EHCI_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = LS1X_EHCI_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ls1x_ehci_device = { + .name = "ls1x-ehci", + .id = -1, + .num_resources = ARRAY_SIZE(ls1x_ehci_resources), + .resource = ls1x_ehci_resources, + .dev = { + .dma_mask = &ls1x_ehci_dmamask, + }, +}; +#endif + +#if IS_ENABLED(CONFIG_RTC_DRV_LOONGSON1) +struct platform_device ls1x_rtc_device = { + .name = "ls1x-rtc", + .id = -1, +}; +#endif diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c new file mode 100644 index 0000000..57f88ea --- /dev/null +++ b/arch/mips/loongson1/common/prom.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Modified from arch/mips/pnx833x/common/prom.c. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +unsigned long memsize, highmemsize; + +char *prom_getenv(char *envname) +{ + char **env = prom_envp; + int i; + + i = strlen(envname); + + while (*env) { + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') + return *env + i + 1; + env++; + } + + return 0; +} + +static inline unsigned long env_or_default(char *env, unsigned long dfl) +{ + char *str = prom_getenv(env); + return str ? simple_strtol(str, 0, 0) : dfl; +} + +void __init prom_init_cmdline(void) +{ + char *c = &(arcs_cmdline[0]); + int i; + + for (i = 1; i < prom_argc; i++) { + strcpy(c, prom_argv[i]); + c += strlen(prom_argv[i]); + if (i < prom_argc-1) + *c++ = ' '; + } + *c = 0; +} + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize = env_or_default("memsize", DEFAULT_MEMSIZE); + highmemsize = env_or_default("highmemsize", 0x0); +} + +void __init prom_free_prom_memory(void) +{ +} + +#define PORT(offset) (u8 *)KSEG1ADDR(LS1X_UART0_BASE + offset) + +void __init prom_putchar(char c) +{ + int timeout; + + timeout = 1024; + + while (((readb(PORT(UART_LSR)) & UART_LSR_THRE) == 0) + && (timeout-- > 0)) + ; + + writeb(c, PORT(UART_TX)); +} diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c new file mode 100644 index 0000000..fb979a7 --- /dev/null +++ b/arch/mips/loongson1/common/reset.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include + +static void ls1x_restart(char *command) +{ + __raw_writel(0x1, LS1X_WDT_EN); + __raw_writel(0x5000000, LS1X_WDT_TIMER); + __raw_writel(0x1, LS1X_WDT_SET); +} + +static void ls1x_halt(void) +{ + while (1) { + if (cpu_wait) + cpu_wait(); + } +} + +static void ls1x_power_off(void) +{ + ls1x_halt(); +} + +static int __init ls1x_reboot_setup(void) +{ + _machine_restart = ls1x_restart; + _machine_halt = ls1x_halt; + pm_power_off = ls1x_power_off; + + return 0; +} + +arch_initcall(ls1x_reboot_setup); diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/common/setup.c new file mode 100644 index 0000000..62128cc --- /dev/null +++ b/arch/mips/loongson1/common/setup.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +void __init plat_mem_setup(void) +{ + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +} + +const char *get_system_type(void) +{ + unsigned int processor_id = (¤t_cpu_data)->processor_id; + + switch (processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON1B: + return "LOONGSON LS1B"; + default: + return "LOONGSON (unknown)"; + } +} diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c new file mode 100644 index 0000000..1ec350d --- /dev/null +++ b/arch/mips/loongson1/ls1b/board.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +static struct platform_device *ls1b_platform_devices[] __initdata = { + &ls1x_uart_device, +#if IS_ENABLED(CONFIG_STMMAC_ETH) + &ls1x_eth0_device, +#endif +#if IS_ENABLED(CONFIG_USB_EHCI_HCD) + &ls1x_ehci_device, +#endif +#if IS_ENABLED(CONFIG_RTC_DRV_LOONGSON1) + &ls1x_rtc_device, +#endif +}; + +static int __init ls1b_platform_init(void) +{ + int err; + + ls1x_serial_setup(); + + err = platform_add_devices(ls1b_platform_devices, + ARRAY_SIZE(ls1b_platform_devices)); + return err; +} + +arch_initcall(ls1b_platform_init); -- 1.7.1 From keguang.zhang@gmail.com Tue Jan 17 06:13:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 06:14:46 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:41663 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903613Ab2AQFNl (ORCPT ); Tue, 17 Jan 2012 06:13:41 +0100 Received: by mail-iy0-f177.google.com with SMTP id k3so595800iae.36 for ; Mon, 16 Jan 2012 21:13:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Mn7ZxyBPx8E5XMOBCkRETMFUSebMbPv3h+xXhuXxE/M=; b=xjw0RBH3W/xDTAA9jRWKv9YxF8xTFO5PNWupr7EGT2wRUUZAMRy77ZFBVIt8T/Ecjs /V6vABqqsLDHkudCPUZQncn5VNN3HrOlD0pVp0Q9GVVkYobDhRCaY6gmf37dWM9nCHCf vCznrF2Q4KBNQlqJNo89hGWB+x8veSI7dw4TI= Received: by 10.50.178.71 with SMTP id cw7mr15854797igc.0.1326777220324; Mon, 16 Jan 2012 21:13:40 -0800 (PST) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id lu10sm36937638igc.0.2012.01.16.21.13.33 (version=SSLv3 cipher=OTHER); Mon, 16 Jan 2012 21:13:39 -0800 (PST) From: Kelvin Cheung To: ralf@linux-mips.org, linux-mips@linux-mips.org, stern@rowland.harvard.edu, linux-usb@vger.kernel.org Cc: gregkh@suse.de, zhzhl555@gmail.com, peppe.cavallaro@st.com, wuzhangjin@gmail.com, linux-kernel@vger.kernel.org, Kelvin Cheung Subject: [PATCH V6 3/5] MIPS: Add Makefile and Kconfig for Loongson1B Date: Tue, 17 Jan 2012 13:12:38 +0800 Message-Id: <1326777160-9930-4-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> References: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 32263 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5185 Lines: 182 This patch adds Makefile and Kconfig related to Loongson1B. Signed-off-by: Kelvin Cheung --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 31 +++++++++++++++++++++++++++++++ arch/mips/loongson1/Kconfig | 21 +++++++++++++++++++++ arch/mips/loongson1/Makefile | 11 +++++++++++ arch/mips/loongson1/Platform | 7 +++++++ arch/mips/loongson1/common/Makefile | 5 +++++ arch/mips/loongson1/ls1b/Makefile | 5 +++++ 7 files changed, 81 insertions(+), 0 deletions(-) create mode 100644 arch/mips/loongson1/Kconfig create mode 100644 arch/mips/loongson1/Makefile create mode 100644 arch/mips/loongson1/Platform create mode 100644 arch/mips/loongson1/common/Makefile create mode 100644 arch/mips/loongson1/ls1b/Makefile diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 5ce8029..d64786d 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -14,6 +14,7 @@ platforms += jz4740 platforms += lantiq platforms += lasat platforms += loongson +platforms += loongson1 platforms += mipssim platforms += mti-malta platforms += netlogic diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d9b8ea8..4c6ad4f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -262,6 +262,17 @@ config MACH_LOONGSON Chinese Academy of Sciences (CAS) in the People's Republic of China. The chief architect is Professor Weiwu Hu. +config MACH_LOONGSON1 + bool "Loongson1 family of machines" + select SYS_SUPPORTS_ZBOOT + help + This enables the support of Loongson1 family of machines. + + Loongson1 is a family of 32-bit MIPS-compatible SoCs. + developed at Institute of Computing Technology (ICT), + Chinese Academy of Sciences (CAS) in the People's Republic + of China. + config MIPS_MALTA bool "MIPS Malta board" select ARCH_MAY_HAVE_PC_FDC @@ -808,6 +819,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/loongson1/Kconfig" source "arch/mips/netlogic/Kconfig" endmenu @@ -1201,6 +1213,14 @@ config CPU_LOONGSON2F have a similar programming interface with FPGA northbridge used in Loongson2E. +config CPU_LOONGSON1B + bool "Loongson 1B" + depends on SYS_HAS_CPU_LOONGSON1B + select CPU_LOONGSON1 + help + The Loongson 1B is a 32-bit SoC, which implements the MIPS32 + release 2 instruction set. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1529,6 +1549,14 @@ config CPU_LOONGSON2 select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM +config CPU_LOONGSON1 + bool + select CPU_MIPS32 + select CPU_MIPSR2 + select CPU_HAS_PREFETCH + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + config SYS_HAS_CPU_LOONGSON2E bool @@ -1538,6 +1566,9 @@ config SYS_HAS_CPU_LOONGSON2F select CPU_SUPPORTS_ADDRWINCFG if 64BIT select CPU_SUPPORTS_UNCACHED_ACCELERATED +config SYS_HAS_CPU_LOONGSON1B + bool + config SYS_HAS_CPU_MIPS32_R1 bool diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig new file mode 100644 index 0000000..237fa21 --- /dev/null +++ b/arch/mips/loongson1/Kconfig @@ -0,0 +1,21 @@ +if MACH_LOONGSON1 + +choice + prompt "Machine Type" + +config LOONGSON1_LS1B + bool "Loongson LS1B board" + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON1B + select DMA_NONCOHERENT + select BOOT_ELF32 + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + +endchoice + +endif # MACH_LOONGSON1 diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile new file mode 100644 index 0000000..e9123c2 --- /dev/null +++ b/arch/mips/loongson1/Makefile @@ -0,0 +1,11 @@ +# +# Common code for all Loongson1 based systems +# + +obj-$(CONFIG_MACH_LOONGSON1) += common/ + +# +# Loongson LS1B board +# + +obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/ diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform new file mode 100644 index 0000000..92804c6 --- /dev/null +++ b/arch/mips/loongson1/Platform @@ -0,0 +1,7 @@ +cflags-$(CONFIG_CPU_LOONGSON1) += \ + $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ + -Wa,-mips32r2 -Wa,--trap + +platform-$(CONFIG_MACH_LOONGSON1) += loongson1/ +cflags-$(CONFIG_MACH_LOONGSON1) += -I$(srctree)/arch/mips/include/asm/mach-loongson1 +load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80010000 diff --git a/arch/mips/loongson1/common/Makefile b/arch/mips/loongson1/common/Makefile new file mode 100644 index 0000000..b279770 --- /dev/null +++ b/arch/mips/loongson1/common/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for common code of loongson1 based machines. +# + +obj-y += clock.o irq.o platform.o prom.o reset.o setup.o diff --git a/arch/mips/loongson1/ls1b/Makefile b/arch/mips/loongson1/ls1b/Makefile new file mode 100644 index 0000000..891eac4 --- /dev/null +++ b/arch/mips/loongson1/ls1b/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for loongson1B based machines. +# + +obj-y += board.o -- 1.7.1 From keguang.zhang@gmail.com Tue Jan 17 06:13:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 06:15:09 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:41663 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903612Ab2AQFNs (ORCPT ); Tue, 17 Jan 2012 06:13:48 +0100 Received: by mail-iy0-f177.google.com with SMTP id k3so595800iae.36 for ; Mon, 16 Jan 2012 21:13:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=WN/ewXiGgRsgAcb9jiqnEH2jC9Ev2Ygj3dhDYylhVtc=; b=OOUcesSZw1RcRPhvKt6fHwHQCzHJZQO/KV85DOTMcezB9up/uG1XKmjYuirHyZ8VIf umq7JwIJWBiY+1Fnj0GR6WvnX8/au5S5e1XP8mLWTajQvf+tgupWfXSW4O30ANxwdPBK YlchhHaA8a3mdyLlll7qpTUEx0Fh/W17RFgJs= Received: by 10.50.183.199 with SMTP id eo7mr15822504igc.5.1326777227920; Mon, 16 Jan 2012 21:13:47 -0800 (PST) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id lu10sm36937638igc.0.2012.01.16.21.13.40 (version=SSLv3 cipher=OTHER); Mon, 16 Jan 2012 21:13:47 -0800 (PST) From: Kelvin Cheung To: ralf@linux-mips.org, linux-mips@linux-mips.org, stern@rowland.harvard.edu, linux-usb@vger.kernel.org Cc: gregkh@suse.de, zhzhl555@gmail.com, peppe.cavallaro@st.com, wuzhangjin@gmail.com, linux-kernel@vger.kernel.org, Kelvin Cheung Subject: [PATCH V6 4/5] USB: Add EHCI bus glue for Loongson1x SoCs Date: Tue, 17 Jan 2012 13:12:39 +0800 Message-Id: <1326777160-9930-5-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> References: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 32264 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5554 Lines: 219 The Loongson1x SoCs have a built-in EHCI controller. This patch adds the necessary glue code to make the generic EHCI driver usable for them. Signed-off-by: Kelvin Cheung --- drivers/usb/Kconfig | 1 + drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-ls1x.c | 170 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 176 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-ls1x.c diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 85d5a01..78ac78b 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -68,6 +68,7 @@ config USB_ARCH_HAS_EHCI default y if ARCH_MSM default y if MICROBLAZE default y if SPARC_LEON + default y if MACH_LOONGSON1 default PCI # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface. diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 47aa22d..d38bd7c 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1291,6 +1291,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_grlib_driver #endif +#ifdef CONFIG_MACH_LOONGSON1 +#include "ehci-ls1x.c" +#define PLATFORM_DRIVER ehci_ls1x_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-ls1x.c b/drivers/usb/host/ehci-ls1x.c new file mode 100644 index 0000000..d3b6720 --- /dev/null +++ b/drivers/usb/host/ehci-ls1x.c @@ -0,0 +1,170 @@ +/* + * Bus Glue for Loongson LS1X built-in EHCI controller. + * + * Copyright (c) 2012 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + + +#include + +static int ehci_ls1x_setup(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int ret; + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + ehci->sbrn = 0x20; + + ehci_reset(ehci); + + /* data structure init */ + ret = ehci_init(hcd); + if (ret) + return ret; + + ehci_port_power(ehci, 0); + + return 0; +} + +static const struct hc_driver ehci_ls1x_hc_driver = { + .description = hcd_name, + .product_desc = "LOONGSON1 EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + */ + .reset = ehci_ls1x_setup, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_hcd_ls1x_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + pr_debug("initializing loongson1 ehci USB Controller\n"); + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no register addr. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + + hcd = usb_create_hcd(&ehci_ls1x_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + hcd->rsrc_start = res->start; + hcd->rsrc_len = resource_size(res); + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (hcd->regs == NULL) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (ret) + goto err_iounmap; + + return ret; + +err_iounmap: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_hcd_ls1x_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static struct platform_driver ehci_ls1x_driver = { + .probe = ehci_hcd_ls1x_probe, + .remove = ehci_hcd_ls1x_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ls1x-ehci", + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ls1x-ehci"); -- 1.7.1 From keguang.zhang@gmail.com Tue Jan 17 06:13:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 06:15:32 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:41663 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903614Ab2AQFN4 (ORCPT ); Tue, 17 Jan 2012 06:13:56 +0100 Received: by mail-iy0-f177.google.com with SMTP id k3so595800iae.36 for ; Mon, 16 Jan 2012 21:13:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=6HW3anLo35s3Ygo1i40p2NrLR8gmiwl/wrKpKNQukE8=; b=qB0ulDJmTmFygNWMHgENaXuSQrwP8/Epjej0VoCCgMGcSz2Xh+tWKBuEi32iIZnH8m 1mKIWH6hadpAE/kkLKS5xTu48LiV9pY8pnDCG+f+94PtxrwSAbr0oYrx+Wn3eFm5YUFm jg7fH7Q+tMngkfMQiU0gt47S3HNTJiBopEtiQ= Received: by 10.50.6.137 with SMTP id b9mr12192457iga.16.1326777235628; Mon, 16 Jan 2012 21:13:55 -0800 (PST) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id lu10sm36937638igc.0.2012.01.16.21.13.48 (version=SSLv3 cipher=OTHER); Mon, 16 Jan 2012 21:13:54 -0800 (PST) From: Kelvin Cheung To: ralf@linux-mips.org, linux-mips@linux-mips.org, stern@rowland.harvard.edu, linux-usb@vger.kernel.org Cc: gregkh@suse.de, zhzhl555@gmail.com, peppe.cavallaro@st.com, wuzhangjin@gmail.com, linux-kernel@vger.kernel.org, Kelvin Cheung Subject: [PATCH V6 5/5] MIPS: Add defconfig for Loongson1B Date: Tue, 17 Jan 2012 13:12:40 +0800 Message-Id: <1326777160-9930-6-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> References: <1326777160-9930-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 32265 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3269 Lines: 121 This patch adds defconfig for Loongson1B. Signed-off-by: Kelvin Cheung --- arch/mips/configs/ls1b_defconfig | 104 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 104 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/ls1b_defconfig diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig new file mode 100644 index 0000000..eab7d16 --- /dev/null +++ b/arch/mips/configs/ls1b_defconfig @@ -0,0 +1,104 @@ +CONFIG_MACH_LOONGSON1=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +# CONFIG_SECCOMP is not set +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TINY_RCU=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_SCSI=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=m +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_DA=y +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=8 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB_HID=m +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_STORAGE=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_LOONGSON1=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_FTRACE is not set +# CONFIG_EARLY_PRINTK is not set -- 1.7.1 From ralf@linux-mips.org Tue Jan 17 15:18:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:19:05 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36685 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903622Ab2AQOSz (ORCPT ); Tue, 17 Jan 2012 15:18:55 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEIs4L016475; Tue, 17 Jan 2012 15:18:54 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEIrm6016469; Tue, 17 Jan 2012 15:18:53 +0100 Date: Tue, 17 Jan 2012 15:18:53 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH V2 01/17] MIPS: lantiq: reorganize xway code Message-ID: <20120117141853.GA16443@linux-mips.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326732224-21336-1-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32266 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Queued. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:19:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:19:28 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36690 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903630Ab2AQOTN (ORCPT ); Tue, 17 Jan 2012 15:19:13 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEJCol016503; Tue, 17 Jan 2012 15:19:12 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEJBuH016502; Tue, 17 Jan 2012 15:19:11 +0100 Date: Tue, 17 Jan 2012 15:19:11 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Thomas Langer Subject: Re: [PATCH RESEND 02/17] MIPS: lantiq: change ltq_request_gpio() call signature Message-ID: <20120117141911.GA16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-2-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-2-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32267 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:19:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:19:53 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36695 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903631Ab2AQOTV (ORCPT ); Tue, 17 Jan 2012 15:19:21 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEJKqj016521; Tue, 17 Jan 2012 15:19:20 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEJKJH016520; Tue, 17 Jan 2012 15:19:20 +0100 Date: Tue, 17 Jan 2012 15:19:20 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Thomas Langer Subject: Re: [PATCH RESEND 03/17] MIPS: lantiq: make irq.c support the FALC-ON Message-ID: <20120117141920.GB16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-3-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-3-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32268 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:19:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:20:17 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36853 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903629Ab2AQOTj (ORCPT ); Tue, 17 Jan 2012 15:19:39 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEJcOs016536; Tue, 17 Jan 2012 15:19:38 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEJbRx016535; Tue, 17 Jan 2012 15:19:37 +0100 Date: Tue, 17 Jan 2012 15:19:37 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Thomas Langer Subject: Re: [PATCH V2 04/17] MIPS: lantiq: add basic support for FALC-ON Message-ID: <20120117141937.GB16443@linux-mips.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> <1326732224-21336-2-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326732224-21336-2-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32269 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:19:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:20:41 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37001 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903632Ab2AQOTu (ORCPT ); Tue, 17 Jan 2012 15:19:50 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEJm40016549; Tue, 17 Jan 2012 15:19:48 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEJmxM016548; Tue, 17 Jan 2012 15:19:48 +0100 Date: Tue, 17 Jan 2012 15:19:48 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Thomas Langer Subject: Re: [PATCH V2 05/17] MIPS: lantiq: add support for FALC-ON GPIOs Message-ID: <20120117141948.GC16443@linux-mips.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> <1326732224-21336-3-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326732224-21336-3-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32270 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:20:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:21:06 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37011 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903627Ab2AQOUL (ORCPT ); Tue, 17 Jan 2012 15:20:11 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEKAFK016580; Tue, 17 Jan 2012 15:20:10 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEK9Hs016577; Tue, 17 Jan 2012 15:20:09 +0100 Date: Tue, 17 Jan 2012 15:20:09 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Thomas Langer Subject: Re: [PATCH RESEND 06/17] MIPS: lantiq: add support for the EASY98000 evaluation board Message-ID: <20120117142009.GC16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-6-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-6-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32271 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:20:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:21:34 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37156 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903634Ab2AQOUT (ORCPT ); Tue, 17 Jan 2012 15:20:19 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEKH3r016612; Tue, 17 Jan 2012 15:20:17 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEKHPY016611; Tue, 17 Jan 2012 15:20:17 +0100 Date: Tue, 17 Jan 2012 15:20:17 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Thomas Langer Subject: Re: [PATCH RESEND 07/17] MIPS: lantiq: fix early printk Message-ID: <20120117142017.GD16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-7-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-7-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32272 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:20:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:22:05 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37159 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903635Ab2AQOU0 (ORCPT ); Tue, 17 Jan 2012 15:20:26 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEKPqk016623; Tue, 17 Jan 2012 15:20:25 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEKP6s016622; Tue, 17 Jan 2012 15:20:25 +0100 Date: Tue, 17 Jan 2012 15:20:25 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Thomas Langer Subject: Re: [PATCH RESEND 08/17] MIPS: lantiq: fix cmdline parsing Message-ID: <20120117142025.GE16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-8-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-8-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32273 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:20:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:22:44 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37166 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903629Ab2AQOUg (ORCPT ); Tue, 17 Jan 2012 15:20:36 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEKYCs016639; Tue, 17 Jan 2012 15:20:34 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEKXKv016634; Tue, 17 Jan 2012 15:20:33 +0100 Date: Tue, 17 Jan 2012 15:20:33 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Matti Laakso Subject: Re: [PATCH RESEND 09/17] MIPS: lantiq: fix STP gpio groups Message-ID: <20120117142033.GF16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-9-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-9-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32274 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:20:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:23:06 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37269 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903638Ab2AQOUq (ORCPT ); Tue, 17 Jan 2012 15:20:46 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEKilU016648; Tue, 17 Jan 2012 15:20:44 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEKi1K016647; Tue, 17 Jan 2012 15:20:44 +0100 Date: Tue, 17 Jan 2012 15:20:44 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Matti Laakso Subject: Re: [PATCH RESEND 10/17] MIPS: lantiq: fix pull gpio up resistors usage Message-ID: <20120117142044.GG16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-10-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-10-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32275 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:20:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:23:32 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37273 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903637Ab2AQOUz (ORCPT ); Tue, 17 Jan 2012 15:20:55 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEKsl2016662; Tue, 17 Jan 2012 15:20:54 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEKs2Z016661; Tue, 17 Jan 2012 15:20:54 +0100 Date: Tue, 17 Jan 2012 15:20:54 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH RESEND 11/17] MIPS: lantiq: add default configs Message-ID: <20120117142054.GH16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-11-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-11-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32276 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:21:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:23:58 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37285 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903640Ab2AQOVI (ORCPT ); Tue, 17 Jan 2012 15:21:08 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEL82w016674; Tue, 17 Jan 2012 15:21:08 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEL8c5016673; Tue, 17 Jan 2012 15:21:08 +0100 Date: Tue, 17 Jan 2012 15:21:08 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH V2 12/17] MAINTAINERS: add entry for Lantiq related files Message-ID: <20120117142108.GD16443@linux-mips.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> <1326732224-21336-4-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326732224-21336-4-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32277 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:21:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:24:25 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37288 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903641Ab2AQOVR (ORCPT ); Tue, 17 Jan 2012 15:21:17 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HELGUa016701; Tue, 17 Jan 2012 15:21:16 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HELGix016700; Tue, 17 Jan 2012 15:21:16 +0100 Date: Tue, 17 Jan 2012 15:21:16 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH RESEND 13/17] NET: MIPS: lantiq: make etop ethernet work on ase/ar9 Message-ID: <20120117142116.GI16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-13-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-13-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32278 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:21:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:24:50 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37298 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903627Ab2AQOV1 (ORCPT ); Tue, 17 Jan 2012 15:21:27 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HELQIF016734; Tue, 17 Jan 2012 15:21:26 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HELQLV016733; Tue, 17 Jan 2012 15:21:26 +0100 Date: Tue, 17 Jan 2012 15:21:26 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH V2 14/17] NET: MIPS: lantiq: non existing phy was not handled gracefully Message-ID: <20120117142126.GE16443@linux-mips.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> <1326732224-21336-5-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326732224-21336-5-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32279 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:21:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:25:21 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37304 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903643Ab2AQOVk (ORCPT ); Tue, 17 Jan 2012 15:21:40 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HELdd5016750; Tue, 17 Jan 2012 15:21:39 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HELd0P016749; Tue, 17 Jan 2012 15:21:39 +0100 Date: Tue, 17 Jan 2012 15:21:39 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH V2 15/17] NET: MIPS: lantiq: return value of request_irq was not handled gracefully Message-ID: <20120117142139.GF16443@linux-mips.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> <1326732224-21336-6-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326732224-21336-6-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32280 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:21:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:25:45 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37315 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903634Ab2AQOVx (ORCPT ); Tue, 17 Jan 2012 15:21:53 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HELqm1016764; Tue, 17 Jan 2012 15:21:52 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HELqQo016763; Tue, 17 Jan 2012 15:21:52 +0100 Date: Tue, 17 Jan 2012 15:21:52 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org, Felix Fietkau Subject: Re: [PATCH V2 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set Message-ID: <20120117142152.GG16443@linux-mips.org> References: <1326732224-21336-1-git-send-email-blogic@openwrt.org> <1326732224-21336-7-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326732224-21336-7-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32281 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From ralf@linux-mips.org Tue Jan 17 15:22:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 15:26:06 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37321 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903651Ab2AQOWM (ORCPT ); Tue, 17 Jan 2012 15:22:12 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0HEMBJ9016777; Tue, 17 Jan 2012 15:22:11 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0HEMBl8016776; Tue, 17 Jan 2012 15:22:11 +0100 Date: Tue, 17 Jan 2012 15:22:11 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH RESEND 17/17] MIPS: lantiq: enable oprofile support on lantiq targets Message-ID: <20120117142211.GJ16442@linux-mips.org> References: <1326314674-9899-1-git-send-email-blogic@openwrt.org> <1326314674-9899-17-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1326314674-9899-17-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32282 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 35 Lines: 3 Queued for -next. Thanks, Ralf From stern@rowland.harvard.edu Tue Jan 17 16:22:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jan 2012 16:23:04 +0100 (CET) Received: from iolanthe.rowland.org ([192.131.102.54]:46564 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1903622Ab2AQPW5 (ORCPT ); Tue, 17 Jan 2012 16:22:57 +0100 Received: (qmail 2151 invoked by uid 2102); 17 Jan 2012 10:22:51 -0500 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 17 Jan 2012 10:22:51 -0500 Date: Tue, 17 Jan 2012 10:22:50 -0500 (EST) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Kelvin Cheung cc: ralf@linux-mips.org, , , , , , , Subject: Re: [PATCH V6 4/5] USB: Add EHCI bus glue for Loongson1x SoCs In-Reply-To: <1326777160-9930-5-git-send-email-keguang.zhang@gmail.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32283 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1382 Lines: 53 On Tue, 17 Jan 2012, Kelvin Cheung wrote: > The Loongson1x SoCs have a built-in EHCI controller. > This patch adds the necessary glue code to make the generic EHCI > driver usable for them. > --- /dev/null > +++ b/drivers/usb/host/ehci-ls1x.c > @@ -0,0 +1,170 @@ > +/* > + * Bus Glue for Loongson LS1X built-in EHCI controller. > + * > + * Copyright (c) 2012 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > + > +#include > + > +static int ehci_ls1x_setup(struct usb_hcd *hcd) > +{ > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + int ret; > + > + ehci->caps = hcd->regs; > + ehci->regs = hcd->regs + > + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); > + dbg_hcs_params(ehci, "reset"); > + dbg_hcc_params(ehci, "reset"); > + > + /* cache this readonly data; minimize chip reads */ > + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); > + ehci->sbrn = 0x20; > + > + ehci_reset(ehci); > + > + /* data structure init */ > + ret = ehci_init(hcd); > + if (ret) > + return ret; > + > + ehci_port_power(ehci, 0); > + > + return 0; > +} Most of this routine should be replaced with a call to ehci_setup(). Alan Stern From keguang.zhang@gmail.com Wed Jan 18 07:39:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Jan 2012 07:40:05 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:64221 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903642Ab2ARGj5 (ORCPT ); Wed, 18 Jan 2012 07:39:57 +0100 Received: by vbbff1 with SMTP id ff1so3214999vbb.36 for ; Tue, 17 Jan 2012 22:39:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=h2eI1eMOvIGEfdqrptJLqB/4G96ggOIvmoR9KM0uc4A=; b=BcHkPGwSnbeYX2O2hTM5+kH0sYeskeYvHgjlT9lNCOtqtxelLK7tC1w+JTVNORkGjl vKd6CtzpLkYgL2qDI4XIZZvy+T83vDa/uUoDixfwiRBHVnTZEFNwbxIvXz1i/JeBzrKY 44gcBuTNdaf1RG9vLJfi28Y9GApC0ygCCv9mo= Received: by 10.52.93.77 with SMTP id cs13mr2850214vdb.71.1326868791543; Tue, 17 Jan 2012 22:39:51 -0800 (PST) MIME-Version: 1.0 Received: by 10.220.184.1 with HTTP; Tue, 17 Jan 2012 22:39:30 -0800 (PST) In-Reply-To: References: <1326777160-9930-5-git-send-email-keguang.zhang@gmail.com> From: Kelvin Cheung Date: Wed, 18 Jan 2012 14:39:30 +0800 Message-ID: Subject: Re: [PATCH V6 4/5] USB: Add EHCI bus glue for Loongson1x SoCs To: Alan Stern Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-usb@vger.kernel.org, gregkh@suse.de, zhzhl555@gmail.com, peppe.cavallaro@st.com, wuzhangjin@gmail.com, linux-kernel@vger.kernel.org Content-Type: multipart/alternative; boundary=bcaec501652ffbc7eb04b6c7b686 X-archive-position: 32284 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4571 Lines: 146 --bcaec501652ffbc7eb04b6c7b686 Content-Type: text/plain; charset=ISO-8859-1 Done. Thanks for review. 2012/1/17 Alan Stern > On Tue, 17 Jan 2012, Kelvin Cheung wrote: > > > The Loongson1x SoCs have a built-in EHCI controller. > > This patch adds the necessary glue code to make the generic EHCI > > driver usable for them. > > > --- /dev/null > > +++ b/drivers/usb/host/ehci-ls1x.c > > @@ -0,0 +1,170 @@ > > +/* > > + * Bus Glue for Loongson LS1X built-in EHCI controller. > > + * > > + * Copyright (c) 2012 Zhang, Keguang > > + * > > + * This program is free software; you can redistribute it and/or > modify it > > + * under the terms of the GNU General Public License version 2 as > published > > + * by the Free Software Foundation. > > + */ > > + > > + > > +#include > > + > > +static int ehci_ls1x_setup(struct usb_hcd *hcd) > > +{ > > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > + int ret; > > + > > + ehci->caps = hcd->regs; > > + ehci->regs = hcd->regs + > > + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); > > + dbg_hcs_params(ehci, "reset"); > > + dbg_hcc_params(ehci, "reset"); > > + > > + /* cache this readonly data; minimize chip reads */ > > + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); > > + ehci->sbrn = 0x20; > > + > > + ehci_reset(ehci); > > + > > + /* data structure init */ > > + ret = ehci_init(hcd); > > + if (ret) > > + return ret; > > + > > + ehci_port_power(ehci, 0); > > + > > + return 0; > > +} > > Most of this routine should be replaced with a call to ehci_setup(). > > Alan Stern > > -- Best Regards! Kelvin --bcaec501652ffbc7eb04b6c7b686 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Done.

Thanks for review.

2012/1/17 Alan Stern <= span dir=3D"ltr"><stern@row= land.harvard.edu>
On Tue, 17 Jan 2012, Kelvin Cheung wrote:

> The Loongson1x SoCs have a built-in EHCI controller.
> This patch adds the necessary glue code to make the generic EHCI
> driver usable for them.

> --- /dev/null
> +++ b/drivers/usb/host/ehci-ls1x.c
> @@ -0,0 +1,170 @@
> +/*
> + * =A0Bus Glue for Loongson LS1X built-in EHCI controller.
> + *
> + * =A0Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
> + *
> + * =A0This program is free software; you can redistribute it and/or m= odify it
> + * =A0under the terms of the GNU General Public License version 2 as = published
> + * =A0by the Free Software Foundation.
> + */
> +
> +
> +#include <linux/platform_device.h>
> +
> +static int ehci_ls1x_setup(struct usb_hcd *hcd)
> +{
> + =A0 =A0 struct ehci_hcd *ehci =3D hcd_to_ehci(hcd);
> + =A0 =A0 int ret;
> +
> + =A0 =A0 ehci->caps =3D hcd->regs;
> + =A0 =A0 ehci->regs =3D hcd->regs +
> + =A0 =A0 =A0 =A0 =A0 =A0 HC_LENGTH(ehci, ehci_readl(ehci, &ehci-&= gt;caps->hc_capbase));
> + =A0 =A0 dbg_hcs_params(ehci, "reset");
> + =A0 =A0 dbg_hcc_params(ehci, "reset");
> +
> + =A0 =A0 /* cache this readonly data; minimize chip reads */
> + =A0 =A0 ehci->hcs_params =3D ehci_readl(ehci, &ehci->caps-= >hcs_params);
> + =A0 =A0 ehci->sbrn =3D 0x20;
> +
> + =A0 =A0 ehci_reset(ehci);
> +
> + =A0 =A0 /* data structure init */
> + =A0 =A0 ret =3D ehci_init(hcd);
> + =A0 =A0 if (ret)
> + =A0 =A0 =A0 =A0 =A0 =A0 return ret;
> +
> + =A0 =A0 ehci_port_power(ehci, 0);
> +
> + =A0 =A0 return 0;
> +}

Most of this routine should be replaced with a call to ehci_set= up().

Alan Stern




--
Best Rega= rds!
Kelvin



--bcaec501652ffbc7eb04b6c7b686-- From keguang.zhang@gmail.com Wed Jan 18 07:41:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Jan 2012 07:41:48 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:55727 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903642Ab2ARGll (ORCPT ); Wed, 18 Jan 2012 07:41:41 +0100 Received: by iaek3 with SMTP id k3so2806173iae.36 for ; Tue, 17 Jan 2012 22:41:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=voOQieJyfw4JAhYKCS5Oh7W8ml8pui59WKV6EPo192Q=; b=sAMpY+nMIOPVVlKeOvi7ZdgNnTJ1WHdD1HnKvgFXVhn3v3loN2xIoIyhcEMUqxX7s+ heUq4oLIwOqHb+ZN308hGeB/ClZmLV07nOWeA1ppCWhPzM6nZxNb0le8OEtTAri6NwyB Us0lpqk/DcsYyUIAwdR8ONtoOq+iBP5HvAJkI= Received: by 10.50.51.199 with SMTP id m7mr18494705igo.23.1326868894832; Tue, 17 Jan 2012 22:41:34 -0800 (PST) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id gh7sm42941173igb.1.2012.01.17.22.41.28 (version=SSLv3 cipher=OTHER); Tue, 17 Jan 2012 22:41:33 -0800 (PST) From: Kelvin Cheung To: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, ralf@linux-mips.org, linux-mips@linux-mips.org Cc: gregkh@suse.de, wuzhangjin@gmail.com, linux-kernel@vger.kernel.org, Kelvin Cheung Subject: [PATCH V6 4/5] USB: Add EHCI bus glue for Loongson1x SoCs (UPDATED) Date: Wed, 18 Jan 2012 14:41:16 +0800 Message-Id: <1326868876-20271-1-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 X-archive-position: 32285 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5249 Lines: 210 Use ehci_setup() in ehci_ls1x_reset(). The Loongson1x SoCs have a built-in EHCI controller. This patch adds the necessary glue code to make the generic EHCI driver usable for them. Signed-off-by: Kelvin Cheung --- drivers/usb/Kconfig | 1 + drivers/usb/host/ehci-hcd.c | 5 ++ drivers/usb/host/ehci-ls1x.c | 159 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-ls1x.c diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 85d5a01..78ac78b 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -68,6 +68,7 @@ config USB_ARCH_HAS_EHCI default y if ARCH_MSM default y if MICROBLAZE default y if SPARC_LEON + default y if MACH_LOONGSON1 default PCI # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface. diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 47aa22d..d38bd7c 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1291,6 +1291,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_grlib_driver #endif +#ifdef CONFIG_MACH_LOONGSON1 +#include "ehci-ls1x.c" +#define PLATFORM_DRIVER ehci_ls1x_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-ls1x.c b/drivers/usb/host/ehci-ls1x.c new file mode 100644 index 0000000..a283e59 --- /dev/null +++ b/drivers/usb/host/ehci-ls1x.c @@ -0,0 +1,159 @@ +/* + * Bus Glue for Loongson LS1X built-in EHCI controller. + * + * Copyright (c) 2012 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + + +#include + +static int ehci_ls1x_reset(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int ret; + + ehci->caps = hcd->regs; + + ret = ehci_setup(hcd); + if (ret) + return ret; + + ehci_port_power(ehci, 0); + + return 0; +} + +static const struct hc_driver ehci_ls1x_hc_driver = { + .description = hcd_name, + .product_desc = "LOONGSON1 EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + */ + .reset = ehci_ls1x_reset, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_hcd_ls1x_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + pr_debug("initializing loongson1 ehci USB Controller\n"); + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no register addr. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + + hcd = usb_create_hcd(&ehci_ls1x_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + hcd->rsrc_start = res->start; + hcd->rsrc_len = resource_size(res); + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (hcd->regs == NULL) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (ret) + goto err_iounmap; + + return ret; + +err_iounmap: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_hcd_ls1x_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static struct platform_driver ehci_ls1x_driver = { + .probe = ehci_hcd_ls1x_probe, + .remove = ehci_hcd_ls1x_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ls1x-ehci", + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ls1x-ehci"); -- 1.7.1 From zhzhl555@gmail.com Wed Jan 18 09:17:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Jan 2012 09:17:34 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:45078 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903644Ab2ARIR3 (ORCPT ); Wed, 18 Jan 2012 09:17:29 +0100 Received: by iaek3 with SMTP id k3so2936362iae.36 for ; Wed, 18 Jan 2012 00:17:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=+iHo++QyNRacD9jZZIa7YgpJ+yaG/X4PHFCTZy2f/+Y=; b=pXzkXI1sHmgDo+qe5n89hwcV2zH8BEpqRHfI42qZDEEPyq5E5GZCJXr3RLFT4a4gZW G1qh1owWs398EZolwzkRZ7q/avGCylcEXBtidyfumaUzUgpXYnMQrOOSlVIhmZSIX3DB a56ccACgOzLHvR/YkO4Hnn8ldMWlzTLKEAdpA= Received: by 10.50.87.132 with SMTP id ay4mr1270389igb.2.1326874643357; Wed, 18 Jan 2012 00:17:23 -0800 (PST) Received: from localhost.localdomain ([182.148.112.76]) by mx.google.com with ESMTPS id 5sm86504429ibe.8.2012.01.18.00.17.16 (version=SSLv3 cipher=OTHER); Wed, 18 Jan 2012 00:17:21 -0800 (PST) From: zhzhl555@gmail.com To: a.zummo@towertech.it, rtc-linux@googlegroups.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: ralf@linux-mips.org, keguang.zhang@gmail.com, wuzhangjin@gmail.com, r0bertz@gentoo.org, zhao zhang Subject: [PATCH V3] MIPS: Add RTC support for loongson1B Date: Wed, 18 Jan 2012 16:17:04 +0800 Message-Id: <1326874624-17867-1-git-send-email-zhzhl555@gmail.com> X-Mailer: git-send-email 1.7.0.4 X-archive-position: 32286 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhzhl555@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 7678 Lines: 268 From: zhao zhang This patch adds RTC support(TOY counter0) for loongson1B SOC change log: V3:Remove sync instruction. V2:Use new module_platform_driver macro. V1:Replace __raw_writel/__raw_readl with writel/readl. Signed-off-by: zhao zhang --- drivers/rtc/Kconfig | 10 +++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-ls1x.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 222 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/rtc-ls1x.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 5a538fc..6f8c2d7 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1070,4 +1070,14 @@ config RTC_DRV_PUV3 This drive can also be built as a module. If so, the module will be called rtc-puv3. +config RTC_DRV_LOONGSON1 + tristate "loongson1 RTC support" + depends on MACH_LOONGSON1 + help + This is a driver for the loongson1 on-chip Counter0 (Time-Of-Year + counter) to be used as a RTC. + + This driver can also be built as a module. If so, the module + will be called rtc-ls1x. + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 6e69823..6c9387a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o obj-$(CONFIG_RTC_DRV_LPC32XX) += rtc-lpc32xx.o +obj-$(CONFIG_RTC_DRV_LOONGSON1) += rtc-ls1x.o obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o obj-$(CONFIG_RTC_DRV_M41T93) += rtc-m41t93.o obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o diff --git a/drivers/rtc/rtc-ls1x.c b/drivers/rtc/rtc-ls1x.c new file mode 100644 index 0000000..7305986 --- /dev/null +++ b/drivers/rtc/rtc-ls1x.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2011 Zhao Zhang + * + * Derived from driver/rtc/rtc-au1xxx.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LS1X_RTC_REG_OFFSET (LS1X_RTC_BASE + 0x20) +#define LS1X_RTC_REGS(x) \ + ((void __iomem *)KSEG1ADDR(LS1X_RTC_REG_OFFSET + (x))) + +/*RTC programmable counters 0 and 1*/ +#define SYS_COUNTER_CNTRL (LS1X_RTC_REGS(0x20)) +#define SYS_CNTRL_ERS (1 << 23) +#define SYS_CNTRL_RTS (1 << 20) +#define SYS_CNTRL_RM2 (1 << 19) +#define SYS_CNTRL_RM1 (1 << 18) +#define SYS_CNTRL_RM0 (1 << 17) +#define SYS_CNTRL_RS (1 << 16) +#define SYS_CNTRL_BP (1 << 14) +#define SYS_CNTRL_REN (1 << 13) +#define SYS_CNTRL_BRT (1 << 12) +#define SYS_CNTRL_TEN (1 << 11) +#define SYS_CNTRL_BTT (1 << 10) +#define SYS_CNTRL_E0 (1 << 8) +#define SYS_CNTRL_ETS (1 << 7) +#define SYS_CNTRL_32S (1 << 5) +#define SYS_CNTRL_TTS (1 << 4) +#define SYS_CNTRL_TM2 (1 << 3) +#define SYS_CNTRL_TM1 (1 << 2) +#define SYS_CNTRL_TM0 (1 << 1) +#define SYS_CNTRL_TS (1 << 0) + +/* Programmable Counter 0 Registers */ +#define SYS_TOYTRIM (LS1X_RTC_REGS(0)) +#define SYS_TOYWRITE0 (LS1X_RTC_REGS(4)) +#define SYS_TOYWRITE1 (LS1X_RTC_REGS(8)) +#define SYS_TOYREAD0 (LS1X_RTC_REGS(0xC)) +#define SYS_TOYREAD1 (LS1X_RTC_REGS(0x10)) +#define SYS_TOYMATCH0 (LS1X_RTC_REGS(0x14)) +#define SYS_TOYMATCH1 (LS1X_RTC_REGS(0x18)) +#define SYS_TOYMATCH2 (LS1X_RTC_REGS(0x1C)) + +/* Programmable Counter 1 Registers */ +#define SYS_RTCTRIM (LS1X_RTC_REGS(0x40)) +#define SYS_RTCWRITE0 (LS1X_RTC_REGS(0x44)) +#define SYS_RTCREAD0 (LS1X_RTC_REGS(0x48)) +#define SYS_RTCMATCH0 (LS1X_RTC_REGS(0x4C)) +#define SYS_RTCMATCH1 (LS1X_RTC_REGS(0x50)) +#define SYS_RTCMATCH2 (LS1X_RTC_REGS(0x54)) + +#define LS1X_SEC_OFFSET (4) +#define LS1X_MIN_OFFSET (10) +#define LS1X_HOUR_OFFSET (16) +#define LS1X_DAY_OFFSET (21) +#define LS1X_MONTH_OFFSET (26) + + +#define LS1X_SEC_MASK (0x3f) +#define LS1X_MIN_MASK (0x3f) +#define LS1X_HOUR_MASK (0x1f) +#define LS1X_DAY_MASK (0x1f) +#define LS1X_MONTH_MASK (0x3f) +#define LS1X_YEAR_MASK (0xffffffff) + +#define ls1x_get_sec(t) (((t) >> LS1X_SEC_OFFSET) & LS1X_SEC_MASK) +#define ls1x_get_min(t) (((t) >> LS1X_MIN_OFFSET) & LS1X_MIN_MASK) +#define ls1x_get_hour(t) (((t) >> LS1X_HOUR_OFFSET) & LS1X_HOUR_MASK) +#define ls1x_get_day(t) (((t) >> LS1X_DAY_OFFSET) & LS1X_DAY_MASK) +#define ls1x_get_month(t) (((t) >> LS1X_MONTH_OFFSET) & LS1X_MONTH_MASK) + +#define RTC_CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) + +static int ls1x_rtc_read_time(struct device *dev, struct rtc_time *rtm) +{ + unsigned long v, t; + + v = readl(SYS_TOYREAD0); + t = readl(SYS_TOYREAD1); + + memset(rtm, 0, sizeof(struct rtc_time)); + t = mktime((t & LS1X_YEAR_MASK), ls1x_get_month(v), + ls1x_get_day(v), ls1x_get_hour(v), + ls1x_get_min(v), ls1x_get_sec(v)); + rtc_time_to_tm(t, rtm); + + return rtc_valid_tm(rtm); +} + +static int ls1x_rtc_set_time(struct device *dev, struct rtc_time *rtm) +{ + unsigned long v, t, c; + int ret = -ETIMEDOUT; + + v = ((rtm->tm_mon + 1) << LS1X_MONTH_OFFSET) + | (rtm->tm_mday << LS1X_DAY_OFFSET) + | (rtm->tm_hour << LS1X_HOUR_OFFSET) + | (rtm->tm_min << LS1X_MIN_OFFSET) + | (rtm->tm_sec << LS1X_SEC_OFFSET); + + writel(v, SYS_TOYWRITE0); + c = 0x10000; + /* add timeout check counter, for more safe */ + while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c) + usleep_range(1000, 3000); + + if (!c) { + dev_err(dev, "set time timeout!\n"); + goto err; + } + + t = rtm->tm_year + 1900; + writel(t, SYS_TOYWRITE1); + c = 0x10000; + while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c) + usleep_range(1000, 3000); + + if (!c) { + dev_err(dev, "set time timeout!\n"); + goto err; + } + return 0; +err: + return ret; +} + +static struct rtc_class_ops ls1x_rtc_ops = { + .read_time = ls1x_rtc_read_time, + .set_time = ls1x_rtc_set_time, +}; + +static int __devinit ls1x_rtc_probe(struct platform_device *pdev) +{ + struct rtc_device *rtcdev; + unsigned long v; + int ret; + + v = readl(SYS_COUNTER_CNTRL); + if (!(v & RTC_CNTR_OK)) { + dev_err(&pdev->dev, "rtc counters not working\n"); + ret = -ENODEV; + goto err; + } + ret = -ETIMEDOUT; + /* set to 1 HZ if needed */ + if (readl(SYS_TOYTRIM) != 32767) { + v = 0x100000; + while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS) && --v) + usleep_range(1000, 3000); + + if (!v) { + dev_err(&pdev->dev, "time out\n"); + goto err; + } + writel(32767, SYS_TOYTRIM); + } + /* this loop coundn't be endless */ + while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS) + usleep_range(1000, 3000); + + rtcdev = rtc_device_register("ls1x-rtc", &pdev->dev, + &ls1x_rtc_ops , THIS_MODULE); + if (IS_ERR(rtcdev)) { + ret = PTR_ERR(rtcdev); + goto err; + } + + platform_set_drvdata(pdev, rtcdev); + return 0; +err: + return ret; +} + +static int __devexit ls1x_rtc_remove(struct platform_device *pdev) +{ + struct rtc_device *rtcdev = platform_get_drvdata(pdev); + + rtc_device_unregister(rtcdev); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver ls1x_rtc_driver = { + .driver = { + .name = "ls1x-rtc", + .owner = THIS_MODULE, + }, + .remove = __devexit_p(ls1x_rtc_remove), + .probe = ls1x_rtc_probe, +}; + +module_platform_driver(ls1x_rtc_driver); + +MODULE_AUTHOR("zhao zhang "); +MODULE_LICENSE("GPL"); + -- 1.7.0.4 From ralf@linux-mips.org Wed Jan 18 14:38:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Jan 2012 14:38:33 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40488 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903649Ab2ARNia (ORCPT ); Wed, 18 Jan 2012 14:38:30 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0IDcS7C019462; Wed, 18 Jan 2012 14:38:28 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0IDcRIc019461; Wed, 18 Jan 2012 14:38:27 +0100 Date: Wed, 18 Jan 2012 14:38:27 +0100 From: Ralf Baechle To: Gabor Juhos Cc: linux-mips@linux-mips.org, Rene Bolldorf Subject: Re: [PATCH v4 0/7] MIPS: ath79: cleanup AR724X PCI support code Message-ID: <20120118133827.GA15510@linux-mips.org> References: <1321887999-14546-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1321887999-14546-1-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32287 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 46 Lines: 5 Whole series queued for 3.4. Thanks, Ralf From ralf@linux-mips.org Wed Jan 18 14:59:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Jan 2012 14:59:43 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:60600 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903651Ab2ARN7j (ORCPT ); Wed, 18 Jan 2012 14:59:39 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0IDxbhs020835; Wed, 18 Jan 2012 14:59:37 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0IDxbri020834; Wed, 18 Jan 2012 14:59:37 +0100 Date: Wed, 18 Jan 2012 14:59:37 +0100 From: Ralf Baechle To: Gabor Juhos Cc: linux-mips@linux-mips.org, =?iso-8859-1?Q?Ren=E9?= Bolldorf , Imre Kaloz Subject: Re: [PATCH v2 00/12] MIPS: ath79: AR724X PCI fixes and AR71XX PCI support Message-ID: <20120118135937.GB15510@linux-mips.org> References: <1322157367-31089-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1322157367-31089-1-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32288 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 59 Lines: 5 I queued this entire series also for 3.4. Thanks, Ralf From ralf@linux-mips.org Wed Jan 18 15:13:06 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Jan 2012 15:13:10 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47893 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903651Ab2ARONG (ORCPT ); Wed, 18 Jan 2012 15:13:06 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0IED4s9021575; Wed, 18 Jan 2012 15:13:04 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0IED4K5021574; Wed, 18 Jan 2012 15:13:04 +0100 Date: Wed, 18 Jan 2012 15:13:04 +0100 From: Ralf Baechle To: Gabor Juhos Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: ath79: avoid a kernel bug on AR913X Message-ID: <20120118141304.GC15510@linux-mips.org> References: <1323619901-2512-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1323619901-2512-1-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32289 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 25 Lines: 3 Thanks, applied. Ralf From linus.walleij@linaro.org Thu Jan 19 14:53:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Jan 2012 14:53:34 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:56023 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903678Ab2ASNx2 (ORCPT ); Thu, 19 Jan 2012 14:53:28 +0100 Received: by yenq11 with SMTP id q11so2398942yen.36 for ; Thu, 19 Jan 2012 05:53:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=WWjBx+0Q1HAvBofe2lJgOo/gmM9rcYdBwI+QmxB5wiU=; b=ZVj3CUc7w8CHWoTycF0gPwAbbskMhr2ZvpYBCpOnXATrl9wiXc6Q5p1/aBz2cRslzf 5tZPvRCiZyfijhYFm7Tl77ZsEZpgDHa69zJZOc5LcDDxk1r2UwJ35m/DArAyV8fRisWR ZLCKZ+rV/+nBAWuCn+Rnyd02x3Bj4ofRLAD3U= MIME-Version: 1.0 Received: by 10.236.185.8 with SMTP id t8mr39417777yhm.30.1326981202654; Thu, 19 Jan 2012 05:53:22 -0800 (PST) Received: by 10.146.167.5 with HTTP; Thu, 19 Jan 2012 05:53:22 -0800 (PST) In-Reply-To: <1326874624-17867-1-git-send-email-zhzhl555@gmail.com> References: <1326874624-17867-1-git-send-email-zhzhl555@gmail.com> Date: Thu, 19 Jan 2012 14:53:22 +0100 X-Google-Sender-Auth: 5W650dofBqf57SOlMFCKhTsCwkM Message-ID: Subject: Re: [PATCH V3] MIPS: Add RTC support for loongson1B From: Linus Walleij To: zhzhl555@gmail.com, Andrew Morton Cc: a.zummo@towertech.it, rtc-linux@googlegroups.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ralf@linux-mips.org, keguang.zhang@gmail.com, wuzhangjin@gmail.com, r0bertz@gentoo.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32290 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linus.walleij@linaro.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 519 Lines: 21 2012/1/18 : > From: zhao zhang > > This patch adds RTC support(TOY counter0) for loongson1B SOC > > change log: > V3:Remove sync instruction. > V2:Use new module_platform_driver macro. > V1:Replace __raw_writel/__raw_readl with writel/readl. > > Signed-off-by: zhao zhang I think this is looking good now. Acked-by: Linus Walleij You need Andrew to pick it up though, so send it directly to him as well. Yours, Linus Walleij From viric@viric.name Thu Jan 19 21:40:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Jan 2012 21:40:26 +0100 (CET) Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:62725 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903680Ab2ASUkW (ORCPT ); Thu, 19 Jan 2012 21:40:22 +0100 Received: from 117.235.221.87.dynamic.jazztel.es ([87.221.235.117] helo=mail.viric.name) by mho-02-ewr.mailhop.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1RnymO-000FoO-22 for linux-mips@linux-mips.org; Thu, 19 Jan 2012 20:40:16 +0000 Received: by mail.viric.name (Postfix, from userid 1000) id F02EE501572; Thu, 19 Jan 2012 21:40:10 +0100 (CET) X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 87.221.235.117 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1+qPrO3l8/LjBQxUb3410Kh Date: Thu, 19 Jan 2012 21:40:10 +0100 From: =?iso-8859-1?Q?Llu=EDs?= Batlle i Rossell To: linux-mips@linux-mips.org Subject: Remove a Kconfig warning on 3.2.1 for fuloong2f Message-ID: <20120119204010.GR21947@vicerveza.homeunix.net> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="HSQ3hISbU3Um6hch" Content-Disposition: inline X-Accept-Language: ca, es, eo, ru, en, jbo, tokipona User-Agent: Mutt/1.5.20 (2009-06-14) Content-Transfer-Encoding: 7bit X-archive-position: 32291 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: viric@viric.name Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2139 Lines: 73 --HSQ3hISbU3Um6hch Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hello, building the kernel 3.2.1 for the fuloong2f I hit a warning at every 'mak= e nconfig'. Here is a patch that takes out the warning, but someone that understands = better than me should check I did not break anything. Regards, Llu=EDs. --HSQ3hISbU3Um6hch Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="0001-Remove-a-warning-I-saw-on-make-nconfig-for-the-Fuloo.patch" >From 4dd3da2b4290b5e790e07d24d2e6daa7cb989ee3 Mon Sep 17 00:00:00 2001 From: Lluis Batlle Date: Thu, 19 Jan 2012 21:35:44 +0100 Subject: [PATCH] Remove a warning I saw on 'make nconfig' for the Fuloong2F. The warning was: warning: (LEMOTE_FULOONG2E && LEMOTE_MACH2F && DEXXON_GDIUM) selects ARCH_SPARSEMEM_ENABLE which has unmet direct dependencies (CPU_CAVIUM_OCTEON) I followed advices from daney on irc. I don't know how to test it, but now I don't see the warning at least. --- arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/Kconfig | 4 ---- 2 files changed, 1 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d46f1da..330800d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1404,6 +1404,7 @@ config CPU_CAVIUM_OCTEON select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select ARCH_SPARSEMEM_ENABLE help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index cad555e..15ba565 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -82,10 +82,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY help Lock the kernel's implementation of memcpy() into L2. -config ARCH_SPARSEMEM_ENABLE - def_bool y - select SPARSEMEM_STATIC - config CAVIUM_OCTEON_HELPER def_bool y depends on OCTEON_ETHERNET || PCI -- 1.7.8 --HSQ3hISbU3Um6hch-- From viric@viric.name Thu Jan 19 22:08:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Jan 2012 22:08:42 +0100 (CET) Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:49310 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903682Ab2ASVIj (ORCPT ); Thu, 19 Jan 2012 22:08:39 +0100 Received: from 117.235.221.87.dynamic.jazztel.es ([87.221.235.117] helo=mail.viric.name) by mho-02-ewr.mailhop.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1RnzDl-0004ns-Gm for linux-mips@linux-mips.org; Thu, 19 Jan 2012 21:08:33 +0000 Received: by mail.viric.name (Postfix, from userid 1000) id 402F0501577; Thu, 19 Jan 2012 22:08:29 +0100 (CET) X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 87.221.235.117 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX19fVaDWXVA3AANlm1Plne6X Date: Thu, 19 Jan 2012 22:08:29 +0100 From: =?iso-8859-1?Q?Llu=EDs?= Batlle i Rossell To: linux-mips@linux-mips.org Subject: MIPS: [PATCH] Fix on Kconfig warning, building for Fuloong2f Message-ID: <20120119210829.GS21947@vicerveza.homeunix.net> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="3MHXEHrrXKLGx71o" Content-Disposition: inline X-Accept-Language: ca, es, eo, ru, en, jbo, tokipona User-Agent: Mutt/1.5.20 (2009-06-14) Content-Transfer-Encoding: 7bit X-archive-position: 32292 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: viric@viric.name Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2257 Lines: 75 --3MHXEHrrXKLGx71o Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable I resubmit the patch I sent some minutes ago, now following better Documentation/SubmittingPatches. Regards, Llu=EDs. --3MHXEHrrXKLGx71o Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: attachment; filename="0001-Remove-a-warning-I-saw-on-make-nconfig-for-the-Fuloo.patch" Content-Transfer-Encoding: quoted-printable >From 533a82b8ffec030d316e22d01a16211c0a3c645d Mon Sep 17 00:00:00 2001 From: =3D?UTF-8?q?Llu=3DC3=3DADs=3D20Batlle=3D20i=3D20Rossell?=3D Date: Thu, 19 Jan 2012 21:35:44 +0100 Subject: [PATCH] Remove a warning I saw on 'make nconfig' for the Fuloong= 2F. MIME-Version: 1.0 Content-Type: text/plain; charset=3DUTF-8 Content-Transfer-Encoding: 8bit The warning was: warning: (LEMOTE_FULOONG2E && LEMOTE_MACH2F && DEXXON_GDIUM) selects ARCH_SPARSEMEM_ENABLE which has unmet direct dependencies (CPU_CAVIUM_OCTEON) I followed advices from daney on irc. I don't know how to test it, but now I don't see the warning at least. Signed-off-by: Llu=EDs Batlle i Rossell --- arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/Kconfig | 4 ---- 2 files changed, 1 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d46f1da..330800d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1404,6 +1404,7 @@ config CPU_CAVIUM_OCTEON select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select ARCH_SPARSEMEM_ENABLE help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kc= onfig index cad555e..15ba565 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -82,10 +82,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY help Lock the kernel's implementation of memcpy() into L2. =20 -config ARCH_SPARSEMEM_ENABLE - def_bool y - select SPARSEMEM_STATIC - config CAVIUM_OCTEON_HELPER def_bool y depends on OCTEON_ETHERNET || PCI --=20 1.7.8 --3MHXEHrrXKLGx71o-- From zumeng.chen@windriver.com Fri Jan 20 04:32:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Jan 2012 04:32:54 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:46448 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903687Ab2ATDcu (ORCPT ); Fri, 20 Jan 2012 04:32:50 +0100 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q0K3WhtB005254 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL) for ; Thu, 19 Jan 2012 19:32:43 -0800 (PST) Received: from [128.224.162.181] (128.224.162.181) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id 14.1.255.0; Thu, 19 Jan 2012 19:32:43 -0800 Message-ID: <4F18DFD6.5040802@windriver.com> Date: Fri, 20 Jan 2012 11:30:30 +0800 From: Zumeng Chen User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.24) Gecko/20111108 Lightning/1.0b2 Thunderbird/3.1.16 MIME-Version: 1.0 To: Subject: Hello, this is test email, please ignore it. Content-Type: text/plain; charset="GB2312" Content-Transfer-Encoding: 7bit X-archive-position: 32293 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zumeng.chen@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1 Lines: 1 From zumeng.chen@windriver.com Sat Jan 21 04:25:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 04:25:57 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:62234 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901161Ab2AUDZu (ORCPT ); Sat, 21 Jan 2012 04:25:50 +0100 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q0L3PSRL004771 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Fri, 20 Jan 2012 19:25:29 -0800 (PST) Received: from [128.224.162.181] (128.224.162.181) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id 14.1.255.0; Fri, 20 Jan 2012 19:25:28 -0800 Message-ID: <4F1A2F96.2040106@windriver.com> Date: Sat, 21 Jan 2012 11:23:02 +0800 From: Zumeng Chen User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.24) Gecko/20111108 Lightning/1.0b2 Thunderbird/3.1.16 MIME-Version: 1.0 To: , CC: , , , , Subject: Re: [PATCH 1/1] mm: msync: fix issues of sys_msync on tmpfs References: <1327036719-1965-1-git-send-email-zumeng.chen@windriver.com> In-Reply-To: <1327036719-1965-1-git-send-email-zumeng.chen@windriver.com> Content-Type: text/plain; charset="GB2312" Content-Transfer-Encoding: 8bit X-archive-position: 32294 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zumeng.chen@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2965 Lines: 88 To: linux-mm@kvack.org, and linux-mips@linux-mips.org ÓÚ 2012Äê01ÔÂ20ÈÕ 13:18, Zumeng Chen дµÀ: > This patch fixes two issues as follows: > > For some filesystem with fsync == noop_fsync, there is not so much thing > to do, so sys_msync just passes by for all arches but some CPUs. > > For some CPUs with cache aliases(dmesg|grep alias), it maybe has an issue, > which reported by msync test suites in ltp-full when the memory of memset > used by msync01 runs into cache alias randomly. > > Consider the following scenario used by msync01 in ltp-full: > fildes = open(TEMPFILE, O_RDWR | O_CREAT, 0666)) < 0); > .../* initialization fildes by write(fildes); */ > addr = mmap(0, page_sz, PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, > fildes, 0); > /* set buf with memset */ > memset(addr + OFFSET_1, 1, BUF_SIZE); > > /* msync the addr before using, or MS_SYNC*/ > msync(addr, page_sz, MS_ASYNC) > > /* Tries to read fildes */ > lseek(fildes, (off_t) OFFSET_1, SEEK_SET) != (off_t) OFFSET_1) { > nread = read(fildes, read_buf, sizeof(read_buf)); > > /* Then test the result */ > if (read_buf[count] != 1) { > > The test result is random too for CPUs with cache alias. So in this > situation, we have to flush the related vma to make sure the read is > correct. > > Signed-off-by: Zumeng Chen > --- > mm/msync.c | 30 ++++++++++++++++++++++++++++++ > 1 files changed, 30 insertions(+), 0 deletions(-) > > diff --git a/mm/msync.c b/mm/msync.c > index 632df45..0021a7e 100644 > --- a/mm/msync.c > +++ b/mm/msync.c > @@ -13,6 +13,14 @@ > #include > #include > #include > +#include > + > +/* Cache aliases should be taken into accounts when msync. */ > +#ifdef cpu_has_dc_aliases > +#define CPU_HAS_CACHE_ALIAS cpu_has_dc_aliases > +#else > +#define CPU_HAS_CACHE_ALIAS 0 > +#endif > > /* > * MS_SYNC syncs the entire file - including mappings. > @@ -78,6 +86,28 @@ SYSCALL_DEFINE3(msync, unsigned long, start, size_t, len, int, flags) > } > file = vma->vm_file; > start = vma->vm_end; > + > + /* > + * For some filesystems with fsync == noop_fsync, msync just > + * passes by but some CPUs. > + * For CPUs with cache alias, msync has to flush the related > + * vma explicitly to make sure data coherency between memory > + * and cache, which includes MS_SYNC or MS_ASYNC. That is to > + * say, cache aliases should not be an async factor, so does > + * msync on other arches without cache aliases. > + */ > + if (file && file->f_op && file->f_op->fsync == noop_fsync) { > + if (CPU_HAS_CACHE_ALIAS) > + flush_cache_range(vma, vma->vm_start, > + vma->vm_end); > + if (start >= end) { > + error = 0; > + goto out_unlock; > + } > + vma = find_vma(mm, start); > + continue; > + } > + > if ((flags & MS_SYNC) && file && > (vma->vm_flags & VM_SHARED)) { > get_file(file); From manuel.lauss@googlemail.com Sat Jan 21 18:13:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 18:13:32 +0100 (CET) Received: from mail-ee0-f49.google.com ([74.125.83.49]:55273 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901168Ab2AURNZ (ORCPT ); Sat, 21 Jan 2012 18:13:25 +0100 Received: by eekb15 with SMTP id b15so594794eek.36 for ; Sat, 21 Jan 2012 09:13:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=CT6f+gaBJGPZYMQj1S2RcFUvZvxOBVi4qfoh1Jk+CnA=; b=jjnrPAhgwKPABZWSVkcoNiSlU2EpR6d+ZZ6oELL7PLKUXXOUgTwmtxbiwjJNTqjrqI t/N1yOJW9cGA1AlkN/DtML3AEuztLtpKxMdHlUNEocNPke4cR7UVn5tcSuQuR9POWQlN t6MHzoM7q/gGLKQf0KrYuUNOj96zNvOSlLmVo= Received: by 10.213.29.5 with SMTP id o5mr496307ebc.140.1327166000559; Sat, 21 Jan 2012 09:13:20 -0800 (PST) Received: from flagship.roarinelk.net (188-22-10-45.adsl.highway.telekom.at. [188.22.10.45]) by mx.google.com with ESMTPS id x4sm28076665eeb.4.2012.01.21.09.13.18 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 21 Jan 2012 09:13:19 -0800 (PST) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 0/3] MIPS: Alchemy: updates for 3.4 Date: Sat, 21 Jan 2012 18:13:12 +0100 Message-Id: <1327165995-27425-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.8.4 X-archive-position: 32295 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 656 Lines: 21 Here's all I have for the next few merge windows: A cleanup and another DB1200 improvement. Thanks, Manuel Lauss Manuel Lauss (3): MIPS: Alchemy: use 64MB RAM as minimum for devboards MIPS: Alchemy: devboards: kill prom.c MIPS: Alchemy: handle db1200 cpld ints as they come in arch/mips/alchemy/devboards/Makefile | 2 +- arch/mips/alchemy/devboards/bcsr.c | 5 +-- arch/mips/alchemy/devboards/platform.c | 30 ++++++++++++++ arch/mips/alchemy/devboards/prom.c | 69 -------------------------------- 4 files changed, 32 insertions(+), 74 deletions(-) delete mode 100644 arch/mips/alchemy/devboards/prom.c -- 1.7.8.4 From manuel.lauss@googlemail.com Sat Jan 21 18:13:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 18:13:53 +0100 (CET) Received: from mail-ee0-f49.google.com ([74.125.83.49]:59112 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901169Ab2AURN1 (ORCPT ); Sat, 21 Jan 2012 18:13:27 +0100 Received: by eekb15 with SMTP id b15so594801eek.36 for ; Sat, 21 Jan 2012 09:13:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=uyHfO1ir7FPcevJpabYYStNy0PQ1TDoqyB13jamPHdg=; b=t6f4pEY6QUe0jgsdrPaC6cwjPzPivuLtd2lTbN9voUFyCJD5v0do1J8WrXiH9sf8P1 NeQ6Ke2XsfFM/gaN+/kLFc9eoCpHpd1eqMe0nbXcWH9mq3OI/nt+nD1d7mTqGYFq1EfL qd/jdEhm4C8CXzdEOyGGgpGilqcJTZ5KbQUoM= Received: by 10.14.16.145 with SMTP id h17mr798991eeh.62.1327166001883; Sat, 21 Jan 2012 09:13:21 -0800 (PST) Received: from flagship.roarinelk.net (188-22-10-45.adsl.highway.telekom.at. [188.22.10.45]) by mx.google.com with ESMTPS id x4sm28076665eeb.4.2012.01.21.09.13.20 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 21 Jan 2012 09:13:21 -0800 (PST) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 1/3] MIPS: Alchemy: use 64MB RAM as minimum for devboards Date: Sat, 21 Jan 2012 18:13:13 +0100 Message-Id: <1327165995-27425-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.8.4 In-Reply-To: <1327165995-27425-1-git-send-email-manuel.lauss@googlemail.com> References: <1327165995-27425-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 32296 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1269 Lines: 41 YAMON on all devboards provides the "memsize" envvar; in the unlikely case that it can't be parsed just assume 64MB, which all boards have at least. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/prom.c | 11 +---------- 1 files changed, 1 insertions(+), 10 deletions(-) diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index 93a2210..57320f2 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -33,15 +33,6 @@ #include #include -#if defined(CONFIG_MIPS_DB1000) || \ - defined(CONFIG_MIPS_PB1100) || \ - defined(CONFIG_MIPS_PB1500) -#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 - -#else /* Au1550/Au1200-based develboards */ -#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000 -#endif - void __init prom_init(void) { unsigned char *memsize_str; @@ -54,7 +45,7 @@ void __init prom_init(void) prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) - memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; + memsize = 64 << 20; /* all devboards have at least 64MB RAM */ add_memory_region(0, memsize, BOOT_MEM_RAM); } -- 1.7.8.4 From manuel.lauss@googlemail.com Sat Jan 21 18:13:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 18:14:17 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:60695 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901170Ab2AURN2 (ORCPT ); Sat, 21 Jan 2012 18:13:28 +0100 Received: by eaak10 with SMTP id k10so321445eaa.36 for ; Sat, 21 Jan 2012 09:13:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=vDqDNqTHj9I3kc3co90X3wTQCwcet0EFeLKAue6yMMA=; b=PY9hkLSHniq3yuPLi60IoUsE8jy+3lDyybJU3pV6tCSu+1bGxkAGv1XhMQZV+2xVvi Aih1WQyGRSoDhElfhqrNv2HRBrtv++3yzC51iFMrXVuOoX9Ad3LglC9DvBvFRx3XMAOI PM2iHT7KIGNYOmomPqUjcVtayGh2fdKOsYaTg= Received: by 10.213.19.73 with SMTP id z9mr512087eba.41.1327166003239; Sat, 21 Jan 2012 09:13:23 -0800 (PST) Received: from flagship.roarinelk.net (188-22-10-45.adsl.highway.telekom.at. [188.22.10.45]) by mx.google.com with ESMTPS id x4sm28076665eeb.4.2012.01.21.09.13.21 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 21 Jan 2012 09:13:22 -0800 (PST) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 2/3] MIPS: Alchemy: devboards: kill prom.c Date: Sat, 21 Jan 2012 18:13:14 +0100 Message-Id: <1327165995-27425-3-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.8.4 In-Reply-To: <1327165995-27425-1-git-send-email-manuel.lauss@googlemail.com> References: <1327165995-27425-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 32297 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4405 Lines: 136 move contents to already existing platform.c file. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/Makefile | 2 +- arch/mips/alchemy/devboards/platform.c | 30 ++++++++++++++++ arch/mips/alchemy/devboards/prom.c | 60 -------------------------------- 3 files changed, 31 insertions(+), 61 deletions(-) delete mode 100644 arch/mips/alchemy/devboards/prom.c diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 3c37fb3..c9e747d 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -2,7 +2,7 @@ # Alchemy Develboards # -obj-y += prom.o bcsr.o platform.o +obj-y += bcsr.o platform.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MIPS_PB1100) += pb1100.o obj-$(CONFIG_MIPS_PB1500) += pb1500.o diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c index 621f70a..f39042e 100644 --- a/arch/mips/alchemy/devboards/platform.c +++ b/arch/mips/alchemy/devboards/platform.c @@ -10,9 +10,39 @@ #include #include +#include #include +#include #include +#include + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = (int)fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str || kstrtoul(memsize_str, 0, &memsize)) + memsize = 64 << 20; /* all devboards have at least 64MB RAM */ + + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +#endif +} + static struct platform_device db1x00_rtc_dev = { .name = "rtc-au1xxx", diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c deleted file mode 100644 index 57320f2..0000000 --- a/arch/mips/alchemy/devboards/prom.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Common code used by all Alchemy develboards. - * - * Extracted from files which had this to say: - * - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -void __init prom_init(void) -{ - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = (int)fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - - prom_init_cmdline(); - memsize_str = prom_getenv("memsize"); - if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) - memsize = 64 << 20; /* all devboards have at least 64MB RAM */ - - add_memory_region(0, memsize, BOOT_MEM_RAM); -} - -void prom_putchar(unsigned char c) -{ -#ifdef CONFIG_MIPS_DB1300 - alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); -#else - alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -#endif -} -- 1.7.8.4 From manuel.lauss@googlemail.com Sat Jan 21 18:13:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 18:14:40 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:41816 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901171Ab2AURNa (ORCPT ); Sat, 21 Jan 2012 18:13:30 +0100 Received: by eaak10 with SMTP id k10so321460eaa.36 for ; Sat, 21 Jan 2012 09:13:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=hm4w709c0JsAoNDi6LeDezDZgaoIg87Wgx1H4HE6QGI=; b=pLAvwtP0zJzWaMVNdxhlTHA2CEdYYAoPYneuv6Wg7PxTGqcQDuIZuzRI9kSmTpmo3+ Y1sArhV1vGACURaj4Vr6daJac61cIYwSxdo8laoVN9LwzhEkGFSRnSpERtSnzMrjk/IS u19sviwQRY7LEWTJyeFobc4WnZadQhspriy2o= Received: by 10.213.109.3 with SMTP id h3mr444616ebp.132.1327166004772; Sat, 21 Jan 2012 09:13:24 -0800 (PST) Received: from flagship.roarinelk.net (188-22-10-45.adsl.highway.telekom.at. [188.22.10.45]) by mx.google.com with ESMTPS id x4sm28076665eeb.4.2012.01.21.09.13.23 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 21 Jan 2012 09:13:24 -0800 (PST) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 3/3] MIPS: Alchemy: handle db1200 cpld ints as they come in Date: Sat, 21 Jan 2012 18:13:15 +0100 Message-Id: <1327165995-27425-4-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.8.4 In-Reply-To: <1327165995-27425-1-git-send-email-manuel.lauss@googlemail.com> References: <1327165995-27425-1-git-send-email-manuel.lauss@googlemail.com> X-archive-position: 32298 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1049 Lines: 33 Remove the loop in the cascade handler and instead unconditionally handle just the first set interrupt coming from the CPLD. This gets rid of a lot of spurious interrupts being triggered for the SMSC91111 ethernet chip especially under high(er) IDE load: "eth0: spurious interrupt (mask = 0xb3)" Verified on DB1200 and DB1300. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/bcsr.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index 1e83ce2..f2039ef 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -90,10 +90,7 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); disable_irq_nosync(irq); - - for ( ; bisr; bisr &= bisr - 1) - generic_handle_irq(bcsr_csc_base + __ffs(bisr)); - + generic_handle_irq(bcsr_csc_base + __ffs(bisr)); enable_irq(irq); } -- 1.7.8.4 From hughd@google.com Sat Jan 21 21:53:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 21:53:58 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:58179 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901169Ab2AUUxu (ORCPT ); Sat, 21 Jan 2012 21:53:50 +0100 Received: by iagw33 with SMTP id w33so3489767iag.36 for ; Sat, 21 Jan 2012 12:53:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=gamma; h=date:from:x-x-sender:to:cc:subject:in-reply-to:message-id :references:user-agent:mime-version:x-gm-message-state:content-type; bh=PXvMJ+7EjRp/EzvFWskVi6JARM7pUOrNCC2x0Nx1GMY=; b=wWi0GqOKX0bzm9bRd6djDLzIGaJft+0t4Xoxlaftvig93JE6ejmtoqarElGTEBj9Sp huqjf329p10mD8PHYr1whaOeUQ3X+OtWUXyRlVZMjT+1Sg0U+uNmRi0Q7p076YSDA3z3 sXulCX9f0+LP4vhzTAwzJkzCAFOAmBWiAO7NY= Received: by 10.50.168.4 with SMTP id zs4mr3420758igb.28.1327179224218; Sat, 21 Jan 2012 12:53:44 -0800 (PST) Received: by 10.50.168.4 with SMTP id zs4mr3420728igb.28.1327179224123; Sat, 21 Jan 2012 12:53:44 -0800 (PST) Received: from [192.168.1.8] (c-67-188-178-35.hsd1.ca.comcast.net. [67.188.178.35]) by mx.google.com with ESMTPS id or2sm6099175igc.5.2012.01.21.12.53.42 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 21 Jan 2012 12:53:43 -0800 (PST) Date: Sat, 21 Jan 2012 12:53:25 -0800 (PST) From: Hugh Dickins X-X-Sender: hugh@eggly.anvils To: Zumeng Chen cc: linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, mingo@elte.hu, ralf@linux-mips.org, bruce.ashfield@windriver.com, linux-mm@kvack.org, linux-mips@linux-mips.org Subject: Re: [PATCH 1/1] mm: msync: fix issues of sys_msync on tmpfs In-Reply-To: <1327036719-1965-1-git-send-email-zumeng.chen@windriver.com> Message-ID: References: <1327036719-1965-1-git-send-email-zumeng.chen@windriver.com> User-Agent: Alpine 2.00 (LSU 1167 2008-08-23) MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmtzhSJ5mI/1ptwNnIVjfIC9ZaQXxFtWUQUvYFjI9dnHpYgML5uE3izI6S0PgRlLRz5LcF6wmEqh8g27jvhKA2fyLq02Rs6pN5MFFtumQVmIpDdL29mM6FNS9c9MxI2qMYbQLbGqEsNNudMX5ubEaVDwqKUvG32QNpV0Ki9AZ0ZluUfTj8= Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32299 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hughd@google.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4299 Lines: 124 On Fri, 20 Jan 2012, Zumeng Chen wrote: > This patch fixes two issues as follows: Two issues? You write of a cache aliasing issue, I don't see a second. > > For some filesystem with fsync == noop_fsync, there is not so much thing > to do, so sys_msync just passes by for all arches but some CPUs. > > For some CPUs with cache aliases(dmesg|grep alias), it maybe has an issue, > which reported by msync test suites in ltp-full when the memory of memset > used by msync01 runs into cache alias randomly. > > Consider the following scenario used by msync01 in ltp-full: > fildes = open(TEMPFILE, O_RDWR | O_CREAT, 0666)) < 0); > .../* initialization fildes by write(fildes); */ > addr = mmap(0, page_sz, PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, > fildes, 0); > /* set buf with memset */ > memset(addr + OFFSET_1, 1, BUF_SIZE); > > /* msync the addr before using, or MS_SYNC*/ > msync(addr, page_sz, MS_ASYNC) Actually, that MS_ASYNC msync() does nothing at all but validate its arguments these days, even on filesystems with an effective fsync(). We write out dirty pages to disk in good time, msync() or not. > > /* Tries to read fildes */ > lseek(fildes, (off_t) OFFSET_1, SEEK_SET) != (off_t) OFFSET_1) { > nread = read(fildes, read_buf, sizeof(read_buf)); My grasp of cache aliasing issues is very poor, please excuse me if I'm wrong; but I don't think a patch to msync() should be necessary at all (and ltp's msync01 test is testing nothing more than args to msync()). In the case of tmpfs, that read() system call above should route through to mm/shmem.c do_shmem_file_read(), which contains these same lines as the more common mm/filemap.c do_generic_file_read(): /* If users can be writing to this page using arbitrary * virtual addresses, take care about potential aliasing * before reading the page on the kernel side. */ if (mapping_writably_mapped(mapping)) flush_dcache_page(page); The mapping_writably_mapped() test ought to be succeeding in this case (please check with printk's, perhaps some change has messed that up), so flush_dcache_page(page) should be called, and any aliasing issues resolved before the data is copied back to userspace. I assume your problem is on MIPS, since you copied Ralf and linux-mips: if the MIPS flush_dcache_page() is not working right, then you'll need to follow up with them. Hugh > > /* Then test the result */ > if (read_buf[count] != 1) { > > The test result is random too for CPUs with cache alias. So in this > situation, we have to flush the related vma to make sure the read is > correct. > > Signed-off-by: Zumeng Chen > --- > mm/msync.c | 30 ++++++++++++++++++++++++++++++ > 1 files changed, 30 insertions(+), 0 deletions(-) > > diff --git a/mm/msync.c b/mm/msync.c > index 632df45..0021a7e 100644 > --- a/mm/msync.c > +++ b/mm/msync.c > @@ -13,6 +13,14 @@ > #include > #include > #include > +#include > + > +/* Cache aliases should be taken into accounts when msync. */ > +#ifdef cpu_has_dc_aliases > +#define CPU_HAS_CACHE_ALIAS cpu_has_dc_aliases > +#else > +#define CPU_HAS_CACHE_ALIAS 0 > +#endif > > /* > * MS_SYNC syncs the entire file - including mappings. > @@ -78,6 +86,28 @@ SYSCALL_DEFINE3(msync, unsigned long, start, size_t, len, int, flags) > } > file = vma->vm_file; > start = vma->vm_end; > + > + /* > + * For some filesystems with fsync == noop_fsync, msync just > + * passes by but some CPUs. > + * For CPUs with cache alias, msync has to flush the related > + * vma explicitly to make sure data coherency between memory > + * and cache, which includes MS_SYNC or MS_ASYNC. That is to > + * say, cache aliases should not be an async factor, so does > + * msync on other arches without cache aliases. > + */ > + if (file && file->f_op && file->f_op->fsync == noop_fsync) { > + if (CPU_HAS_CACHE_ALIAS) > + flush_cache_range(vma, vma->vm_start, > + vma->vm_end); > + if (start >= end) { > + error = 0; > + goto out_unlock; > + } > + vma = find_vma(mm, start); > + continue; > + } > + > if ((flags & MS_SYNC) && file && > (vma->vm_flags & VM_SHARED)) { > get_file(file); > -- > 1.7.0.4 From hauke@hauke-m.de Sat Jan 21 23:19:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 23:19:54 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45775 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901168Ab2AUWTr (ORCPT ); Sat, 21 Jan 2012 23:19:47 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 6303D8F68; Sat, 21 Jan 2012 23:19:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZvJH45zIil6o; Sat, 21 Jan 2012 23:19:43 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id B00B68F60; Sat, 21 Jan 2012 23:19:42 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua, Hauke Mehrtens Subject: [PATCH 0/7] EHCI and OHCI for bcma and ssb Date: Sat, 21 Jan 2012 23:19:20 +0100 Message-Id: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32300 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1713 Lines: 38 This patch series adds an EHCI and an OHCI driver for bcma and ssb based SoCs. These SoCs provide one device with two address spaces one for the OHCI and one for the EHCI part. The USB controllers are using the same interface as an PCI controller. This patch series is based on the mips Linux tree. It was in OpenWrt for some time and it was reviewed by George Kashperko recently. Hauke Mehrtens (7): bcma: scan for extra address space bcma: add function to check every 10 us if a reg is set USB: OHCI: Add a generic platform device driver USB: EHCI: Add a generic platform device driver USB: Add driver for the bcma bus USB: Add driver for the ssb bus USB: OHCI: remove old SSB OHCI driver drivers/bcma/core.c | 52 ++++--- drivers/bcma/scan.c | 18 ++- drivers/usb/host/Kconfig | 57 ++++++-- drivers/usb/host/Makefile | 2 + drivers/usb/host/bcma-hcd.c | 307 ++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-platform.c | 211 ++++++++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 26 +--- drivers/usb/host/ohci-platform.c | 193 ++++++++++++++++++++++++ drivers/usb/host/ohci-ssb.c | 260 -------------------------------- drivers/usb/host/ssb-hcd.c | 270 +++++++++++++++++++++++++++++++++ include/linux/bcma/bcma.h | 4 + 12 files changed, 1089 insertions(+), 316 deletions(-) create mode 100644 drivers/usb/host/bcma-hcd.c create mode 100644 drivers/usb/host/ehci-platform.c create mode 100644 drivers/usb/host/ohci-platform.c delete mode 100644 drivers/usb/host/ohci-ssb.c create mode 100644 drivers/usb/host/ssb-hcd.c -- 1.7.5.4 From hauke@hauke-m.de Sat Jan 21 23:19:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 23:20:19 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45781 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901169Ab2AUWTs (ORCPT ); Sat, 21 Jan 2012 23:19:48 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 154918F60; Sat, 21 Jan 2012 23:19:48 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1U5yyLFaE4yF; Sat, 21 Jan 2012 23:19:43 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 2A44F8F61; Sat, 21 Jan 2012 23:19:43 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua, Hauke Mehrtens Subject: [PATCH 1/7] bcma: scan for extra address space Date: Sat, 21 Jan 2012 23:19:21 +0100 Message-Id: <1327184367-8824-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> References: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32301 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1808 Lines: 63 Some cores like the USB core have two address spaces. In the USB host controller one address space is used for the OHCI and the other for the EHCI controller interface. The USB controller is the only core I found with two address spaces. This code is based on the AI scan function ai_scan() in shared/aiutils.c i the Broadcom SDK. Signed-off-by: Hauke Mehrtens --- drivers/bcma/scan.c | 18 +++++++++++++++++- include/linux/bcma/bcma.h | 1 + 2 files changed, 18 insertions(+), 1 deletions(-) diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c index cad9948..c12a7fe 100644 --- a/drivers/bcma/scan.c +++ b/drivers/bcma/scan.c @@ -286,6 +286,22 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, return -EILSEQ; } + + /* First Slave Address Descriptor should be port 0: + * the main register space for the core + */ + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); + if (tmp <= 0) { + /* Try again to see if it is a bridge */ + tmp = bcma_erom_get_addr_desc(bus, eromptr, + SCAN_ADDR_TYPE_BRIDGE, 0); + if (tmp > 0) { + pr_info("found bridge\n"); + return -ENXIO; + } + } + core->addr = tmp; + /* get & parse slave ports */ for (i = 0; i < ports[1]; i++) { for (j = 0; ; j++) { @@ -298,7 +314,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, break; } else { if (i == 0 && j == 0) - core->addr = tmp; + core->addr1 = tmp; } } } diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 83c209f..7fe41e1 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -138,6 +138,7 @@ struct bcma_device { u8 core_index; u32 addr; + u32 addr1; u32 wrap; void __iomem *io_addr; -- 1.7.5.4 From hauke@hauke-m.de Sat Jan 21 23:19:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 23:20:47 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45797 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901170Ab2AUWTu (ORCPT ); Sat, 21 Jan 2012 23:19:50 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 2DEEE8F61; Sat, 21 Jan 2012 23:19:50 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ejTwbxsLZ-HK; Sat, 21 Jan 2012 23:19:46 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 8D73D8F62; Sat, 21 Jan 2012 23:19:43 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua, Hauke Mehrtens Subject: [PATCH 2/7] bcma: add function to check every 10 us if a reg is set Date: Sat, 21 Jan 2012 23:19:22 +0100 Message-Id: <1327184367-8824-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> References: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32302 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3297 Lines: 113 This function checks if a reg get set or cleared every 10 microseconds. It is used in bcma_core_set_clockmode() and bcma_core_pll_ctl() to reduce code duplication. In addition it is needed in the USB host driver. Signed-off-by: Hauke Mehrtens --- drivers/bcma/core.c | 52 ++++++++++++++++++++++++++------------------- include/linux/bcma/bcma.h | 3 ++ 2 files changed, 33 insertions(+), 22 deletions(-) diff --git a/drivers/bcma/core.c b/drivers/bcma/core.c index 893f6e0..f7b7358 100644 --- a/drivers/bcma/core.c +++ b/drivers/bcma/core.c @@ -52,11 +52,36 @@ int bcma_core_enable(struct bcma_device *core, u32 flags) } EXPORT_SYMBOL_GPL(bcma_core_enable); +/* Wait for bitmask in a register to get set or cleared. + * timeout is in units of ten-microseconds. + */ +int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask, int timeout, + int set) +{ + int i; + u32 val; + + for (i = 0; i < timeout; i++) { + val = bcma_read32(dev, reg); + if (set) { + if ((val & bitmask) == bitmask) + return 0; + } else { + if (!(val & bitmask)) + return 0; + } + udelay(10); + } + pr_err("Timeout waiting for bitmask %08X on register %04X to %s.\n", + bitmask, reg, (set ? "set" : "clear")); + + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(bcma_wait_bits); + void bcma_core_set_clockmode(struct bcma_device *core, enum bcma_clkmode clkmode) { - u16 i; - WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON && core->id.id != BCMA_CORE_PCIE && core->id.id != BCMA_CORE_80211); @@ -65,15 +90,8 @@ void bcma_core_set_clockmode(struct bcma_device *core, case BCMA_CLKMODE_FAST: bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); udelay(64); - for (i = 0; i < 1500; i++) { - if (bcma_read32(core, BCMA_CLKCTLST) & - BCMA_CLKCTLST_HAVEHT) { - i = 0; - break; - } - udelay(10); - } - if (i) + if (bcma_wait_bits(core, BCMA_CLKCTLST, BCMA_CLKCTLST_HAVEHT, + 1500, 1)) pr_err("HT force timeout\n"); break; case BCMA_CLKMODE_DYNAMIC: @@ -85,22 +103,12 @@ EXPORT_SYMBOL_GPL(bcma_core_set_clockmode); void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on) { - u16 i; - WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ); WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST); if (on) { bcma_set32(core, BCMA_CLKCTLST, req); - for (i = 0; i < 10000; i++) { - if ((bcma_read32(core, BCMA_CLKCTLST) & status) == - status) { - i = 0; - break; - } - udelay(10); - } - if (i) + if (bcma_wait_bits(core, BCMA_CLKCTLST, status, 10000, 1)) pr_err("PLL enable timeout\n"); } else { pr_warn("Disabling PLL not supported yet!\n"); diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 7fe41e1..ebff87c 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -283,6 +283,9 @@ static inline void bcma_maskset16(struct bcma_device *cc, bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); } +extern int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask, + int timeout, int set); + extern bool bcma_core_is_enabled(struct bcma_device *core); extern void bcma_core_disable(struct bcma_device *core, u32 flags); extern int bcma_core_enable(struct bcma_device *core, u32 flags); -- 1.7.5.4 From hauke@hauke-m.de Sat Jan 21 23:19:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 23:21:13 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45808 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901171Ab2AUWTw (ORCPT ); Sat, 21 Jan 2012 23:19:52 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 82AA48F62; Sat, 21 Jan 2012 23:19:52 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hJcWSFOjH5+g; Sat, 21 Jan 2012 23:19:48 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id EEA488F63; Sat, 21 Jan 2012 23:19:43 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua, Hauke Mehrtens Subject: [PATCH 3/7] USB: OHCI: Add a generic platform device driver Date: Sat, 21 Jan 2012 23:19:23 +0100 Message-Id: <1327184367-8824-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> References: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32303 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6149 Lines: 252 This adds a generic driver for platform devices. It works like the PCI driver and is based on it. This is for devices which do not have an own bus but their OHCI controller works like a PCI controller. It will be used for the Broadcom bcma and ssb USB OHCI controller. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 10 ++ drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-platform.c | 193 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 208 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ohci-platform.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 91413ca..6651ed6 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -393,6 +393,16 @@ config USB_CNS3XXX_OHCI Enable support for the CNS3XXX SOC's on-chip OHCI controller. It is needed for low-speed USB 1.0 device support. +config USB_OHCI_HCD_PLATFORM + bool "OHCI driver for a platform device" + depends on USB_OHCI_HCD && EXPERIMENTAL + default n + ---help--- + Adds an OHCI host driver for a generic platform device, which + provieds a memory space and an irq. + + If unsure, say N. + config USB_OHCI_BIG_ENDIAN_DESC bool depends on USB_OHCI_HCD diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 34b9edd..50fbbf9 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1121,6 +1121,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_xls_driver #endif +#ifdef CONFIG_USB_OHCI_HCD_PLATFORM +#include "ohci-platform.c" +#define PLATFORM_DRIVER ohci_platform_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c new file mode 100644 index 0000000..1b5fc73 --- /dev/null +++ b/drivers/usb/host/ohci-platform.c @@ -0,0 +1,193 @@ +/* + * Generic platform ohci driver + * + * Copyright 2007 Michael Buesch + * Copyright 2011 Hauke Mehrtens + * + * Derived from the OCHI-SSB driver + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include + +static int ohci_platform_reset(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int err; + + ohci_hcd_init(ohci); + err = ohci_init(ohci); + + return err; +} + +static int ohci_platform_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int err; + + err = ohci_run(ohci); + if (err < 0) { + ohci_err(ohci, "can't start\n"); + ohci_stop(hcd); + } + + return err; +} + +static const struct hc_driver ohci_platform_hc_driver = { + .description = "platform-usb-ohci", + .product_desc = "Generic Platform OHCI Controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + + .irq = ohci_irq, + .flags = HCD_MEMORY | HCD_USB11, + + .reset = ohci_platform_reset, + .start = ohci_platform_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + + .get_frame_number = ohci_get_frame, + + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ohci_bus_suspend, + .bus_resume = ohci_bus_resume, +#endif + + .start_port_reset = ohci_start_port_reset, +}; + +static int ohci_platform_attach(struct platform_device *dev) +{ + struct usb_hcd *hcd; + struct resource *res_irq, *res_mem; + int err = -ENOMEM; + + hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev, + dev_name(&dev->dev)); + if (!hcd) + goto err_return; + + res_irq = platform_get_resource(dev, IORESOURCE_IRQ, 0); + if (!res_irq) { + err = -ENXIO; + goto err_return; + } + res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res_mem) { + err = -ENXIO; + goto err_return; + } + hcd->rsrc_start = res_mem->start; + hcd->rsrc_len = res_mem->end - res_mem->start + 1; + + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) + goto err_put_hcd; + err = usb_add_hcd(hcd, res_irq->start, IRQF_SHARED); + if (err) + goto err_iounmap; + + platform_set_drvdata(dev, hcd); + + return err; + +err_iounmap: + iounmap(hcd->regs); +err_put_hcd: + usb_put_hcd(hcd); +err_return: + return err; +} + +static int ohci_platform_probe(struct platform_device *dev) +{ + int err; + + if (usb_disabled()) + return -ENODEV; + + err = ohci_platform_attach(dev); + + return err; +} + +static int ohci_platform_remove(struct platform_device *dev) +{ + struct usb_hcd *hcd; + + hcd = platform_get_drvdata(dev); + if (!hcd) + return -ENODEV; + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static void ohci_platform_shutdown(struct platform_device *dev) +{ + struct usb_hcd *hcd; + + hcd = platform_get_drvdata(dev); + if (!hcd) + return; + + if (hcd->driver->shutdown) + hcd->driver->shutdown(hcd); +} + +#ifdef CONFIG_PM + +static int ohci_platform_suspend(struct platform_device *dev, + pm_message_t state) +{ + + return 0; +} + +static int ohci_platform_resume(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + ohci_finish_controller_resume(hcd); + return 0; +} + +#else /* !CONFIG_PM */ +#define ohci_platform_suspend NULL +#define ohci_platform_resume NULL +#endif /* CONFIG_PM */ + +static const struct platform_device_id ohci_platform_table[] = { + { "ohci-platform", 0 }, + { } +}; +MODULE_DEVICE_TABLE(platform, ohci_platform_table); + +static struct platform_driver ohci_platform_driver = { + .id_table = ohci_platform_table, + .probe = ohci_platform_probe, + .remove = ohci_platform_remove, + .shutdown = ohci_platform_shutdown, + .suspend = ohci_platform_suspend, + .resume = ohci_platform_resume, + .driver = { + .name = "ohci-platform", + } +}; -- 1.7.5.4 From hauke@hauke-m.de Sat Jan 21 23:19:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 23:21:39 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45817 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903704Ab2AUWTz (ORCPT ); Sat, 21 Jan 2012 23:19:55 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id AEBB98F63; Sat, 21 Jan 2012 23:19:55 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MZapiaf0oG1c; Sat, 21 Jan 2012 23:19:50 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 56AF78F64; Sat, 21 Jan 2012 23:19:44 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua, Hauke Mehrtens Subject: [PATCH 4/7] USB: EHCI: Add a generic platform device driver Date: Sat, 21 Jan 2012 23:19:24 +0100 Message-Id: <1327184367-8824-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> References: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32304 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6767 Lines: 270 This adds a generic driver for platform devices. It works like the PCI driver and is based on it. This is for devices which do not have an own bus but their EHCI controller works like a PCI controller. It will be used for the Broadcom bcma and ssb USB EHCI controller. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 10 ++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-platform.c | 211 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-platform.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 6651ed6..e7b5efe 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -403,6 +403,16 @@ config USB_OHCI_HCD_PLATFORM If unsure, say N. +config USB_EHCI_HCD_PLATFORM + bool "Generic EHCI driver for a platform device" + depends on USB_EHCI_HCD && EXPERIMENTAL + default n + ---help--- + Adds an EHCI host driver for a generic platform device, which + provieds a memory space and an irq. + + If unsure, say N. + config USB_OHCI_BIG_ENDIAN_DESC bool depends on USB_OHCI_HCD diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index a007a9f..afe0984 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1376,6 +1376,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_mv_driver #endif +#ifdef CONFIG_USB_EHCI_HCD_PLATFORM +#include "ehci-platform.c" +#define PLATFORM_DRIVER ehci_platform_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c new file mode 100644 index 0000000..1c20c02 --- /dev/null +++ b/drivers/usb/host/ehci-platform.c @@ -0,0 +1,211 @@ +/* + * Generic platform ehci driver + * + * Copyright 2007 Steven Brown + * Copyright 2010-2011 Hauke Mehrtens + * + * Derived from the ohci-ssb driver + * Copyright 2007 Michael Buesch + * + * Derived from the EHCI-PCI driver + * Copyright (c) 2000-2004 by David Brownell + * + * Derived from the ohci-pci driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include + +static int ehci_platform_reset(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval; + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); + + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + + retval = ehci_halt(ehci); + if (retval) + return retval; + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + ehci_reset(ehci); + + ehci_port_power(ehci, 1); + + return retval; +} + +static const struct hc_driver ehci_platform_hc_driver = { + .description = "platform-usb-ehci", + .product_desc = "Generic Platform EHCI Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + .reset = ehci_platform_reset, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#if defined(CONFIG_PM) + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .update_device = ehci_update_device, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_platform_attach(struct platform_device *dev) +{ + struct usb_hcd *hcd; + struct resource *res_irq, *res_mem; + int err = -ENOMEM; + + hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev, + dev_name(&dev->dev)); + if (!hcd) + goto err_return; + + res_irq = platform_get_resource(dev, IORESOURCE_IRQ, 0); + if (!res_irq) { + err = -ENXIO; + goto err_return; + } + res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res_mem) { + err = -ENXIO; + goto err_return; + } + hcd->rsrc_start = res_mem->start; + hcd->rsrc_len = res_mem->end - res_mem->start + 1; + + /* + * start & size modified per sbutils.c + */ + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) + goto err_put_hcd; + err = usb_add_hcd(hcd, res_irq->start, IRQF_SHARED); + if (err) + goto err_iounmap; + + platform_set_drvdata(dev, hcd); + + return err; + +err_iounmap: + iounmap(hcd->regs); +err_put_hcd: + usb_put_hcd(hcd); +err_return: + return err; +} + +static int ehci_platform_probe(struct platform_device *dev) +{ + int err; + + if (usb_disabled()) + return -ENODEV; + + err = ehci_platform_attach(dev); + + return err; +} + +static int ehci_platform_remove(struct platform_device *dev) +{ + struct usb_hcd *hcd; + + hcd = platform_get_drvdata(dev); + if (!hcd) + return -ENODEV; + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static void ehci_platform_shutdown(struct platform_device *dev) +{ + struct usb_hcd *hcd; + + hcd = platform_get_drvdata(dev); + if (!hcd) + return; + + if (hcd->driver->shutdown) + hcd->driver->shutdown(hcd); +} + +#ifdef CONFIG_PM + +static int ehci_platform_suspend(struct platform_device *dev, + pm_message_t state) +{ + return 0; +} + +static int ehci_platform_resume(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + ehci_finish_controller_resume(hcd); + return 0; +} + +#else /* !CONFIG_PM */ +#define ehci_platform_suspend NULL +#define ehci_platform_resume NULL +#endif /* CONFIG_PM */ + +static const struct platform_device_id ehci_platform_table[] = { + { "ehci-platform", 0 }, + { } +}; +MODULE_DEVICE_TABLE(platform, ehci_platform_table); + +static struct platform_driver ehci_platform_driver = { + .id_table = ehci_platform_table, + .probe = ehci_platform_probe, + .remove = ehci_platform_remove, + .shutdown = ehci_platform_shutdown, + .suspend = ehci_platform_suspend, + .resume = ehci_platform_resume, + .driver = { + .name = "ehci-platform", + } +}; -- 1.7.5.4 From hauke@hauke-m.de Sat Jan 21 23:19:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 23:22:03 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45828 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903707Ab2AUWT6 (ORCPT ); Sat, 21 Jan 2012 23:19:58 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 8D5EF8F69; Sat, 21 Jan 2012 23:19:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9frhdWtm3n0a; Sat, 21 Jan 2012 23:19:52 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id B82638F65; Sat, 21 Jan 2012 23:19:44 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua, Hauke Mehrtens Subject: [PATCH 5/7] USB: Add driver for the bcma bus Date: Sat, 21 Jan 2012 23:19:25 +0100 Message-Id: <1327184367-8824-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> References: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32305 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9743 Lines: 361 This adds a USB driver using the generic platform device driver for the USB controller found on the Broadcom bcma bus. The bcma bus just exposes one device which serves the OHCI and the EHCI controller at the same time. This driver probes for this USB controller and creates and registers two new platform devices which will be probed by the new generic platform device driver. This makes it possible to use the EHCI and the OCHI controller on the bcma bus at the same time. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 12 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/bcma-hcd.c | 307 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 320 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/bcma-hcd.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index e7b5efe..b15ce91 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -633,3 +633,15 @@ config USB_PXA168_EHCI help Enable support for Marvell PXA168 SoC's on-chip EHCI host controller + +config USB_HCD_BCMA + tristate "BCMA usb host driver" + depends on BCMA && EXPERIMENTAL + select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD + select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD + help + Enbale support for the EHCI and OCHI host controller on an bcma bus. + It converts the bcma driver into two platform device drivers + for ehci and ohci. + + If unsure, say N. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7ca290f..f2c2846 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -37,3 +37,4 @@ obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o +obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c new file mode 100644 index 0000000..ef46364 --- /dev/null +++ b/drivers/usb/host/bcma-hcd.c @@ -0,0 +1,307 @@ +/* + * Broadcom specific Advanced Microcontroller Bus + * Broadcom USB-core driver (BCMA bus glue) + * + * Copyright 2011 Hauke Mehrtens + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch + * + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Derived from the USBcore related parts of Broadcom-SB + * Copyright 2005-2011 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include +#include +#include + +MODULE_AUTHOR("Hauke Mehrtens"); +MODULE_DESCRIPTION("Common USB driver for BCMA Bus"); +MODULE_LICENSE("GPL"); + +struct bcma_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; +}; + +static void __devinit bcma_hcd_4716wa(struct bcma_device *dev) +{ +#ifdef CONFIG_BCMA_DRIVER_MIPS + /* Work around for 4716 failures. */ + if (dev->bus->chipinfo.id == 0x4716) { + u32 tmp; + + tmp = bcma_cpu_clock(&dev->bus->drv_mips); + if (tmp >= 480000000) + tmp = 0x1846b; /* set CDR to 0x11(fast) */ + else if (tmp == 453000000) + tmp = 0x1046b; /* set CDR to 0x10(slow) */ + else + tmp = 0; + + /* Change Shim mdio control reg to fix host not acking at + * high frequencies + */ + if (tmp) { + bcma_write32(dev, 0x524, 0x1); /* write sel to enable */ + udelay(500); + + bcma_write32(dev, 0x524, tmp); + udelay(500); + bcma_write32(dev, 0x524, 0x4ab); + udelay(500); + bcma_read32(dev, 0x528); + bcma_write32(dev, 0x528, 0x80000000); + } + } +#endif /* CONFIG_BCMA_DRIVER_MIPS */ +} + +/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +static void __devinit bcma_hcd_init_chip(struct bcma_device *dev) +{ + u32 tmp; + + /* + * USB 2.0 special considerations: + * + * 1. Since the core supports both OHCI and EHCI functions, it must + * only be reset once. + * + * 2. In addition to the standard SI reset sequence, the Host Control + * Register must be programmed to bring the USB core and various + * phy components out of reset. + */ + if (!bcma_core_is_enabled(dev)) { + bcma_core_enable(dev, 0); + mdelay(10); + if (dev->id.rev >= 5) { + /* Enable Misc PLL */ + tmp = bcma_read32(dev, 0x1e0); + tmp |= 0x100; + bcma_write32(dev, 0x1e0, tmp); + if (bcma_wait_bits(dev, 0x1e0, 1 << 24, 100, 1)) + printk(KERN_EMERG "Failed to enable misc PPL!\n"); + + /* Take out of resets */ + bcma_write32(dev, 0x200, 0x4ff); + udelay(25); + bcma_write32(dev, 0x200, 0x6ff); + udelay(25); + + /* Make sure digital and AFE are locked in USB PHY */ + bcma_write32(dev, 0x524, 0x6b); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0xab); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0x2b); + udelay(50); + tmp = bcma_read32(dev, 0x524); + udelay(50); + bcma_write32(dev, 0x524, 0x10ab); + udelay(50); + tmp = bcma_read32(dev, 0x524); + + if (bcma_wait_bits(dev, 0x528, 0xc000, 10000, 1)) { + tmp = bcma_read32(dev, 0x528); + printk(KERN_EMERG + "USB20H mdio_rddata 0x%08x\n", tmp); + } + bcma_write32(dev, 0x528, 0x80000000); + tmp = bcma_read32(dev, 0x314); + udelay(265); + bcma_write32(dev, 0x200, 0x7ff); + udelay(10); + + /* Take USB and HSIC out of non-driving modes */ + bcma_write32(dev, 0x510, 0); + } else { + bcma_write32(dev, 0x200, 0x7ff); + + udelay(1); + } + + bcma_hcd_4716wa(dev); + } +} + +static struct platform_device * __devinit +bcma_hcd_create_pdev(struct bcma_device *dev, char *name, u32 addr) +{ + struct platform_device *hci_dev; + struct resource hci_res[2]; + int ret = -ENOMEM; + + memset(hci_res, 0, sizeof(hci_res)); + + hci_res[0].start = addr; + hci_res[0].end = hci_res[0].start + 0x1000 - 1; + hci_res[0].flags = IORESOURCE_MEM; + + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + + hci_dev = platform_device_alloc(name, 0); + if (!hci_dev) + goto err_alloc; + + hci_dev->dev.parent = &dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(hci_dev, hci_res, + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; + + ret = platform_device_add(hci_dev); + if (ret) { +err_alloc: + platform_device_put(hci_dev); + return ERR_PTR(ret); + } + + return hci_dev; +} + +static int __devinit bcma_hcd_probe(struct bcma_device *dev) +{ + int err; + u16 chipid_top; + u32 ohci_addr; + struct bcma_hcd_device *usb_dev; + struct bcma_chipinfo *chipinfo; + + chipinfo = &dev->bus->chipinfo; + /* USBcores are only connected on embedded devices. */ + chipid_top = (chipinfo->id & 0xFF00); + if (chipid_top != 0x4700 && chipid_top != 0x5300) + return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + + if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + + usb_dev = kzalloc(sizeof(struct bcma_hcd_device), GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + + bcma_hcd_init_chip(dev); + + /* In AI chips EHCI is addrspace 0, OHCI is 1 */ + ohci_addr = dev->addr1; + if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749) + && chipinfo->rev == 0) + ohci_addr = 0x18009000; + + usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, "ohci-platform", + ohci_addr); + if (IS_ERR(usb_dev->ohci_dev)) { + err = PTR_ERR(usb_dev->ohci_dev); + goto err_free_usb_dev; + } + + usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, "ehci-platform", + dev->addr); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; + } + + bcma_set_drvdata(dev, usb_dev); + return 0; + +err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +err_free_usb_dev: + kfree(usb_dev); + return err; +} + +static void __devexit bcma_hcd_remove(struct bcma_device *dev) +{ + struct bcma_hcd_device *usb_dev; + struct platform_device *ohci_dev; + struct platform_device *ehci_dev; + + usb_dev = bcma_get_drvdata(dev); + if (!usb_dev) + return; + + ohci_dev = usb_dev->ohci_dev; + ehci_dev = usb_dev->ehci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); + + bcma_core_disable(dev, 0); +} + +static void bcma_hcd_shutdown(struct bcma_device *dev) +{ + bcma_core_disable(dev, 0); +} + +#ifdef CONFIG_PM + +static int bcma_hcd_suspend(struct bcma_device *dev, pm_message_t state) +{ + bcma_core_disable(dev, 0); + + return 0; +} + +static int bcma_hcd_resume(struct bcma_device *dev) +{ + bcma_core_enable(dev, 0); + + return 0; +} + +#else /* !CONFIG_PM */ +#define bcma_hcd_suspend NULL +#define bcma_hcd_resume NULL +#endif /* CONFIG_PM */ + +static const struct bcma_device_id bcma_hcd_table[] __devinitconst = { + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), + BCMA_CORETABLE_END +}; +MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); + +static struct bcma_driver bcma_hcd_driver = { + .name = KBUILD_MODNAME, + .id_table = bcma_hcd_table, + .probe = bcma_hcd_probe, + .remove = __devexit_p(bcma_hcd_remove), + .shutdown = bcma_hcd_shutdown, + .suspend = bcma_hcd_suspend, + .resume = bcma_hcd_resume, +}; + +static int __init bcma_hcd_init(void) +{ + return bcma_driver_register(&bcma_hcd_driver); +} +module_init(bcma_hcd_init); + +static void __exit bcma_hcd_exit(void) +{ + bcma_driver_unregister(&bcma_hcd_driver); +} +module_exit(bcma_hcd_exit); -- 1.7.5.4 From hauke@hauke-m.de Sat Jan 21 23:20:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 23:22:29 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45833 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903708Ab2AUWUB (ORCPT ); Sat, 21 Jan 2012 23:20:01 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id E67888F6A; Sat, 21 Jan 2012 23:20:00 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qj1uJAkAc4no; Sat, 21 Jan 2012 23:19:56 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 1C31F8F66; Sat, 21 Jan 2012 23:19:45 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua, Hauke Mehrtens Subject: [PATCH 6/7] USB: Add driver for the ssb bus Date: Sat, 21 Jan 2012 23:19:26 +0100 Message-Id: <1327184367-8824-7-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> References: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32306 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 8983 Lines: 328 This adds a USB driver using the generic platform device driver for the USB controller found on the Broadcom ssb bus. The ssb bus just exposes one device which serves the OHCI and the EHCI controller at the same time. This driver probes for this USB controller and creates and registers two new platform devices which will be probed by the new generic platform device driver. This makes it possible to use the EHCI and the OCHI controller on the ssb bus at the same time. The old ssb OHCI USB driver will be removed in the next step as this driver also provide an OHCI driver and an EHCI for the cores supporting it. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 12 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ssb-hcd.c | 270 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 283 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ssb-hcd.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b15ce91..2825dc4 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -645,3 +645,15 @@ config USB_HCD_BCMA for ehci and ohci. If unsure, say N. + +config USB_HCD_SSB + tristate "SSB usb host driver" + depends on SSB && EXPERIMENTAL + select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD + select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD + help + Enbale support for the EHCI and OCHI host controller on an bcma bus. + It converts the bcma driver into two platform device drivers + for ehci and ohci. + + If unsure, say N. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f2c2846..9c52966 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o obj-$(CONFIG_MIPS_ALCHEMY) += alchemy-common.o obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o +obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o diff --git a/drivers/usb/host/ssb-hcd.c b/drivers/usb/host/ssb-hcd.c new file mode 100644 index 0000000..889b425 --- /dev/null +++ b/drivers/usb/host/ssb-hcd.c @@ -0,0 +1,270 @@ +/* + * Sonics Silicon Backplane + * Broadcom USB-core driver (SSB bus glue) + * + * Copyright 2011 Hauke Mehrtens + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch + * + * Derived from the OHCI-PCI driver + * Copyright 1999 Roman Weissgaerber + * Copyright 2000-2002 David Brownell + * Copyright 1999 Linus Torvalds + * Copyright 1999 Gregory P. Smith + * + * Derived from the USBcore related parts of Broadcom-SB + * Copyright 2005-2011 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include +#include +#include + +MODULE_AUTHOR("Hauke Mehrtens"); +MODULE_DESCRIPTION("Common USB driver for SSB Bus"); +MODULE_LICENSE("GPL"); + +#define SSB_HCD_TMSLOW_HOSTMODE (1 << 29) + +struct ssb_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; + + u32 enable_flags; +}; + +static void __devinit ssb_hcd_5354wa(struct ssb_device *dev) +{ +#ifdef CONFIG_SSB_DRIVER_MIPS + /* Work around for 5354 failures */ + if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { + /* Change syn01 reg */ + ssb_write32(dev, 0x894, 0x00fe00fe); + + /* Change syn03 reg */ + ssb_write32(dev, 0x89c, ssb_read32(dev, 0x89c) | 0x1); + } +#endif +} + +static void __devinit ssb_hcd_usb20wa(struct ssb_device *dev) +{ + if (dev->id.coreid == SSB_DEV_USB20_HOST) { + /* + * USB 2.0 special considerations: + * + * In addition to the standard SSB reset sequence, the Host + * Control Register must be programmed to bring the USB core + * and various phy components out of reset. + */ + ssb_write32(dev, 0x200, 0x7ff); + + /* Change Flush control reg */ + ssb_write32(dev, 0x400, ssb_read32(dev, 0x400) & ~8); + ssb_read32(dev, 0x400); + + /* Change Shim control reg */ + ssb_write32(dev, 0x304, ssb_read32(dev, 0x304) & ~0x100); + ssb_read32(dev, 0x304); + + udelay(1); + + ssb_hcd_5354wa(dev); + } +} + +/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +static u32 __devinit ssb_hcd_init_chip(struct ssb_device *dev) +{ + u32 flags = 0; + + if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) + /* Put the device into host-mode. */ + flags |= SSB_HCD_TMSLOW_HOSTMODE; + + ssb_device_enable(dev, flags); + + ssb_hcd_usb20wa(dev); + + return flags; +} + +static struct platform_device * __devinit +ssb_hcd_create_pdev(struct ssb_device *dev, char *name, u32 addr, u32 len) +{ + struct platform_device *hci_dev; + struct resource hci_res[2]; + int ret = -ENOMEM; + + memset(hci_res, 0, sizeof(hci_res)); + + hci_res[0].start = addr; + hci_res[0].end = hci_res[0].start + len - 1; + hci_res[0].flags = IORESOURCE_MEM; + + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + + hci_dev = platform_device_alloc(name, 0); + if (!hci_dev) + goto err_alloc; + + hci_dev->dev.parent = dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(hci_dev, hci_res, 2); + if (ret) + goto err_alloc; + + ret = platform_device_add(hci_dev); + if (ret) { +err_alloc: + platform_device_put(hci_dev); + return ERR_PTR(ret); + } + + return hci_dev; +} + +static int __devinit ssb_hcd_probe(struct ssb_device *dev, + const struct ssb_device_id *id) +{ + int err, tmp; + int start, len; + u16 chipid_top; + struct ssb_hcd_device *usb_dev; + + /* USBcores are only connected on embedded devices. */ + chipid_top = (dev->bus->chip_id & 0xFF00); + if (chipid_top != 0x4700 && chipid_top != 0x5300) + return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + + if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + + usb_dev = kzalloc(sizeof(struct ssb_hcd_device), GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + + /* We currently always attach SSB_DEV_USB11_HOSTDEV + * as HOST OHCI. If we want to attach it as Client device, + * we must branch here and call into the (yet to + * be written) Client mode driver. Same for remove(). */ + usb_dev->enable_flags = ssb_hcd_init_chip(dev); + + tmp = ssb_read32(dev, SSB_ADMATCH0); + + start = ssb_admatch_base(tmp); + len = ssb_admatch_size(tmp); + usb_dev->ohci_dev = ssb_hcd_create_pdev(dev, "ohci-platform", start, + len); + if (IS_ERR(usb_dev->ohci_dev)) { + err = PTR_ERR(usb_dev->ohci_dev); + goto err_free_usb_dev; + } + + if (dev->id.coreid == SSB_DEV_USB20_HOST) { + start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */ + len = 0x100; /* ehci reg block size */ + usb_dev->ehci_dev = ssb_hcd_create_pdev(dev, "ehci-platform", + start, len); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; + } + } + + ssb_set_drvdata(dev, usb_dev); + return 0; + +err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +err_free_usb_dev: + kfree(usb_dev); + return err; +} + +static void __devexit ssb_hcd_remove(struct ssb_device *dev) +{ + struct ssb_hcd_device *usb_dev; + struct platform_device *ohci_dev; + struct platform_device *ehci_dev; + + usb_dev = ssb_get_drvdata(dev); + if (!usb_dev) + return; + + ohci_dev = usb_dev->ohci_dev; + ehci_dev = usb_dev->ehci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); + + ssb_device_disable(dev, 0); +} + +static void __devexit ssb_hcd_shutdown(struct ssb_device *dev) +{ + ssb_device_disable(dev, 0); +} + +#ifdef CONFIG_PM + +static int ssb_hcd_suspend(struct ssb_device *dev, pm_message_t state) +{ + ssb_device_disable(dev, 0); + + return 0; +} + +static int ssb_hcd_resume(struct ssb_device *dev) +{ + struct ssb_hcd_device *usb_dev = ssb_get_drvdata(dev); + + ssb_device_enable(dev, usb_dev->enable_flags); + + return 0; +} + +#else /* !CONFIG_PM */ +#define ssb_hcd_suspend NULL +#define ssb_hcd_resume NULL +#endif /* CONFIG_PM */ + +static const struct ssb_device_id ssb_hcd_table[] __devinitconst = { + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), + SSB_DEVTABLE_END +}; +MODULE_DEVICE_TABLE(ssb, ssb_hcd_table); + +static struct ssb_driver ssb_hcd_driver = { + .name = KBUILD_MODNAME, + .id_table = ssb_hcd_table, + .probe = ssb_hcd_probe, + .remove = __devexit_p(ssb_hcd_remove), + .shutdown = ssb_hcd_shutdown, + .suspend = ssb_hcd_suspend, + .resume = ssb_hcd_resume, +}; + +static int __init ssb_hcd_init(void) +{ + return ssb_driver_register(&ssb_hcd_driver); +} +module_init(ssb_hcd_init); + +static void __exit ssb_hcd_exit(void) +{ + ssb_driver_unregister(&ssb_hcd_driver); +} +module_exit(ssb_hcd_exit); -- 1.7.5.4 From hauke@hauke-m.de Sat Jan 21 23:20:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Jan 2012 23:22:57 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45846 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903709Ab2AUWUE (ORCPT ); Sat, 21 Jan 2012 23:20:04 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id ADFA68F6B; Sat, 21 Jan 2012 23:20:04 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id a4dseZCEf-w8; Sat, 21 Jan 2012 23:19:58 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 873D98F67; Sat, 21 Jan 2012 23:19:45 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: stern@rowland.harvard.edu, linux-usb@vger.kernel.org, zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua, Hauke Mehrtens Subject: [PATCH 7/7] USB: OHCI: remove old SSB OHCI driver Date: Sat, 21 Jan 2012 23:19:27 +0100 Message-Id: <1327184367-8824-8-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> References: <1327184367-8824-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32307 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 9433 Lines: 364 This is now replaced by the new ssb USB driver, which also supports devices with an EHCI controller. Signed-off-by: Hauke Mehrtens --- drivers/usb/host/Kconfig | 13 -- drivers/usb/host/ohci-hcd.c | 21 +---- drivers/usb/host/ohci-ssb.c | 260 ------------------------------------------- 3 files changed, 1 insertions(+), 293 deletions(-) delete mode 100644 drivers/usb/host/ohci-ssb.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 2825dc4..3649510 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -360,19 +360,6 @@ config USB_OHCI_HCD_PCI Enables support for PCI-bus plug-in USB controller cards. If unsure, say Y. -config USB_OHCI_HCD_SSB - bool "OHCI support for Broadcom SSB OHCI core" - depends on USB_OHCI_HCD && (SSB = y || SSB = USB_OHCI_HCD) && EXPERIMENTAL - default n - ---help--- - Support for the Sonics Silicon Backplane (SSB) attached - Broadcom USB OHCI core. - - This device is present in some embedded devices with - Broadcom based SSB bus. - - If unsure, say N. - config USB_OHCI_SH bool "OHCI support for SuperH USB controller" depends on USB_OHCI_HCD && SUPERH diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 50fbbf9..a2f4d4e 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1081,11 +1081,6 @@ MODULE_LICENSE ("GPL"); #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver #endif -#ifdef CONFIG_USB_OHCI_HCD_SSB -#include "ohci-ssb.c" -#define SSB_OHCI_DRIVER ssb_ohci_driver -#endif - #ifdef CONFIG_MFD_SM501 #include "ohci-sm501.c" #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver @@ -1134,8 +1129,7 @@ MODULE_LICENSE ("GPL"); !defined(SA1111_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && \ !defined(SM501_OHCI_DRIVER) && \ - !defined(TMIO_OHCI_DRIVER) && \ - !defined(SSB_OHCI_DRIVER) + !defined(TMIO_OHCI_DRIVER) #error "missing bus glue for ohci-hcd" #endif @@ -1201,12 +1195,6 @@ static int __init ohci_hcd_mod_init(void) goto error_pci; #endif -#ifdef SSB_OHCI_DRIVER - retval = ssb_driver_register(&SSB_OHCI_DRIVER); - if (retval) - goto error_ssb; -#endif - #ifdef SM501_OHCI_DRIVER retval = platform_driver_register(&SM501_OHCI_DRIVER); if (retval < 0) @@ -1230,10 +1218,6 @@ static int __init ohci_hcd_mod_init(void) platform_driver_unregister(&SM501_OHCI_DRIVER); error_sm501: #endif -#ifdef SSB_OHCI_DRIVER - ssb_driver_unregister(&SSB_OHCI_DRIVER); - error_ssb: -#endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); error_pci: @@ -1281,9 +1265,6 @@ static void __exit ohci_hcd_mod_exit(void) #ifdef SM501_OHCI_DRIVER platform_driver_unregister(&SM501_OHCI_DRIVER); #endif -#ifdef SSB_OHCI_DRIVER - ssb_driver_unregister(&SSB_OHCI_DRIVER); -#endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); #endif diff --git a/drivers/usb/host/ohci-ssb.c b/drivers/usb/host/ohci-ssb.c deleted file mode 100644 index 5ba1859..0000000 --- a/drivers/usb/host/ohci-ssb.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Sonics Silicon Backplane - * Broadcom USB-core OHCI driver - * - * Copyright 2007 Michael Buesch - * - * Derived from the OHCI-PCI driver - * Copyright 1999 Roman Weissgaerber - * Copyright 2000-2002 David Brownell - * Copyright 1999 Linus Torvalds - * Copyright 1999 Gregory P. Smith - * - * Derived from the USBcore related parts of Broadcom-SB - * Copyright 2005 Broadcom Corporation - * - * Licensed under the GNU/GPL. See COPYING for details. - */ -#include - - -#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29) - -struct ssb_ohci_device { - struct ohci_hcd ohci; /* _must_ be at the beginning. */ - - u32 enable_flags; -}; - -static inline -struct ssb_ohci_device *hcd_to_ssb_ohci(struct usb_hcd *hcd) -{ - return (struct ssb_ohci_device *)(hcd->hcd_priv); -} - - -static int ssb_ohci_reset(struct usb_hcd *hcd) -{ - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - struct ohci_hcd *ohci = &ohcidev->ohci; - int err; - - ohci_hcd_init(ohci); - err = ohci_init(ohci); - - return err; -} - -static int ssb_ohci_start(struct usb_hcd *hcd) -{ - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - struct ohci_hcd *ohci = &ohcidev->ohci; - int err; - - err = ohci_run(ohci); - if (err < 0) { - ohci_err(ohci, "can't start\n"); - ohci_stop(hcd); - } - - return err; -} - -static const struct hc_driver ssb_ohci_hc_driver = { - .description = "ssb-usb-ohci", - .product_desc = "SSB OHCI Controller", - .hcd_priv_size = sizeof(struct ssb_ohci_device), - - .irq = ohci_irq, - .flags = HCD_MEMORY | HCD_USB11, - - .reset = ssb_ohci_reset, - .start = ssb_ohci_start, - .stop = ohci_stop, - .shutdown = ohci_shutdown, - - .urb_enqueue = ohci_urb_enqueue, - .urb_dequeue = ohci_urb_dequeue, - .endpoint_disable = ohci_endpoint_disable, - - .get_frame_number = ohci_get_frame, - - .hub_status_data = ohci_hub_status_data, - .hub_control = ohci_hub_control, -#ifdef CONFIG_PM - .bus_suspend = ohci_bus_suspend, - .bus_resume = ohci_bus_resume, -#endif - - .start_port_reset = ohci_start_port_reset, -}; - -static void ssb_ohci_detach(struct ssb_device *dev) -{ - struct usb_hcd *hcd = ssb_get_drvdata(dev); - - if (hcd->driver->shutdown) - hcd->driver->shutdown(hcd); - usb_remove_hcd(hcd); - iounmap(hcd->regs); - release_mem_region(hcd->rsrc_start, hcd->rsrc_len); - usb_put_hcd(hcd); - ssb_device_disable(dev, 0); -} - -static int ssb_ohci_attach(struct ssb_device *dev) -{ - struct ssb_ohci_device *ohcidev; - struct usb_hcd *hcd; - int err = -ENOMEM; - u32 tmp, flags = 0; - - if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) || - dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32))) - return -EOPNOTSUPP; - - if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) { - /* Put the device into host-mode. */ - flags |= SSB_OHCI_TMSLOW_HOSTMODE; - ssb_device_enable(dev, flags); - } else if (dev->id.coreid == SSB_DEV_USB20_HOST) { - /* - * USB 2.0 special considerations: - * - * In addition to the standard SSB reset sequence, the Host - * Control Register must be programmed to bring the USB core - * and various phy components out of reset. - */ - ssb_device_enable(dev, 0); - ssb_write32(dev, 0x200, 0x7ff); - - /* Change Flush control reg */ - tmp = ssb_read32(dev, 0x400); - tmp &= ~8; - ssb_write32(dev, 0x400, tmp); - tmp = ssb_read32(dev, 0x400); - - /* Change Shim control reg */ - tmp = ssb_read32(dev, 0x304); - tmp &= ~0x100; - ssb_write32(dev, 0x304, tmp); - tmp = ssb_read32(dev, 0x304); - - udelay(1); - - /* Work around for 5354 failures */ - if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { - /* Change syn01 reg */ - tmp = 0x00fe00fe; - ssb_write32(dev, 0x894, tmp); - - /* Change syn03 reg */ - tmp = ssb_read32(dev, 0x89c); - tmp |= 0x1; - ssb_write32(dev, 0x89c, tmp); - } - } else - ssb_device_enable(dev, 0); - - hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev, - dev_name(dev->dev)); - if (!hcd) - goto err_dev_disable; - ohcidev = hcd_to_ssb_ohci(hcd); - ohcidev->enable_flags = flags; - - tmp = ssb_read32(dev, SSB_ADMATCH0); - hcd->rsrc_start = ssb_admatch_base(tmp); - hcd->rsrc_len = ssb_admatch_size(tmp); - hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); - if (!hcd->regs) - goto err_put_hcd; - err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED); - if (err) - goto err_iounmap; - - ssb_set_drvdata(dev, hcd); - - return err; - -err_iounmap: - iounmap(hcd->regs); -err_put_hcd: - usb_put_hcd(hcd); -err_dev_disable: - ssb_device_disable(dev, flags); - return err; -} - -static int ssb_ohci_probe(struct ssb_device *dev, - const struct ssb_device_id *id) -{ - int err; - u16 chipid_top; - - /* USBcores are only connected on embedded devices. */ - chipid_top = (dev->bus->chip_id & 0xFF00); - if (chipid_top != 0x4700 && chipid_top != 0x5300) - return -ENODEV; - - /* TODO: Probably need checks here; is the core connected? */ - - if (usb_disabled()) - return -ENODEV; - - /* We currently always attach SSB_DEV_USB11_HOSTDEV - * as HOST OHCI. If we want to attach it as Client device, - * we must branch here and call into the (yet to - * be written) Client mode driver. Same for remove(). */ - - err = ssb_ohci_attach(dev); - - return err; -} - -static void ssb_ohci_remove(struct ssb_device *dev) -{ - ssb_ohci_detach(dev); -} - -#ifdef CONFIG_PM - -static int ssb_ohci_suspend(struct ssb_device *dev, pm_message_t state) -{ - ssb_device_disable(dev, 0); - - return 0; -} - -static int ssb_ohci_resume(struct ssb_device *dev) -{ - struct usb_hcd *hcd = ssb_get_drvdata(dev); - struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); - - ssb_device_enable(dev, ohcidev->enable_flags); - - ohci_finish_controller_resume(hcd); - return 0; -} - -#else /* !CONFIG_PM */ -#define ssb_ohci_suspend NULL -#define ssb_ohci_resume NULL -#endif /* CONFIG_PM */ - -static const struct ssb_device_id ssb_ohci_table[] = { - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), - SSB_DEVTABLE_END -}; -MODULE_DEVICE_TABLE(ssb, ssb_ohci_table); - -static struct ssb_driver ssb_ohci_driver = { - .name = KBUILD_MODNAME, - .id_table = ssb_ohci_table, - .probe = ssb_ohci_probe, - .remove = ssb_ohci_remove, - .suspend = ssb_ohci_suspend, - .resume = ssb_ohci_resume, -}; -- 1.7.5.4 From stern@rowland.harvard.edu Sun Jan 22 04:41:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jan 2012 04:41:38 +0100 (CET) Received: from netrider.rowland.org ([192.131.102.5]:59977 "HELO netrider.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1901167Ab2AVDla (ORCPT ); Sun, 22 Jan 2012 04:41:30 +0100 Received: (qmail 32631 invoked by uid 500); 21 Jan 2012 22:41:26 -0500 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 21 Jan 2012 22:41:26 -0500 Date: Sat, 21 Jan 2012 22:41:26 -0500 (EST) From: Alan Stern X-X-Sender: stern@netrider.rowland.org To: Hauke Mehrtens cc: ralf@linux-mips.org, , USB list , , , , Subject: Re: [PATCH 4/7] USB: EHCI: Add a generic platform device driver In-Reply-To: <1327184367-8824-5-git-send-email-hauke@hauke-m.de> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32308 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2285 Lines: 76 On Sat, 21 Jan 2012, Hauke Mehrtens wrote: > This adds a generic driver for platform devices. It works like the PCI > driver and is based on it. This is for devices which do not have an own > bus but their EHCI controller works like a PCI controller. It will be > used for the Broadcom bcma and ssb USB EHCI controller. Before adding a generic platform driver for EHCI, you should give some to thought to how it might be generalized. There are a lot of EHCI platform drivers, all differing in various major or minor respects. It should be possible to replace a lot of them with the generic driver, but first it will need some way to cope with a few minor quirks. Please consider this, and think about which of the existing drivers could be replaced. > --- /dev/null > +++ b/drivers/usb/host/ehci-platform.c > @@ -0,0 +1,211 @@ > +/* > + * Generic platform ehci driver > + * > + * Copyright 2007 Steven Brown > + * Copyright 2010-2011 Hauke Mehrtens > + * > + * Derived from the ohci-ssb driver > + * Copyright 2007 Michael Buesch > + * > + * Derived from the EHCI-PCI driver > + * Copyright (c) 2000-2004 by David Brownell > + * > + * Derived from the ohci-pci driver > + * Copyright 1999 Roman Weissgaerber > + * Copyright 2000-2002 David Brownell > + * Copyright 1999 Linus Torvalds > + * Copyright 1999 Gregory P. Smith > + * > + * Licensed under the GNU/GPL. See COPYING for details. > + */ > +#include > + > +static int ehci_platform_reset(struct usb_hcd *hcd) > +{ > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + int retval; > + > + ehci->caps = hcd->regs; > + ehci->regs = hcd->regs + > + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); > + > + dbg_hcs_params(ehci, "reset"); > + dbg_hcc_params(ehci, "reset"); > + > + /* cache this readonly data; minimize chip reads */ > + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); > + > + retval = ehci_halt(ehci); > + if (retval) > + return retval; > + > + /* data structure init */ > + retval = ehci_init(hcd); > + if (retval) > + return retval; > + > + ehci_reset(ehci); > + > + ehci_port_power(ehci, 1); > + > + return retval; > +} Most of this routine should be replaced with a call to ehci_setup. Alan Stern From hauke@hauke-m.de Sun Jan 22 16:02:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jan 2012 16:02:31 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:47220 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901171Ab2AVPCY (ORCPT ); Sun, 22 Jan 2012 16:02:24 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 1AA968F61; Sun, 22 Jan 2012 16:02:23 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NKy-1YhTLkH2; Sun, 22 Jan 2012 16:02:14 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 446388F60; Sun, 22 Jan 2012 16:02:14 +0100 (CET) Message-ID: <4F1C24F5.2020506@hauke-m.de> Date: Sun, 22 Jan 2012 16:02:13 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111124 Thunderbird/8.0 MIME-Version: 1.0 To: Alan Stern CC: ralf@linux-mips.org, linux-mips@linux-mips.org, USB list , zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua Subject: Re: [PATCH 4/7] USB: EHCI: Add a generic platform device driver References: In-Reply-To: X-Enigmail-Version: 1.4a1pre Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32309 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3181 Lines: 93 On 01/22/2012 04:41 AM, Alan Stern wrote: > On Sat, 21 Jan 2012, Hauke Mehrtens wrote: > >> This adds a generic driver for platform devices. It works like the PCI >> driver and is based on it. This is for devices which do not have an own >> bus but their EHCI controller works like a PCI controller. It will be >> used for the Broadcom bcma and ssb USB EHCI controller. > > Before adding a generic platform driver for EHCI, you should give some > to thought to how it might be generalized. There are a lot of EHCI > platform drivers, all differing in various major or minor respects. > It should be possible to replace a lot of them with the generic driver, > but first it will need some way to cope with a few minor quirks. > > Please consider this, and think about which of the existing drivers > could be replaced. For now I just build this for bcma and ssb based SoCs. Yes there are some drivers which could be replaced with this one, but most (all ??) of them do something special in the device probing and this have to be moved to somewhere else e.g. where the platform device is created. I could rename it so it would not be generic any more, but I think it is the wrong approach. ;-) I am not able and do not have the time to convert all EHCI platform drivers, where it is possible to this generic platform driver, as I do not have the devices to test this and time is limited. If someone else wants to improve something on these "generic" platform drivers to make them work with an other device I am totally fine with it. > >> --- /dev/null >> +++ b/drivers/usb/host/ehci-platform.c >> @@ -0,0 +1,211 @@ >> +/* >> + * Generic platform ehci driver >> + * >> + * Copyright 2007 Steven Brown >> + * Copyright 2010-2011 Hauke Mehrtens >> + * >> + * Derived from the ohci-ssb driver >> + * Copyright 2007 Michael Buesch >> + * >> + * Derived from the EHCI-PCI driver >> + * Copyright (c) 2000-2004 by David Brownell >> + * >> + * Derived from the ohci-pci driver >> + * Copyright 1999 Roman Weissgaerber >> + * Copyright 2000-2002 David Brownell >> + * Copyright 1999 Linus Torvalds >> + * Copyright 1999 Gregory P. Smith >> + * >> + * Licensed under the GNU/GPL. See COPYING for details. >> + */ >> +#include >> + >> +static int ehci_platform_reset(struct usb_hcd *hcd) >> +{ >> + struct ehci_hcd *ehci = hcd_to_ehci(hcd); >> + int retval; >> + >> + ehci->caps = hcd->regs; >> + ehci->regs = hcd->regs + >> + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); >> + >> + dbg_hcs_params(ehci, "reset"); >> + dbg_hcc_params(ehci, "reset"); >> + >> + /* cache this readonly data; minimize chip reads */ >> + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); >> + >> + retval = ehci_halt(ehci); >> + if (retval) >> + return retval; >> + >> + /* data structure init */ >> + retval = ehci_init(hcd); >> + if (retval) >> + return retval; >> + >> + ehci_reset(ehci); >> + >> + ehci_port_power(ehci, 1); >> + >> + return retval; >> +} > > Most of this routine should be replaced with a call to ehci_setup. Thanks for the info, this is changed. > > Alan Stern > Hauke From greg@kroah.com Sun Jan 22 20:27:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jan 2012 20:27:24 +0100 (CET) Received: from out3-smtp.messagingengine.com ([66.111.4.27]:38273 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901173Ab2AVT1R (ORCPT ); Sun, 22 Jan 2012 20:27:17 +0100 Received: from compute5.internal (compute5.nyi.mail.srv.osa [10.202.2.45]) by gateway1.nyi.mail.srv.osa (Postfix) with ESMTP id 77A1620368 for ; Sun, 22 Jan 2012 14:27:15 -0500 (EST) Received: from frontend2.nyi.mail.srv.osa ([10.202.2.161]) by compute5.internal (MEProxy); Sun, 22 Jan 2012 14:27:15 -0500 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d= messagingengine.com; h=date:from:to:cc:subject:message-id :references:mime-version:content-type:in-reply-to; s=smtpout; bh=PcHVgK0lHnf4XsLrBKRE0t5cMvo=; b=VlSDcIYiFlx23z3cNysc+a1IUBXq /ZOMGkAHo0sFfhk+e+TY0Qow9RcmUKHwUKwSF47wiFjJnzMjGYBpRRCXdnnr+tX3 CHeooj20KAB1ORtQEIsfCIwp01pmp4f/hSFry/HwepWQqJ1xa3RAOdtxKKfzc567 nFwqCThPzYDvYKk= X-Sasl-enc: DPphdUu3uZbniG/kdPsy9QFCtkrUL5s6nW/Zl4igL+cH 1327260434 Received: from localhost (m1e0f36d0.tmodns.net [208.54.15.30]) by mail.messagingengine.com (Postfix) with ESMTPSA id 84562482488; Sun, 22 Jan 2012 14:27:14 -0500 (EST) Date: Sun, 22 Jan 2012 14:23:46 -0500 From: Greg KH To: Hauke Mehrtens Cc: Alan Stern , ralf@linux-mips.org, linux-mips@linux-mips.org, USB list , zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua Subject: Re: [PATCH 4/7] USB: EHCI: Add a generic platform device driver Message-ID: <20120122192346.GA1691@kroah.com> References: <4F1C24F5.2020506@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4F1C24F5.2020506@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32310 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: greg@kroah.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1996 Lines: 45 On Sun, Jan 22, 2012 at 04:02:13PM +0100, Hauke Mehrtens wrote: > On 01/22/2012 04:41 AM, Alan Stern wrote: > > On Sat, 21 Jan 2012, Hauke Mehrtens wrote: > > > >> This adds a generic driver for platform devices. It works like the PCI > >> driver and is based on it. This is for devices which do not have an own > >> bus but their EHCI controller works like a PCI controller. It will be > >> used for the Broadcom bcma and ssb USB EHCI controller. > > > > Before adding a generic platform driver for EHCI, you should give some > > to thought to how it might be generalized. There are a lot of EHCI > > platform drivers, all differing in various major or minor respects. > > It should be possible to replace a lot of them with the generic driver, > > but first it will need some way to cope with a few minor quirks. > > > > Please consider this, and think about which of the existing drivers > > could be replaced. > > For now I just build this for bcma and ssb based SoCs. Yes there are > some drivers which could be replaced with this one, but most (all ??) of > them do something special in the device probing and this have to be > moved to somewhere else e.g. where the platform device is created. > I could rename it so it would not be generic any more, but I think it is > the wrong approach. ;-) > I am not able and do not have the time to convert all EHCI platform > drivers, where it is possible to this generic platform driver, as I do > not have the devices to test this and time is limited. Time is not limited for us, sorry, this seems like the correct thing to do, and because of that, we (well I at least) will not accept this patch as-is. Please go rework it to be as Alan suggested. > If someone else wants to improve something on these "generic" platform > drivers to make them work with an other device I am totally fine with it. I think that someone just became you :) Yes, this isn't fair, but it's how Linux kernel development works, sorry. thanks, greg k-h From paul.gortmaker@windriver.com Sun Jan 22 21:03:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jan 2012 21:03:19 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:48332 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901341Ab2AVUDN (ORCPT ); Sun, 22 Jan 2012 21:03:13 +0100 Received: from yow-lpgnfs-02.corp.ad.wrs.com (yow-lpgnfs-02.ottawa.windriver.com [128.224.149.8]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id q0MK30ZP017584; Sun, 22 Jan 2012 12:03:00 -0800 (PST) From: Paul Gortmaker To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, Paul Gortmaker , Jayachandran C Subject: [PATCH] mips: fix netlogic defconfigs for coverage builds Date: Sun, 22 Jan 2012 15:02:46 -0500 Message-Id: <1327262566-2676-1-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 1.7.7.2 X-archive-position: 32311 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.gortmaker@windriver.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2039 Lines: 60 The toolchain prefix will most likely be site specific and is not guaranteed to always be "mips-linux-gnu-", so simply don't specify one. A quick "git grep" shows this to be consistent amongst other cross compiled targets. Similarly, the site specific initramfs source location should not be used, since that won't exist for most people, and it prevents them from doing coverage builds on the defconfigs, such as those done in linux-next and run routinely by many others. Signed-off-by: Paul Gortmaker CC: Jayachandran C diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig index 4479fd6..28c6b27 100644 --- a/arch/mips/configs/nlm_xlp_defconfig +++ b/arch/mips/configs/nlm_xlp_defconfig @@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y # CONFIG_SECCOMP is not set CONFIG_USE_OF=y CONFIG_EXPERIMENTAL=y -CONFIG_CROSS_COMPILE="mips-linux-gnu-" +CONFIG_CROSS_COMPILE="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -22,7 +22,7 @@ CONFIG_AUDIT=y CONFIG_CGROUPS=y CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlp" +CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_INITRAMFS_COMPRESSION_LZMA=y diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig index 7c68666..d0b857d 100644 --- a/arch/mips/configs/nlm_xlr_defconfig +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_KEXEC=y CONFIG_EXPERIMENTAL=y -CONFIG_CROSS_COMPILE="mips-linux-gnu-" +CONFIG_CROSS_COMPILE="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -22,7 +22,7 @@ CONFIG_AUDIT=y CONFIG_NAMESPACES=y CONFIG_SCHED_AUTOGROUP=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlr" +CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_INITRAMFS_COMPRESSION_GZIP=y -- 1.7.7.2 From ralf@linux-mips.org Mon Jan 23 14:32:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Jan 2012 14:33:07 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:33338 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903735Ab2AWNc4 (ORCPT ); Mon, 23 Jan 2012 14:32:56 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id q0NDWsvO010812; Mon, 23 Jan 2012 14:32:54 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id q0NDWqDT010811; Mon, 23 Jan 2012 14:32:52 +0100 Date: Mon, 23 Jan 2012 14:32:52 +0100 From: Ralf Baechle To: Paul Gortmaker Cc: linux-mips@linux-mips.org, Jayachandran C , David VomLehn Subject: Re: [PATCH] mips: fix netlogic defconfigs for coverage builds Message-ID: <20120123133252.GA10454@linux-mips.org> References: <1327262566-2676-1-git-send-email-paul.gortmaker@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1327262566-2676-1-git-send-email-paul.gortmaker@windriver.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32312 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1171 Lines: 28 On Sun, Jan 22, 2012 at 03:02:46PM -0500, Paul Gortmaker wrote: > The toolchain prefix will most likely be site specific and is > not guaranteed to always be "mips-linux-gnu-", so simply don't > specify one. A quick "git grep" shows this to be consistent > amongst other cross compiled targets. > > Similarly, the site specific initramfs source location should not > be used, since that won't exist for most people, and it prevents > them from doing coverage builds on the defconfigs, such as those > done in linux-next and run routinely by many others. I ran into that issue as well. My build script does something like sed -i -e s@^CONFIG_CROSS_COMPILE=\"[^\"]*\"\$@CONFIG_CROSS_COMPILE=\"\"@ sed -i -e s@^CONFIG_INITRAMFS_SOURCE=\"[^\"]*\"\$@CONFIG_INITRAMFS_SOURCE=\"\"@ sed -i -e s/^CONFIG_DEBUG_INFO=y\$/#\ CONFIG_DEBUG_INFO\ is\ not\ set/ to patch up two two annoying settings and the last one to make the compiler run a little quicker and increase chances for a hit in ccache. But for benefit of the rest of the world I've applied tihs patch and will also patch up powertv_defconfig which now is the last CONFIG_CROSS_COMPILE user. Thanks! Ralf From stern@rowland.harvard.edu Mon Jan 23 17:29:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Jan 2012 17:29:51 +0100 (CET) Received: from iolanthe.rowland.org ([192.131.102.54]:56272 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1903806Ab2AWQ3q (ORCPT ); Mon, 23 Jan 2012 17:29:46 +0100 Received: (qmail 1564 invoked by uid 2102); 23 Jan 2012 11:29:43 -0500 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 23 Jan 2012 11:29:43 -0500 Date: Mon, 23 Jan 2012 11:29:43 -0500 (EST) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Hauke Mehrtens , Greg KH cc: ralf@linux-mips.org, , USB list , , , , Subject: Re: [PATCH 4/7] USB: EHCI: Add a generic platform device driver In-Reply-To: <20120122192346.GA1691@kroah.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32313 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3042 Lines: 64 On Sun, 22 Jan 2012, Greg KH wrote: > On Sun, Jan 22, 2012 at 04:02:13PM +0100, Hauke Mehrtens wrote: > > On 01/22/2012 04:41 AM, Alan Stern wrote: > > > On Sat, 21 Jan 2012, Hauke Mehrtens wrote: > > > > > >> This adds a generic driver for platform devices. It works like the PCI > > >> driver and is based on it. This is for devices which do not have an own > > >> bus but their EHCI controller works like a PCI controller. It will be > > >> used for the Broadcom bcma and ssb USB EHCI controller. > > > > > > Before adding a generic platform driver for EHCI, you should give some > > > to thought to how it might be generalized. There are a lot of EHCI > > > platform drivers, all differing in various major or minor respects. > > > It should be possible to replace a lot of them with the generic driver, > > > but first it will need some way to cope with a few minor quirks. > > > > > > Please consider this, and think about which of the existing drivers > > > could be replaced. > > > > For now I just build this for bcma and ssb based SoCs. Yes there are > > some drivers which could be replaced with this one, but most (all ??) of > > them do something special in the device probing and this have to be > > moved to somewhere else e.g. where the platform device is created. > > I could rename it so it would not be generic any more, but I think it is > > the wrong approach. ;-) > > I am not able and do not have the time to convert all EHCI platform > > drivers, where it is possible to this generic platform driver, as I do > > not have the devices to test this and time is limited. > > Time is not limited for us, sorry, this seems like the correct thing to > do, and because of that, we (well I at least) will not accept this patch > as-is. > > Please go rework it to be as Alan suggested. > > > If someone else wants to improve something on these "generic" platform > > drivers to make them work with an other device I am totally fine with it. > > I think that someone just became you :) > > Yes, this isn't fair, but it's how Linux kernel development works, > sorry. The work doesn't have to be all done right away. Still, I think it makes sense to separate out the "generic platform" drivers from the rest of this patch series. Some platform drivers require additional storage for things like pointers to clocks or OTG transceivers. For example see ehci-mv.c, which allocates its own ehci_hcd_mv structure along with ehci_hcd. Some other drivers even define their own private version of ehci_hcd, such as ehci-fsl.c. If you can figure out a good way to expend the ehci_hcd structure so that it can accomodate the extra fields needed by all these drivers in a generic way, that would be an excellent start and well worth merging. Maybe just adding a "void *platform_data" field would be enough. As for special activities during device probing... Many of these can be handled later on, easily enough, by adding appropriate quirk flags. We don't have to worry about that part right now. Alan Stern From juhosg@openwrt.org Mon Jan 23 19:29:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Jan 2012 19:29:18 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:46146 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903825Ab2AWS3O (ORCPT ); Mon, 23 Jan 2012 19:29:14 +0100 X-Virus-Scanned: at arrakis.dune.hu Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id C9E2723C00B6; Mon, 23 Jan 2012 19:29:12 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos Subject: [PATCH] MIPS: ath79: fix AR933X WMAC reset code Date: Mon, 23 Jan 2012 19:29:07 +0100 Message-Id: <1327343347-26928-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 32314 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 824 Lines: 35 The current code puts the built-in WMAC device of the AR933X SoCs into reset instead of starting it. This causes a hard lock on AR933X based boards when the wireless driver tries to access the device. Signed-off-by: Gabor Juhos --- Ralf, This one is for 3.3. Thanks, Gabor arch/mips/ath79/dev-wmac.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index e215070..9c717bf 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void) static int ar933x_wmac_reset(void) { - ath79_device_reset_clear(AR933X_RESET_WMAC); ath79_device_reset_set(AR933X_RESET_WMAC); + ath79_device_reset_clear(AR933X_RESET_WMAC); return 0; } -- 1.7.2.1 From hauke@hauke-m.de Mon Jan 23 21:58:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Jan 2012 21:58:13 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:50626 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903866Ab2AWU6E (ORCPT ); Mon, 23 Jan 2012 21:58:04 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id EF29A8F61; Mon, 23 Jan 2012 21:58:03 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8irDUGqGXf9O; Mon, 23 Jan 2012 21:58:00 +0100 (CET) Received: from [192.168.1.220] (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 2804F8F60; Mon, 23 Jan 2012 21:58:00 +0100 (CET) Message-ID: <4F1DC9D4.8090008@hauke-m.de> Date: Mon, 23 Jan 2012 21:57:56 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111124 Thunderbird/8.0 MIME-Version: 1.0 To: Alan Stern CC: Greg KH , ralf@linux-mips.org, linux-mips@linux-mips.org, USB list , zajec5@gmail.com, linux-wireless@vger.kernel.org, m@bues.ch, george@znau.edu.ua Subject: Re: [PATCH 4/7] USB: EHCI: Add a generic platform device driver References: In-Reply-To: X-Enigmail-Version: 1.4a1pre Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 32315 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3537 Lines: 75 On 01/23/2012 05:29 PM, Alan Stern wrote: > On Sun, 22 Jan 2012, Greg KH wrote: > >> On Sun, Jan 22, 2012 at 04:02:13PM +0100, Hauke Mehrtens wrote: >>> On 01/22/2012 04:41 AM, Alan Stern wrote: >>>> On Sat, 21 Jan 2012, Hauke Mehrtens wrote: >>>> >>>>> This adds a generic driver for platform devices. It works like the PCI >>>>> driver and is based on it. This is for devices which do not have an own >>>>> bus but their EHCI controller works like a PCI controller. It will be >>>>> used for the Broadcom bcma and ssb USB EHCI controller. >>>> >>>> Before adding a generic platform driver for EHCI, you should give some >>>> to thought to how it might be generalized. There are a lot of EHCI >>>> platform drivers, all differing in various major or minor respects. >>>> It should be possible to replace a lot of them with the generic driver, >>>> but first it will need some way to cope with a few minor quirks. >>>> >>>> Please consider this, and think about which of the existing drivers >>>> could be replaced. >>> >>> For now I just build this for bcma and ssb based SoCs. Yes there are >>> some drivers which could be replaced with this one, but most (all ??) of >>> them do something special in the device probing and this have to be >>> moved to somewhere else e.g. where the platform device is created. >>> I could rename it so it would not be generic any more, but I think it is >>> the wrong approach. ;-) >>> I am not able and do not have the time to convert all EHCI platform >>> drivers, where it is possible to this generic platform driver, as I do >>> not have the devices to test this and time is limited. >> >> Time is not limited for us, sorry, this seems like the correct thing to >> do, and because of that, we (well I at least) will not accept this patch >> as-is. >> >> Please go rework it to be as Alan suggested. >> >>> If someone else wants to improve something on these "generic" platform >>> drivers to make them work with an other device I am totally fine with it. >> >> I think that someone just became you :) >> >> Yes, this isn't fair, but it's how Linux kernel development works, >> sorry. > > The work doesn't have to be all done right away. Still, I think it > makes sense to separate out the "generic platform" drivers from the > rest of this patch series. Ok, but how should these patches being merged as my plan is to get them all into 3.4 in some way? The bcma hcd driver depends on changes in drivers/bcma and will also depend on these generic platform driver. > Some platform drivers require additional storage for things like > pointers to clocks or OTG transceivers. For example see ehci-mv.c, > which allocates its own ehci_hcd_mv structure along with ehci_hcd. > Some other drivers even define their own private version of ehci_hcd, > such as ehci-fsl.c. If you can figure out a good way to expend the > ehci_hcd structure so that it can accomodate the extra fields needed by > all these drivers in a generic way, that would be an excellent start > and well worth merging. Maybe just adding a "void *platform_data" > field would be enough. Yes I will have a look at most/all these drivers and will come up with a new version of the generic platform driver in some days. Thanks for these examples you mentioned. > As for special activities during device probing... Many of these can > be handled later on, easily enough, by adding appropriate quirk flags. > We don't have to worry about that part right now. Yes I also thought about such flags. > Alan Stern > Hauke From stern@rowland.harvard.edu Mon Jan 23 22:34:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Jan 2012 22:34:09 +0100 (CET) Received: from iolanthe.rowland.org ([192.131.102.54]:56370 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1903866Ab2AWVeE (ORCPT ); Mon, 23 Jan 2012 22:34:04 +0100 Received: (qmail 10705 invoked by uid 2102); 23 Jan 2012 16:34:02 -0500 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 23 Jan 2012 16:34:02 -0500 Date: Mon, 23 Jan 2012 16:34:02 -0500 (EST) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Hauke Mehrtens cc: Greg KH , , , USB list , , , , Subject: Re: [PATCH 4/7] USB: EHCI: Add a generic platform device driver In-Reply-To: <4F1DC9D4.8090008@hauke-m.de> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 32316 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1074 Lines: 23 On Mon, 23 Jan 2012, Hauke Mehrtens wrote: > > The work doesn't have to be all done right away. Still, I think it > > makes sense to separate out the "generic platform" drivers from the > > rest of this patch series. > Ok, but how should these patches being merged as my plan is to get them > all into 3.4 in some way? The bcma hcd driver depends on changes in > drivers/bcma and will also depend on these generic platform driver. Like I said, we don't need a fully general generic platform driver right away. If you make a small number of additions so that it is clear how to use the two generic drivers instead of some of the existing platform drivers, and then submit the generic drivers as a separate standalone patch series, that should be good enough. Greg will probably be very happy to merge it, if it includes an explicit plan for replacing some existing drivers. Then the bcma stuff can be added on top, as a separate patch series. Once that's done, we can start making an effort to assimilate the platform drivers into the generic drivers. Alan Stern From john.stultz@linaro.org Tue Jan 24 01:07:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jan 2012 01:07:38 +0100 (CET) Received: from e32.co.us.ibm.com ([32.97.110.150]:58395 "EHLO e32.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903867Ab2AXAH3 (ORCPT ); Tue, 24 Jan 2012 01:07:29 +0100 Received: from /spool/local by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 23 Jan 2012 17:07:22 -0700 Received: from d03dlp02.boulder.ibm.com (9.17.202.178) by e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Mon, 23 Jan 2012 17:06:17 -0700 Received: from d03relay03.boulder.ibm.com (d03relay03.boulder.ibm.com [9.17.195.228]) by d03dlp02.boulder.ibm.com (Postfix) with ESMTP id 74C483E40055; Mon, 23 Jan 2012 17:06:16 -0700 (MST) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d03relay03.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q0O06AEi160132; Mon, 23 Jan 2012 17:06:13 -0700 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q0O069a7004339; Mon, 23 Jan 2012 17:06:10 -0700 Received: from kernel.beaverton.ibm.com (kernel.beaverton.ibm.com [9.47.67.96]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q0O068tD004236; Mon, 23 Jan 2012 17:06:09 -0700 Received: by kernel.beaverton.ibm.com (Postfix, from userid 1056) id B0A9EBFE5C; Mon, 23 Jan 2012 16:06:07 -0800 (PST) From: John Stultz To: lkml Cc: John Stultz , Ralf Baechle , Yong Zhang , linux-mips@linux-mips.org Subject: [PATCH 3/3] clocksource: Convert mips pnx8550 to use clocksource_register_hz Date: Mon, 23 Jan 2012 16:05:50 -0800 Message-Id: <1327363550-19952-4-git-send-email-john.stultz@linaro.org> X-Mailer: git-send-email 1.7.3.2.146.gca209 In-Reply-To: <1327363550-19952-1-git-send-email-john.stultz@linaro.org> References: <1327363550-19952-1-git-send-email-john.stultz@linaro.org> X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12012400-3270-0000-0000-0000036FE78C X-archive-position: 32317 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john.stultz@linaro.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1070 Lines: 33 This patch converts the registration to use clocksource_register_hz() but is clearly broken, as the pnx_clocksource doesn't seem to set a proper mult/shift pair. CC: Ralf Baechle CC: Yong Zhang CC: linux-mips@linux-mips.org Signed-off-by: John Stultz --- arch/mips/pnx8550/common/time.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/arch/mips/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c index 831d6b3..006ac88 100644 --- a/arch/mips/pnx8550/common/time.c +++ b/arch/mips/pnx8550/common/time.c @@ -104,7 +104,12 @@ __init void plat_time_init(void) pnx8xxx_clockevent.cpumask = cpu_none_mask; clockevents_register_device(&pnx8xxx_clockevent); - clocksource_register(&pnx_clocksource); + + /* + * XXX - Nothing seems to set pnx_clocksource mult/shift! + * So I don't know what freq to use here. Help! -johnstul + */ + clocksource_register_hz(&pnx_clocksource, 0); /* Timer 1 start */ configPR = read_c0_config7(); -- 1.7.3.2.146.gca209 From standby24x7@gmail.com Sat Jan 28 14:38:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 28 Jan 2012 14:38:14 +0100 (CET) Received: from i118-21-156-233.s30.a048.ap.plala.or.jp ([118.21.156.233]:53981 "EHLO rinabert.homeip.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903650Ab2A1NiH (ORCPT ); Sat, 28 Jan 2012 14:38:07 +0100 Received: from rinabert.homeip.net (localhost [127.0.0.1]) by rinabert.homeip.net (8.14.5/8.14.5) with ESMTP id q0SDbLJL007437; Sat, 28 Jan 2012 22:37:21 +0900 Received: (from root@localhost) by rinabert.homeip.net (8.14.5/8.14.5/Submit) id q0SDbDuW007436; Sat, 28 Jan 2012 22:37:13 +0900 From: Masanari Iida To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: standby24x7@gmail.com, linux-kernel@vger.kernel.org, trivial@kernel.org Subject: [PATCH] [trivial] mips: Fix typo in bcm63xx/setup.c Date: Sat, 28 Jan 2012 22:36:56 +0900 Message-Id: <1327757816-7401-1-git-send-email-standby24x7@gmail.com> X-Mailer: git-send-email 1.7.6.5 X-archive-position: 32318 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: standby24x7@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 716 Lines: 24 Correct spelling "reseting" to "resetting" in arch/mips/bcm63xx/setup.c Signed-off-by: Masanari Iida --- arch/mips/bcm63xx/setup.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index d209f85..356b055 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -33,7 +33,7 @@ static void bcm6348_a1_reboot(void) u32 reg; /* soft reset all blocks */ - printk(KERN_INFO "soft-reseting all blocks ...\n"); + printk(KERN_INFO "soft-resetting all blocks ...\n"); reg = bcm_perf_readl(PERF_SOFTRESET_REG); reg &= ~SOFTRESET_6348_ALL; bcm_perf_writel(reg, PERF_SOFTRESET_REG); -- 1.7.6.5 From cernekee@gmail.com Sat Jan 28 23:38:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 28 Jan 2012 23:38:25 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:50028 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903662Ab2A1WiS convert rfc822-to-8bit (ORCPT ); Sat, 28 Jan 2012 23:38:18 +0100 Received: by pbdx9 with SMTP id x9so3313486pbd.36 for ; Sat, 28 Jan 2012 14:38:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=0i+RjziX8xr1fw1XyWqYc3ttsNXRW/8Z5EzgKlkyr40=; b=RRJfoJqnNF3aaXzqz6P4SPT+/fOKX7TKmuGc4tTb16k5q9ZHS6qRasvkrVsGrVvy85 GE1jbJ9UAIE1XF3cwBfw5jyTAJzMvx5RG76lei4vvcTAGl5OVTjHBMfPk+y+iH3ob7XL 2LvRJZW1zIzucIThSKdOqPh7Szlw+dufKDVTM= MIME-Version: 1.0 Received: by 10.68.73.4 with SMTP id h4mr27207845pbv.27.1327790290371; Sat, 28 Jan 2012 14:38:10 -0800 (PST) Received: by 10.68.234.166 with HTTP; Sat, 28 Jan 2012 14:38:10 -0800 (PST) In-Reply-To: <66457f7750d7d14229fcf8d0b011aba63185a75d.1322163031.git.mst@redhat.com> References: <66457f7750d7d14229fcf8d0b011aba63185a75d.1322163031.git.mst@redhat.com> Date: Sat, 28 Jan 2012 14:38:10 -0800 Message-ID: Subject: Re: [PATCH-RFC 06/10] mips: switch to GENERIC_PCI_IOMAP From: Kevin Cernekee To: Ralf Baechle , "Michael S. Tsirkin" Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Mikael Starvik , Jesper Nilsson , Richard Kuo , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Michal Simek , Jonas Bonn , Kyle McMartin , Helge Deller , "James E.J. Bottomley" , Benjamin Herrenschmidt , Paul Mackerras , Chen Liqin , Lennox Wu , Paul Mundt , "David S. Miller" , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Arnd Bergmann , Andrew Morton , Nicolas Pitre , Paul Bolle , Olof Johansson , Rob Herring , Paul Gortmaker , Kumar Gala , Michael Ellerman , Fabio Baltieri , Lucas De Marchi , "John W. Linville" , Lasse Collin , Arend van Spriel , Franky Lin , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-cris-kernel@axis.com, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linux@openrisc.net, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, Jesse Barnes , linux-pci@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 32319 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2047 Lines: 49 On Thu, Nov 24, 2011 at 12:18 PM, Michael S. Tsirkin wrote: > mips copied pci_iomap from generic code, probably to avoid > pulling the rest of iomap.c in.  Since that's in > a separate file now, we can reuse the common implementation. [snip] > -       if (flags & IORESOURCE_IO) > -               return ioport_map_pci(dev, start, len); While investigating a new warning on the 3.3-rc1 MIPS build (unused static function ioport_map_pci()), I noticed that this patch has shown up in Linus' tree as commit eab90291d35438bcebf7c3dc85be66d0f24e3002. I am not completely clear on the implications it has on mapping PCI I/O regions: Prior to this change, the MIPS version of pci_iomap() called a MIPS-specific function, ioport_map_pci(), which tried to use the PCI controller's io_map_base field to determine the base address of the PCI I/O space. It also had a fallback mechanism to deal with the case where io_map_base is unset. Now, in 3.3-rc1, the generic version of pci_iomap() is used instead. This code just calls arch/mips/lib/iomap.c:ioport_map() on these regions. ioport_map() falls through to ioport_map_legacy(), which always uses mips_io_port_base (not the PCI controller's io_map_base) as the base address. But on MIPS, it is still permissible to use different I/O port bases for PCI devices and for legacy (ISA?) devices. Is this new behavior desirable, or are there any supported platforms on which adverse effects might be seen? As for my part, I don't use PCI I/O regions at all - just memory regions. I'm more worried about making sure my tree builds with 0 warnings. If we do want to move ahead with the switch to GENERIC_PCI_IOMAP now, I have patches to scrap iomap-pci.c entirely and squash the unused function warning. If we still want to support the case where io_map_base != mips_io_port_base, maybe it would be better to revert commit eab90291 for 3.3. Might also want to take a look at SH since it also appears to have an orphaned ioport_map_pci() function. What are your thoughts? From cernekee@gmail.com Sun Jan 29 00:12:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 29 Jan 2012 00:12:52 +0100 (CET) Received: from [69.28.251.93] ([69.28.251.93]:46856 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1903662Ab2A1XMo (ORCPT ); Sun, 29 Jan 2012 00:12:44 +0100 Received: (qmail 17689 invoked from network); 28 Jan 2012 23:12:39 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 28 Jan 2012 23:12:39 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 28 Jan 2012 15:12:39 -0800 From: Kevin Cernekee To: Ralf Baechle , David Daney Cc: , Subject: [PATCH] MIPS: Fix duplicate instances of ARCH_SPARSEMEM_ENABLE Date: Sat, 28 Jan 2012 15:07:49 -0800 Message-Id: <0736d2becb10905c35eec74f04c63970@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 32320 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1325 Lines: 38 "config ARCH_SPARSEMEM_ENABLE" exists in both arch/mips/Kconfig and arch/mips/cavium-octeon/Kconfig, but the dependencies are not the same. This results in warnings when a non-Cavium platform tries to select ARCH_SPARSEMEM_ENABLE: $ make lemote2f_defconfig ARCH=mips warning: (LEMOTE_FULOONG2E && LEMOTE_MACH2F) selects ARCH_SPARSEMEM_ENABLE which has unmet direct dependencies (CPU_CAVIUM_OCTEON) warning: (LEMOTE_FULOONG2E && LEMOTE_MACH2F) selects ARCH_SPARSEMEM_ENABLE which has unmet direct dependencies (CPU_CAVIUM_OCTEON) # # configuration written to .config # Proposed workaround is to use a Cavium-specific config option which "select"s the desired options. Signed-off-by: Kevin Cernekee --- arch/mips/cavium-octeon/Kconfig | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index f9e275a..eda8266 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -82,8 +82,9 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY help Lock the kernel's implementation of memcpy() into L2. -config ARCH_SPARSEMEM_ENABLE +config CAVIUM_OCTEON_SPARSEMEM_ENABLE def_bool y + select ARCH_SPARSEMEM_ENABLE select SPARSEMEM_STATIC config IOMMU_HELPER -- 1.7.6.3 From mst@redhat.com Sun Jan 29 23:43:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 29 Jan 2012 23:44:01 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:12558 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903686Ab2A2Wnw (ORCPT ); Sun, 29 Jan 2012 23:43:52 +0100 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0TMh6QU030435 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Sun, 29 Jan 2012 17:43:07 -0500 Received: from redhat.com (vpn-203-124.tlv.redhat.com [10.35.203.124]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q0TMgcAV018377; Sun, 29 Jan 2012 17:42:39 -0500 Date: Mon, 30 Jan 2012 00:45:07 +0200 From: "Michael S. Tsirkin" To: Kevin Cernekee Cc: Ralf Baechle , Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Mikael Starvik , Jesper Nilsson , Richard Kuo , Tony Luck , Fenghua Yu , Geert Uytterhoeven , Michal Simek , Jonas Bonn , Kyle McMartin , Helge Deller , "James E.J. Bottomley" , Benjamin Herrenschmidt , Paul Mackerras , Chen Liqin , Lennox Wu , Paul Mundt , "David S. Miller" , Guan Xuetao , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Arnd Bergmann , Andrew Morton , Nicolas Pitre , Paul Bolle , Olof Johansson , Rob Herring , Paul Gortmaker , Kumar Gala , Michael Ellerman , Fabio Baltieri , Lucas De Marchi , "John W. Linville" , Lasse Collin , Arend van Spriel , Franky Lin , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-cris-kernel@axis.com, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linux@openrisc.net, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, Jesse Barnes , linux-pci@vger.kernel.org Subject: Re: [PATCH-RFC 06/10] mips: switch to GENERIC_PCI_IOMAP Message-ID: <20120129223339.GA22666@redhat.com> References: <66457f7750d7d14229fcf8d0b011aba63185a75d.1322163031.git.mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-archive-position: 32321 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 980 Lines: 25 On Sat, Jan 28, 2012 at 02:38:10PM -0800, Kevin Cernekee wrote: > On Thu, Nov 24, 2011 at 12:18 PM, Michael S. Tsirkin wrote: > > mips copied pci_iomap from generic code, probably to avoid > > pulling the rest of iomap.c in.  Since that's in > > a separate file now, we can reuse the common implementation. > > [snip] > > > -       if (flags & IORESOURCE_IO) > > -               return ioport_map_pci(dev, start, len); > > While investigating a new warning on the 3.3-rc1 MIPS build (unused > static function ioport_map_pci()), I noticed that this patch has shown > up in Linus' tree as commit eab90291d35438bcebf7c3dc85be66d0f24e3002. > > I am not completely clear on the implications it has on mapping PCI I/O regions: Yes, my bad, I missed the difference between ioport_map_pci and ioport_map for both MIPS and SH. I'll post a patch to fix this, which is probably preferable to reintroducing the code duplication where it might trip us up again. -- MST From mst@redhat.com Mon Jan 30 13:16:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 13:16:24 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:41863 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901169Ab2A3MQT (ORCPT ); Mon, 30 Jan 2012 13:16:19 +0100 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0UCG7rg015830 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 30 Jan 2012 07:16:07 -0500 Received: from redhat.com (vpn-203-146.tlv.redhat.com [10.35.203.146]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id q0UCFvSg016862; Mon, 30 Jan 2012 07:15:58 -0500 Date: Mon, 30 Jan 2012 14:18:25 +0200 From: "Michael S. Tsirkin" To: Kevin Cernekee Cc: Ralf Baechle , Paul Mundt , Arnd Bergmann , "Michael S. Tsirkin" , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [PATCH 0/3] arch: fix ioport mapping on mips,sh Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Mutt-Fcc: =sent User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-archive-position: 32322 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1169 Lines: 33 Kevin Cernekee reported that recent cleanup that replaced pci_iomap with a generic function failed to take into account the differences in io port handling on mips and sh architectures. Rather than revert the changes reintroducing the code duplication, this patchset fixes this by adding ability for architectures to override ioport mapping for pci devices. I put this in my tree that feeds into linux-next and intend to ask Linus to pull this fix if this doesn't cause any issues and there are no objections. The patches were tested on x86 and compiled on mips and sh. Would appreciate reviews/acks/testing reports. Michael S. Tsirkin (3): lib: add NO_GENERIC_PCI_IOPORT_MAP mips: use the the PCI controller's io_map_base sh: use the the PCI channels's io_map_base arch/mips/Kconfig | 1 + arch/mips/lib/iomap-pci.c | 4 ++-- arch/sh/Kconfig | 1 + arch/sh/drivers/pci/pci.c | 4 ++-- include/asm-generic/pci_iomap.h | 5 +++++ lib/Kconfig | 3 +++ lib/pci_iomap.c | 12 +++++++++++- 7 files changed, 25 insertions(+), 5 deletions(-) -- 1.7.8.2.325.g247f9 From mst@redhat.com Mon Jan 30 13:16:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 13:16:48 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:41126 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903686Ab2A3MQb (ORCPT ); Mon, 30 Jan 2012 13:16:31 +0100 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0UCGMYd029129 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 30 Jan 2012 07:16:22 -0500 Received: from redhat.com (vpn-203-146.tlv.redhat.com [10.35.203.146]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id q0UCGBgb028283; Mon, 30 Jan 2012 07:16:12 -0500 Date: Mon, 30 Jan 2012 14:18:39 +0200 From: "Michael S. Tsirkin" To: Kevin Cernekee Cc: Ralf Baechle , Paul Mundt , Arnd Bergmann , "Michael S. Tsirkin" , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Mutt-Fcc: =sent User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-archive-position: 32323 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2433 Lines: 76 Some architectures need to override the way IO port mapping is does not PCI devices. Supply a generic function that calls ioport_map, and make it possible for architectures to override. Signed-off-by: Michael S. Tsirkin --- include/asm-generic/pci_iomap.h | 5 +++++ lib/Kconfig | 3 +++ lib/pci_iomap.c | 12 +++++++++++- 3 files changed, 19 insertions(+), 1 deletions(-) diff --git a/include/asm-generic/pci_iomap.h b/include/asm-generic/pci_iomap.h index 8de4b73..2aff58e 100644 --- a/include/asm-generic/pci_iomap.h +++ b/include/asm-generic/pci_iomap.h @@ -15,6 +15,11 @@ struct pci_dev; #ifdef CONFIG_PCI /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); +/* Create a virtual mapping cookie for a port on a given PCI device. + * Do not call this directly, it exists to make it easier for architectures + * to override. */ +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, + unsigned int nr); #else static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) { diff --git a/lib/Kconfig b/lib/Kconfig index 169eb7c..1df1388 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -19,6 +19,9 @@ config RATIONAL config GENERIC_FIND_FIRST_BIT bool +config NO_GENERIC_PCI_IOPORT_MAP + bool + config GENERIC_PCI_IOMAP bool diff --git a/lib/pci_iomap.c b/lib/pci_iomap.c index 4b0fdc2..1dfda29 100644 --- a/lib/pci_iomap.c +++ b/lib/pci_iomap.c @@ -9,6 +9,16 @@ #include #ifdef CONFIG_PCI +#ifndef CONFIG_NO_GENERIC_PCI_IOPORT_MAP +/* Architectures can override ioport mapping while + * still using the rest of the generic infrastructure. */ +void __iomem *__pci_ioport_map(struct pci_dev *dev, + unsigned long port, + unsigned int nr) +{ + return ioport_map(port, nr); +} +#endif /** * pci_iomap - create a virtual mapping cookie for a PCI BAR * @dev: PCI device that owns the BAR @@ -34,7 +44,7 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) if (maxlen && len > maxlen) len = maxlen; if (flags & IORESOURCE_IO) - return ioport_map(start, len); + return __pci_ioport_map(dev, start, len); if (flags & IORESOURCE_MEM) { if (flags & IORESOURCE_CACHEABLE) return ioremap(start, len); -- 1.7.8.2.325.g247f9 From mst@redhat.com Mon Jan 30 13:16:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 13:17:12 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:33821 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2A3MQi (ORCPT ); Mon, 30 Jan 2012 13:16:38 +0100 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0UCGXlH016135 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 30 Jan 2012 07:16:33 -0500 Received: from redhat.com (vpn-203-146.tlv.redhat.com [10.35.203.146]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id q0UCGPd6001694; Mon, 30 Jan 2012 07:16:26 -0500 Date: Mon, 30 Jan 2012 14:18:53 +0200 From: "Michael S. Tsirkin" To: Kevin Cernekee Cc: Ralf Baechle , Paul Mundt , Arnd Bergmann , "Michael S. Tsirkin" , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [PATCH 2/3] mips: use the the PCI controller's io_map_base Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Mutt-Fcc: =sent User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-archive-position: 32324 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1536 Lines: 46 commit eab90291d35438bcebf7c3dc85be66d0f24e3002 failed to take into account the PCI controller's io_map_base for mapping IO BARs. This also caused a new warning on mips. Fix this, without re-introducing code duplication, by setting NO_GENERIC_PCI_IOPORT_MAP and supplying a mips-specific __pci_ioport_map. Reported-by: Kevin Cernekee Signed-off-by: Michael S. Tsirkin --- arch/mips/Kconfig | 1 + arch/mips/lib/iomap-pci.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c4c1312..5ab6e89 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2356,6 +2356,7 @@ config PCI depends on HW_HAS_PCI select PCI_DOMAINS select GENERIC_PCI_IOMAP + select NO_GENERIC_PCI_IOPORT_MAP help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside diff --git a/arch/mips/lib/iomap-pci.c b/arch/mips/lib/iomap-pci.c index 2635b1a..fd35daa 100644 --- a/arch/mips/lib/iomap-pci.c +++ b/arch/mips/lib/iomap-pci.c @@ -10,8 +10,8 @@ #include #include -static void __iomem *ioport_map_pci(struct pci_dev *dev, - unsigned long port, unsigned int nr) +void __iomem *__pci_ioport_map(struct pci_dev *dev, + unsigned long port, unsigned int nr) { struct pci_controller *ctrl = dev->bus->sysdata; unsigned long base = ctrl->io_map_base; -- 1.7.8.2.325.g247f9 From mst@redhat.com Mon Jan 30 13:16:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 13:17:36 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:27958 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903685Ab2A3MQu (ORCPT ); Mon, 30 Jan 2012 13:16:50 +0100 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0UCGjJ8032637 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 30 Jan 2012 07:16:45 -0500 Received: from redhat.com (vpn-203-146.tlv.redhat.com [10.35.203.146]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id q0UCGbiT001738; Mon, 30 Jan 2012 07:16:38 -0500 Date: Mon, 30 Jan 2012 14:19:05 +0200 From: "Michael S. Tsirkin" To: Kevin Cernekee Cc: Ralf Baechle , Paul Mundt , Arnd Bergmann , "Michael S. Tsirkin" , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [PATCH 3/3] sh: use the the PCI channels's io_map_base Message-ID: <60def7835613710ecae4878ae5742c45b05791df.1327877053.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Mutt-Fcc: =sent User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-archive-position: 32325 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1507 Lines: 45 commit 43db595e8b5d78ce5ad2feab719814a76e3ad2e5 failed to take into account the PCI channels's io_map_base for mapping IO BARs. This also caused a new warning on sh. Fix this, without re-introducing code duplication, by setting NO_GENERIC_PCI_IOPORT_MAP and supplying a sh-specific __pci_ioport_map. Reported-by: Kevin Cernekee Signed-off-by: Michael S. Tsirkin --- arch/sh/Kconfig | 1 + arch/sh/drivers/pci/pci.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 3c8db65..713fb58 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -859,6 +859,7 @@ config PCI depends on SYS_SUPPORTS_PCI select PCI_DOMAINS select GENERIC_PCI_IOMAP + select NO_GENERIC_PCI_IOPORT_MAP help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 8f18dd0..1e7b0e2 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -356,8 +356,8 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, #ifndef CONFIG_GENERIC_IOMAP -static void __iomem *ioport_map_pci(struct pci_dev *dev, - unsigned long port, unsigned int nr) +void __iomem *__pci_ioport_map(struct pci_dev *dev, + unsigned long port, unsigned int nr) { struct pci_channel *chan = dev->sysdata; -- 1.7.8.2.325.g247f9 From mcdonald.shane@gmail.com Mon Jan 30 15:19:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 15:19:42 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:57024 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903688Ab2A3OTi (ORCPT ); Mon, 30 Jan 2012 15:19:38 +0100 Received: by iafj26 with SMTP id j26so6481266iaf.36 for ; Mon, 30 Jan 2012 06:19:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=glOgYlptzA46iGk28AjtcKAojoMSeqrZIp1Tgre1SME=; b=t07NKW6fciECKqtzJo5AvqQZFqqO4zDdFjB1uDbaIe00fOOuqwFJTvYGbAYFg/0BIU JgyrL+aC+MIJ7xrGFMfgVACLVt/gQOuIzXEqj44OY+m1Hh84o1fv4joGpRSDp2tB24qK 9fjGb5EIKoncDZ4iC3xP2vilKCjqhFZehF/6Y= MIME-Version: 1.0 Received: by 10.42.168.6 with SMTP id u6mr11369008icy.9.1327933171756; Mon, 30 Jan 2012 06:19:31 -0800 (PST) Received: by 10.231.54.4 with HTTP; Mon, 30 Jan 2012 06:19:31 -0800 (PST) In-Reply-To: References: Date: Mon, 30 Jan 2012 08:19:31 -0600 Message-ID: Subject: Re: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP From: Shane McDonald To: "Michael S. Tsirkin" Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Arnd Bergmann , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 32326 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 435 Lines: 15 Just a minor nit on the comment: On Mon, Jan 30, 2012 at 6:18 AM, Michael S. Tsirkin wrote: > Some architectures need to override the way > IO port mapping is does not PCI devices. Should this line read "IO port mapping is done on PCI devices."? > Supply a generic function that calls > ioport_map, and make it possible for architectures > to override. > > Signed-off-by: Michael S. Tsirkin Shane From mst@redhat.com Mon Jan 30 15:23:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 15:23:53 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:6372 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903686Ab2A3OXs (ORCPT ); Mon, 30 Jan 2012 15:23:48 +0100 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0UENgM6001763 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 30 Jan 2012 09:23:42 -0500 Received: from redhat.com (vpn-203-146.tlv.redhat.com [10.35.203.146]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id q0UENTK3007613; Mon, 30 Jan 2012 09:23:31 -0500 Date: Mon, 30 Jan 2012 16:25:57 +0200 From: "Michael S. Tsirkin" To: Shane McDonald Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Arnd Bergmann , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP Message-ID: <20120130142557.GA7382@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-archive-position: 32327 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 572 Lines: 18 On Mon, Jan 30, 2012 at 08:19:31AM -0600, Shane McDonald wrote: > Just a minor nit on the comment: > > On Mon, Jan 30, 2012 at 6:18 AM, Michael S. Tsirkin wrote: > > Some architectures need to override the way > > IO port mapping is does not PCI devices. > > Should this line read "IO port mapping is done on PCI devices."? Right, good catch. I'll fix this up in git. > > Supply a generic function that calls > > ioport_map, and make it possible for architectures > > to override. > > > > Signed-off-by: Michael S. Tsirkin > > Shane From arnd@arndb.de Mon Jan 30 16:52:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 16:52:25 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.17.8]:53606 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903693Ab2A3PwV (ORCPT ); Mon, 30 Jan 2012 16:52:21 +0100 Received: from klappe2.localnet (deibp9eh1--blueice3n2.emea.ibm.com [195.212.29.180]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0M5V4W-1SpCCk2a1Q-00xctF; Mon, 30 Jan 2012 16:51:51 +0100 From: Arnd Bergmann To: "Michael S. Tsirkin" Subject: Re: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP Date: Mon, 30 Jan 2012 15:51:46 +0000 User-Agent: KMail/1.12.2 (Linux/3.3.0-rc1; KDE/4.3.2; x86_64; ; ) Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org References: In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201201301551.46907.arnd@arndb.de> X-Provags-ID: V02:K0:cJ6K0n3+KbPZf09E6BUK0YrxBfCnYSoBrcL2kOnh9ta Z2P8/Z+X+GU6rR/g+/zM7CghI7mfTqJ7BU91kWvD/nKk/OWiGt MQk16FklkEyy2egrM0kal8kGhTf2l5wT1XklJJU7McXda5PJCf gbQ0dHXaJKrWSTx2V4LHMDKWcD2or2aCU9BzGo1KTUzw7TC4iN JHMgF3K13CTMsi7QcC+C7+qNx48L0RG1vPGeSATdC09TV2YSnz ZddW6qFv00oHjwZBiFX7UsZQJKvcyW6YqXQwpgItPUUdWd/vj8 ickYhzDOo3wEKax5WKEC94umngbigX3YgvOv3yEzs5eeJBcj42 ofglebNMSiL5kKKPW7y8= X-archive-position: 32328 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arnd@arndb.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2089 Lines: 56 On Monday 30 January 2012, Michael S. Tsirkin wrote: > --- a/include/asm-generic/pci_iomap.h > +++ b/include/asm-generic/pci_iomap.h > @@ -15,6 +15,11 @@ struct pci_dev; > #ifdef CONFIG_PCI > /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ > extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); > +/* Create a virtual mapping cookie for a port on a given PCI device. > + * Do not call this directly, it exists to make it easier for architectures > + * to override. */ > +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, > + unsigned int nr); > #else > static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) > { > index 4b0fdc2..1dfda29 100644 > --- a/lib/pci_iomap.c > +++ b/lib/pci_iomap.c > @@ -9,6 +9,16 @@ > #include > > #ifdef CONFIG_PCI > +#ifndef CONFIG_NO_GENERIC_PCI_IOPORT_MAP > +/* Architectures can override ioport mapping while > + * still using the rest of the generic infrastructure. */ > +void __iomem *__pci_ioport_map(struct pci_dev *dev, > + unsigned long port, > + unsigned int nr) > +{ > + return ioport_map(port, nr); > +} > +#endif > /** > * pci_iomap - create a virtual mapping cookie for a PCI BAR > * @dev: PCI device that owns the BAR This looks correct, but it would be nicer to express this with an inline function and keeping the new #ifdef to the header file, like +/* + * Create a virtual mapping cookie for a port on a given PCI device. + * Do not call this directly, it exists to make it easier for architectures + * to override. + */ +#ifdef CONFIG_NO_GENERIC_PCI_IOPORT_MAP +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, + unsigned int nr); +#else +static inline void __iomem *__pci_ioport_map(struct pci_dev *dev, + unsigned long port, unsigned int nr) +{ + return ioport_map(port, nr); +} +#endif Arnd From arnd@arndb.de Mon Jan 30 17:10:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 17:10:40 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.17.8]:53314 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903692Ab2A3QKa (ORCPT ); Mon, 30 Jan 2012 17:10:30 +0100 Received: from klappe2.localnet (deibp9eh1--blueice3n2.emea.ibm.com [195.212.29.180]) by mrelayeu.kundenserver.de (node=mrbap1) with ESMTP (Nemesis) id 0MCfaM-1RiaPc3YuY-008or0; Mon, 30 Jan 2012 17:09:59 +0100 From: Arnd Bergmann To: "Michael S. Tsirkin" Subject: Re: [PATCH 0/3] arch: fix ioport mapping on mips,sh Date: Mon, 30 Jan 2012 16:09:55 +0000 User-Agent: KMail/1.12.2 (Linux/3.3.0-rc1; KDE/4.3.2; x86_64; ; ) Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org References: In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201201301609.56105.arnd@arndb.de> X-Provags-ID: V02:K0:YRmjaTYJpZu6S8WxSZdsxdgrZ4yBP5TfISB8Z6OHH/Z CO+Ztb/1clhmgzcjEejOSB8X08T+EYcfPe2yyWQYRhwYVc5CDl JQj3RbhTCyCU3OOY/EWMH9w9rxOgaP81SVJQWKxCpJzZU9hoO/ od6lhFDtsstc9ZF9Fy1xxo0E9vXsQHiS21D//bqkfadjYpAz00 MT7bH/MtHT8FyGPv9lWvfn/VugcY2zTm1HG7NWGSGrjJoPL21G 0fEtc5l2MV72qevHUPa73HEpXWiqN6wq88WIunZImUhr2hQNbH K/nMw9WrRcpjRa3lJKProgmUFgqscMRrm1iLU7KrH3xjyPLNLB Y8bU3210GHolkMOpzDpU= X-archive-position: 32329 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arnd@arndb.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1881 Lines: 43 On Monday 30 January 2012, Michael S. Tsirkin wrote: > Kevin Cernekee reported that recent cleanup > that replaced pci_iomap with a generic function > failed to take into account the differences > in io port handling on mips and sh architectures. > > Rather than revert the changes reintroducing the > code duplication, this patchset fixes this > by adding ability for architectures to override > ioport mapping for pci devices. > > I put this in my tree that feeds into linux-next > and intend to ask Linus to pull this fix if this > doesn't cause any issues and there are no objections. > > The patches were tested on x86 and compiled on mips and sh. > Would appreciate reviews/acks/testing reports. Looks good to me, except for the one detail I've commented on in the third patch. Acked-by: Arnd Bergmann I do wonder if the sh and mips implementations are robust enough however (independent of your work): It seems that an ioport number is treated differently in pci_iomap than it is using ioport_map and inb/outb, the assumption being that the port number is a local index per PCI domain. This would mean that any port access other than pci_iomap would only work on the primary PCI domain. There are two IMHO better solutions that I've seen on other architectures: 1. create a larger (e.g. 1MB) io port mapping range in virtual memory that is split into 64kb per domain, and use the domain number to find the per domain range when setting the resources. Port numbers will be larger than 65535 this way, but PCI will ignore the upper address bits for any access so it works fine. 2. split the 64kb io port range into subsections per domain (on page granularity, e.g. 2 domains with 32kb or at most 16 domains with 4kb) and map them virtually contiguous, then reassign all io port resources so that only the correct region for each domain is used. Arnd From mst@redhat.com Mon Jan 30 17:16:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 17:16:18 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:39459 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903694Ab2A3QQL (ORCPT ); Mon, 30 Jan 2012 17:16:11 +0100 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0UGG2oh012894 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 30 Jan 2012 11:16:02 -0500 Received: from redhat.com (vpn-203-146.tlv.redhat.com [10.35.203.146]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id q0UGFplZ016452; Mon, 30 Jan 2012 11:15:52 -0500 Date: Mon, 30 Jan 2012 18:18:19 +0200 From: "Michael S. Tsirkin" To: Arnd Bergmann Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP Message-ID: <20120130161818.GA9345@redhat.com> References: <201201301551.46907.arnd@arndb.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201201301551.46907.arnd@arndb.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-archive-position: 32330 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2478 Lines: 67 On Mon, Jan 30, 2012 at 03:51:46PM +0000, Arnd Bergmann wrote: > On Monday 30 January 2012, Michael S. Tsirkin wrote: > > --- a/include/asm-generic/pci_iomap.h > > +++ b/include/asm-generic/pci_iomap.h > > @@ -15,6 +15,11 @@ struct pci_dev; > > #ifdef CONFIG_PCI > > /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ > > extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); > > +/* Create a virtual mapping cookie for a port on a given PCI device. > > + * Do not call this directly, it exists to make it easier for architectures > > + * to override. */ > > +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, > > + unsigned int nr); > > #else > > static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) > > { > > index 4b0fdc2..1dfda29 100644 > > --- a/lib/pci_iomap.c > > +++ b/lib/pci_iomap.c > > @@ -9,6 +9,16 @@ > > #include > > > > #ifdef CONFIG_PCI > > +#ifndef CONFIG_NO_GENERIC_PCI_IOPORT_MAP > > +/* Architectures can override ioport mapping while > > + * still using the rest of the generic infrastructure. */ > > +void __iomem *__pci_ioport_map(struct pci_dev *dev, > > + unsigned long port, > > + unsigned int nr) > > +{ > > + return ioport_map(port, nr); > > +} > > +#endif > > /** > > * pci_iomap - create a virtual mapping cookie for a PCI BAR > > * @dev: PCI device that owns the BAR > > This looks correct, but it would be nicer to express this with an inline > function and keeping the new #ifdef to the header file, like > > +/* > + * Create a virtual mapping cookie for a port on a given PCI device. > + * Do not call this directly, it exists to make it easier for architectures > + * to override. > + */ > +#ifdef CONFIG_NO_GENERIC_PCI_IOPORT_MAP > +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, > + unsigned int nr); > +#else > +static inline void __iomem *__pci_ioport_map(struct pci_dev *dev, > + unsigned long port, unsigned int nr) > +{ > + return ioport_map(port, nr); > +} > +#endif > > Arnd It would be nicer in that it would make the kernel a bit smaller for generic architectures but this would need to go into a separate header: it depends on io.h and io.h depends on pci_iomap.h. Worth it? -- MST From sshtylyov@mvista.com Mon Jan 30 17:49:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 17:49:56 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:55635 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903700Ab2A3Qtu (ORCPT ); Mon, 30 Jan 2012 17:49:50 +0100 Received: by bke5 with SMTP id 5so4929434bke.36 for ; Mon, 30 Jan 2012 08:49:44 -0800 (PST) Received: by 10.204.10.80 with SMTP id o16mr6021463bko.50.1327942184418; Mon, 30 Jan 2012 08:49:44 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id ci12sm38728634bkb.13.2012.01.30.08.49.41 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Jan 2012 08:49:42 -0800 (PST) Message-ID: <4F26D815.3040105@mvista.com> Date: Mon, 30 Jan 2012 20:49:09 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:6.0) Gecko/20110812 Thunderbird/6.0 MIME-Version: 1.0 To: "Michael S. Tsirkin" CC: Kevin Cernekee , Ralf Baechle , Paul Mundt , Arnd Bergmann , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 2/3] mips: use the the PCI controller's io_map_base References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32331 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 548 Lines: 20 Hello. On 01/30/2012 03:18 PM, Michael S. Tsirkin wrote: > commit eab90291d35438bcebf7c3dc85be66d0f24e3002 Please add that commit's summary in parens. > failed to take into account the PCI controller's > io_map_base for mapping IO BARs. > This also caused a new warning on mips. > Fix this, without re-introducing code duplication, > by setting NO_GENERIC_PCI_IOPORT_MAP > and supplying a mips-specific __pci_ioport_map. > Reported-by: Kevin Cernekee > Signed-off-by: Michael S. Tsirkin WBR, Sergei From sshtylyov@mvista.com Mon Jan 30 17:51:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 17:51:29 +0100 (CET) Received: from mail-bk0-f49.google.com ([209.85.214.49]:50816 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903702Ab2A3QvY (ORCPT ); Mon, 30 Jan 2012 17:51:24 +0100 Received: by bke5 with SMTP id 5so4931558bke.36 for ; Mon, 30 Jan 2012 08:51:19 -0800 (PST) Received: by 10.204.153.199 with SMTP id l7mr9214159bkw.88.1327942278965; Mon, 30 Jan 2012 08:51:18 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru. [213.79.90.226]) by mx.google.com with ESMTPS id ez5sm38722436bkc.15.2012.01.30.08.51.17 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Jan 2012 08:51:18 -0800 (PST) Message-ID: <4F26D875.7050403@mvista.com> Date: Mon, 30 Jan 2012 20:50:45 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (X11; Linux i686; rv:6.0) Gecko/20110812 Thunderbird/6.0 MIME-Version: 1.0 To: "Michael S. Tsirkin" CC: Kevin Cernekee , Ralf Baechle , Paul Mundt , Arnd Bergmann , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 3/3] sh: use the the PCI channels's io_map_base References: <60def7835613710ecae4878ae5742c45b05791df.1327877053.git.mst@redhat.com> In-Reply-To: <60def7835613710ecae4878ae5742c45b05791df.1327877053.git.mst@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32332 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 541 Lines: 21 Hello. On 01/30/2012 03:19 PM, Michael S. Tsirkin wrote: > commit 43db595e8b5d78ce5ad2feab719814a76e3ad2e5 Please add that commit's summary in parens. > failed to take into account the PCI channels's > io_map_base for mapping IO BARs. > This also caused a new warning on sh. > Fix this, without re-introducing code duplication, > by setting NO_GENERIC_PCI_IOPORT_MAP > and supplying a sh-specific __pci_ioport_map. > Reported-by: Kevin Cernekee > Signed-off-by: Michael S. Tsirkin WBR, Sergei From ddaney.cavm@gmail.com Mon Jan 30 18:03:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 18:03:22 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:47317 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903698Ab2A3RDN (ORCPT ); Mon, 30 Jan 2012 18:03:13 +0100 Received: by yhjj72 with SMTP id j72so1892323yhj.36 for ; Mon, 30 Jan 2012 09:03:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=0Fz3HIz3jZEZlUuClcwvxGbnLR+n2pq8L4fFjgLwGf0=; b=qGmZ7W58SFl0re+FZAMdtk1rfcJfXtOh199LNO/Ozbin2Z4PFNh24tgmRaCHzCihTb 9FYmngUqdL38fgE6EFBkNyQnSfyX8CPw01MF0zkXo0QA1yyPdaBVZtdcW3QlyzQCqj/k KN5ImrwUVZSa1o97nfXmlgL30QXneiEIANJdE= Received: by 10.236.80.39 with SMTP id j27mr27527409yhe.92.1327942987444; Mon, 30 Jan 2012 09:03:07 -0800 (PST) Received: from dd1.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id i12sm47770903anm.6.2012.01.30.09.03.05 (version=SSLv3 cipher=OTHER); Mon, 30 Jan 2012 09:03:06 -0800 (PST) Message-ID: <4F26CD48.3040809@gmail.com> Date: Mon, 30 Jan 2012 09:03:04 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , David Daney , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: Fix duplicate instances of ARCH_SPARSEMEM_ENABLE References: <0736d2becb10905c35eec74f04c63970@localhost> In-Reply-To: <0736d2becb10905c35eec74f04c63970@localhost> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 32333 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1532 Lines: 42 On 01/28/2012 03:07 PM, Kevin Cernekee wrote: > "config ARCH_SPARSEMEM_ENABLE" exists in both arch/mips/Kconfig and > arch/mips/cavium-octeon/Kconfig, but the dependencies are not the same. > This results in warnings when a non-Cavium platform tries to select > ARCH_SPARSEMEM_ENABLE: > > $ make lemote2f_defconfig ARCH=mips > warning: (LEMOTE_FULOONG2E&& LEMOTE_MACH2F) selects ARCH_SPARSEMEM_ENABLE which has unmet direct dependencies (CPU_CAVIUM_OCTEON) > warning: (LEMOTE_FULOONG2E&& LEMOTE_MACH2F) selects ARCH_SPARSEMEM_ENABLE which has unmet direct dependencies (CPU_CAVIUM_OCTEON) > # > # configuration written to .config > # > > Proposed workaround is to use a Cavium-specific config option which > "select"s the desired options. > > Signed-off-by: Kevin Cernekee > --- > arch/mips/cavium-octeon/Kconfig | 3 ++- > 1 files changed, 2 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig > index f9e275a..eda8266 100644 > --- a/arch/mips/cavium-octeon/Kconfig > +++ b/arch/mips/cavium-octeon/Kconfig > @@ -82,8 +82,9 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY > help > Lock the kernel's implementation of memcpy() into L2. > > -config ARCH_SPARSEMEM_ENABLE > +config CAVIUM_OCTEON_SPARSEMEM_ENABLE > def_bool y > + select ARCH_SPARSEMEM_ENABLE > select SPARSEMEM_STATIC > > config IOMMU_HELPER NAK! A cleaner patch for this was already done here: http://patchwork.linux-mips.org/patch/3285/ From cernekee@gmail.com Mon Jan 30 19:38:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 19:38:15 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:61952 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903700Ab2A3SiJ (ORCPT ); Mon, 30 Jan 2012 19:38:09 +0100 Received: by dadz9 with SMTP id z9so3407117dad.36 for ; Mon, 30 Jan 2012 10:38:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=C4WGZsbwNYQIjS6j00QgwzT6wzUh/YjytanaiGZQXhk=; b=q4jyczTmd+DUVx4EJPSVNz4E//Efc+MPQIKaa1LHRksYsPUpsYjcAEGN/pDM+jGKg5 pgtNtXmYJkT8NKhEEL8maJB4UDXucYqzqEPCPGoebHK5Feq5WDFTc0pzDc+T6hr53lsa 7xPxmXDATbBWftHlKL5On4tedCCIYW3x048bw= MIME-Version: 1.0 Received: by 10.68.130.201 with SMTP id og9mr43325418pbb.61.1327948682951; Mon, 30 Jan 2012 10:38:02 -0800 (PST) Received: by 10.68.234.166 with HTTP; Mon, 30 Jan 2012 10:38:02 -0800 (PST) In-Reply-To: <4F26CD48.3040809@gmail.com> References: <0736d2becb10905c35eec74f04c63970@localhost> <4F26CD48.3040809@gmail.com> Date: Mon, 30 Jan 2012 10:38:02 -0800 Message-ID: Subject: Re: [PATCH] MIPS: Fix duplicate instances of ARCH_SPARSEMEM_ENABLE From: Kevin Cernekee To: David Daney , viric@viric.name Cc: Ralf Baechle , David Daney , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 32334 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 390 Lines: 14 On Mon, Jan 30, 2012 at 9:03 AM, David Daney wrote: > NAK! > > A cleaner patch for this was already done here: > > http://patchwork.linux-mips.org/patch/3285/ This patch fixed the problem for me, but it doesn't apply cleanly to the current head of tree since the context (CAVIUM_OCTEON_HELPER) has changed. Lluis, do you want to go ahead and submit a V2? Thanks. From arnd@arndb.de Mon Jan 30 21:05:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jan 2012 21:05:05 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.126.187]:56671 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903703Ab2A3UFA (ORCPT ); Mon, 30 Jan 2012 21:05:00 +0100 Received: from klappe2.localnet (HSI-KBW-46-223-44-216.hsi.kabel-badenwuerttemberg.de [46.223.44.216]) by mrelayeu.kundenserver.de (node=mreu0) with ESMTP (Nemesis) id 0MJYS7-1Rtt8q2dER-002uIK; Mon, 30 Jan 2012 21:04:36 +0100 From: Arnd Bergmann To: "Michael S. Tsirkin" Subject: Re: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP Date: Mon, 30 Jan 2012 20:04:32 +0000 User-Agent: KMail/1.12.2 (Linux/3.3.0-rc1; KDE/4.3.2; x86_64; ; ) Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org References: <201201301551.46907.arnd@arndb.de> <20120130161818.GA9345@redhat.com> In-Reply-To: <20120130161818.GA9345@redhat.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201201302004.33083.arnd@arndb.de> X-Provags-ID: V02:K0:ZNS912xatw+iD7ZLS287Q+NKxYf+kk+kMcCGVS81KSq wi9DOEBYVVloDKXEFGDv0RhA1yuMgB3Ot0m75Y8aynC/BPnIlQ yrDEqVE8kbqoV+ZbBijJ5vbhJ67xHzebv+Eoen9iODbyQv/Pak hMWqI6Yzt9tTZU/8owt/TQ2bYuD9KgrHJU6G0oXnt5sB/8cKkR rbzJb2EMH7D5Omd9fVVvZo9Uhep7m7Yw6fJvtO+fb9N+0gc41n AtPE5Fg4Y1s9rJYq6dYwaUl9rZOaah/sVWQbCEHxhftG+1D5Bx GIC93MoyUw2RIC3xnUiFwNPQEGRG4YQ8byVanFX+lr66athX3w 2HohRC9RBsKHDtIFneTI= X-archive-position: 32335 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arnd@arndb.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1176 Lines: 35 On Monday 30 January 2012, Michael S. Tsirkin wrote: > > > > +/* > > + * Create a virtual mapping cookie for a port on a given PCI device. > > + * Do not call this directly, it exists to make it easier for architectures > > + * to override. > > + */ > > +#ifdef CONFIG_NO_GENERIC_PCI_IOPORT_MAP > > +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, > > + unsigned int nr); > > +#else > > +static inline void __iomem *__pci_ioport_map(struct pci_dev *dev, > > + unsigned long port, unsigned int nr) > > +{ > > + return ioport_map(port, nr); > > +} > > +#endif > > > > Arnd > > It would be nicer in that it would > make the kernel a bit smaller for generic architectures > but this would need to go into a separate header: > it depends on io.h and io.h depends on pci_iomap.h. Adding extra dependencies is not good here, I agree. Maybe a better solution is to use a macro instead of an inline function then: #define __pci_ioport_map(dev, port, nr) ioport_map(port, nr) In general, macros should be avoided, but I think it's the best tradeoff in this case. Arnd From hauke@hauke-m.de Tue Jan 31 00:04:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 00:04:21 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41764 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903705Ab2A3XEQ (ORCPT ); Tue, 31 Jan 2012 00:04:16 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 19F6F8F68; Tue, 31 Jan 2012 00:04:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id B6F99mUoS62O; Tue, 31 Jan 2012 00:04:12 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 668328F60; Tue, 31 Jan 2012 00:04:12 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 0/7] bcma: add PCIe host controller Date: Tue, 31 Jan 2012 00:03:30 +0100 Message-Id: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32336 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1294 Lines: 32 These patches are adding support for a PCIe Host controller found on some Broadcom SoCs using bcma as the System bus. This was tested with one BCM4716 based device, a Netgear WNDR3400 with a BCM43224 connected through PCIe. These patches are based on wireless-testing. Hauke Mehrtens (7): bcma: add the core unit number bcma: add constants for PCI and use them bcma: export bcma_pcie_read() bcma: make some functions __devinit bcma: add PCIe host controller bcma: add bus num counter bcma: add extra sprom check arch/mips/pci/pci-bcm47xx.c | 49 ++- drivers/bcma/bcma_private.h | 8 +- drivers/bcma/driver_pci.c | 168 ++++----- drivers/bcma/driver_pci_host.c | 578 ++++++++++++++++++++++++++- drivers/bcma/host_pci.c | 4 +- drivers/bcma/main.c | 14 +- drivers/bcma/scan.c | 14 + drivers/bcma/sprom.c | 7 + include/linux/bcma/bcma.h | 2 + include/linux/bcma/bcma_driver_chipcommon.h | 16 + include/linux/bcma/bcma_driver_pci.h | 125 ++++++- include/linux/bcma/bcma_regs.h | 27 ++ 12 files changed, 908 insertions(+), 104 deletions(-) -- 1.7.5.4 From hauke@hauke-m.de Tue Jan 31 00:04:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 00:04:47 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41770 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903706Ab2A3XER (ORCPT ); Tue, 31 Jan 2012 00:04:17 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 6AF288F60; Tue, 31 Jan 2012 00:04:17 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XgPAo1uRXYps; Tue, 31 Jan 2012 00:04:12 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 9D42B8F61; Tue, 31 Jan 2012 00:04:12 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 1/7] bcma: add the core unit number Date: Tue, 31 Jan 2012 00:03:31 +0100 Message-Id: <1327964617-7910-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> References: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32337 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1898 Lines: 63 Some SoCs have two pcie or gmac cores and we need to know the number of the specific core on the bus. This is the case for the BCM4706. Signed-off-by: Hauke Mehrtens --- drivers/bcma/scan.c | 14 ++++++++++++++ include/linux/bcma/bcma.h | 1 + 2 files changed, 15 insertions(+), 0 deletions(-) diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c index cad9948..e513aa8 100644 --- a/drivers/bcma/scan.c +++ b/drivers/bcma/scan.c @@ -212,6 +212,17 @@ static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus, return NULL; } +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid) +{ + struct bcma_device *core; + + list_for_each_entry_reverse(core, &bus->cores, list) { + if (core->id.id == coreid) + return core; + } + return NULL; +} + static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, struct bcma_device_id *match, int core_num, struct bcma_device *core) @@ -392,6 +403,7 @@ int bcma_bus_scan(struct bcma_bus *bus) bcma_scan_switch_core(bus, erombase); while (eromptr < eromend) { + struct bcma_device *other_core; struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL); if (!core) return -ENOMEM; @@ -411,6 +423,8 @@ int bcma_bus_scan(struct bcma_bus *bus) core->core_index = core_num++; bus->nr_cores++; + other_core = bcma_find_core_reverse(bus, core->id.id); + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1; pr_info("Core %d found: %s " "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 83c209f..024a6e2 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -136,6 +136,7 @@ struct bcma_device { bool dev_registered; u8 core_index; + u8 core_unit; u32 addr; u32 wrap; -- 1.7.5.4 From hauke@hauke-m.de Tue Jan 31 00:04:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 00:05:12 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41784 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904011Ab2A3XEW (ORCPT ); Tue, 31 Jan 2012 00:04:22 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 1A6BA8F61; Tue, 31 Jan 2012 00:04:22 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CyV6cadnPsEP; Tue, 31 Jan 2012 00:04:17 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 0A19E8F63; Tue, 31 Jan 2012 00:04:13 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 3/7] bcma: export bcma_pcie_read() Date: Tue, 31 Jan 2012 00:03:33 +0100 Message-Id: <1327964617-7910-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> References: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32338 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1266 Lines: 38 This will be needed by the host controller. Signed-off-by: Hauke Mehrtens --- drivers/bcma/bcma_private.h | 3 +++ drivers/bcma/driver_pci.c | 2 +- 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h index 0def898..6109da5 100644 --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h @@ -48,6 +48,9 @@ extern int __init bcma_host_pci_init(void); extern void __exit bcma_host_pci_exit(void); #endif /* CONFIG_BCMA_HOST_PCI */ +/* driver_pci.c */ +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c index 970a38e..20ceebd 100644 --- a/drivers/bcma/driver_pci.c +++ b/drivers/bcma/driver_pci.c @@ -17,7 +17,7 @@ * R/W ops. **************************************************/ -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) { pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); -- 1.7.5.4 From hauke@hauke-m.de Tue Jan 31 00:04:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 00:05:36 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41794 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904012Ab2A3XEY (ORCPT ); Tue, 31 Jan 2012 00:04:24 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 167998F68; Tue, 31 Jan 2012 00:04:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2xeoL3M-kylf; Tue, 31 Jan 2012 00:04:16 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id CD4538F62; Tue, 31 Jan 2012 00:04:12 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 2/7] bcma: add constants for PCI and use them Date: Tue, 31 Jan 2012 00:03:32 +0100 Message-Id: <1327964617-7910-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> References: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32339 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14292 Lines: 337 There are many magic numbers used in the PCIe code. Replace them with some constants from the Broadcom SDK and also use them in the pcie host controller. Signed-off-by: Hauke Mehrtens --- drivers/bcma/driver_pci.c | 124 +++++++++++++++++++--------------- include/linux/bcma/bcma_driver_pci.h | 85 +++++++++++++++++++++++ 2 files changed, 155 insertions(+), 54 deletions(-) diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c index 4fde625..970a38e 100644 --- a/drivers/bcma/driver_pci.c +++ b/drivers/bcma/driver_pci.c @@ -4,6 +4,7 @@ * * Copyright 2005, Broadcom Corporation * Copyright 2006, 2007, Michael Buesch + * Copyright 2011, 2012, Hauke Mehrtens * * Licensed under the GNU/GPL. See COPYING for details. */ @@ -18,38 +19,39 @@ static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) { - pcicore_write32(pc, 0x130, address); - pcicore_read32(pc, 0x130); - return pcicore_read32(pc, 0x134); + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA); } #if 0 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data) { - pcicore_write32(pc, 0x130, address); - pcicore_read32(pc, 0x130); - pcicore_write32(pc, 0x134, data); + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data); } #endif static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy) { - const u16 mdio_control = 0x128; - const u16 mdio_data = 0x12C; u32 v; int i; - v = (1 << 30); /* Start of Transaction */ - v |= (1 << 28); /* Write Transaction */ - v |= (1 << 17); /* Turnaround */ - v |= (0x1F << 18); + v = BCMA_CORE_PCI_MDIODATA_START; + v |= BCMA_CORE_PCI_MDIODATA_WRITE; + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR << + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); + v |= BCMA_CORE_PCI_MDIODATA_TA; v |= (phy << 4); - pcicore_write32(pc, mdio_data, v); + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); udelay(10); for (i = 0; i < 200; i++) { - v = pcicore_read32(pc, mdio_control); - if (v & 0x100 /* Trans complete */) + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) break; msleep(1); } @@ -57,79 +59,84 @@ static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy) static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address) { - const u16 mdio_control = 0x128; - const u16 mdio_data = 0x12C; int max_retries = 10; u16 ret = 0; u32 v; int i; - v = 0x80; /* Enable Preamble Sequence */ - v |= 0x2; /* MDIO Clock Divisor */ - pcicore_write32(pc, mdio_control, v); + /* enable mdio access to SERDES */ + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); if (pc->core->id.rev >= 10) { max_retries = 200; bcma_pcie_mdio_set_phy(pc, device); + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); + } else { + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); } - v = (1 << 30); /* Start of Transaction */ - v |= (1 << 29); /* Read Transaction */ - v |= (1 << 17); /* Turnaround */ - if (pc->core->id.rev < 10) - v |= (u32)device << 22; - v |= (u32)address << 18; - pcicore_write32(pc, mdio_data, v); + v = BCMA_CORE_PCI_MDIODATA_START; + v |= BCMA_CORE_PCI_MDIODATA_READ; + v |= BCMA_CORE_PCI_MDIODATA_TA; + + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); /* Wait for the device to complete the transaction */ udelay(10); for (i = 0; i < max_retries; i++) { - v = pcicore_read32(pc, mdio_control); - if (v & 0x100 /* Trans complete */) { + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) { udelay(10); - ret = pcicore_read32(pc, mdio_data); + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA); break; } msleep(1); } - pcicore_write32(pc, mdio_control, 0); + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); return ret; } static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device, u8 address, u16 data) { - const u16 mdio_control = 0x128; - const u16 mdio_data = 0x12C; int max_retries = 10; u32 v; int i; - v = 0x80; /* Enable Preamble Sequence */ - v |= 0x2; /* MDIO Clock Divisor */ - pcicore_write32(pc, mdio_control, v); + /* enable mdio access to SERDES */ + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); if (pc->core->id.rev >= 10) { max_retries = 200; bcma_pcie_mdio_set_phy(pc, device); + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); + } else { + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); } - v = (1 << 30); /* Start of Transaction */ - v |= (1 << 28); /* Write Transaction */ - v |= (1 << 17); /* Turnaround */ - if (pc->core->id.rev < 10) - v |= (u32)device << 22; - v |= (u32)address << 18; + v = BCMA_CORE_PCI_MDIODATA_START; + v |= BCMA_CORE_PCI_MDIODATA_WRITE; + v |= BCMA_CORE_PCI_MDIODATA_TA; v |= data; - pcicore_write32(pc, mdio_data, v); + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); /* Wait for the device to complete the transaction */ udelay(10); for (i = 0; i < max_retries; i++) { - v = pcicore_read32(pc, mdio_control); - if (v & 0x100 /* Trans complete */) + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) break; msleep(1); } - pcicore_write32(pc, mdio_control, 0); + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); } /************************************************** @@ -138,20 +145,29 @@ static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device, static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc) { - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; + u32 tmp; + + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG); + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT) + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE | + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY; + else + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE; } static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc) { - const u8 serdes_pll_device = 0x1D; - const u8 serdes_rx_device = 0x1F; u16 tmp; - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, - bcma_pcicore_polarity_workaround(pc)); - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); - if (tmp & 0x4000) - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX, + BCMA_CORE_PCI_SERDES_RX_CTRL, + bcma_pcicore_polarity_workaround(pc)); + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, + BCMA_CORE_PCI_SERDES_PLL_CTRL); + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN) + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, + BCMA_CORE_PCI_SERDES_PLL_CTRL, + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN); } /************************************************** diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h index 3871b66..67ea7be 100644 --- a/include/linux/bcma/bcma_driver_pci.h +++ b/include/linux/bcma/bcma_driver_pci.h @@ -53,6 +53,35 @@ struct pci_dev; #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */ #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */ +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */ +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */ +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */ +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */ +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */ +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */ +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */ +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */ +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */ +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */ +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */ +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */ +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */ +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */ +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */ +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */ +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */ +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */ +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */ +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */ +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */ +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */ #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */ #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */ #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */ @@ -72,6 +101,62 @@ struct pci_dev; #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */ #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */ +/* PCIE protocol PHY diagnostic registers */ +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */ +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */ +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */ +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */ +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */ +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */ +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */ +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ + +/* PCIE protocol DLLP diagnostic registers */ +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */ +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */ +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */ +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16) +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */ +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */ +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */ +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */ +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ + +/* SERDES RX registers */ +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */ +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */ +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */ +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */ + +/* SERDES PLL registers */ +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */ +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ + /* PCIcore specific boardflags */ #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ -- 1.7.5.4 From hauke@hauke-m.de Tue Jan 31 00:04:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 00:06:02 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41800 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904013Ab2A3XE0 (ORCPT ); Tue, 31 Jan 2012 00:04:26 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id DDDCF8F62; Tue, 31 Jan 2012 00:04:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BrDBiuppXC8u; Tue, 31 Jan 2012 00:04:22 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 3A5A98F64; Tue, 31 Jan 2012 00:04:13 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 4/7] bcma: make some functions __devinit Date: Tue, 31 Jan 2012 00:03:34 +0100 Message-Id: <1327964617-7910-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> References: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32340 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4307 Lines: 121 bcma_core_pci_hostmode_init() has to be in __devinit as it will call a function in that section and so all functions calling it also have to be in __devinit. Signed-off-by: Hauke Mehrtens --- drivers/bcma/bcma_private.h | 4 ++-- drivers/bcma/driver_pci.c | 6 +++--- drivers/bcma/driver_pci_host.c | 2 +- drivers/bcma/host_pci.c | 4 ++-- drivers/bcma/main.c | 2 +- include/linux/bcma/bcma_driver_pci.h | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h index 6109da5..63c5242 100644 --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h @@ -13,7 +13,7 @@ struct bcma_bus; /* main.c */ -int bcma_bus_register(struct bcma_bus *bus); +int __devinit bcma_bus_register(struct bcma_bus *bus); void bcma_bus_unregister(struct bcma_bus *bus); int __init bcma_bus_early_register(struct bcma_bus *bus, struct bcma_device *core_cc, @@ -52,7 +52,7 @@ extern void __exit bcma_host_pci_exit(void); u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ #endif diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c index 20ceebd..161c8ba 100644 --- a/drivers/bcma/driver_pci.c +++ b/drivers/bcma/driver_pci.c @@ -174,12 +174,12 @@ static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc) * Init. **************************************************/ -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) { bcma_pcicore_serdes_workaround(pc); } -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) +static bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) { struct bcma_bus *bus = pc->core->bus; u16 chipid_top; @@ -204,7 +204,7 @@ static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) return true; } -void bcma_core_pci_init(struct bcma_drv_pci *pc) +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) { if (pc->setup_done) return; diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c index eb332b7..99e040b 100644 --- a/drivers/bcma/driver_pci_host.c +++ b/drivers/bcma/driver_pci_host.c @@ -8,7 +8,7 @@ #include "bcma_private.h" #include -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) { pr_err("No support for PCI core in hostmode yet\n"); } diff --git a/drivers/bcma/host_pci.c b/drivers/bcma/host_pci.c index f59244e..e3928d6 100644 --- a/drivers/bcma/host_pci.c +++ b/drivers/bcma/host_pci.c @@ -154,8 +154,8 @@ const struct bcma_host_ops bcma_host_pci_ops = { .awrite32 = bcma_host_pci_awrite32, }; -static int bcma_host_pci_probe(struct pci_dev *dev, - const struct pci_device_id *id) +static int __devinit bcma_host_pci_probe(struct pci_dev *dev, + const struct pci_device_id *id) { struct bcma_bus *bus; int err = -ENOMEM; diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c index febbc0a..3363036 100644 --- a/drivers/bcma/main.c +++ b/drivers/bcma/main.c @@ -132,7 +132,7 @@ static void bcma_unregister_cores(struct bcma_bus *bus) } } -int bcma_bus_register(struct bcma_bus *bus) +int __devinit bcma_bus_register(struct bcma_bus *bus) { int err; struct bcma_device *core; diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h index 67ea7be..679d4ca 100644 --- a/include/linux/bcma/bcma_driver_pci.h +++ b/include/linux/bcma/bcma_driver_pci.h @@ -169,7 +169,7 @@ struct bcma_drv_pci { #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset) #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val) -extern void bcma_core_pci_init(struct bcma_drv_pci *pc); +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc); extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, bool enable); -- 1.7.5.4 From hauke@hauke-m.de Tue Jan 31 00:04:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 00:06:27 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41811 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904014Ab2A3XE3 (ORCPT ); Tue, 31 Jan 2012 00:04:29 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 391AC8F6A; Tue, 31 Jan 2012 00:04:29 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Gx45fOc5l+17; Tue, 31 Jan 2012 00:04:26 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 92E4E8F66; Tue, 31 Jan 2012 00:04:13 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 6/7] bcma: add bus num counter Date: Tue, 31 Jan 2012 00:03:36 +0100 Message-Id: <1327964617-7910-7-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> References: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32341 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1890 Lines: 61 If we have two bcma buses on one computer the second will not work without this patch. Now each bus gets an own number. Signed-off-by: Hauke Mehrtens --- drivers/bcma/main.c | 12 +++++++++++- include/linux/bcma/bcma.h | 1 + 2 files changed, 12 insertions(+), 1 deletions(-) diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c index 3363036..bcd1c01 100644 --- a/drivers/bcma/main.c +++ b/drivers/bcma/main.c @@ -13,6 +13,12 @@ MODULE_DESCRIPTION("Broadcom's specific AMBA driver"); MODULE_LICENSE("GPL"); +/* contains the number the next bus should get. */ +static unsigned int bcma_bus_next_num = 0; + +/* bcma_buses_mutex locks the bcma_bus_next_num */ +static DEFINE_MUTEX(bcma_buses_mutex); + static int bcma_bus_match(struct device *dev, struct device_driver *drv); static int bcma_device_probe(struct device *dev); static int bcma_device_remove(struct device *dev); @@ -93,7 +99,7 @@ static int bcma_register_cores(struct bcma_bus *bus) core->dev.release = bcma_release_core_dev; core->dev.bus = &bcma_bus_type; - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id); + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id); switch (bus->hosttype) { case BCMA_HOSTTYPE_PCI: @@ -137,6 +143,10 @@ int __devinit bcma_bus_register(struct bcma_bus *bus) int err; struct bcma_device *core; + mutex_lock(&bcma_buses_mutex); + bus->num = bcma_bus_next_num++; + mutex_unlock(&bcma_buses_mutex); + /* Scan for devices (cores) */ err = bcma_bus_scan(bus); if (err) { diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 024a6e2..b9f65fb 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -196,6 +196,7 @@ struct bcma_bus { struct list_head cores; u8 nr_cores; u8 init_done:1; + u8 num; struct bcma_drv_cc drv_cc; struct bcma_drv_pci drv_pci; -- 1.7.5.4 From hauke@hauke-m.de Tue Jan 31 00:04:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 00:06:56 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41819 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904015Ab2A3XEd (ORCPT ); Tue, 31 Jan 2012 00:04:33 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 5B45F8F62; Tue, 31 Jan 2012 00:04:33 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tUZdfU0MeMpi; Tue, 31 Jan 2012 00:04:24 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id 69E8F8F65; Tue, 31 Jan 2012 00:04:13 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 5/7] bcma: add PCIe host controller Date: Tue, 31 Jan 2012 00:03:35 +0100 Message-Id: <1327964617-7910-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> References: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32342 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 26072 Lines: 859 Some SoCs have a PCIe host controller to make it possible to attach some other devices to it, like an other Wifi card. This code was tested with an Netgear WNDR3400 (bcm4716 based), but should work with all bcma based SoCs. Signed-off-by: Hauke Mehrtens --- arch/mips/pci/pci-bcm47xx.c | 49 +++- drivers/bcma/bcma_private.h | 1 + drivers/bcma/driver_pci.c | 38 +-- drivers/bcma/driver_pci_host.c | 576 +++++++++++++++++++++++++++++++++- include/linux/bcma/bcma_driver_pci.h | 38 +++ include/linux/bcma/bcma_regs.h | 27 ++ 6 files changed, 690 insertions(+), 39 deletions(-) diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c index 400535a..c682468 100644 --- a/arch/mips/pci/pci-bcm47xx.c +++ b/arch/mips/pci/pci-bcm47xx.c @@ -25,6 +25,7 @@ #include #include #include +#include #include int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) @@ -32,15 +33,12 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return 0; } -int pcibios_plat_dev_init(struct pci_dev *dev) -{ #ifdef CONFIG_BCM47XX_SSB +static int bcm47xx_pcibios_plat_dev_init_ssb(struct pci_dev *dev) +{ int res; u8 slot, pin; - if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB) - return 0; - res = ssb_pcibios_plat_dev_init(dev); if (res < 0) { printk(KERN_ALERT "PCI: Failed to init device %s\n", @@ -60,6 +58,47 @@ int pcibios_plat_dev_init(struct pci_dev *dev) } dev->irq = res; + return 0; +} #endif + +#ifdef CONFIG_BCM47XX_BCMA +static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev) +{ + int res; + + res = bcma_core_pci_plat_dev_init(dev); + if (res < 0) { + printk(KERN_ALERT "PCI: Failed to init device %s\n", + pci_name(dev)); + return res; + } + + res = bcma_core_pci_pcibios_map_irq(dev); + + /* IRQ-0 and IRQ-1 are software interrupts. */ + if (res < 2) { + printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n", + pci_name(dev)); + return res; + } + + dev->irq = res; return 0; } +#endif + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ +#ifdef CONFIG_BCM47XX_SSB + if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB) + return bcm47xx_pcibios_plat_dev_init_ssb(dev); + else +#endif +#ifdef CONFIG_BCM47XX_BCMA + if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) + return bcm47xx_pcibios_plat_dev_init_bcma(dev); + else +#endif + return 0; +} diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h index 63c5242..b81755b 100644 --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h @@ -52,6 +52,7 @@ extern void __exit bcma_host_pci_exit(void); u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c index 161c8ba..82e4898 100644 --- a/drivers/bcma/driver_pci.c +++ b/drivers/bcma/driver_pci.c @@ -2,7 +2,7 @@ * Broadcom specific AMBA * PCI Core * - * Copyright 2005, Broadcom Corporation + * Copyright 2005, 2011, Broadcom Corporation * Copyright 2006, 2007, Michael Buesch * Copyright 2011, 2012, Hauke Mehrtens * @@ -179,47 +179,19 @@ static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) bcma_pcicore_serdes_workaround(pc); } -static bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) -{ - struct bcma_bus *bus = pc->core->bus; - u16 chipid_top; - - chipid_top = (bus->chipinfo.id & 0xFF00); - if (chipid_top != 0x4700 && - chipid_top != 0x5300) - return false; - -#ifdef CONFIG_SSB_DRIVER_PCICORE - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI) - return false; -#endif /* CONFIG_SSB_DRIVER_PCICORE */ - -#if 0 - /* TODO: on BCMA we use address from EROM instead of magic formula */ - u32 tmp; - return !mips_busprobe32(tmp, (bus->mmio + - (pc->core->core_index * BCMA_CORE_SIZE))); -#endif - - return true; -} - void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) { if (pc->setup_done) return; - if (bcma_core_pci_is_in_hostmode(pc)) { #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE + pc->hostmode = bcma_core_pci_is_in_hostmode(pc); + if (pc->hostmode) bcma_core_pci_hostmode_init(pc); -#else - pr_err("Driver compiled without support for hostmode PCI\n"); #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ - } else { - bcma_core_pci_clientmode_init(pc); - } - pc->setup_done = true; + if (!pc->hostmode) + bcma_core_pci_clientmode_init(pc); } int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c index 99e040b..4e20bcf 100644 --- a/drivers/bcma/driver_pci_host.c +++ b/drivers/bcma/driver_pci_host.c @@ -2,13 +2,587 @@ * Broadcom specific AMBA * PCI Core in hostmode * + * Copyright 2005 - 2011, Broadcom Corporation + * Copyright 2006, 2007, Michael Buesch + * Copyright 2011, 2012, Hauke Mehrtens + * * Licensed under the GNU/GPL. See COPYING for details. */ #include "bcma_private.h" +#include #include +#include + +/* Probe a 32bit value on the bus and catch bus exceptions. + * Returns nonzero on a bus exception. + * This is MIPS specific */ +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) + +/* Assume one-hot slot wiring */ +#define BCMA_PCI_SLOT_MAX 16 +#define PCI_CONFIG_SPACE_SIZE 256 + +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) +{ + struct bcma_bus *bus = pc->core->bus; + u16 chipid_top; + u32 tmp; + + chipid_top = (bus->chipinfo.id & 0xFF00); + if (chipid_top != 0x4700 && + chipid_top != 0x5300) + return false; + + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { + pr_info("This PCI core is disabled and not working\n"); + return false; + } + + bcma_core_enable(pc->core, 0); + + return !mips_busprobe32(tmp, pc->core->io_addr); +} + +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address) +{ + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA); +} + +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address, + u32 data) +{ + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data); +} + +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev, + unsigned int func, unsigned int off) +{ + u32 addr = 0; + + /* Issue config commands only when the data link is up (atleast + * one external pcie device is present). + */ + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG) + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP)) + goto out; + + /* Type 0 transaction */ + /* Slide the PCI window to the appropriate slot */ + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); + /* Calculate the address */ + addr = pc->host_controller->host_cfg_addr; + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT); + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT); + addr |= (off & ~3); + +out: + return addr; +} + +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev, + unsigned int func, unsigned int off, + void *buf, int len) +{ + int err = -EINVAL; + u32 addr, val; + void __iomem *mmio = 0; + + WARN_ON(!pc->hostmode); + if (unlikely(len != 1 && len != 2 && len != 4)) + goto out; + if (dev == 0) { + /* we support only two functions on device 0 */ + if (func > 1) + return -EINVAL; + + /* accesses to config registers with offsets >= 256 + * requires indirect access. + */ + if (off >= PCI_CONFIG_SPACE_SIZE) { + addr = (func << 12); + addr |= (off & 0x0FFF); + val = bcma_pcie_read_config(pc, addr); + } else { + addr = BCMA_CORE_PCI_PCICFG0; + addr |= (func << 8); + addr |= (off & 0xfc); + val = pcicore_read32(pc, addr); + } + } else { + addr = bcma_get_cfgspace_addr(pc, dev, func, off); + if (unlikely(!addr)) + goto out; + err = -ENOMEM; + mmio = ioremap_nocache(addr, len); + if (!mmio) + goto out; + + if (mips_busprobe32(val, mmio)) { + val = 0xffffffff; + goto unmap; + } + + val = readl(mmio); + } + val >>= (8 * (off & 3)); + + switch (len) { + case 1: + *((u8 *)buf) = (u8)val; + break; + case 2: + *((u16 *)buf) = (u16)val; + break; + case 4: + *((u32 *)buf) = (u32)val; + break; + } + err = 0; +unmap: + if (mmio) + iounmap(mmio); +out: + return err; +} + +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, + unsigned int func, unsigned int off, + const void *buf, int len) +{ + int err = -EINVAL; + u32 addr = 0, val = 0; + void __iomem *mmio = 0; + u16 chipid = pc->core->bus->chipinfo.id; + + WARN_ON(!pc->hostmode); + if (unlikely(len != 1 && len != 2 && len != 4)) + goto out; + if (dev == 0) { + /* accesses to config registers with offsets >= 256 + * requires indirect access. + */ + if (off < PCI_CONFIG_SPACE_SIZE) { + addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0; + addr |= (func << 8); + addr |= (off & 0xfc); + mmio = ioremap_nocache(addr, len); + if (!mmio) + goto out; + } + } else { + addr = bcma_get_cfgspace_addr(pc, dev, func, off); + if (unlikely(!addr)) + goto out; + err = -ENOMEM; + mmio = ioremap_nocache(addr, len); + if (!mmio) + goto out; + + if (mips_busprobe32(val, mmio)) { + val = 0xffffffff; + goto unmap; + } + } + + switch (len) { + case 1: + val = readl(mmio); + val &= ~(0xFF << (8 * (off & 3))); + val |= *((const u8 *)buf) << (8 * (off & 3)); + break; + case 2: + val = readl(mmio); + val &= ~(0xFFFF << (8 * (off & 3))); + val |= *((const u16 *)buf) << (8 * (off & 3)); + break; + case 4: + val = *((const u32 *)buf); + break; + } + if (dev == 0 && !addr) { + /* accesses to config registers with offsets >= 256 + * requires indirect access. + */ + addr = (func << 12); + addr |= (off & 0x0FFF); + bcma_pcie_write_config(pc, addr, val); + } else { + writel(val, mmio); + + if (chipid == 0x4716 || chipid == 0x4748) + readl(mmio); + } + + err = 0; +unmap: + if (mmio) + iounmap(mmio); +out: + return err; +} + +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus, + unsigned int devfn, + int reg, int size, u32 *val) +{ + unsigned long flags; + int err; + struct bcma_drv_pci *pc; + struct bcma_drv_pci_host *pc_host; + + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); + pc = pc_host->pdev; + + spin_lock_irqsave(&pc_host->cfgspace_lock, flags); + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn), + PCI_FUNC(devfn), reg, val, size); + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); + + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; +} + +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus, + unsigned int devfn, + int reg, int size, u32 val) +{ + unsigned long flags; + int err; + struct bcma_drv_pci *pc; + struct bcma_drv_pci_host *pc_host; + + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); + pc = pc_host->pdev; + + spin_lock_irqsave(&pc_host->cfgspace_lock, flags); + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn), + PCI_FUNC(devfn), reg, &val, size); + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); + + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; +} + +/* return cap_offset if requested capability exists in the PCI config space */ +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc, + unsigned int dev, + unsigned int func, u8 req_cap_id, + unsigned char *buf, u32 *buflen) +{ + u8 cap_id; + u8 cap_ptr = 0; + u32 bufsize; + u8 byte_val; + + /* check for Header type 0 */ + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val, + sizeof(u8)); + if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL) + return cap_ptr; + + /* check if the capability pointer field exists */ + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val, + sizeof(u8)); + if (!(byte_val & PCI_STATUS_CAP_LIST)) + return cap_ptr; + + /* check if the capability pointer is 0x00 */ + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr, + sizeof(u8)); + if (cap_ptr == 0x00) + return cap_ptr; + + /* loop thr'u the capability list and see if the requested capabilty + * exists */ + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8)); + while (cap_id != req_cap_id) { + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr, + sizeof(u8)); + if (cap_ptr == 0x00) + return cap_ptr; + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, + sizeof(u8)); + } + + /* found the caller requested capability */ + if ((buf != NULL) && (buflen != NULL)) { + u8 cap_data; + + bufsize = *buflen; + if (!bufsize) + return cap_ptr; + + *buflen = 0; + + /* copy the cpability data excluding cap ID and next ptr */ + cap_data = cap_ptr + 2; + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE) + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data; + *buflen = bufsize; + while (bufsize--) { + bcma_extpci_read_config(pc, dev, func, cap_data, buf, + sizeof(u8)); + cap_data++; + buf++; + } + } + + return cap_ptr; +} + +/* If the root port is capable of returning Config Request + * Retry Status (CRS) Completion Status to software then + * enable the feature. + */ +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) +{ + u8 cap_ptr, root_ctrl, root_cap, dev; + u16 val16; + int i; + + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL, + NULL); + root_cap = cap_ptr + PCI_EXP_RTCAP; + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16)); + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) { + /* Enable CRS software visibility */ + root_ctrl = cap_ptr + PCI_EXP_RTCTL; + val16 = PCI_EXP_RTCTL_CRSSVE; + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16, + sizeof(u16)); + + /* Initiate a configuration request to read the vendor id + * field of the device function's config space header after + * 100 ms wait time from the end of Reset. If the device is + * not done with its internal initialization, it must at + * least return a completion TLP, with a completion status + * of "Configuration Request Retry Status (CRS)". The root + * complex must complete the request to the host by returning + * a read-data value of 0001h for the Vendor ID field and + * all 1s for any additional bytes included in the request. + * Poll using the config reads for max wait time of 1 sec or + * until we receive the successful completion status. Repeat + * the procedure for all the devices. + */ + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) { + for (i = 0; i < 100000; i++) { + bcma_extpci_read_config(pc, dev, 0, + PCI_VENDOR_ID, &val16, + sizeof(val16)); + if (val16 != 0x1) + break; + udelay(10); + } + if (val16 == 0x1) + pr_err("PCI: Broken device in slot %d\n", dev); + } + } +} void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) { - pr_err("No support for PCI core in hostmode yet\n"); + struct bcma_bus *bus = pc->core->bus; + struct bcma_drv_pci_host *pc_host; + u32 tmp; + u32 pci_membase_1G; + unsigned long io_map_base; + + pr_info("PCIEcore in host mode found\n"); + + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); + if (!pc_host) { + pr_err("can not allocate memory"); + return; + } + + pc->host_controller = pc_host; + pc_host->pci_controller.io_resource = &pc_host->io_resource; + pc_host->pci_controller.mem_resource = &pc_host->mem_resource; + pc_host->pci_controller.pci_ops = &pc_host->pci_ops; + pc_host->pdev = pc; + + pci_membase_1G = BCMA_SOC_PCI_DMA; + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG; + + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config; + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config; + + pc_host->mem_resource.name = "BCMA PCIcore external memory", + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA; + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1; + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; + + pc_host->io_resource.name = "BCMA PCIcore external I/O", + pc_host->io_resource.start = 0x100; + pc_host->io_resource.end = 0x7FF; + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; + + /* Reset RC */ + udelay(3000); + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); + udelay(1000); + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | + BCMA_CORE_PCI_CTL_RST_OE); + + /* 64 MB I/O access window. On 4716, use + * sbtopcie0 to access the device registers. We + * can't use address match 2 (1 GB window) region + * as mips can't generate 64-bit address on the + * backplane. + */ + if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) { + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + + BCMA_SOC_PCI_MEM_SZ - 1; + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM); + } else if (bus->chipinfo.id == 0x5300) { + tmp = BCMA_CORE_PCI_SBTOPCI_MEM; + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF; + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST; + if (pc->core->core_unit == 0) { + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + + BCMA_SOC_PCI_MEM_SZ - 1; + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32; + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, + tmp | BCMA_SOC_PCI_MEM); + } else if (pc->core->core_unit == 1) { + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM; + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM + + BCMA_SOC_PCI_MEM_SZ - 1; + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32; + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG; + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, + tmp | BCMA_SOC_PCI1_MEM); + } + } else + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, + BCMA_CORE_PCI_SBTOPCI_IO); + + /* 64 MB configuration access window */ + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); + + /* 1 GB memory access window */ + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2, + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G); + + + /* As per PCI Express Base Spec 1.1 we need to wait for + * at least 100 ms from the end of a reset (cold/warm/hot) + * before issuing configuration requests to PCI Express + * devices. + */ + udelay(100000); + + bcma_core_pci_enable_crs(pc); + + /* Enable PCI bridge BAR0 memory & master access */ + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); + + /* Enable PCI interrupts */ + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA); + + /* Ok, ready to run, register it to the system. + * The following needs change, if we want to port hostmode + * to non-MIPS platform. */ + io_map_base = (unsigned long)ioremap_nocache(BCMA_SOC_PCI_MEM, + 0x04000000); + pc_host->pci_controller.io_map_base = io_map_base; + set_io_port_base(pc_host->pci_controller.io_map_base); + /* Give some time to the PCI controller to configure itself with the new + * values. Not waiting at this point causes crashes of the machine. */ + mdelay(10); + register_pci_controller(&pc_host->pci_controller); + return; +} + +/* Early PCI fixup for a device on the PCI-core bridge. */ +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev) +{ + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { + /* This is not a device on the PCI-core bridge. */ + return; + } + if (PCI_SLOT(dev->devfn) != 0) + return; + + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev)); + + /* Enable PCI bridge bus mastering and memory space */ + pci_set_master(dev); + if (pcibios_enable_device(dev, ~0) < 0) { + pr_err("PCI: BCMA bridge enable failed\n"); + return; + } + + /* Enable PCI bridge BAR1 prefetch and burst */ + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3); +} +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge); + +/* Early PCI fixup for all PCI-cores to set the correct memory address. */ +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev) +{ + struct resource *res; + int pos; + + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { + /* This is not a device on the PCI-core bridge. */ + return; + } + if (PCI_SLOT(dev->devfn) == 0) + return; + + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev)); + + for (pos = 0; pos < 6; pos++) { + res = &dev->resource[pos]; + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) + pci_assign_resource(dev, pos); + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses); + +/* This function is called when doing a pci_enable_device(). + * We must first check if the device is a device on the PCI-core bridge. */ +int bcma_core_pci_plat_dev_init(struct pci_dev *dev) +{ + struct bcma_drv_pci_host *pc_host; + + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { + /* This is not a device on the PCI-core bridge. */ + return -ENODEV; + } + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, + pci_ops); + + pr_info("PCI: Fixing up device %s\n", pci_name(dev)); + + /* Fix up interrupt lines */ + dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2; + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + + return 0; +} +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init); + +/* PCI device IRQ mapping. */ +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) +{ + struct bcma_drv_pci_host *pc_host; + + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { + /* This is not a device on the PCI-core bridge. */ + return -ENODEV; + } + + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, + pci_ops); + return bcma_core_mips_irq(pc_host->pdev->core) + 2; } +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h index 679d4ca..46c71e2 100644 --- a/include/linux/bcma/bcma_driver_pci.h +++ b/include/linux/bcma/bcma_driver_pci.h @@ -160,9 +160,44 @@ struct pci_dev; /* PCIcore specific boardflags */ #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ +/* PCIE Config space accessing MACROS */ +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */ +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */ +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */ +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */ + +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */ +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */ +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */ +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */ + +/* PCIE Root Capability Register bits (Host mode only) */ +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 + +struct bcma_drv_pci; + +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE +struct bcma_drv_pci_host { + struct bcma_drv_pci *pdev; + + u32 host_cfg_addr; + spinlock_t cfgspace_lock; + + struct pci_controller pci_controller; + struct pci_ops pci_ops; + struct resource mem_resource; + struct resource io_resource; +}; +#endif + struct bcma_drv_pci { struct bcma_device *core; u8 setup_done:1; + u8 hostmode:1; + +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE + struct bcma_drv_pci_host *host_controller; +#endif }; /* Register access */ @@ -173,4 +208,7 @@ extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc); extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, bool enable); +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); + #endif /* LINUX_BCMA_DRIVER_PCI_H_ */ diff --git a/include/linux/bcma/bcma_regs.h b/include/linux/bcma/bcma_regs.h index 9faae2a..5a71d57 100644 --- a/include/linux/bcma/bcma_regs.h +++ b/include/linux/bcma/bcma_regs.h @@ -56,4 +56,31 @@ #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ +/* SiliconBackplane Address Map. + * All regions may not exist on all chips. + */ +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */ +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */ +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024) +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */ +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */ +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */ + + +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */ +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */ +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */ +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 + * (2 ZettaBytes), low 32 bits + */ +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 + * (2 ZettaBytes), high 32 bits + */ + +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */ +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */ +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2 + * (2 ZettaBytes), high 32 bits + */ + #endif /* LINUX_BCMA_REGS_H_ */ -- 1.7.5.4 From hauke@hauke-m.de Tue Jan 31 00:04:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 00:07:20 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:41823 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904016Ab2A3XEe (ORCPT ); Tue, 31 Jan 2012 00:04:34 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 9A0998F60; Tue, 31 Jan 2012 00:04:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nbizJnQIE7yk; Tue, 31 Jan 2012 00:04:29 +0100 (CET) Received: from localhost.localdomain (unknown [134.102.132.222]) by hauke-m.de (Postfix) with ESMTPSA id C1AFC8F67; Tue, 31 Jan 2012 00:04:13 +0100 (CET) From: Hauke Mehrtens To: linville@tuxdriver.com Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens Subject: [PATCH 7/7] bcma: add extra sprom check Date: Tue, 31 Jan 2012 00:03:37 +0100 Message-Id: <1327964617-7910-8-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> References: <1327964617-7910-1-git-send-email-hauke@hauke-m.de> X-archive-position: 32343 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2412 Lines: 64 This check is needed on the BCM43224 device as it says in the capabilities it has an sprom but is extra check says it has not. Signed-off-by: Hauke Mehrtens --- drivers/bcma/sprom.c | 7 +++++++ include/linux/bcma/bcma_driver_chipcommon.h | 16 ++++++++++++++++ 2 files changed, 23 insertions(+), 0 deletions(-) diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c index e35134f..ca77525 100644 --- a/drivers/bcma/sprom.c +++ b/drivers/bcma/sprom.c @@ -250,6 +250,7 @@ int bcma_sprom_get(struct bcma_bus *bus) { u16 offset; u16 *sprom; + u32 sromctrl; int err = 0; if (!bus->drv_cc.core) @@ -258,6 +259,12 @@ int bcma_sprom_get(struct bcma_bus *bus) if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM)) return -ENOENT; + if (bus->drv_cc.core->id.rev >= 32) { + sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL); + if (!(sromctrl & BCMA_CC_SROM_CONTROL_PRESENT)) + return -ENOENT; + } + sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), GFP_KERNEL); if (!sprom) diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h index a33086a..e72938b 100644 --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h @@ -181,6 +181,22 @@ #define BCMA_CC_FLASH_CFG 0x0128 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ #define BCMA_CC_FLASH_WAITCNT 0x012C +#define BCMA_CC_SROM_CONTROL 0x0190 +#define BCMA_CC_SROM_CONTROL_START 0x80000000 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 /* 0x1E0 is defined as shared BCMA_CLKCTLST */ #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ #define BCMA_CC_UART0_DATA 0x0300 -- 1.7.5.4 From mst@redhat.com Tue Jan 31 01:19:58 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 01:20:07 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:55494 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903705Ab2AaAT6 (ORCPT ); Tue, 31 Jan 2012 01:19:58 +0100 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0V0JjCA027208 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 30 Jan 2012 19:19:45 -0500 Received: from redhat.com (vpn-203-134.tlv.redhat.com [10.35.203.134]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id q0V0Jb29028240; Mon, 30 Jan 2012 19:19:38 -0500 Date: Tue, 31 Jan 2012 02:22:05 +0200 From: "Michael S. Tsirkin" To: Arnd Bergmann Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP Message-ID: <20120131002203.GA14344@redhat.com> References: <201201301551.46907.arnd@arndb.de> <20120130161818.GA9345@redhat.com> <201201302004.33083.arnd@arndb.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201201302004.33083.arnd@arndb.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-archive-position: 32344 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3267 Lines: 88 On Mon, Jan 30, 2012 at 08:04:32PM +0000, Arnd Bergmann wrote: > On Monday 30 January 2012, Michael S. Tsirkin wrote: > > > > > > +/* > > > + * Create a virtual mapping cookie for a port on a given PCI device. > > > + * Do not call this directly, it exists to make it easier for architectures > > > + * to override. > > > + */ > > > +#ifdef CONFIG_NO_GENERIC_PCI_IOPORT_MAP > > > +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, > > > + unsigned int nr); > > > +#else > > > +static inline void __iomem *__pci_ioport_map(struct pci_dev *dev, > > > + unsigned long port, unsigned int nr) > > > +{ > > > + return ioport_map(port, nr); > > > +} > > > +#endif > > > > > > Arnd > > > > It would be nicer in that it would > > make the kernel a bit smaller for generic architectures > > but this would need to go into a separate header: > > it depends on io.h and io.h depends on pci_iomap.h. > > Adding extra dependencies is not good here, I agree. > Maybe a better solution is to use a macro instead of an inline > function then: > > #define __pci_ioport_map(dev, port, nr) ioport_map(port, nr) > > In general, macros should be avoided, but I think it's the > best tradeoff in this case. > > Arnd I have an idea: we can make the generic one inline if we keep it in the .c file. So something like the below on top of my patch will probably work. Ack? diff --git a/include/asm-generic/pci_iomap.h b/include/asm-generic/pci_iomap.h index 2aff58e..2ec1bdb 100644 --- a/include/asm-generic/pci_iomap.h +++ b/include/asm-generic/pci_iomap.h @@ -15,11 +15,6 @@ struct pci_dev; #ifdef CONFIG_PCI /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); -/* Create a virtual mapping cookie for a port on a given PCI device. - * Do not call this directly, it exists to make it easier for architectures - * to override. */ -extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, - unsigned int nr); #else static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) { @@ -27,4 +22,12 @@ static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned lon } #endif +#ifdef CONFIG_NO_GENERIC_PCI_IOPORT_MAP +/* Create a virtual mapping cookie for a port on a given PCI device. + * Do not call this directly, it exists to make it easier for architectures + * to override. */ +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, + unsigned int nr); +#endif + #endif /* __ASM_GENERIC_IO_H */ diff --git a/lib/pci_iomap.c b/lib/pci_iomap.c index 1dfda29..8102f28 100644 --- a/lib/pci_iomap.c +++ b/lib/pci_iomap.c @@ -12,9 +12,9 @@ #ifndef CONFIG_NO_GENERIC_PCI_IOPORT_MAP /* Architectures can override ioport mapping while * still using the rest of the generic infrastructure. */ -void __iomem *__pci_ioport_map(struct pci_dev *dev, - unsigned long port, - unsigned int nr) +static inline void __iomem *__pci_ioport_map(struct pci_dev *dev, + unsigned long port, + unsigned int nr) { return ioport_map(port, nr); } From florian@openwrt.org Tue Jan 31 15:08:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:08:38 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:60357 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904021Ab2AaOIc (ORCPT ); Tue, 31 Jan 2012 15:08:32 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id F135A1119D1; Tue, 31 Jan 2012 15:08:31 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id B-bR6ET+eoDY; Tue, 31 Jan 2012 15:08:31 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 6B8CD32CE5B; Tue, 31 Jan 2012 15:08:31 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 2/2] MIPS: BCM63XX: be consistent in clock bits enable naming Date: Tue, 31 Jan 2012 15:08:08 +0100 Message-Id: <1328018888-5533-3-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328018888-5533-1-git-send-email-florian@openwrt.org> References: <1328018888-5533-1-git-send-email-florian@openwrt.org> X-archive-position: 32345 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3327 Lines: 95 Remove the _CLK suffix from the BCM6368 clock bits definitions to be consistent with what is already present. Signed-off-by: Florian Fainelli --- arch/mips/bcm63xx/clk.c | 6 ++-- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 36 ++++++++++---------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index 9d57c71..8d2ea22 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk, int enable) { if (!BCMCPU_IS_6368()) return; - bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN | + bcm_hwclock_set(CKCTL_6368_ROBOSW_EN | CKCTL_6368_SWPKT_USB_EN | CKCTL_6368_SWPKT_SAR_EN, enable); if (enable) { @@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, int enable) if (BCMCPU_IS_6348()) bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); else if (BCMCPU_IS_6368()) - bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable); + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); } static struct clk clk_usbh = { @@ -199,7 +199,7 @@ static void xtm_set(struct clk *clk, int enable) if (!BCMCPU_IS_6368()) return; - bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN | + bcm_hwclock_set(CKCTL_6368_SAR_EN | CKCTL_6368_SWPKT_SAR_EN, enable); if (enable) { diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 94d4faa..6ddd081 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -90,29 +90,29 @@ #define CKCTL_6368_PHYMIPS_EN (1 << 6) #define CKCTL_6368_SWPKT_USB_EN (1 << 7) #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) -#define CKCTL_6368_SPI_CLK_EN (1 << 9) -#define CKCTL_6368_USBD_CLK_EN (1 << 10) -#define CKCTL_6368_SAR_CLK_EN (1 << 11) -#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12) -#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13) -#define CKCTL_6368_PCM_CLK_EN (1 << 14) -#define CKCTL_6368_USBH_CLK_EN (1 << 15) +#define CKCTL_6368_SPI_EN (1 << 9) +#define CKCTL_6368_USBD_EN (1 << 10) +#define CKCTL_6368_SAR_EN (1 << 11) +#define CKCTL_6368_ROBOSW_EN (1 << 12) +#define CKCTL_6368_UTOPIA_EN (1 << 13) +#define CKCTL_6368_PCM_EN (1 << 14) +#define CKCTL_6368_USBH_EN (1 << 15) #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) -#define CKCTL_6368_NAND_CLK_EN (1 << 17) -#define CKCTL_6368_IPSEC_CLK_EN (1 << 17) +#define CKCTL_6368_NAND_EN (1 << 17) +#define CKCTL_6368_IPSEC_EN (1 << 17) #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ CKCTL_6368_SWPKT_SAR_EN | \ - CKCTL_6368_SPI_CLK_EN | \ - CKCTL_6368_USBD_CLK_EN | \ - CKCTL_6368_SAR_CLK_EN | \ - CKCTL_6368_ROBOSW_CLK_EN | \ - CKCTL_6368_UTOPIA_CLK_EN | \ - CKCTL_6368_PCM_CLK_EN | \ - CKCTL_6368_USBH_CLK_EN | \ + CKCTL_6368_SPI_EN | \ + CKCTL_6368_USBD_EN | \ + CKCTL_6368_SAR_EN | \ + CKCTL_6368_ROBOSW_EN | \ + CKCTL_6368_UTOPIA_EN | \ + CKCTL_6368_PCM_EN | \ + CKCTL_6368_USBH_EN | \ CKCTL_6368_DISABLE_GLESS_EN | \ - CKCTL_6368_NAND_CLK_EN | \ - CKCTL_6368_IPSEC_CLK_EN) + CKCTL_6368_NAND_EN | \ + CKCTL_6368_IPSEC_EN) /* System PLL Control register */ #define PERF_SYS_PLL_CTL_REG 0x8 -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:08:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:09:02 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:60354 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904020Ab2AaOIc (ORCPT ); Tue, 31 Jan 2012 15:08:32 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id C0748352909; Tue, 31 Jan 2012 15:08:31 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PdiBjKP6w0zm; Tue, 31 Jan 2012 15:08:31 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 6612C1119D1; Tue, 31 Jan 2012 15:08:31 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 1/2] MIPS: BCM63XX: fix platform_devices id Date: Tue, 31 Jan 2012 15:08:07 +0100 Message-Id: <1328018888-5533-2-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328018888-5533-1-git-send-email-florian@openwrt.org> References: <1328018888-5533-1-git-send-email-florian@openwrt.org> X-archive-position: 32346 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1172 Lines: 38 There is only one watchdog and VoIP DSP platform devices per board, use -1 as the platform_device id accordingly. Signed-off-by: Florian Fainelli --- arch/mips/bcm63xx/dev-dsp.c | 2 +- arch/mips/bcm63xx/dev-wdt.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm63xx/dev-dsp.c b/arch/mips/bcm63xx/dev-dsp.c index da46d1d..5bb5b15 100644 --- a/arch/mips/bcm63xx/dev-dsp.c +++ b/arch/mips/bcm63xx/dev-dsp.c @@ -31,7 +31,7 @@ static struct resource voip_dsp_resources[] = { static struct platform_device bcm63xx_voip_dsp_device = { .name = "bcm63xx-voip-dsp", - .id = 0, + .id = -1, .num_resources = ARRAY_SIZE(voip_dsp_resources), .resource = voip_dsp_resources, }; diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c index 3e6c716..2a2346a 100644 --- a/arch/mips/bcm63xx/dev-wdt.c +++ b/arch/mips/bcm63xx/dev-wdt.c @@ -21,7 +21,7 @@ static struct resource wdt_resources[] = { static struct platform_device bcm63xx_wdt_device = { .name = "bcm63xx-wdt", - .id = 0, + .id = -1, .num_resources = ARRAY_SIZE(wdt_resources), .resource = wdt_resources, }; -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:08:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:09:27 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:60356 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904018Ab2AaOIc (ORCPT ); Tue, 31 Jan 2012 15:08:32 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id C6A233530EB; Tue, 31 Jan 2012 15:08:31 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XcHQn37hyoQ2; Tue, 31 Jan 2012 15:08:31 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 565AD3101FA; Tue, 31 Jan 2012 15:08:31 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 0/2] MIPS: BCM63XX: misc cleanup Date: Tue, 31 Jan 2012 15:08:06 +0100 Message-Id: <1328018888-5533-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32347 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 547 Lines: 16 This patch set contains some small cleanups. This is the preliminary serie of other changes. Florian Fainelli (2): MIPS: BCM63XX: fix platform_devices id MIPS: BCM63XX: be consistent in clock bits enable naming arch/mips/bcm63xx/clk.c | 6 ++-- arch/mips/bcm63xx/dev-dsp.c | 2 +- arch/mips/bcm63xx/dev-wdt.c | 2 +- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 36 ++++++++++---------- 4 files changed, 23 insertions(+), 23 deletions(-) -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:11:17 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59597 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904018Ab2AaOLK (ORCPT ); Tue, 31 Jan 2012 15:11:10 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id A14BE3585DD; Tue, 31 Jan 2012 15:11:10 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oS4r-UVMSRiT; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id EFA19358975; Tue, 31 Jan 2012 15:11:09 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 0/9 v3] MIPS: BCM63XX: add support for SPI Date: Tue, 31 Jan 2012 15:10:39 +0100 Message-Id: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32348 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1627 Lines: 36 This patch set depend on the serie "MIPS: BCM63XX: misc cleanup" and adds support for the SPI controller found in BCM63xx SoCs. Grant, it probably makes sense to get this merged via the MIPS tree since it mostly depends on it. Florian Fainelli (9): MIPS: BCM63XX: add IRQ_SPI and CPU specific SPI IRQ values MIPS: BCM63XX: define BCM6358 SPI base address MIPS: BCM63XX: add BCM6368 SPI clock mask MIPS: BCM63XX: define SPI register sizes. MIPS: BCM63XX: remove SPI2 register MIPS: BCM63XX: define internal registers offsets of the SPI controller MIPS: BCM63XX: add stub to register the SPI platform driver MIPS: BCM63XX: make board setup code register the spi platform device spi: add Broadcom BCM63xx SPI controller driver arch/mips/bcm63xx/Makefile | 3 +- arch/mips/bcm63xx/boards/board_bcm963xx.c | 3 + arch/mips/bcm63xx/clk.c | 6 +- arch/mips/bcm63xx/dev-spi.c | 119 +++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 23 +- .../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 89 ++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 119 +++++ drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/spi-bcm63xx.c | 486 ++++++++++++++++++++ 10 files changed, 842 insertions(+), 13 deletions(-) create mode 100644 arch/mips/bcm63xx/dev-spi.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h create mode 100644 drivers/spi/spi-bcm63xx.c -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:11:41 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59603 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904022Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id C76493586EB; Tue, 31 Jan 2012 15:11:10 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7oe-azHHCEbh; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 2C9573586EA; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 4/9 v3] MIPS: BCM63XX: define SPI register sizes. Date: Tue, 31 Jan 2012 15:10:43 +0100 Message-Id: <1328019048-5892-5-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32349 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1058 Lines: 30 There are two distinct sizes for the SPI register depending on the SoC generation (6338 & 6348 vs 6358 & 6368). Signed-off-by: Florian Fainelli --- Changes since v2: - added different sizes accounting for the different SPI controller FIFO sizes No changes in v1 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 016dc9e..4c1e147 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -135,6 +135,10 @@ enum bcm63xx_regs_set { #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) #define RSET_DSL_SIZE 4096 #define RSET_WDT_SIZE 12 +#define BCM_6338_RSET_SPI_SIZE 64 +#define BCM_6348_RSET_SPI_SIZE 64 +#define BCM_6358_RSET_SPI_SIZE 1804 +#define BCM_6368_RSET_SPI_SIZE 1804 #define RSET_ENET_SIZE 2048 #define RSET_ENETDMA_SIZE 2048 #define RSET_ENETSW_SIZE 65536 -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:12:03 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59602 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904021Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id AEAE63454A0; Tue, 31 Jan 2012 15:11:10 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qgulPldNwtN1; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 141ED3586EB; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 2/9 v3] MIPS: BCM63XX: define BCM6358 SPI base address Date: Tue, 31 Jan 2012 15:10:41 +0100 Message-Id: <1328019048-5892-3-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32350 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 841 Lines: 23 Signed-off-by: Florian Fainelli --- No changes in v1 and v2 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 9975727..016dc9e 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -289,7 +289,7 @@ enum bcm63xx_regs_set { #define BCM_6358_UART0_BASE (0xfffe0100) #define BCM_6358_UART1_BASE (0xfffe0120) #define BCM_6358_GPIO_BASE (0xfffe0080) -#define BCM_6358_SPI_BASE (0xdeadbeef) +#define BCM_6358_SPI_BASE (0xfffe0800) #define BCM_6358_SPI2_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800) #define BCM_6358_OHCI0_BASE (0xfffe1400) -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:12:25 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59612 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904023Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id D96FD3586EA; Tue, 31 Jan 2012 15:11:10 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xd8KJbvSoEBo; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 3327F358744; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 5/9 v3] MIPS: BCM63XX: remove SPI2 register Date: Tue, 31 Jan 2012 15:10:44 +0100 Message-Id: <1328019048-5892-6-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32351 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3434 Lines: 85 This register was introduced with the support of the BCM6368 CPU in the idea that its internal layout was different from the other CPUs SPI controller. The controller is actually the same as the one present on BCM6358 so we can remove this register and use the usual SPI register instead. Signed-off-by: Florian Fainelli --- No changes in v1 and v2 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 10 +--------- 1 files changed, 1 insertions(+), 9 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 4c1e147..82a8175 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -102,7 +102,6 @@ enum bcm63xx_regs_set { RSET_UART1, RSET_GPIO, RSET_SPI, - RSET_SPI2, RSET_UDC0, RSET_OHCI0, RSET_OHCI_PRIV, @@ -166,7 +165,6 @@ enum bcm63xx_regs_set { #define BCM_6338_UART1_BASE (0xdeadbeef) #define BCM_6338_GPIO_BASE (0xfffe0400) #define BCM_6338_SPI_BASE (0xfffe0c00) -#define BCM_6338_SPI2_BASE (0xdeadbeef) #define BCM_6338_UDC0_BASE (0xdeadbeef) #define BCM_6338_USBDMA_BASE (0xfffe2400) #define BCM_6338_OHCI0_BASE (0xdeadbeef) @@ -210,7 +208,6 @@ enum bcm63xx_regs_set { #define BCM_6345_UART1_BASE (0xdeadbeef) #define BCM_6345_GPIO_BASE (0xfffe0400) #define BCM_6345_SPI_BASE (0xdeadbeef) -#define BCM_6345_SPI2_BASE (0xdeadbeef) #define BCM_6345_UDC0_BASE (0xdeadbeef) #define BCM_6345_USBDMA_BASE (0xfffe2800) #define BCM_6345_ENET0_BASE (0xfffe1800) @@ -253,7 +250,6 @@ enum bcm63xx_regs_set { #define BCM_6348_UART1_BASE (0xdeadbeef) #define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_SPI_BASE (0xfffe0c00) -#define BCM_6348_SPI2_BASE (0xdeadbeef) #define BCM_6348_UDC0_BASE (0xfffe1000) #define BCM_6348_OHCI0_BASE (0xfffe1b00) #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) @@ -294,7 +290,6 @@ enum bcm63xx_regs_set { #define BCM_6358_UART1_BASE (0xfffe0120) #define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_SPI_BASE (0xfffe0800) -#define BCM_6358_SPI2_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800) #define BCM_6358_OHCI0_BASE (0xfffe1400) #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) @@ -335,8 +330,7 @@ enum bcm63xx_regs_set { #define BCM_6368_UART0_BASE (0xb0000100) #define BCM_6368_UART1_BASE (0xb0000120) #define BCM_6368_GPIO_BASE (0xb0000080) -#define BCM_6368_SPI_BASE (0xdeadbeef) -#define BCM_6368_SPI2_BASE (0xb0000800) +#define BCM_6368_SPI_BASE (0xb0000800) #define BCM_6368_UDC0_BASE (0xdeadbeef) #define BCM_6368_OHCI0_BASE (0xb0001600) #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) @@ -383,7 +377,6 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, UART1) \ __GEN_RSET_BASE(__cpu, GPIO) \ __GEN_RSET_BASE(__cpu, SPI) \ - __GEN_RSET_BASE(__cpu, SPI2) \ __GEN_RSET_BASE(__cpu, UDC0) \ __GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ @@ -422,7 +415,6 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ - [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \ [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:12:48 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59627 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904027Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 1F0AF358722; Tue, 31 Jan 2012 15:11:11 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AwosbyQqHrGB; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 4F69E35880C; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 8/9 v3] MIPS: BCM63XX: make board setup code register the spi platform device Date: Tue, 31 Jan 2012 15:10:47 +0100 Message-Id: <1328019048-5892-9-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32352 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 859 Lines: 31 Signed-off-by: Florian Fainelli --- No changes since v1 and v2 arch/mips/bcm63xx/boards/board_bcm963xx.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 2f1773f..ea65c0f 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #define PFX "board_bcm963xx: " @@ -890,6 +891,8 @@ int __init board_register_devices(void) } #endif + bcm63xx_spi_register(); + /* read base address of boot chip select (0) */ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); val &= MPI_CSBASE_BASE_MASK; -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:13:11 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59622 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904025Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 115E435872E; Tue, 31 Jan 2012 15:11:11 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RdAfrkkutIIv; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 4344035878C; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 6/9 v3] MIPS: BCM63XX: define internal registers offsets of the SPI controller Date: Tue, 31 Jan 2012 15:10:45 +0100 Message-Id: <1328019048-5892-7-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32353 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4594 Lines: 145 BCM6338, BCM6348, BCM6358 and BCM6368 basically use the same SPI controller though the internal registers are shuffled, which still allows a common driver to drive that IP block. Signed-off-by: Florian Fainelli --- Changes since v2: - removed invalid SPI_CLK_25MHZ definition No changes in v1 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 119 +++++++++++++++++++++ 1 files changed, 119 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 6ddd081..c21aa34 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -973,4 +973,123 @@ #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) +/************************************************************************* + * _REG relative to RSET_SPI + *************************************************************************/ + +/* BCM 6338 SPI core */ +#define SPI_6338_CMD 0x00 /* 16-bits register */ +#define SPI_6338_INT_STATUS 0x02 +#define SPI_6338_INT_MASK_ST 0x03 +#define SPI_6338_INT_MASK 0x04 +#define SPI_6338_ST 0x05 +#define SPI_6338_CLK_CFG 0x06 +#define SPI_6338_FILL_BYTE 0x07 +#define SPI_6338_MSG_TAIL 0x09 +#define SPI_6338_RX_TAIL 0x0b +#define SPI_6338_MSG_CTL 0x40 +#define SPI_6338_MSG_DATA 0x41 +#define SPI_6338_MSG_DATA_SIZE 0x3f +#define SPI_6338_RX_DATA 0x80 +#define SPI_6338_RX_DATA_SIZE 0x3f + +/* BCM 6348 SPI core */ +#define SPI_6348_CMD 0x00 /* 16-bits register */ +#define SPI_6348_INT_STATUS 0x02 +#define SPI_6348_INT_MASK_ST 0x03 +#define SPI_6348_INT_MASK 0x04 +#define SPI_6348_ST 0x05 +#define SPI_6348_CLK_CFG 0x06 +#define SPI_6348_FILL_BYTE 0x07 +#define SPI_6348_MSG_TAIL 0x09 +#define SPI_6348_RX_TAIL 0x0b +#define SPI_6348_MSG_CTL 0x40 +#define SPI_6348_MSG_DATA 0x41 +#define SPI_6348_MSG_DATA_SIZE 0x3f +#define SPI_6348_RX_DATA 0x80 +#define SPI_6348_RX_DATA_SIZE 0x3f + +/* BCM 6358 SPI core */ +#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ +#define SPI_6358_MSG_DATA 0x02 +#define SPI_6358_MSG_DATA_SIZE 0x21e +#define SPI_6358_RX_DATA 0x400 +#define SPI_6358_RX_DATA_SIZE 0x220 +#define SPI_6358_CMD 0x700 /* 16-bits register */ +#define SPI_6358_INT_STATUS 0x702 +#define SPI_6358_INT_MASK_ST 0x703 +#define SPI_6358_INT_MASK 0x704 +#define SPI_6358_ST 0x705 +#define SPI_6358_CLK_CFG 0x706 +#define SPI_6358_FILL_BYTE 0x707 +#define SPI_6358_MSG_TAIL 0x709 +#define SPI_6358_RX_TAIL 0x70B + +/* BCM 6358 SPI core */ +#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ +#define SPI_6368_MSG_DATA 0x02 +#define SPI_6368_MSG_DATA_SIZE 0x21e +#define SPI_6368_RX_DATA 0x400 +#define SPI_6368_RX_DATA_SIZE 0x220 +#define SPI_6368_CMD 0x700 /* 16-bits register */ +#define SPI_6368_INT_STATUS 0x702 +#define SPI_6368_INT_MASK_ST 0x703 +#define SPI_6368_INT_MASK 0x704 +#define SPI_6368_ST 0x705 +#define SPI_6368_CLK_CFG 0x706 +#define SPI_6368_FILL_BYTE 0x707 +#define SPI_6368_MSG_TAIL 0x709 +#define SPI_6368_RX_TAIL 0x70B + +/* Shared SPI definitions */ + +/* Message configuration */ +#define SPI_FD_RW 0x00 +#define SPI_HD_W 0x01 +#define SPI_HD_R 0x02 +#define SPI_BYTE_CNT_SHIFT 0 +#define SPI_MSG_TYPE_SHIFT 14 + +/* Command */ +#define SPI_CMD_NOOP 0x00 +#define SPI_CMD_SOFT_RESET 0x01 +#define SPI_CMD_HARD_RESET 0x02 +#define SPI_CMD_START_IMMEDIATE 0x03 +#define SPI_CMD_COMMAND_SHIFT 0 +#define SPI_CMD_COMMAND_MASK 0x000f +#define SPI_CMD_DEVICE_ID_SHIFT 4 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 +#define SPI_CMD_ONE_BYTE_SHIFT 11 +#define SPI_CMD_ONE_WIRE_SHIFT 12 +#define SPI_DEV_ID_0 0 +#define SPI_DEV_ID_1 1 +#define SPI_DEV_ID_2 2 +#define SPI_DEV_ID_3 3 + +/* Interrupt mask */ +#define SPI_INTR_CMD_DONE 0x01 +#define SPI_INTR_RX_OVERFLOW 0x02 +#define SPI_INTR_TX_UNDERFLOW 0x04 +#define SPI_INTR_TX_OVERFLOW 0x08 +#define SPI_INTR_RX_UNDERFLOW 0x10 +#define SPI_INTR_CLEAR_ALL 0x1f + +/* Status */ +#define SPI_RX_EMPTY 0x02 +#define SPI_CMD_BUSY 0x04 +#define SPI_SERIAL_BUSY 0x08 + +/* Clock configuration */ +#define SPI_CLK_20MHZ 0x00 +#define SPI_CLK_0_391MHZ 0x01 +#define SPI_CLK_0_781MHZ 0x02 /* default */ +#define SPI_CLK_1_563MHZ 0x03 +#define SPI_CLK_3_125MHZ 0x04 +#define SPI_CLK_6_250MHZ 0x05 +#define SPI_CLK_12_50MHZ 0x06 +#define SPI_CLK_MASK 0x07 +#define SPI_SSOFFTIME_MASK 0x38 +#define SPI_SSOFFTIME_SHIFT 3 +#define SPI_BYTE_SWAP 0x80 + #endif /* BCM63XX_REGS_H_ */ -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:13:35 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59623 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904026Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id E8191358744; Tue, 31 Jan 2012 15:11:10 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9r97P04Acu1c; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 1DC26345024; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 3/9 v3] MIPS: BCM63XX: add BCM6368 SPI clock mask Date: Tue, 31 Jan 2012 15:10:42 +0100 Message-Id: <1328019048-5892-4-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32354 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 683 Lines: 28 Signed-off-by: Florian Fainelli --- No changes in v1 and v2 arch/mips/bcm63xx/clk.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index 8d2ea22..be49b9a 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -181,9 +181,11 @@ static void spi_set(struct clk *clk, int enable) mask = CKCTL_6338_SPI_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_SPI_EN; - else - /* BCMCPU_IS_6358 */ + else if (BCMCPU_IS_6358()) mask = CKCTL_6358_SPI_EN; + else + /* BCMCPU_IS_6368 */ + mask = CKCTL_6368_SPI_EN; bcm_hwclock_set(mask, enable); } -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:13:58 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59620 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904024Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 08C9C3586AF; Tue, 31 Jan 2012 15:11:11 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gW5OOWUFEhOd; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 0387F3588D7; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 1/9 v3] MIPS: BCM63XX: add IRQ_SPI and CPU specific SPI IRQ values Date: Tue, 31 Jan 2012 15:10:40 +0100 Message-Id: <1328019048-5892-2-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32355 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2525 Lines: 70 Signed-off-by: Florian Fainelli --- No changes in v1 and v2 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 5b8d15b..9975727 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -478,6 +478,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) */ enum bcm63xx_irq { IRQ_TIMER = 0, + IRQ_SPI, IRQ_UART0, IRQ_UART1, IRQ_DSL, @@ -509,6 +510,7 @@ enum bcm63xx_irq { * 6338 irqs */ #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6338_UART1_IRQ 0 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) @@ -539,6 +541,7 @@ enum bcm63xx_irq { * 6345 irqs */ #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6345_SPI_IRQ 0 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6345_UART1_IRQ 0 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) @@ -569,6 +572,7 @@ enum bcm63xx_irq { * 6348 irqs */ #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6348_UART1_IRQ 0 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) @@ -599,6 +603,7 @@ enum bcm63xx_irq { * 6358 irqs */ #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) @@ -638,6 +643,7 @@ enum bcm63xx_irq { #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) @@ -677,6 +683,7 @@ extern const int *bcm63xx_irqs; #define __GEN_CPU_IRQ_TABLE(__cpu) \ [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ + [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \ [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:14:26 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59629 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904028Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 2F0D5345024; Tue, 31 Jan 2012 15:11:11 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ffUjQjaKrBm6; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 4C0FD3587D3; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli Subject: [PATCH 7/9 v3] MIPS: BCM63XX: add stub to register the SPI platform driver Date: Tue, 31 Jan 2012 15:10:46 +0100 Message-Id: <1328019048-5892-8-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32356 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 6950 Lines: 254 This patch adds the necessary stub to register the SPI platform driver. Since the registers are shuffled between the 4 BCM63xx CPUs supported by this SPI driver we also need to generate the internal register layout and export this layout for the driver to use it properly. Signed-off-by: Florian Fainelli --- Changes since v2: - added different resource size due to different fifo sizes No changes in v1 arch/mips/bcm63xx/Makefile | 3 +- arch/mips/bcm63xx/dev-spi.c | 119 ++++++++++++++++++++ .../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 89 +++++++++++++++ 3 files changed, 210 insertions(+), 1 deletions(-) create mode 100644 arch/mips/bcm63xx/dev-spi.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 6dfdc69..4049cd5 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,5 +1,6 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ - dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o + dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \ + dev-wdt.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c new file mode 100644 index 0000000..67fa45b --- /dev/null +++ b/arch/mips/bcm63xx/dev-spi.c @@ -0,0 +1,119 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009-2011 Florian Fainelli + * Copyright (C) 2010 Tanguy Bouzeloc + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef BCMCPU_RUNTIME_DETECT +/* + * register offsets + */ +static const unsigned long bcm6338_regs_spi[] = { + __GEN_SPI_REGS_TABLE(6338) +}; + +static const unsigned long bcm6348_regs_spi[] = { + __GEN_SPI_REGS_TABLE(6348) +}; + +static const unsigned long bcm6358_regs_spi[] = { + __GEN_SPI_REGS_TABLE(6358) +}; + +static const unsigned long bcm6368_regs_spi[] = { + __GEN_SPI_REGS_TABLE(6368) +}; + +const unsigned long *bcm63xx_regs_spi; +EXPORT_SYMBOL(bcm63xx_regs_spi); + +static __init void bcm63xx_spi_regs_init(void) +{ + if (BCMCPU_IS_6338()) + bcm63xx_regs_spi = bcm6338_regs_spi; + if (BCMCPU_IS_6348()) + bcm63xx_regs_spi = bcm6348_regs_spi; + if (BCMCPU_IS_6358()) + bcm63xx_regs_spi = bcm6358_regs_spi; + if (BCMCPU_IS_6368()) + bcm63xx_regs_spi = bcm6368_regs_spi; +} +#else +static __init void bcm63xx_spi_regs_init(void) { } +#endif + +static struct resource spi_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct bcm63xx_spi_pdata spi_pdata = { + .bus_num = 0, + .num_chipselect = 8, +}; + +static struct platform_device bcm63xx_spi_device = { + .name = "bcm63xx-spi", + .id = -1, + .num_resources = ARRAY_SIZE(spi_resources), + .resource = spi_resources, + .dev = { + .platform_data = &spi_pdata, + }, +}; + +int __init bcm63xx_spi_register(void) +{ + struct clk *periph_clk; + + if (BCMCPU_IS_6345()) + return -ENODEV; + + periph_clk = clk_get(NULL, "periph"); + if (IS_ERR(periph_clk)) { + pr_err("unable to get periph clock\n"); + return -ENODEV; + } + + /* Set bus frequency */ + spi_pdata.speed_hz = clk_get_rate(periph_clk); + + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI); + spi_resources[0].end = spi_resources[0].start; + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI); + + if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { + spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1; + spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE; + } + + if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { + spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; + spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; + } + + bcm63xx_spi_regs_init(); + + return platform_device_register(&bcm63xx_spi_device); +} diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h new file mode 100644 index 0000000..7d98dbe --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h @@ -0,0 +1,89 @@ +#ifndef BCM63XX_DEV_SPI_H +#define BCM63XX_DEV_SPI_H + +#include +#include +#include + +int __init bcm63xx_spi_register(void); + +struct bcm63xx_spi_pdata { + unsigned int fifo_size; + int bus_num; + int num_chipselect; + u32 speed_hz; +}; + +enum bcm63xx_regs_spi { + SPI_CMD, + SPI_INT_STATUS, + SPI_INT_MASK_ST, + SPI_INT_MASK, + SPI_ST, + SPI_CLK_CFG, + SPI_FILL_BYTE, + SPI_MSG_TAIL, + SPI_RX_TAIL, + SPI_MSG_CTL, + SPI_MSG_DATA, + SPI_RX_DATA, +}; + +#define __GEN_SPI_RSET_BASE(__cpu, __rset) \ + case SPI_## __rset: \ + return SPI_## __cpu ##_## __rset; + +#define __GEN_SPI_RSET(__cpu) \ + switch (reg) { \ + __GEN_SPI_RSET_BASE(__cpu, CMD) \ + __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \ + __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \ + __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \ + __GEN_SPI_RSET_BASE(__cpu, ST) \ + __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \ + __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \ + __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \ + __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \ + __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \ + __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \ + __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \ + } + +#define __GEN_SPI_REGS_TABLE(__cpu) \ + [SPI_CMD] = SPI_## __cpu ##_CMD, \ + [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \ + [SPI_INT_MASK_ST] = SPI_## __cpu ##_INT_MASK_ST, \ + [SPI_INT_MASK] = SPI_## __cpu ##_INT_MASK, \ + [SPI_ST] = SPI_## __cpu ##_ST, \ + [SPI_CLK_CFG] = SPI_## __cpu ##_CLK_CFG, \ + [SPI_FILL_BYTE] = SPI_## __cpu ##_FILL_BYTE, \ + [SPI_MSG_TAIL] = SPI_## __cpu ##_MSG_TAIL, \ + [SPI_RX_TAIL] = SPI_## __cpu ##_RX_TAIL, \ + [SPI_MSG_CTL] = SPI_## __cpu ##_MSG_CTL, \ + [SPI_MSG_DATA] = SPI_## __cpu ##_MSG_DATA, \ + [SPI_RX_DATA] = SPI_## __cpu ##_RX_DATA, + +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) +{ +#ifdef BCMCPU_RUNTIME_DETECT + extern const unsigned long *bcm63xx_regs_spi; + + return bcm63xx_regs_spi[reg]; +#else +#ifdef CONFIG_BCM63XX_CPU_6338 + __GEN_SPI_RSET(6338) +#endif +#ifdef CONFIG_BCM63XX_CPU_6348 + __GEN_SPI_RSET(6348) +#endif +#ifdef CONFIG_BCM63XX_CPU_6358 + __GEN_SPI_RSET(6358) +#endif +#ifdef CONFIG_BCM63XX_CPU_6368 + __GEN_SPI_RSET(6368) +#endif +#endif + return 0; +} + +#endif /* BCM63XX_DEV_SPI_H */ -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:11:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:14:50 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59631 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904029Ab2AaOLL (ORCPT ); Tue, 31 Jan 2012 15:11:11 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 5525635873F; Tue, 31 Jan 2012 15:11:11 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zCEvMC9HcvbQ; Tue, 31 Jan 2012 15:11:10 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 581893588B2; Tue, 31 Jan 2012 15:11:10 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, Florian Fainelli , Tanguy Bouzeloc Subject: [PATCH 9/9 v3] spi: add Broadcom BCM63xx SPI controller driver Date: Tue, 31 Jan 2012 15:10:48 +0100 Message-Id: <1328019048-5892-10-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> X-archive-position: 32357 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 14452 Lines: 550 This patch adds support for the SPI controller found on the Broadcom BCM63xx SoCs. Signed-off-by: Tanguy Bouzeloc Signed-off-by: Florian Fainelli --- Changes since v2: - reworked bcm63xx_spi_setup_transfer to choose closest spi transfer frequency - removed invalid 25Mhz frequency - fixed some minor checkpatch issues Changes since v1: - switched to the devm_* API which frees resources automatically - switched to dev_pm_ops - use module_platform_driver - remove MODULE_VERSION() - fixed return value when clock is not present using PTR_ERR() - fixed probe() error path to disable clock in case of failure drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/spi-bcm63xx.c | 486 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 493 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/spi-bcm63xx.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3f9a47e..16818ac 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -94,6 +94,12 @@ config SPI_AU1550 If you say yes to this option, support will be included for the PSC SPI controller found on Au1550, Au1200 and Au1300 series. +config SPI_BCM63XX + tristate "Broadcom BCM63xx SPI controller" + depends on BCM63XX + help + Enable support for the SPI controller on the Broadcom BCM63xx SoCs. + config SPI_BITBANG tristate "Utilities for Bitbanging SPI masters" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 61c3261..be38f73 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.o obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o obj-$(CONFIG_SPI_ATH79) += spi-ath79.o obj-$(CONFIG_SPI_AU1550) += spi-au1550.o +obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c new file mode 100644 index 0000000..eba8505 --- /dev/null +++ b/drivers/spi/spi-bcm63xx.c @@ -0,0 +1,486 @@ +/* + * Broadcom BCM63xx SPI controller support + * + * Copyright (C) 2009-2011 Florian Fainelli + * Copyright (C) 2010 Tanguy Bouzeloc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PFX KBUILD_MODNAME +#define DRV_VER "0.1.2" + +struct bcm63xx_spi { + spinlock_t lock; + int stopping; + struct completion done; + + void __iomem *regs; + int irq; + + /* Platform data */ + u32 speed_hz; + unsigned fifo_size; + + /* Data buffers */ + const unsigned char *tx_ptr; + unsigned char *rx_ptr; + + /* data iomem */ + u8 __iomem *tx_io; + const u8 __iomem *rx_io; + + int remaining_bytes; + + struct clk *clk; + struct platform_device *pdev; +}; + +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, + unsigned int offset) +{ + return bcm_readw(bs->regs + bcm63xx_spireg(offset)); +} + +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, + unsigned int offset) +{ + return bcm_readw(bs->regs + bcm63xx_spireg(offset)); +} + +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, + u8 value, unsigned int offset) +{ + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); +} + +static inline void bcm_spi_writew(struct bcm63xx_spi *bs, + u16 value, unsigned int offset) +{ + bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); +} + +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { + { 20000000, SPI_CLK_20MHZ }, + { 12500000, SPI_CLK_12_50MHZ }, + { 6250000, SPI_CLK_6_250MHZ }, + { 3125000, SPI_CLK_3_125MHZ }, + { 1563000, SPI_CLK_1_563MHZ }, + { 781000, SPI_CLK_0_781MHZ }, + { 391000, SPI_CLK_0_391MHZ } +}; + +static int bcm63xx_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) +{ + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); + u8 bits_per_word; + u8 clk_cfg, reg; + u32 hz; + int i; + + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; + hz = (t) ? t->speed_hz : spi->max_speed_hz; + if (bits_per_word != 8) { + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", + __func__, bits_per_word); + return -EINVAL; + } + + if (spi->chip_select > spi->master->num_chipselect) { + dev_err(&spi->dev, "%s, unsupported slave %d\n", + __func__, spi->chip_select); + return -EINVAL; + } + + /* Find the closest clock configuration */ + for (i = 0; i < SPI_CLK_MASK; i++) { + if (hz <= bcm63xx_spi_freq_table[i][0]) { + clk_cfg = bcm63xx_spi_freq_table[i][1]; + break; + } + } + + /* No matching configuration found, default to lowest */ + if (i == SPI_CLK_MASK) + clk_cfg = SPI_CLK_0_391MHZ; + + /* clear existing clock configuration bits of the register */ + reg = bcm_spi_readb(bs, SPI_CLK_CFG); + reg &= ~SPI_CLK_MASK; + reg |= clk_cfg; + + bcm_spi_writeb(bs, reg, SPI_CLK_CFG); + dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", + clk_cfg, hz); + + return 0; +} + +/* the spi->mode bits understood by this driver: */ +#define MODEBITS (SPI_CPOL | SPI_CPHA) + +static int bcm63xx_spi_setup(struct spi_device *spi) +{ + struct bcm63xx_spi *bs; + int ret; + + bs = spi_master_get_devdata(spi->master); + + if (bs->stopping) + return -ESHUTDOWN; + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + if (spi->mode & ~MODEBITS) { + dev_err(&spi->dev, "%s, unsupported mode bits %x\n", + __func__, spi->mode & ~MODEBITS); + return -EINVAL; + } + + ret = bcm63xx_spi_setup_transfer(spi, NULL); + if (ret < 0) { + dev_err(&spi->dev, "setup: unsupported mode bits %x\n", + spi->mode & ~MODEBITS); + return ret; + } + + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0); + + return 0; +} + +/* Fill the TX FIFO with as many bytes as possible */ +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs) +{ + u8 size; + + /* Fill the Tx FIFO with as many bytes as possible */ + size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes : + bs->fifo_size; + memcpy_toio(bs->tx_io, bs->tx_ptr, size); + bs->remaining_bytes -= size; +} + +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) +{ + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); + u16 msg_ctl; + u16 cmd; + + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", + t->tx_buf, t->rx_buf, t->len); + + /* Transmitter is inhibited */ + bs->tx_ptr = t->tx_buf; + bs->rx_ptr = t->rx_buf; + init_completion(&bs->done); + + if (t->tx_buf) { + bs->remaining_bytes = t->len; + bcm63xx_spi_fill_tx_fifo(bs); + } + + /* Enable the command done interrupt which + * we use to determine completion of a command */ + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); + + /* Fill in the Message control register */ + msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); + + if (t->rx_buf && t->tx_buf) + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT); + else if (t->rx_buf) + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT); + else if (t->tx_buf) + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT); + + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); + + /* Issue the transfer */ + cmd = SPI_CMD_START_IMMEDIATE; + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); + cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); + bcm_spi_writew(bs, cmd, SPI_CMD); + wait_for_completion(&bs->done); + + /* Disable the CMD_DONE interrupt */ + bcm_spi_writeb(bs, 0, SPI_INT_MASK); + + return t->len - bs->remaining_bytes; +} + +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m) +{ + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); + struct spi_transfer *t; + int ret = 0; + + if (unlikely(list_empty(&m->transfers))) + return -EINVAL; + + if (bs->stopping) + return -ESHUTDOWN; + + list_for_each_entry(t, &m->transfers, transfer_list) { + ret += bcm63xx_txrx_bufs(spi, t); + } + + m->complete(m->context); + + return ret; +} + +/* This driver supports single master mode only. Hence + * CMD_DONE is the only interrupt we care about + */ +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) +{ + struct spi_master *master = (struct spi_master *)dev_id; + struct bcm63xx_spi *bs = spi_master_get_devdata(master); + u8 intr; + u16 cmd; + + /* Read interupts and clear them immediately */ + intr = bcm_spi_readb(bs, SPI_INT_STATUS); + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); + bcm_spi_writeb(bs, 0, SPI_INT_MASK); + + /* A tansfer completed */ + if (intr & SPI_INTR_CMD_DONE) { + u8 rx_tail; + + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); + + /* Read out all the data */ + if (rx_tail) + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail); + + /* See if there is more data to send */ + if (bs->remaining_bytes > 0) { + bcm63xx_spi_fill_tx_fifo(bs); + + /* Start the transfer */ + bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT, + SPI_MSG_CTL); + cmd = bcm_spi_readw(bs, SPI_CMD); + cmd |= SPI_CMD_START_IMMEDIATE; + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); + bcm_spi_writew(bs, cmd, SPI_CMD); + } else { + complete(&bs->done); + } + } + + return IRQ_HANDLED; +} + + +static int __init bcm63xx_spi_probe(struct platform_device *pdev) +{ + struct resource *r; + struct device *dev = &pdev->dev; + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data; + int irq; + struct spi_master *master; + struct clk *clk; + struct bcm63xx_spi *bs; + int ret; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(dev, "no iomem\n"); + ret = -ENXIO; + goto out; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "no irq\n"); + ret = -ENXIO; + goto out; + } + + clk = clk_get(dev, "spi"); + if (IS_ERR(clk)) { + dev_err(dev, "no clock for device\n"); + ret = PTR_ERR(clk); + goto out; + } + + master = spi_alloc_master(dev, sizeof(*bs)); + if (!master) { + dev_err(dev, "out of memory\n"); + ret = -ENOMEM; + goto out_clk; + } + + bs = spi_master_get_devdata(master); + init_completion(&bs->done); + + platform_set_drvdata(pdev, master); + bs->pdev = pdev; + + if (!devm_request_mem_region(&pdev->dev, r->start, + resource_size(r), PFX)) { + dev_err(dev, "iomem request failed\n"); + ret = -ENXIO; + goto out_err; + } + + bs->regs = devm_ioremap_nocache(&pdev->dev, r->start, + resource_size(r)); + if (!bs->regs) { + dev_err(dev, "unable to ioremap regs\n"); + ret = -ENOMEM; + goto out_err; + } + + bs->irq = irq; + bs->clk = clk; + bs->fifo_size = pdata->fifo_size; + + ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, + pdev->name, master); + if (ret) { + dev_err(dev, "unable to request irq\n"); + goto out_err; + } + + master->bus_num = pdata->bus_num; + master->num_chipselect = pdata->num_chipselect; + master->setup = bcm63xx_spi_setup; + master->transfer = bcm63xx_transfer; + bs->speed_hz = pdata->speed_hz; + bs->stopping = 0; + bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); + bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); + spin_lock_init(&bs->lock); + + /* Initialize hardware */ + clk_enable(bs->clk); + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); + + /* register and we are done */ + ret = spi_register_master(master); + if (ret) { + dev_err(dev, "spi register failed\n"); + goto out_clk_disable; + } + + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n", + r->start, irq, bs->fifo_size, DRV_VER); + + return 0; + +out_clk_disable: + clk_disable(clk); +out_err: + platform_set_drvdata(pdev, NULL); + spi_master_put(master); +out_clk: + clk_put(clk); +out: + return ret; +} + +static int __exit bcm63xx_spi_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcm63xx_spi *bs = spi_master_get_devdata(master); + + /* reset spi block */ + bcm_spi_writeb(bs, 0, SPI_INT_MASK); + spin_lock(&bs->lock); + bs->stopping = 1; + + /* HW shutdown */ + clk_disable(bs->clk); + clk_put(bs->clk); + + spin_unlock(&bs->lock); + platform_set_drvdata(pdev, 0); + spi_unregister_master(master); + + return 0; +} + +#ifdef CONFIG_PM +static int bcm63xx_spi_suspend(struct device *dev) +{ + struct spi_master *master = + platform_get_drvdata(to_platform_device(dev)); + struct bcm63xx_spi *bs = spi_master_get_devdata(master); + + clk_disable(bs->clk); + + return 0; +} + +static int bcm63xx_spi_resume(struct device *dev) +{ + struct spi_master *master = + platform_get_drvdata(to_platform_device(dev)); + struct bcm63xx_spi *bs = spi_master_get_devdata(master); + + clk_enable(bs->clk); + + return 0; +} + +static const struct dev_pm_ops bcm63xx_spi_pm_ops = { + .suspend = bcm63xx_spi_suspend, + .resume = bcm63xx_spi_resume, +}; + +#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) +#else +#define BCM63XX_SPI_PM_OPS NULL +#endif + +static struct platform_driver bcm63xx_spi_driver = { + .driver = { + .name = "bcm63xx-spi", + .owner = THIS_MODULE, + .pm = BCM63XX_SPI_PM_OPS, + }, + .probe = bcm63xx_spi_probe, + .remove = __exit_p(bcm63xx_spi_remove), +}; + +module_platform_driver(bcm63xx_spi_driver); + +MODULE_ALIAS("platform:bcm63xx_spi"); +MODULE_AUTHOR("Florian Fainelli "); +MODULE_AUTHOR("Tanguy Bouzeloc "); +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); +MODULE_LICENSE("GPL"); -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:12:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:15:16 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59750 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904023Ab2AaOMs (ORCPT ); Tue, 31 Jan 2012 15:12:48 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 1245835E45B; Tue, 31 Jan 2012 15:12:48 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UqYWwCursDvm; Tue, 31 Jan 2012 15:12:47 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id A65CD31C642; Tue, 31 Jan 2012 15:12:47 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au, Florian Fainelli Subject: [PATCH 0/5 v2] MIPS: BCM63XX: add support for hardware RNG Date: Tue, 31 Jan 2012 15:12:20 +0100 Message-Id: <1328019145-5946-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32358 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1191 Lines: 28 This patch set depends on the serie "MIPS: BCM63XX: add support for SPI" and adds support for the RNG block found in BCM6368 SoCs. Herbert, Matt, this will probably better to get this merged via the MIPS tree considering the patches it depends on. Florian Fainelli (5): MIPS: BCM63XX: fix BCM6368 IPSec clock bit MIPS: BCM63XX: add support for "ipsec" clock MIPS: BCM63XX: add RNG peripheral definitions MIPS: BCM63XX: add RNG driver platform_device stub hw_random: add Broadcom BCM63xx RNG driver arch/mips/bcm63xx/Makefile | 4 +- arch/mips/bcm63xx/clk.c | 14 ++ arch/mips/bcm63xx/dev-rng.c | 40 +++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 ++- drivers/char/hw_random/Kconfig | 14 ++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/bcm63xx-rng.c | 175 +++++++++++++++++++++ 8 files changed, 270 insertions(+), 3 deletions(-) create mode 100644 arch/mips/bcm63xx/dev-rng.c create mode 100644 drivers/char/hw_random/bcm63xx-rng.c -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:12:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:15:42 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59754 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904034Ab2AaOMs (ORCPT ); Tue, 31 Jan 2012 15:12:48 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 2E3CD35F3C7; Tue, 31 Jan 2012 15:12:48 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0xgFGtqluBeS; Tue, 31 Jan 2012 15:12:47 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id AB2B1326BFA; Tue, 31 Jan 2012 15:12:47 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au, Florian Fainelli Subject: [PATCH 1/5 v2] MIPS: BCM63XX: fix BCM6368 IPSec clock bit Date: Tue, 31 Jan 2012 15:12:21 +0100 Message-Id: <1328019145-5946-2-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019145-5946-1-git-send-email-florian@openwrt.org> References: <1328019145-5946-1-git-send-email-florian@openwrt.org> X-archive-position: 32359 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 867 Lines: 26 The IPsec clock bit is 18 and not 17. Signed-off-by: Florian Fainelli --- Changes since v1: - rebased against "MIPS: BCM63XX: misc cleanup" arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index c21aa34..be107e9 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -99,7 +99,7 @@ #define CKCTL_6368_USBH_EN (1 << 15) #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) #define CKCTL_6368_NAND_EN (1 << 17) -#define CKCTL_6368_IPSEC_EN (1 << 17) +#define CKCTL_6368_IPSEC_EN (1 << 18) #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ CKCTL_6368_SWPKT_SAR_EN | \ -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:12:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:16:11 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59760 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904036Ab2AaOMs (ORCPT ); Tue, 31 Jan 2012 15:12:48 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 467B635D006; Tue, 31 Jan 2012 15:12:48 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FLXBmDzUp8xV; Tue, 31 Jan 2012 15:12:47 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id B6117358976; Tue, 31 Jan 2012 15:12:47 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au, Florian Fainelli Subject: [PATCH 2/5 v2] MIPS: BCM63XX: add support for "ipsec" clock Date: Tue, 31 Jan 2012 15:12:22 +0100 Message-Id: <1328019145-5946-3-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019145-5946-1-git-send-email-florian@openwrt.org> References: <1328019145-5946-1-git-send-email-florian@openwrt.org> X-archive-position: 32360 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1070 Lines: 46 This module is only available on BCM6368 so far and does not require resetting the block. Signed-off-by: Florian Fainelli --- Changes since v1: - rebased against "MIPS: BCM63XX: misc cleanup" arch/mips/bcm63xx/clk.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index be49b9a..1db48ad 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -224,6 +224,18 @@ static struct clk clk_xtm = { }; /* + * IPsec clock + */ +static void ipsec_set(struct clk *clk, int enable) +{ + bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable); +} + +static struct clk clk_ipsec = { + .set = ipsec_set, +}; + +/* * Internal peripheral clock */ static struct clk clk_periph = { @@ -280,6 +292,8 @@ struct clk *clk_get(struct device *dev, const char *id) return &clk_periph; if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) return &clk_pcm; + if (BCMCPU_IS_6368() && !strcmp(id, "ipsec")) + return &clk_ipsec; return ERR_PTR(-ENOENT); } -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:12:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:16:39 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59758 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904037Ab2AaOMs (ORCPT ); Tue, 31 Jan 2012 15:12:48 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 38297326BFA; Tue, 31 Jan 2012 15:12:48 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vgo0MeURhd-C; Tue, 31 Jan 2012 15:12:47 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id D16BD35D006; Tue, 31 Jan 2012 15:12:47 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au, Florian Fainelli Subject: [PATCH 4/5 v2] MIPS: BCM63XX: add RNG driver platform_device stub Date: Tue, 31 Jan 2012 15:12:24 +0100 Message-Id: <1328019145-5946-5-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019145-5946-1-git-send-email-florian@openwrt.org> References: <1328019145-5946-1-git-send-email-florian@openwrt.org> X-archive-position: 32361 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2124 Lines: 73 Signed-off-by: Florian Fainelli --- Changes since v1: - renamed TRNG -> RNG, trng -> rng - fixed platform_device identifier since there is only one device arch/mips/bcm63xx/Makefile | 4 ++-- arch/mips/bcm63xx/dev-rng.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 2 deletions(-) create mode 100644 arch/mips/bcm63xx/dev-rng.c diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 4049cd5..349b206 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,6 +1,6 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ - dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \ - dev-wdt.o + dev-dsp.o dev-enet.o dev-pcmcia.o dev-rng.o dev-spi.o \ + dev-uart.o dev-wdt.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/dev-rng.c b/arch/mips/bcm63xx/dev-rng.c new file mode 100644 index 0000000..d277b4d --- /dev/null +++ b/arch/mips/bcm63xx/dev-rng.c @@ -0,0 +1,40 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Florian Fainelli + */ + +#include +#include +#include +#include + +static struct resource rng_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device bcm63xx_rng_device = { + .name = "bcm63xx-rng", + .id = -1, + .num_resources = ARRAY_SIZE(rng_resources), + .resource = rng_resources, +}; + +int __init bcm63xx_rng_register(void) +{ + if (!BCMCPU_IS_6368()) + return -ENODEV; + + rng_resources[0].start = bcm63xx_regset_address(RSET_RNG); + rng_resources[0].end = rng_resources[0].start; + rng_resources[0].end += RSET_RNG_SIZE - 1; + + return platform_device_register(&bcm63xx_rng_device); +} +arch_initcall(bcm63xx_rng_register); -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:12:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:17:04 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59765 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904038Ab2AaOMs (ORCPT ); Tue, 31 Jan 2012 15:12:48 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 68D66358976; Tue, 31 Jan 2012 15:12:48 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id roZ35Ixyb7dv; Tue, 31 Jan 2012 15:12:47 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id BE30E338ACE; Tue, 31 Jan 2012 15:12:47 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au, Florian Fainelli Subject: [PATCH 3/5 v2] MIPS: BCM63XX: add RNG peripheral definitions Date: Tue, 31 Jan 2012 15:12:23 +0100 Message-Id: <1328019145-5946-4-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019145-5946-1-git-send-email-florian@openwrt.org> References: <1328019145-5946-1-git-send-email-florian@openwrt.org> X-archive-position: 32362 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 3644 Lines: 111 Signed-off-by: Florian Fainelli --- Changes since v1: - renamed TRNG -> RNG to be consistent everywhere arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 +++++++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 14 ++++++++++++++ 2 files changed, 23 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 82a8175..0c981aa 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -129,6 +129,7 @@ enum bcm63xx_regs_set { RSET_PCMDMA, RSET_PCMDMAC, RSET_PCMDMAS, + RSET_RNG }; #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) @@ -152,6 +153,7 @@ enum bcm63xx_regs_set { #define RSET_XTMDMA_SIZE 256 #define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) #define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) +#define RSET_RNG_SIZE 20 /* * 6338 register sets base address @@ -195,6 +197,7 @@ enum bcm63xx_regs_set { #define BCM_6338_PCMDMA_BASE (0xdeadbeef) #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) +#define BCM_6338_RNG_BASE (0xdeadbeef) /* * 6345 register sets base address @@ -238,6 +241,7 @@ enum bcm63xx_regs_set { #define BCM_6345_PCMDMA_BASE (0xdeadbeef) #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) +#define BCM_6345_RNG_BASE (0xdeadbeef) /* * 6348 register sets base address @@ -278,6 +282,7 @@ enum bcm63xx_regs_set { #define BCM_6348_PCMDMA_BASE (0xdeadbeef) #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) +#define BCM_6348_RNG_BASE (0xdeadbeef) /* * 6358 register sets base address @@ -318,6 +323,7 @@ enum bcm63xx_regs_set { #define BCM_6358_PCMDMA_BASE (0xfffe1800) #define BCM_6358_PCMDMAC_BASE (0xfffe1900) #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) +#define BCM_6358_RNG_BASE (0xdeadbeef) /* @@ -359,6 +365,7 @@ enum bcm63xx_regs_set { #define BCM_6368_PCMDMA_BASE (0xb0005800) #define BCM_6368_PCMDMAC_BASE (0xb0005a00) #define BCM_6368_PCMDMAS_BASE (0xb0005c00) +#define BCM_6368_RNG_BASE (0xb0004180) extern const unsigned long *bcm63xx_regs_base; @@ -404,6 +411,7 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, PCMDMA) \ __GEN_RSET_BASE(__cpu, PCMDMAC) \ __GEN_RSET_BASE(__cpu, PCMDMAS) \ + __GEN_RSET_BASE(__cpu, RNG) \ } #define __GEN_CPU_REGS_TABLE(__cpu) \ @@ -442,6 +450,7 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ + [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index be107e9..6fdde35 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -1092,4 +1092,18 @@ #define SPI_SSOFFTIME_SHIFT 3 #define SPI_BYTE_SWAP 0x80 +/************************************************************************* + * _REG relative to RSET_RNG + *************************************************************************/ + +#define RNG_CTRL 0x00 +#define RNG_EN (1 << 0) + +#define RNG_STAT 0x04 +#define RNG_AVAIL_MASK (0xff000000) + +#define RNG_DATA 0x08 +#define RNG_THRES 0x0c +#define RNG_MASK 0x10 + #endif /* BCM63XX_REGS_H_ */ -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 15:12:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 15:17:30 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:59770 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904039Ab2AaOMs (ORCPT ); Tue, 31 Jan 2012 15:12:48 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 94310338ACE; Tue, 31 Jan 2012 15:12:48 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WIlvhfEDoGMp; Tue, 31 Jan 2012 15:12:48 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id D76FB35D627; Tue, 31 Jan 2012 15:12:47 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au, Florian Fainelli Subject: [PATCH 5/5 v2] hw_random: add Broadcom BCM63xx RNG driver Date: Tue, 31 Jan 2012 15:12:25 +0100 Message-Id: <1328019145-5946-6-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328019145-5946-1-git-send-email-florian@openwrt.org> References: <1328019145-5946-1-git-send-email-florian@openwrt.org> X-archive-position: 32363 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5902 Lines: 232 Signed-off-by: Florian Fainelli --- Changes since v1: - renamed TRNG -> RNG and trng -> rng drivers/char/hw_random/Kconfig | 14 +++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/bcm63xx-rng.c | 175 ++++++++++++++++++++++++++++++++++ 3 files changed, 190 insertions(+), 0 deletions(-) create mode 100644 drivers/char/hw_random/bcm63xx-rng.c diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 0689bf6..f29d1bc 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -73,6 +73,20 @@ config HW_RANDOM_ATMEL If unsure, say Y. +config HW_RANDOM_BCM63XX + tristate "Broadcom BCM63xx Random Number Generator support" + depends on HW_RANDOM && BCM63XX + default HW_RANDOM + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on the Broadcom BCM63xx SoCs. + + To compile this driver as a module, choose M here: the + module will be called bcm63xx-rng + + If unusure, say Y. + + config HW_RANDOM_GEODE tristate "AMD Geode HW Random Number Generator support" depends on HW_RANDOM && X86_32 && PCI diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index b2ff526..8cfac60 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o +obj-$(CONFIG_HW_RANDOM_BCM63XX) += bcm63xx-rng.o obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o n2-rng-y := n2-drv.o n2-asm.o diff --git a/drivers/char/hw_random/bcm63xx-rng.c b/drivers/char/hw_random/bcm63xx-rng.c new file mode 100644 index 0000000..b789dbf --- /dev/null +++ b/drivers/char/hw_random/bcm63xx-rng.c @@ -0,0 +1,175 @@ +/* + * Broadcom BCM63xx Random Number Generator support + * + * Copyright (C) 2011, Florian Fainelli + * Copyright (C) 2009, Broadcom Corporation + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct bcm63xx_rng_priv { + struct clk *clk; + void __iomem *regs; +}; + +#define to_rng_priv(rng) ((struct bcm63xx_rng_priv *)rng->priv) + +static int bcm63xx_rng_init(struct hwrng *rng) +{ + struct bcm63xx_rng_priv *priv = to_rng_priv(rng); + u32 val; + + val = bcm_readl(priv->regs + RNG_CTRL); + val |= RNG_EN; + bcm_writel(val, priv->regs + RNG_CTRL); + + return 0; +} + +static void bcm63xx_rng_cleanup(struct hwrng *rng) +{ + struct bcm63xx_rng_priv *priv = to_rng_priv(rng); + u32 val; + + val = bcm_readl(priv->regs + RNG_CTRL); + val &= ~RNG_EN; + bcm_writel(val, priv->regs + RNG_CTRL); +} + +static int bcm63xx_rng_data_present(struct hwrng *rng, int wait) +{ + struct bcm63xx_rng_priv *priv = to_rng_priv(rng); + + return bcm_readl(priv->regs + RNG_STAT) & RNG_AVAIL_MASK; +} + +static int bcm63xx_rng_data_read(struct hwrng *rng, u32 *data) +{ + struct bcm63xx_rng_priv *priv = to_rng_priv(rng); + + *data = bcm_readl(priv->regs + RNG_DATA); + + return 4; +} + +static int __init bcm63xx_rng_probe(struct platform_device *pdev) +{ + struct resource *r; + struct clk *clk; + int ret; + struct bcm63xx_rng_priv *priv; + struct hwrng *rng; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no iomem resource\n"); + ret = -ENXIO; + goto out; + } + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(&pdev->dev, "no memory for private structure\n"); + ret = -ENOMEM; + goto out; + } + + rng = kzalloc(sizeof(*rng), GFP_KERNEL); + if (!rng) { + dev_err(&pdev->dev, "no memory for rng structure\n"); + ret = -ENOMEM; + goto out_free_priv; + } + + platform_set_drvdata(pdev, rng); + rng->priv = (unsigned long)priv; + rng->name = pdev->name; + rng->init = bcm63xx_rng_init; + rng->cleanup = bcm63xx_rng_cleanup; + rng->data_present = bcm63xx_rng_data_present; + rng->data_read = bcm63xx_rng_data_read; + + clk = clk_get(&pdev->dev, "ipsec"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "no clock for device\n"); + ret = PTR_ERR(clk); + goto out_free_rng; + } + + priv->clk = clk; + + if (!devm_request_mem_region(&pdev->dev, r->start, + resource_size(r), pdev->name)) { + dev_err(&pdev->dev, "request mem failed"); + ret = -ENOMEM; + goto out_free_rng; + } + + priv->regs = devm_ioremap_nocache(&pdev->dev, r->start, + resource_size(r)); + if (!priv->regs) { + dev_err(&pdev->dev, "ioremap failed"); + ret = -ENOMEM; + goto out_free_rng; + } + + clk_enable(clk); + + ret = hwrng_register(rng); + if (ret) { + dev_err(&pdev->dev, "failed to register rng device\n"); + goto out_clk_disable; + } + + dev_info(&pdev->dev, "registered RNG driver\n"); + + return 0; + +out_clk_disable: + clk_disable(clk); +out_free_rng: + platform_set_drvdata(pdev, NULL); + kfree(rng); +out_free_priv: + kfree(priv); +out: + return ret; +} + +static int __devexit bcm63xx_rng_remove(struct platform_device *pdev) +{ + struct hwrng *rng = platform_get_drvdata(pdev); + struct bcm63xx_rng_priv *priv = to_rng_priv(rng); + + hwrng_unregister(rng); + clk_disable(priv->clk); + kfree(priv); + kfree(rng); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver bcm63xx_rng_driver = { + .probe = bcm63xx_rng_probe, + .remove = __devexit_p(bcm63xx_rng_remove), + .driver = { + .name = "bcm63xx-rng", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(bcm63xx_rng_driver); + +MODULE_AUTHOR("Florian Fainelli "); +MODULE_DESCRIPTION("Broadcom BCM63xx RNG driver"); +MODULE_LICENSE("GPL"); -- 1.7.5.4 From arnd@arndb.de Tue Jan 31 17:00:03 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 17:00:09 +0100 (CET) Received: from moutng.kundenserver.de ([212.227.17.8]:49294 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904020Ab2AaQAD (ORCPT ); Tue, 31 Jan 2012 17:00:03 +0100 Received: from klappe2.localnet (deibp9eh1--blueice3n2.emea.ibm.com [195.212.29.180]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0Ll22r-1SSxmE1vRV-00aNLU; Tue, 31 Jan 2012 16:59:27 +0100 From: Arnd Bergmann To: "Michael S. Tsirkin" Subject: Re: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP Date: Tue, 31 Jan 2012 15:59:25 +0000 User-Agent: KMail/1.12.2 (Linux/3.3.0-rc1; KDE/4.3.2; x86_64; ; ) Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org References: <201201302004.33083.arnd@arndb.de> <20120131002203.GA14344@redhat.com> In-Reply-To: <20120131002203.GA14344@redhat.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201201311559.26050.arnd@arndb.de> X-Provags-ID: V02:K0:5unnTK8DY+pSXKJjyVKmUK1M6m9dlrxePP5EZqGBVFx QV18CtY7T6d+IeJJJCq+wVShQDnjlxVKGldTEfJ6eC1v9TFKmP o2FeUeWbWWqp3OZsOc2o4RxadowXInGyAfwtalJ45rdjt2m2WH A+KS3h1YHN1dSObRrAJBpwLYM0Ru8Y0JXVpzQfy83dzm+fvFhX Qtd0djvLe8cCqYjsvEw3XY93Mqn6q23+1WXSCgZ54sexf5RZ+o /T1A3ia82jgv68qmhofYwcvAryFZeX4lk5oNTxH7aAAzybFbhv 1N10cSAbaaZ1UimrWldnaKIEahh5JKXKPPfHtSEg1dJXn5z3+6 N4aDMWITUjtA2IreCvdk= X-archive-position: 32364 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arnd@arndb.de Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 798 Lines: 18 On Tuesday 31 January 2012, Michael S. Tsirkin wrote: > I have an idea: we can make the generic one inline > if we keep it in the .c file. So something like > the below on top of my patch will probably work. > Ack? IMHO this is still worse than the macro, because it breaks common practice. The common way to do this is #ifdef/#else/#endif in the header file to provide either an extern or a macro/inline definition, while having the inline definition in a separate place makes it harder to understand what's going on. E.g. a frequent review comment is to not put extern declarations inside of #ifdef, but if someone tries that here, it would break. You also still need the #ifdef in the implementation file, which we try to avoid normally just like we try to avoid macros where possible. Arnd From florian@openwrt.org Tue Jan 31 18:19:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:19:17 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:58205 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904023Ab2AaRTK (ORCPT ); Tue, 31 Jan 2012 18:19:10 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 05184447ED0; Tue, 31 Jan 2012 18:19:10 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kFhKSMTsNnH7; Tue, 31 Jan 2012 18:19:09 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 9C02A434D36; Tue, 31 Jan 2012 18:19:09 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 3/3 v4] MIPS: introduce CPU_R4K_CACHE_TLB Date: Tue, 31 Jan 2012 18:18:45 +0100 Message-Id: <1328030325-21918-3-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328030325-21918-1-git-send-email-florian@openwrt.org> References: <1328030325-21918-1-git-send-email-florian@openwrt.org> X-archive-position: 32365 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2627 Lines: 68 R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: Florian Fainelli --- Changes since v2/v3: - rebased against mips-for-linux-next (remove XLP) Changes since v1: - removed CPU_XLR already covered by CPU_R4K_CACHE_TLB - add back CPU_R8000 to Kconfig exception list and Makefile arch/mips/Kconfig | 4 ++++ arch/mips/mm/Makefile | 17 +---------------- 2 files changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3367ce2..6f08f64 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1847,6 +1847,10 @@ config CPU_R4K_FPU bool default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) +config CPU_R4K_CACHE_TLB + bool + default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + choice prompt "MIPS MT options" diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 4aa2028..29ca3df 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -11,27 +11,12 @@ obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o -obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o -obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o -obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o -obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o -obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o -obj-$(CONFIG_CPU_XLP) += c-r4k.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:19:40 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:58204 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904020Ab2AaRTK (ORCPT ); Tue, 31 Jan 2012 18:19:10 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id E571D448589; Tue, 31 Jan 2012 18:19:09 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id s8E6qLNAvTnj; Tue, 31 Jan 2012 18:19:09 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 7E0A9447ED0; Tue, 31 Jan 2012 18:19:09 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 1/3 v4] MIPS: introduce CPU_GENERIC_DUMP_TLB Date: Tue, 31 Jan 2012 18:18:43 +0100 Message-Id: <1328030325-21918-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32366 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2101 Lines: 66 Allows us not to duplicate more lines in arch/mips/lib/Makefile. Signed-off-by: Florian Fainelli --- Changes since v3: - change patch subjet to match introduced Kconfig symbol Changes since v2: - rebased against mips-for-linux-next (remove XLR & XLP) arch/mips/Kconfig | 4 ++++ arch/mips/lib/Makefile | 21 +-------------------- 2 files changed, 5 insertions(+), 20 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c4c1312..0a52846 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1839,6 +1839,10 @@ config SIBYTE_DMA_PAGEOPS config CPU_HAS_PREFETCH bool +config CPU_GENERIC_DUMP_TLB + bool + default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX) + choice prompt "MIPS MT options" diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 2a7c74f..d8c290c 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -8,28 +8,9 @@ lib-y += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \ obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o -obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o -obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o -obj-$(CONFIG_CPU_R10000) += dump_tlb.o +obj-$(CONFIG_CPU_GENERIC_DUMP_TLB) += dump_tlb.o obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o -obj-$(CONFIG_CPU_R4300) += dump_tlb.o -obj-$(CONFIG_CPU_R4X00) += dump_tlb.o -obj-$(CONFIG_CPU_R5000) += dump_tlb.o -obj-$(CONFIG_CPU_R5432) += dump_tlb.o -obj-$(CONFIG_CPU_R5500) += dump_tlb.o -obj-$(CONFIG_CPU_R6000) += -obj-$(CONFIG_CPU_R8000) += -obj-$(CONFIG_CPU_RM7000) += dump_tlb.o -obj-$(CONFIG_CPU_RM9000) += dump_tlb.o -obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o -obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o -obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o -obj-$(CONFIG_CPU_XLR) += dump_tlb.o -obj-$(CONFIG_CPU_XLP) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:20:02 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:58208 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904026Ab2AaRTK (ORCPT ); Tue, 31 Jan 2012 18:19:10 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 4DBA9434D36; Tue, 31 Jan 2012 18:19:10 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id H+McPc0RyNkL; Tue, 31 Jan 2012 18:19:09 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 88E4D447FD8; Tue, 31 Jan 2012 18:19:09 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 2/3 v4] MIPS: introduce CPU_R4K_FPU Date: Tue, 31 Jan 2012 18:18:44 +0100 Message-Id: <1328030325-21918-2-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328030325-21918-1-git-send-email-florian@openwrt.org> References: <1328030325-21918-1-git-send-email-florian@openwrt.org> X-archive-position: 32367 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2413 Lines: 67 R4K-style CPUs have this boolean defined by default. Allows us to remove some lines in arch/mips/kernel/Makefile. Signed-off-by: Florian Fainelli --- Changes since v2/v3: - rebased against mips-for-linux-next Changes since v1: - removed CPU_XLR already covered by CPU_R4K_FPU arch/mips/Kconfig | 4 ++++ arch/mips/kernel/Makefile | 19 +------------------ 2 files changed, 5 insertions(+), 18 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0a52846..3367ce2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1843,6 +1843,10 @@ config CPU_GENERIC_DUMP_TLB bool default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX) +config CPU_R4K_FPU + bool + default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + choice prompt "MIPS MT options" diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 0c6877e..3d33c85 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -34,28 +34,11 @@ obj-$(CONFIG_MODULES) += mips_ksyms.o module.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o -obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5500) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o -obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_XLP) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:20:26 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:57801 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904028Ab2AaRTa (ORCPT ); Tue, 31 Jan 2012 18:19:30 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 532C14486D5; Tue, 31 Jan 2012 18:19:30 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uDyN5xSghHYw; Tue, 31 Jan 2012 18:19:30 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id E317B44775B; Tue, 31 Jan 2012 18:19:29 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 1/6] MIPS: Alchemy: use IS_ENABLED() macro Date: Tue, 31 Jan 2012 18:19:03 +0100 Message-Id: <1328030348-21967-2-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328030348-21967-1-git-send-email-florian@openwrt.org> References: <1328030348-21967-1-git-send-email-florian@openwrt.org> X-archive-position: 32368 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2580 Lines: 71 Signed-off-by: Florian Fainelli --- arch/mips/alchemy/board-mtx1.c | 4 ++-- arch/mips/alchemy/devboards/pb1100.c | 4 ++-- arch/mips/alchemy/devboards/pb1500.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c index 295f1a9..9996948 100644 --- a/arch/mips/alchemy/board-mtx1.c +++ b/arch/mips/alchemy/board-mtx1.c @@ -81,10 +81,10 @@ static void mtx1_power_off(void) void __init board_setup(void) { -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_OHCI_HCD) /* Enable USB power switch */ alchemy_gpio_direction_output(204, 0); -#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ +#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */ /* Initialize sys_pinfunc */ au_writel(SYS_PF_NI2, SYS_PINFUNC); diff --git a/arch/mips/alchemy/devboards/pb1100.c b/arch/mips/alchemy/devboards/pb1100.c index cff50d0..78c77a4 100644 --- a/arch/mips/alchemy/devboards/pb1100.c +++ b/arch/mips/alchemy/devboards/pb1100.c @@ -46,7 +46,7 @@ void __init board_setup(void) alchemy_gpio1_input_enable(); udelay(100); -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_OHCI_HCD) { u32 pin_func, sys_freqctrl, sys_clksrc; @@ -93,7 +93,7 @@ void __init board_setup(void) pin_func |= SYS_PF_USB; au_writel(pin_func, SYS_PINFUNC); } -#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ +#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */ /* Enable sys bus clock divider when IDLE state or no bus activity. */ au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); diff --git a/arch/mips/alchemy/devboards/pb1500.c b/arch/mips/alchemy/devboards/pb1500.c index e7b807b..232fee9 100644 --- a/arch/mips/alchemy/devboards/pb1500.c +++ b/arch/mips/alchemy/devboards/pb1500.c @@ -53,7 +53,7 @@ void __init board_setup(void) alchemy_gpio_direction_input(201); alchemy_gpio_direction_input(203); -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_OHCI_HCD) /* Zero and disable FREQ2 */ sys_freqctrl = au_readl(SYS_FREQCTRL0); @@ -87,7 +87,7 @@ void __init board_setup(void) /* 2nd USB port is USB host */ pin_func |= SYS_PF_USB; au_writel(pin_func, SYS_PINFUNC); -#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ +#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */ #ifdef CONFIG_PCI { -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:20:51 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:57804 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904029Ab2AaRTa (ORCPT ); Tue, 31 Jan 2012 18:19:30 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 61EA44488F3; Tue, 31 Jan 2012 18:19:30 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id skt2pfyVmwvc; Tue, 31 Jan 2012 18:19:30 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 047AB44848A; Tue, 31 Jan 2012 18:19:30 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 2/6] MIPS: PNX833x: use IS_ENABLED() macro Date: Tue, 31 Jan 2012 18:19:04 +0100 Message-Id: <1328030348-21967-3-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328030348-21967-1-git-send-email-florian@openwrt.org> References: <1328030348-21967-1-git-send-email-florian@openwrt.org> X-archive-position: 32369 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1020 Lines: 30 Signed-off-by: Florian Fainelli --- arch/mips/pnx833x/stb22x/board.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c index 644eb7c..4b328ac 100644 --- a/arch/mips/pnx833x/stb22x/board.c +++ b/arch/mips/pnx833x/stb22x/board.c @@ -91,7 +91,7 @@ void __init pnx833x_board_setup(void) pnx833x_gpio_select_function_alt(32); pnx833x_gpio_select_function_alt(33); -#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) +#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM) /* Setup MIU for NAND access on CS0... * * (it seems that we must also configure CS1 for reliable operation, @@ -117,7 +117,7 @@ void __init pnx833x_board_setup(void) pnx833x_gpio_select_output(5); pnx833x_gpio_write(1, 5); -#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE) +#elif IS_ENABLED(CONFIG_MTD_CFI) /* Set up MIU for 16-bit NOR access on CS0 and CS1... */ -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:21:14 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:57812 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904034Ab2AaRTb (ORCPT ); Tue, 31 Jan 2012 18:19:31 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id B0517448294; Tue, 31 Jan 2012 18:19:30 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rNAqKFTf4ZSk; Tue, 31 Jan 2012 18:19:30 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 234BA4487EA; Tue, 31 Jan 2012 18:19:30 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 5/6] MIPS: DEC: use IS_ENABLED() Date: Tue, 31 Jan 2012 18:19:07 +0100 Message-Id: <1328030348-21967-6-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328030348-21967-1-git-send-email-florian@openwrt.org> References: <1328030348-21967-1-git-send-email-florian@openwrt.org> X-archive-position: 32370 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 631 Lines: 21 Signed-off-by: Florian Fainelli --- arch/mips/dec/prom/memory.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c index e95ff30..8c62316 100644 --- a/arch/mips/dec/prom/memory.c +++ b/arch/mips/dec/prom/memory.c @@ -101,7 +101,7 @@ void __init prom_free_prom_memory(void) * the first page reserved for the exception handlers. */ -#if defined(CONFIG_DECLANCE) || defined(CONFIG_DECLANCE_MODULE) +#if IS_ENABLED(CONFIG_DECLANCE) /* * Leave 128 KB reserved for Lance memory for * IOASIC DECstations. -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:21:37 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:57811 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904033Ab2AaRTb (ORCPT ); Tue, 31 Jan 2012 18:19:31 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 9F02144775B; Tue, 31 Jan 2012 18:19:30 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6hXin7x7tuyv; Tue, 31 Jan 2012 18:19:30 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 092A3448589; Tue, 31 Jan 2012 18:19:30 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 3/6] MIPS: TXX9: use IS_ENABLED() macro Date: Tue, 31 Jan 2012 18:19:05 +0100 Message-Id: <1328030348-21967-4-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328030348-21967-1-git-send-email-florian@openwrt.org> References: <1328030348-21967-1-git-send-email-florian@openwrt.org> X-archive-position: 32371 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 4554 Lines: 124 Signed-off-by: Florian Fainelli --- arch/mips/txx9/generic/setup.c | 12 +++++------- arch/mips/txx9/generic/setup_tx4939.c | 2 +- arch/mips/txx9/rbtx4939/setup.c | 11 +++++------ 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index ae77a79..560fe89 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -632,7 +632,7 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr, unsigned long size, const struct physmap_flash_data *pdata) { -#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +#if IS_ENABLED(CONFIG_MTD_PHYSMAP) struct resource res = { .start = addr, .end = addr + size - 1, @@ -670,8 +670,7 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr, void __init txx9_ndfmc_init(unsigned long baseaddr, const struct txx9ndfmc_platform_data *pdata) { -#if defined(CONFIG_MTD_NAND_TXX9NDFMC) || \ - defined(CONFIG_MTD_NAND_TXX9NDFMC_MODULE) +#if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC) struct resource res = { .start = baseaddr, .end = baseaddr + 0x1000 - 1, @@ -687,7 +686,7 @@ void __init txx9_ndfmc_init(unsigned long baseaddr, #endif } -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#if IS_ENABLED(CONFIG_LEDS_GPIO) static DEFINE_SPINLOCK(txx9_iocled_lock); #define TXX9_IOCLED_MAXLEDS 8 @@ -810,7 +809,7 @@ void __init txx9_iocled_init(unsigned long baseaddr, void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq, const struct txx9dmac_platform_data *pdata) { -#if defined(CONFIG_TXX9_DMAC) || defined(CONFIG_TXX9_DMAC_MODULE) +#if IS_ENABLED(CONFIG_TXX9_DMAC) struct resource res[] = { { .start = baseaddr, @@ -866,8 +865,7 @@ void __init txx9_aclc_init(unsigned long baseaddr, int irq, unsigned int dma_chan_out, unsigned int dma_chan_in) { -#if defined(CONFIG_SND_SOC_TXX9ACLC) || \ - defined(CONFIG_SND_SOC_TXX9ACLC_MODULE) +#if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC) unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS; struct resource res[] = { { diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c index 6567895..5ff7a95 100644 --- a/arch/mips/txx9/generic/setup_tx4939.c +++ b/arch/mips/txx9/generic/setup_tx4939.c @@ -317,7 +317,7 @@ void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask) } } -#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) +#if IS_ENABLED(CONFIG_TC35815) static u32 tx4939_get_eth_speed(struct net_device *dev) { struct ethtool_cmd cmd; diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 2ad8973..e15641d 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -40,8 +40,7 @@ static void __init rbtx4939_time_init(void) tx4939_time_init(0); } -#if defined(__BIG_ENDIAN) && \ - (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) +#if defined(__BIG_ENDIAN) && IS_ENABLED(CONFIG_SMC91X) #define HAVE_RBTX4939_IOSWAB #define IS_CE1_ADDR(addr) \ ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1)) @@ -187,7 +186,7 @@ static void __init rbtx4939_update_ioc_pen(void) #define RBTX4939_MAX_7SEGLEDS 8 -#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) +#if IS_ENABLED(CONFIG_LEDS_CLASS) static u8 led_val[RBTX4939_MAX_7SEGLEDS]; struct rbtx4939_led_data { struct led_classdev cdev; @@ -263,7 +262,7 @@ static inline void rbtx4939_led_setup(void) static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val) { -#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) +#if IS_ENABLED(CONFIG_LEDS_CLASS) unsigned long flags; local_irq_save(flags); /* bit7: reserved for LED class */ @@ -287,7 +286,7 @@ static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val) __rbtx4939_7segled_putc(pos, val); } -#if defined(CONFIG_MTD_RBTX4939) || defined(CONFIG_MTD_RBTX4939_MODULE) +#if IS_ENABLED(CONFIG_MTD_RBTX4939) /* special mapping for boot rom */ static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs) { @@ -463,7 +462,7 @@ static void __init rbtx4939_device_init(void) .flags = SMC91X_USE_16BIT, }; struct platform_device *pdev; -#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) +#if IS_ENABLED(CONFIG_TC35815) int i, j; unsigned char ethaddr[2][6]; u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:22:01 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:57806 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904031Ab2AaRTa (ORCPT ); Tue, 31 Jan 2012 18:19:30 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 4C1ED44895A; Tue, 31 Jan 2012 18:19:30 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MUQxrKAW5-Mi; Tue, 31 Jan 2012 18:19:29 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id D624E434D36; Tue, 31 Jan 2012 18:19:29 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 0/6] MIPS: use IS_ENABLED() macro Date: Tue, 31 Jan 2012 18:19:02 +0100 Message-Id: <1328030348-21967-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 X-archive-position: 32372 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1027 Lines: 26 This patch replaces the traditionnal use of: CONFIG_FOO || CONFIG_FOO_MODULE by IS_ENABLED(CONFIG_FOO) Florian Fainelli (6): MIPS: Alchemy: use IS_ENABLED() macro MIPS: PNX833x: use IS_ENABLED() macro MIPS: TXX9: use IS_ENABLED() macro MIPS: TX49XX: use IS_ENABLED() MIPS: DEC: use IS_ENABLED() MIPS: loongson: use IS_ENABLED() arch/mips/alchemy/board-mtx1.c | 4 ++-- arch/mips/alchemy/devboards/pb1100.c | 4 ++-- arch/mips/alchemy/devboards/pb1500.c | 4 ++-- arch/mips/dec/prom/memory.c | 2 +- arch/mips/include/asm/mach-loongson/loongson.h | 3 ++- arch/mips/include/asm/mach-tx49xx/mangle-port.h | 2 +- arch/mips/pnx833x/stb22x/board.c | 4 ++-- arch/mips/txx9/generic/setup.c | 12 +++++------- arch/mips/txx9/generic/setup_tx4939.c | 2 +- arch/mips/txx9/rbtx4939/setup.c | 11 +++++------ 10 files changed, 23 insertions(+), 25 deletions(-) -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:22:22 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:57808 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904032Ab2AaRTa (ORCPT ); Tue, 31 Jan 2012 18:19:30 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 7D47B434D36; Tue, 31 Jan 2012 18:19:30 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NtNrM15GgxIW; Tue, 31 Jan 2012 18:19:30 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 132E8448602; Tue, 31 Jan 2012 18:19:30 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 4/6] MIPS: TX49XX: use IS_ENABLED() Date: Tue, 31 Jan 2012 18:19:06 +0100 Message-Id: <1328030348-21967-5-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328030348-21967-1-git-send-email-florian@openwrt.org> References: <1328030348-21967-1-git-send-email-florian@openwrt.org> X-archive-position: 32373 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 748 Lines: 21 Signed-off-by: Florian Fainelli --- arch/mips/include/asm/mach-tx49xx/mangle-port.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h index 5e6912f..490867b 100644 --- a/arch/mips/include/asm/mach-tx49xx/mangle-port.h +++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h @@ -9,7 +9,7 @@ #define ioswabb(a, x) (x) #define __mem_ioswabb(a, x) (x) #if defined(CONFIG_TOSHIBA_RBTX4939) && \ - (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \ + IS_ENABLED(CONFIG_SMC91X) && \ defined(__BIG_ENDIAN) #define NEEDS_TXX9_IOSWABW extern u16 (*ioswabw)(volatile u16 *a, u16 x); -- 1.7.5.4 From florian@openwrt.org Tue Jan 31 18:19:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:22:44 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:57815 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904035Ab2AaRTb (ORCPT ); Tue, 31 Jan 2012 18:19:31 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id BADAA44848A; Tue, 31 Jan 2012 18:19:30 +0100 (CET) X-Virus-Scanned: amavisd-new at Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7bQ3S6AnhIeE; Tue, 31 Jan 2012 18:19:30 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 3299F448957; Tue, 31 Jan 2012 18:19:30 +0100 (CET) From: Florian Fainelli To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 6/6] MIPS: loongson: use IS_ENABLED() Date: Tue, 31 Jan 2012 18:19:08 +0100 Message-Id: <1328030348-21967-7-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328030348-21967-1-git-send-email-florian@openwrt.org> References: <1328030348-21967-1-git-send-email-florian@openwrt.org> X-archive-position: 32374 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 901 Lines: 29 Signed-off-by: Florian Fainelli --- arch/mips/include/asm/mach-loongson/loongson.h | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 1e29b9d..06367c3 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -14,6 +14,7 @@ #include #include #include +#include /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); @@ -66,7 +67,7 @@ extern int mach_i8259_irq(void); #include static inline void do_perfcnt_IRQ(void) { -#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE) +#if IS_ENABLED(CONFIG_OPROFILE) do_IRQ(LOONGSON2_PERFCNT_IRQ); #endif } -- 1.7.5.4 From omaplinuxkernel@gmail.com Tue Jan 31 18:52:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 18:52:56 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:39221 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904039Ab2AaRwu convert rfc822-to-8bit (ORCPT ); Tue, 31 Jan 2012 18:52:50 +0100 Received: by vbbfs19 with SMTP id fs19so286667vbb.36 for ; Tue, 31 Jan 2012 09:52:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=KrO1D2DB2ii0EEIjSrnVx6ZTs7uCA3VPpjcxN/o8SOM=; b=GdUKEAwtlAoJZkZnSab6xdtMneE9zl8saZhQ7WdLr2L06zskQFB8YJv02gKSgb9avd qnMQhud2XvV7+Ll9c1UqullVB9Tmw3II6HM4pVpz6IOF+2dkKVGmKT/TmgY3OtZhYLjF 8FFGEukYQ1XpEte7AJBCC6PtSX/2d8V7MBwE0= MIME-Version: 1.0 Received: by 10.52.27.111 with SMTP id s15mr11110731vdg.120.1328032363930; Tue, 31 Jan 2012 09:52:43 -0800 (PST) Received: by 10.220.187.76 with HTTP; Tue, 31 Jan 2012 09:52:43 -0800 (PST) In-Reply-To: <1328019048-5892-10-git-send-email-florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> <1328019048-5892-10-git-send-email-florian@openwrt.org> Date: Tue, 31 Jan 2012 23:22:43 +0530 Message-ID: Subject: Re: [PATCH 9/9 v3] spi: add Broadcom BCM63xx SPI controller driver From: Shubhrajyoti Datta To: Florian Fainelli Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, Tanguy Bouzeloc , spi-devel-general@lists.sourceforge.net Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 32375 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: omaplinuxkernel@gmail.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 5070 Lines: 143 Hi Florian, On Tue, Jan 31, 2012 at 7:40 PM, Florian Fainelli wrote: > This patch adds support for the SPI controller found on the Broadcom BCM63xx > SoCs. > > Signed-off-by: Tanguy Bouzeloc > Signed-off-by: Florian Fainelli > --- > Changes since v2: > - reworked bcm63xx_spi_setup_transfer to choose closest spi transfer >  frequency > - removed invalid 25Mhz frequency > - fixed some minor checkpatch issues > > Changes since v1: > - switched to the devm_* API which frees resources automatically > - switched to dev_pm_ops > - use module_platform_driver > - remove MODULE_VERSION() > - fixed return value when clock is not present using PTR_ERR() > - fixed probe() error path to disable clock in case of failure > >  drivers/spi/Kconfig       |    6 + >  drivers/spi/Makefile      |    1 + >  drivers/spi/spi-bcm63xx.c |  486 +++++++++++++++++++++++++++++++++++++++++++++ >  3 files changed, 493 insertions(+), 0 deletions(-) >  create mode 100644 drivers/spi/spi-bcm63xx.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 3f9a47e..16818ac 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -94,6 +94,12 @@ config SPI_AU1550 >          If you say yes to this option, support will be included for the >          PSC SPI controller found on Au1550, Au1200 and Au1300 series. > > +config SPI_BCM63XX > +       tristate "Broadcom BCM63xx SPI controller" > +       depends on BCM63XX > +       help > +          Enable support for the SPI controller on the Broadcom BCM63xx SoCs. > + >  config SPI_BITBANG >        tristate "Utilities for Bitbanging SPI masters" >        help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 61c3261..be38f73 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA)              += spi-altera.o >  obj-$(CONFIG_SPI_ATMEL)                        += spi-atmel.o >  obj-$(CONFIG_SPI_ATH79)                        += spi-ath79.o >  obj-$(CONFIG_SPI_AU1550)               += spi-au1550.o > +obj-$(CONFIG_SPI_BCM63XX)              += spi-bcm63xx.o >  obj-$(CONFIG_SPI_BFIN)                 += spi-bfin5xx.o >  obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o >  obj-$(CONFIG_SPI_BITBANG)              += spi-bitbang.o > diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c > new file mode 100644 > index 0000000..eba8505 > --- /dev/null > +++ b/drivers/spi/spi-bcm63xx.c > @@ -0,0 +1,486 @@ > +/* > + * Broadcom BCM63xx SPI controller support > + * > + * Copyright (C) 2009-2011 Florian Fainelli > + * Copyright (C) 2010 Tanguy Bouzeloc > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the > + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define PFX            KBUILD_MODNAME > +#define DRV_VER                "0.1.2" > + > +struct bcm63xx_spi { > +       spinlock_t              lock; > +       int                     stopping; > +       struct completion       done; > + > +       void __iomem            *regs; > +       int                     irq; > + > +       /* Platform data */ > +       u32                     speed_hz; > +       unsigned                fifo_size; > + > +       /* Data buffers */ > +       const unsigned char     *tx_ptr; > +       unsigned char           *rx_ptr; > + > +       /* data iomem */ > +       u8 __iomem              *tx_io; > +       const u8 __iomem        *rx_io; > + > +       int                     remaining_bytes; > + > +       struct clk              *clk; > +       struct platform_device  *pdev; > +}; > + > +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, > +                               unsigned int offset) > +{ > +       return bcm_readw(bs->regs + bcm63xx_spireg(offset)); are you sure it should be bcm_readw > +} > + > +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, > +                               unsigned int offset) > +{ > +       return bcm_readw(bs->regs + bcm63xx_spireg(offset)); > +} > + From grant.likely@secretlab.ca Tue Jan 31 21:19:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 21:19:41 +0100 (CET) Received: from mail-lpp01m010-f49.google.com ([209.85.215.49]:43323 "EHLO mail-lpp01m010-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904023Ab2AaUTf (ORCPT ); Tue, 31 Jan 2012 21:19:35 +0100 Received: by laam7 with SMTP id m7so291881laa.36 for ; Tue, 31 Jan 2012 12:19:29 -0800 (PST) Received: by 10.152.148.106 with SMTP id tr10mr12126015lab.41.1328041169351; Tue, 31 Jan 2012 12:19:29 -0800 (PST) Received: from localhost (S0106d8b37715ee14.cg.shawcable.net. [68.146.14.168]) by mx.google.com with ESMTPS id i9sm18029268lbz.3.2012.01.31.12.19.25 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 31 Jan 2012 12:19:28 -0800 (PST) Received: by localhost (Postfix, from userid 1000) id 968A13E0E86; Tue, 31 Jan 2012 13:19:22 -0700 (MST) Date: Tue, 31 Jan 2012 13:19:22 -0700 From: Grant Likely To: Florian Fainelli Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, spi-devel-general@lists.sourceforge.net, Tanguy Bouzeloc Subject: Re: [PATCH 9/9 v3] spi: add Broadcom BCM63xx SPI controller driver Message-ID: <20120131201922.GE22611@ponder.secretlab.ca> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> <1328019048-5892-10-git-send-email-florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1328019048-5892-10-git-send-email-florian@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 32376 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2348 Lines: 83 On Tue, Jan 31, 2012 at 03:10:48PM +0100, Florian Fainelli wrote: > This patch adds support for the SPI controller found on the Broadcom BCM63xx > SoCs. > > Signed-off-by: Tanguy Bouzeloc > Signed-off-by: Florian Fainelli > --- > Changes since v2: > - reworked bcm63xx_spi_setup_transfer to choose closest spi transfer > frequency > - removed invalid 25Mhz frequency > - fixed some minor checkpatch issues > > Changes since v1: > - switched to the devm_* API which frees resources automatically > - switched to dev_pm_ops > - use module_platform_driver > - remove MODULE_VERSION() > - fixed return value when clock is not present using PTR_ERR() > - fixed probe() error path to disable clock in case of failure > > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-bcm63xx.c | 486 +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 493 insertions(+), 0 deletions(-) > create mode 100644 drivers/spi/spi-bcm63xx.c > Looks okay. There are a couple of problems that needs to be fixed below, but otherwise: Acked-by: Grant Likely Merge this through the same tree as patches 1-8 g. > +static int __init bcm63xx_spi_probe(struct platform_device *pdev) __devinit > +static int __exit bcm63xx_spi_remove(struct platform_device *pdev) __devexit > +static const struct dev_pm_ops bcm63xx_spi_pm_ops = { > + .suspend = bcm63xx_spi_suspend, > + .resume = bcm63xx_spi_resume, > +}; > + > +#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) > +#else > +#define BCM63XX_SPI_PM_OPS NULL A bit ugly. Do this instead in the else clause and drop the BCM63XX_SPI_PM_OPS: #define bcm63xx_spi_pm_ops NULL > +#endif > + > +static struct platform_driver bcm63xx_spi_driver = { > + .driver = { > + .name = "bcm63xx-spi", > + .owner = THIS_MODULE, > + .pm = BCM63XX_SPI_PM_OPS, > + }, > + .probe = bcm63xx_spi_probe, > + .remove = __exit_p(bcm63xx_spi_remove), __devexit_p > +}; > + > +module_platform_driver(bcm63xx_spi_driver); > + > +MODULE_ALIAS("platform:bcm63xx_spi"); > +MODULE_AUTHOR("Florian Fainelli "); > +MODULE_AUTHOR("Tanguy Bouzeloc "); > +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); > +MODULE_LICENSE("GPL"); > -- > 1.7.5.4 > From mst@redhat.com Tue Jan 31 22:19:15 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 22:19:22 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:28752 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904026Ab2AaVTP (ORCPT ); Tue, 31 Jan 2012 22:19:15 +0100 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q0VLIwwP027581 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 31 Jan 2012 16:18:58 -0500 Received: from redhat.com (vpn-203-148.tlv.redhat.com [10.35.203.148]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id q0VLInw8020014; Tue, 31 Jan 2012 16:18:50 -0500 Date: Tue, 31 Jan 2012 23:18:54 +0200 From: "Michael S. Tsirkin" To: Arnd Bergmann Cc: Kevin Cernekee , Ralf Baechle , Paul Mundt , Jesse Barnes , Myron Stowe , Paul Gortmaker , Lucas De Marchi , Dmitry Kasatkin , James Morris , "John W. Linville" , Michael Witten , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 1/3] lib: add NO_GENERIC_PCI_IOPORT_MAP Message-ID: <20120131211853.GC6843@redhat.com> References: <201201301551.46907.arnd@arndb.de> <20120130161818.GA9345@redhat.com> <201201302004.33083.arnd@arndb.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201201302004.33083.arnd@arndb.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-archive-position: 32377 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mst@redhat.com Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 1342 Lines: 38 On Mon, Jan 30, 2012 at 08:04:32PM +0000, Arnd Bergmann wrote: > On Monday 30 January 2012, Michael S. Tsirkin wrote: > > > > > > +/* > > > + * Create a virtual mapping cookie for a port on a given PCI device. > > > + * Do not call this directly, it exists to make it easier for architectures > > > + * to override. > > > + */ > > > +#ifdef CONFIG_NO_GENERIC_PCI_IOPORT_MAP > > > +extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, > > > + unsigned int nr); > > > +#else > > > +static inline void __iomem *__pci_ioport_map(struct pci_dev *dev, > > > + unsigned long port, unsigned int nr) > > > +{ > > > + return ioport_map(port, nr); > > > +} > > > +#endif > > > > > > Arnd > > > > It would be nicer in that it would > > make the kernel a bit smaller for generic architectures > > but this would need to go into a separate header: > > it depends on io.h and io.h depends on pci_iomap.h. > > Adding extra dependencies is not good here, I agree. > Maybe a better solution is to use a macro instead of an inline > function then: > > #define __pci_ioport_map(dev, port, nr) ioport_map(port, nr) > > In general, macros should be avoided, but I think it's the > best tradeoff in this case. > > Arnd OK, I did exactly that. Thanks! From florian@openwrt.org Tue Jan 31 22:20:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 22:20:56 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:37180 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904026Ab2AaVUt (ORCPT ); Tue, 31 Jan 2012 22:20:49 +0100 Received: by wgbdr13 with SMTP id dr13so443416wgb.24 for ; Tue, 31 Jan 2012 13:20:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; bh=HAcCWEKPy3nNvFOQ1mhSrgWxkMS1GJGbJ6W7FwCTfpI=; b=WAUwzCM4QEHRgppnzdOz9KGUq6Y5nC3tbkRbapYIDLN6EZxWDYC/vlSTv7XhydGa3H +/btrtYMd9KbrBedboQaWSPQYF+nKGXrrAYX1i4jyBiv0X7lwoeLfHiuVLSIj5iPGQC1 l+uv7TenSA0JizF2mks4DHMgnY+jhJQZt+n48= Received: by 10.180.19.97 with SMTP id d1mr37420614wie.12.1328044844474; Tue, 31 Jan 2012 13:20:44 -0800 (PST) Received: from bender.localnet ([2a01:e35:2f70:4010:22cf:30ff:fe38:5254]) by mx.google.com with ESMTPS id t15sm40083478wiv.6.2012.01.31.13.20.42 (version=SSLv3 cipher=OTHER); Tue, 31 Jan 2012 13:20:43 -0800 (PST) From: Florian Fainelli Organization: OpenWrt To: Grant Likely Subject: Re: [PATCH 9/9 v3] spi: add Broadcom BCM63xx SPI controller driver Date: Tue, 31 Jan 2012 22:20:41 +0100 User-Agent: KMail/1.13.6 (Linux/2.6.38-9-generic; KDE/4.6.5; x86_64; ; ) Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, spi-devel-general@lists.sourceforge.net, Tanguy Bouzeloc References: <1328019048-5892-1-git-send-email-florian@openwrt.org> <1328019048-5892-10-git-send-email-florian@openwrt.org> <20120131201922.GE22611@ponder.secretlab.ca> In-Reply-To: <20120131201922.GE22611@ponder.secretlab.ca> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201201312220.41561.florian@openwrt.org> X-archive-position: 32378 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 2834 Lines: 95 Hello Grant, On Tuesday 31 January 2012 21:19:22 Grant Likely wrote: > On Tue, Jan 31, 2012 at 03:10:48PM +0100, Florian Fainelli wrote: > > This patch adds support for the SPI controller found on the Broadcom > > BCM63xx SoCs. > > > > Signed-off-by: Tanguy Bouzeloc > > Signed-off-by: Florian Fainelli > > --- > > Changes since v2: > > - reworked bcm63xx_spi_setup_transfer to choose closest spi transfer > > > > frequency > > > > - removed invalid 25Mhz frequency > > - fixed some minor checkpatch issues > > > > Changes since v1: > > - switched to the devm_* API which frees resources automatically > > - switched to dev_pm_ops > > - use module_platform_driver > > - remove MODULE_VERSION() > > - fixed return value when clock is not present using PTR_ERR() > > - fixed probe() error path to disable clock in case of failure > > > > drivers/spi/Kconfig | 6 + > > drivers/spi/Makefile | 1 + > > drivers/spi/spi-bcm63xx.c | 486 > > +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 493 > > insertions(+), 0 deletions(-) > > create mode 100644 drivers/spi/spi-bcm63xx.c > > Looks okay. There are a couple of problems that needs to be fixed > below, but otherwise: > > Acked-by: Grant Likely > > Merge this through the same tree as patches 1-8 > > g. > > > +static int __init bcm63xx_spi_probe(struct platform_device *pdev) > > __devinit > > > +static int __exit bcm63xx_spi_remove(struct platform_device *pdev) > > __devexit > > > +static const struct dev_pm_ops bcm63xx_spi_pm_ops = { > > + .suspend = bcm63xx_spi_suspend, > > + .resume = bcm63xx_spi_resume, > > +}; > > + > > +#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) > > +#else > > +#define BCM63XX_SPI_PM_OPS NULL > > A bit ugly. Do this instead in the else clause and drop the > BCM63XX_SPI_PM_OPS: > > #define bcm63xx_spi_pm_ops NULL This won't work, because driver.pm must be set to a pointer to a struct dev_pm_ops, that's why I used this trick to make it build fine in both cases. If I follow your advice, with driver.pm = &bcm63xx_spi_pm_ops, it won't build for CONFIG_PM=n. > > > +#endif > > + > > +static struct platform_driver bcm63xx_spi_driver = { > > + .driver = { > > + .name = "bcm63xx-spi", > > + .owner = THIS_MODULE, > > + .pm = BCM63XX_SPI_PM_OPS, > > + }, > > + .probe = bcm63xx_spi_probe, > > + .remove = __exit_p(bcm63xx_spi_remove), > > __devexit_p > > > +}; > > + > > +module_platform_driver(bcm63xx_spi_driver); > > + > > +MODULE_ALIAS("platform:bcm63xx_spi"); > > +MODULE_AUTHOR("Florian Fainelli "); > > +MODULE_AUTHOR("Tanguy Bouzeloc "); > > +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); > > +MODULE_LICENSE("GPL"); -- Florian From grant.likely@secretlab.ca Tue Jan 31 22:59:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jan 2012 22:59:48 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:58245 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1904026Ab2AaV7l convert rfc822-to-8bit (ORCPT ); Tue, 31 Jan 2012 22:59:41 +0100 Received: by pbdx9 with SMTP id x9so621136pbd.36 for ; Tue, 31 Jan 2012 13:59:35 -0800 (PST) Received: by 10.68.73.196 with SMTP id n4mr52982063pbv.33.1328047174191; Tue, 31 Jan 2012 13:59:34 -0800 (PST) MIME-Version: 1.0 Received: by 10.68.224.170 with HTTP; Tue, 31 Jan 2012 13:59:14 -0800 (PST) In-Reply-To: <201201312220.41561.florian@openwrt.org> References: <1328019048-5892-1-git-send-email-florian@openwrt.org> <1328019048-5892-10-git-send-email-florian@openwrt.org> <20120131201922.GE22611@ponder.secretlab.ca> <201201312220.41561.florian@openwrt.org> From: Grant Likely Date: Tue, 31 Jan 2012 14:59:14 -0700 X-Google-Sender-Auth: CDQDNoHBnR8sOw185xG2OCQgb18 Message-ID: Subject: Re: [PATCH 9/9 v3] spi: add Broadcom BCM63xx SPI controller driver To: Florian Fainelli Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, spi-devel-general@lists.sourceforge.net, Tanguy Bouzeloc Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 32379 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips Return-Path: Content-Length: 820 Lines: 24 On Tue, Jan 31, 2012 at 2:20 PM, Florian Fainelli wrote: > On Tuesday 31 January 2012 21:19:22 Grant Likely wrote: >> > +static const struct dev_pm_ops bcm63xx_spi_pm_ops = { >> > +   .suspend        = bcm63xx_spi_suspend, >> > +   .resume         = bcm63xx_spi_resume, >> > +}; >> > + >> > +#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) >> > +#else >> > +#define BCM63XX_SPI_PM_OPS NULL >> >> A bit ugly.  Do this instead in the else clause and drop the >> BCM63XX_SPI_PM_OPS: >> >> #define bcm63xx_spi_pm_ops NULL > > This won't work, because driver.pm must be set to a pointer to a struct > dev_pm_ops, that's why I used this trick to make it build fine in both cases. > If I follow your advice, with driver.pm = &bcm63xx_spi_pm_ops, it won't build > for CONFIG_PM=n. Okay, fair enough. g.