Subject: Re: SMVP Support on MIPS34KC (linux-2.6.35)

From: "Steven J. Hill" <[email-masked]>
Date: Fri, 27 Jul 2012 12:19:32 -0500

Hello Joe.

The 2.6.35.9 is obsolete with regards to SMVP support. You should grab the
latest 3.4.2 kernel that has complete and working SMVP. To access it, do the
following:

git clone git://git.linux-mips.org/pub/scm/linux-mti
git checkout -b linux-mti-3.4.2 origin/linux-mti-3.4.2

Use the 'arch/mips/configs/maltasmvp_defconfig' as your base configuration
file. If you have any issues, please let me know.

- -Steve

P.S. You can also reach me at <sjhill AT mips DOT com>

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From: JoeJ <[email-masked]>
Date: Mon, 30 Jul 2012 06:20:59 -0700 (PDT)

Hi Steve,

 Thanks for the suggestion. We moved to 3.4.2 kernel and observed the same
issue, ie System hangs while booting. In 3.4.2 port, we are using mips
timers (count & compare - csrc-r4k.c & cevt-r4k.c) as clocksource. The last
few prints on the console are : 

Synchronize counters across 2 CPUs: done.
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
Switching to clocksource MIPS

As mentioned in my previous post, even with 3.4.2 kernel, the control loops
in stop_machine_cpu_stop function. Do you suspect anything here? 
btw, if we set "clocksource=jiffies" in the bootargs, the system boot goes
fine. The issue is observed only during switching from default clocksource
to MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS
clocksource. 

Please suggest on the possible debug approach for this issue. 
 
Thanks for your support. 

Regards,
Joe

sjhill-3 wrote:
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From: "Steven J. Hill" <[email-masked]>
Date: Mon, 30 Jul 2012 09:52:23 -0500

On 07/30/2012 08:20 AM, JoeJ wrote:
> 
> Synchronize counters across 2 CPUs: done. NET: Registered protocol family
> 16 bio: create slab <bio-0> at 0 Switching to clocksource MIPS
> 
> 
> As mentioned in my previous post, even with 3.4.2 kernel, the control
> loops in stop_machine_cpu_stop function. Do you suspect anything here? btw,
> if we set "clocksource=jiffies" in the bootargs, the system boot goes fine.
> The issue is observed only during switching from default clocksource to
> MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS 
> clocksource.
> 
Make user that you select both CONFIG_CSRC_R4K ad CONFIG_CSRC_GIC for your
clock sources. The GIC counter will be used from synchronization across the
CPUs. Secondly, the hang is not actually a hard hang. Wait 50 seconds and I
bet you will see the boot complete.

- -Steve

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From: Jeffin <[email-masked]>
Date: Mon, 30 Jul 2012 20:58:23 +0530

Hi Steve,

    CONFIG_CSRC_R4K is defined . However,  I have not
enabled CONFIG_CSRC_GIC and gic_present is initialized to 'zero' . I am a
bit confused about CONFIG_SRC_GIC macros. I am not sure if GIC is an
external timer outside the mips 34Kc core (specific to malta reference
board)? In that case, we might have to replace to GIC source code with our
own General purpose timer code. Can you please confirm if i am missing
something here? It will be verfy helpful if you can explain a bit about the
significance of CSRC_R4K & CSRC_GIC macros definitions in SMVP model.

 We have been stuck with this issue for quiet sometime and looking for ways
to resolve this at the best possible way. Your suggestions are really
helpful in this regard.

Regards,
Jeffin

On Mon, Jul 30, 2012 at 8:22 PM, Steven J. Hill
<[email-masked]>wrote:

> iEYEARECAAYFAlAWn6cACgkQgyK5H2Ic36f47wCbBM7J8Bl0iEyELwxx2sYHBRxZ
> SukAniQlkEwYyNdolwPhi1vOJgxNrba+
> =NW6E

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From: "Steven J. Hill" <[email-masked]>
Date: Mon, 30 Jul 2012 16:02:24 -0500

Jeffin,

You will need to file an official support request with MIPS to proceed
further. Additional time spent on this will need to be tracked. Thanks.

- -Steve