From roy.qing.li@gmail.com Mon Jul 2 06:34:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Jul 2012 06:34:47 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:44534 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901168Ab2GBEen (ORCPT ); Mon, 2 Jul 2012 06:34:43 +0200 Received: by pbbrq13 with SMTP id rq13so7942484pbb.36 for ; Sun, 01 Jul 2012 21:34:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer; bh=nQwYUgQd5HVDNRB1k3UgWX84MrCbzHT5HBbCA2c9wUw=; b=VdE0DlgUn6XtOYBrDu6xmoRncFAkC4nIUKTbdNCur6sDpLoiyDrvCpmsTN1BjIP8gO smV17Lc2HFCBdjBiaC5/IkK0yU7kO3gUs5RbCMGmeOcyYQXIvaR1AGUDZuR/DD0D+ZPD 1MhiI4RPD0JC18uvjzbfk4CTTbAFKuWLv31jYw5GcU/8hya0JxPzgFgUXrRyhqF8rk86 c7rgGv+fle01bvhvYz4jWOtZWwmYFBxcM15/xyXEcBg4H6iQblVaosz9CGNNB+u/NJx6 eJkroOQHW+M1XTl0O1FbX5eGo0VRbmOUzAQQT+RZuPSCKhDWXZIU+TJ564Evd0BqAV91 ddSA== Received: by 10.66.74.97 with SMTP id s1mr18529198pav.11.1341203676465; Sun, 01 Jul 2012 21:34:36 -0700 (PDT) Received: from localhost ([61.148.56.138]) by mx.google.com with ESMTPS id qi8sm12018430pbc.36.2012.07.01.21.34.33 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 01 Jul 2012 21:34:35 -0700 (PDT) From: roy.qing.li@gmail.com To: linux-mips@linux-mips.org Subject: [PATCH] MIPS: fix tc_id calculation Date: Mon, 2 Jul 2012 12:34:30 +0800 Message-Id: <1341203670-17544-1-git-send-email-roy.qing.li@gmail.com> X-Mailer: git-send-email 1.7.1 X-archive-position: 33873 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: roy.qing.li@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 886 Lines: 30 From: RongQing.Li Now the tc_id is: (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC; After substitute macro: (read_c0_tcbind() >> 21) & ((0xff) << 21) It should be: (read_c0_tcbind() & ((0xff)<< 21)) >>21 Signed-off-by: RongQing.Li --- arch/mips/kernel/smp-cmp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index e7e03ec..afc379c 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -102,7 +102,7 @@ static void cmp_init_secondary(void) c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; #endif #ifdef CONFIG_MIPS_MT_SMTC - c->tc_id = (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC; + c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT; #endif } -- 1.7.1 From pjohn@mvista.com Thu Jul 5 14:11:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jul 2012 14:11:58 +0200 (CEST) Received: from mail-gh0-f177.google.com ([209.85.160.177]:36154 "EHLO mail-gh0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903721Ab2GEMLw (ORCPT ); Thu, 5 Jul 2012 14:11:52 +0200 Received: by ghbf11 with SMTP id f11so7901930ghb.36 for ; Thu, 05 Jul 2012 05:11:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding:x-gm-message-state; bh=o6+GPzyMCbi3nqUUAGBjIBjAlayTPOwYkGsMGY9tLoE=; b=AcItprrvSCnTTZwLCoLLJv+6VKPlC8Cm7urN3Wy5y2UYmNV11wEFB5jQrfsfwhVTuG MoxwBcRUEG7Dvnr+Xz/8uPD6l9nM6lo1ZXz+2F2USum9i67zmA6vWrew7w1MVssyta6s ygh0XUWxKh+T4hxw4M+kh00JwClgHyvyhC5vySAtb0YzrZqEih+VZ7WwPACXyyaXvlzu 3YjWfkgHZltP6Mqq8MXw6cM2GAY/xIbVBOCKldmGq0VOesZAU6PwVp71PTsp1WS4O8Qx 4QSlYmzF8nlpNK5/NcOdLgNJ+qSdfj9cGIYdIl46ytss1St5W39/hYNRZt9JIW2ax2Gi ZI2A== Received: by 10.66.81.3 with SMTP id v3mr18497497pax.62.1341490305806; Thu, 05 Jul 2012 05:11:45 -0700 (PDT) Received: from [10.162.4.5] ([115.119.134.194]) by mx.google.com with ESMTPS id og4sm19670023pbb.48.2012.07.05.05.11.42 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 05 Jul 2012 05:11:44 -0700 (PDT) Subject: [PATCH v2] Octeon 6xxx: Add Power Throttling support for CN6xxx and above From: philby john To: linux-mips@linux-mips.org Cc: "Daney, David" , "Kapoor, Prasun" , "ralf@linux-mips.org" Content-Type: text/plain; charset="ansi_x3.4-1968" Date: Thu, 05 Jul 2012 17:40:03 +0530 Message-ID: <1341490203.28372.3.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.32.3 (2.32.3-1.fc14) Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkuC6BESzgKBnZoyCQYzma85ObSU2VFU6keES4+qXIGWqTt/zuLOuxOWAFsEmZBeKbKgSIS X-archive-position: 33875 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 11481 Lines: 423 >From 51898ada30d5eae7bff92dfb774df5a05ff670a4 Mon Sep 17 00:00:00 2001 From: Philby John Date: Thu, 5 Jul 2012 17:35:45 +0530 Subject: [PATCH v2] Octeon 6xxx: Add Power Throttling support for CN6xxx and above This patch adds the sysfs primitives for power throttling. Octeon2 supports dynamic power control which aids to cut down power consumption. The code exposes a "percentage" power throttling limiter by means of /sys interface for each available cpu. Setting this value to 0 will set power consumption to a minimum as it will only execute a couple instructions every PERIOD as set in the PowThrottle register. If set to 100% for that particular cpu, it will consume maximum power. Functionality tested on an Octeon 63xx. Signed-off-by: Philby John --- arch/mips/cavium-octeon/Makefile | 1 + arch/mips/cavium-octeon/octeon-pwr-throtl.c | 379 +++++++++++++++++++++++++++ 2 files changed, 380 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cavium-octeon/octeon-pwr-throtl.c diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 19eb043..115ceb5 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -15,3 +15,4 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SYSFS) += octeon-pwr-throtl.o diff --git a/arch/mips/cavium-octeon/octeon-pwr-throtl.c b/arch/mips/cavium-octeon/octeon-pwr-throtl.c new file mode 100644 index 0000000..5a340f4 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon-pwr-throtl.c @@ -0,0 +1,379 @@ +/* + * octeon-pwr-throtl.c - interface for controlling power throttling on Octeon + * based platforms 6xxx and above. + * Octeon2 supports dynamic power control which aids to cut down power + * consumption. The code exposes a "percentage" power throttling limiter by + * means of /sys interface for each available cpu. Setting this value to 0 + * will set power consumption to a minimum as it will only execute a couple + * instructions every PERIOD as set in the PowThrottle register. + * If set to 100% for that particular cpu, it will consume maximum power. + * + * Copyright (C) 2012 MontaVista LLC. + * Author: Philby John + * Credits: This driver is derived from Dmitriy Zavin's (dmitriyz@google.com) + * thermal throttle event support code. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +enum cvmx_power_throttle_field_index { + CVMX_PTH_INDEX_MAXPOW, + CVMX_PTH_INDEX_POWER, + CVMX_PTH_INDEX_THROTT, + CVMX_PTH_INDEX_RESERVED, + CVMX_PTH_INDEX_DISTAG, + CVMX_PTH_INDEX_PERIOD, + CVMX_PTH_INDEX_POWLIM, + CVMX_PTH_INDEX_MAXTHR, + CVMX_PTH_INDEX_MINTHR, + CVMX_PTH_INDEX_HRMPOWADJ, + CVMX_PTH_INDEX_OVRRD, + CVMX_PTH_INDEX_MAX +}; + +#define CVMX_PTH_GET_MASK(len, pos) \ + ((((uint64_t)1 << (len)) - 1) << (pos)) + +/* + * a field of the POWTHROTTLE register + */ +static struct cvmx_power_throttle_rfield_t { + char name[16]; /* the field's name */ + int32_t pos; /* position of the field's LSb */ + int32_t len; /* the field's length */ + int present; /* 1 for present */ +} cvmx_power_throttle_rfield[] = { + {"MAXPOW", 56, 8, 0}, + {"POWER" , 48, 8, 0}, + {"THROTT", 40, 8, 0}, + {"Reserved", 28, 12, 0}, + {"DISTAG", 27, 1, 0}, + {"PERIOD", 24, 3, 0}, + {"POWLIM", 16, 8, 0}, + {"MAXTHR", 8, 8, 0}, + {"MINTHR", 0, 8, 0}, + {"HRMPOWADJ", 32, 8, 0}, + {"OVRRD", 28, 1, 0} +}; + +static uint64_t cvmx_power_throttle_csr_addr(int ppid); + +static int cvmx_power_throttle_initialized; + +/* + * Initialize cvmx_power_throttle_rfield[] based on model. + */ +static void cvmx_power_throttle_init(void) +{ + int i; + struct cvmx_power_throttle_rfield_t *p; + + for (i = 0; i < CVMX_PTH_INDEX_MAX; i++) + cvmx_power_throttle_rfield[i].present = 1; + + if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + /* + * These fields do not come with o63 + */ + p = &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_HRMPOWADJ]; + p->present = 0; + p = &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_OVRRD]; + p->present = 0; + } else { + /* + * The reserved field shrinks in models newer than o63 + */ + p = &cvmx_power_throttle_rfield[CVMX_PTH_INDEX_RESERVED]; + p->pos = 29; + p->len = 3; + } +} + +static uint64_t cvmx_power_throttle_get_field(uint64_t r, + enum cvmx_power_throttle_field_index i) +{ + uint64_t m; + struct cvmx_power_throttle_rfield_t *p; + + if (i > CVMX_PTH_INDEX_MAX) + return -EINVAL; + + p = &cvmx_power_throttle_rfield[i]; + if (!p->present) + return (uint64_t) -1; + m = CVMX_PTH_GET_MASK(p->len, p->pos); + + return (r & m) >> p->pos; +} + +/* + * Set the i'th field of power-throttle register r to v. + */ +static int cvmx_power_throttle_set_field(int i, uint64_t r, uint64_t v) +{ + uint64_t m; + struct cvmx_power_throttle_rfield_t *p; + + if (i > CVMX_PTH_INDEX_MAX) + return -EINVAL; + + p = &cvmx_power_throttle_rfield[i]; + m = CVMX_PTH_GET_MASK(p->len, p->pos); + + return (~m & r) | ((v << p->pos) & m); +} + +static void cvmx_init_throttle_feedback(unsigned int cpu) +{ + uint64_t csr_addr, r; + + csr_addr = cvmx_power_throttle_csr_addr(cpu); + r = cvmx_read_csr(csr_addr); + r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_MINTHR, r, 0x0); + cvmx_write_csr(csr_addr, r); + r = cvmx_read_csr(csr_addr); + r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_MAXTHR, r, 0xFF); + cvmx_write_csr(csr_addr, r); +} + +/* + * Get the POWLIM field as percentage% of the MAXPOW field in r. + */ +static int cvmx_power_throttle_get_powlim(unsigned int cpu) +{ + uint64_t t, csr_addr, r, s; + + csr_addr = cvmx_power_throttle_csr_addr(cpu); + r = cvmx_read_csr(csr_addr); + t = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_MAXPOW); + if (!OCTEON_IS_MODEL(OCTEON_CN63XX)) { + s = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_HRMPOWADJ); + if (t < s) + return -EINVAL; + t = t - s; + } + s = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_POWLIM); + r = (s * 100)/t; + return r > 100 ? 100 : r; +} + +/* + * Set the POWLIM field as percentage% of the MAXPOW field in r. + */ +static uint64_t cvmx_power_throttle_set_powlim(int ppid, + uint8_t percentage) +{ + uint64_t t, csr_addr, r; + + if (percentage > 101) + return -EINVAL; + csr_addr = cvmx_power_throttle_csr_addr(ppid); + r = cvmx_read_csr(csr_addr); + t = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_MAXPOW); + if (!OCTEON_IS_MODEL(OCTEON_CN63XX)) { + uint64_t s; + s = cvmx_power_throttle_get_field(r, CVMX_PTH_INDEX_HRMPOWADJ); + if (t < s) + return -EINVAL; + t = t - s; + } + if (percentage > 0) + t = percentage * t / 100; + else + t = 0; + r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_POWLIM, r, t); + cvmx_write_csr(csr_addr, r); + return r; +} + +/* + * Given ppid, calculate its PowThrottle register's L2C_COP0_MAP CSR + * address. (ppid == PTH_PPID_BCAST is for broadcasting) + */ +static uint64_t cvmx_power_throttle_csr_addr(int ppid) +{ + uint64_t csr_addr, reg_num, reg_reg, reg_sel; + + if (ppid > CVMX_MAX_CORES) + return -EINVAL; + /* + * register 11 selection 6 + */ + reg_reg = 11; + reg_sel = 6; + reg_num = (ppid << 8) + (reg_reg << 3) + reg_sel; + csr_addr = CVMX_L2C_COP0_MAPX(0) + ((reg_num) << 3); + return csr_addr; +} + +static uint64_t cvmx_power_throttle_get_register(int ppid) +{ + uint64_t csr_addr; + + if (!cvmx_power_throttle_initialized) { + cvmx_power_throttle_init(); + cvmx_power_throttle_initialized = 1; + } + csr_addr = cvmx_power_throttle_csr_addr(ppid); + if (csr_addr == 0) + return -EINVAL; + + return cvmx_read_csr(csr_addr); +} + +#define CVMX_PTH_AVAILABLE \ + (cvmx_power_throttle_get_register(0) != (uint64_t)-1) + +#define define_pwr_throttle_one_rw(_name) \ + static DEVICE_ATTR(_name, 0644, power_throt_show_##_name, \ + power_throt_store_##_name) \ + +#define define_pwr_throttle_show_func(name) \ + \ +static ssize_t power_throt_show_##name( \ + struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + unsigned int cpu = dev->id; \ + ssize_t ret; \ + \ + preempt_disable(); /* CPU hotplug */ \ + if (cpu_online(cpu)) \ + ret = sprintf(buf, "%d\n", \ + cvmx_power_throttle_get_powlim(cpu)); \ + else \ + ret = 0; \ + preempt_enable(); \ + \ + return ret; \ +} + +#define define_pwr_throttle_store_func(name) \ + \ +static ssize_t power_throt_store_##name( \ + struct device *dev, \ + struct device_attribute *attr, \ + const char *buf, \ + size_t size) \ +{ \ + unsigned int cpu = dev->id; \ + unsigned long val; \ + int error; \ + \ + error = kstrtoul(buf, 0, &val); \ + if (error) \ + return error; \ + \ + preempt_disable(); \ + cvmx_power_throttle_set_powlim(cpu, val); \ + preempt_enable(); \ + \ + return size; \ +} + +define_pwr_throttle_store_func(percentage); +define_pwr_throttle_show_func(percentage); +define_pwr_throttle_one_rw(percentage); + +static struct attribute *pwr_throttle_attrs[] = { + &dev_attr_percentage.attr, + NULL +}; + +static struct attribute_group pwr_throttle_attr_group = { + .attrs = pwr_throttle_attrs, + .name = "power_throttle" +}; + +/* Mutex protecting device creation against CPU hotplug: */ +static DEFINE_MUTEX(pwr_throttl_cpu_lock); + +static __cpuinit int power_throttle_add_dev(struct device *dev) +{ + int err; + + err = sysfs_create_group(&dev->kobj, &pwr_throttle_attr_group); + if (err) + return err; + return err; +} + +static __cpuinit void power_throttle_remove_dev(struct device *dev) +{ + sysfs_remove_group(&dev->kobj, &pwr_throttle_attr_group); +} + +static __cpuinit int +power_throttle_cpu_callback(struct notifier_block *nfb, + unsigned long action, + void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + struct device *dev; + int err = 0; + + dev = get_cpu_device(cpu); + + switch (action) { + case CPU_ONLINE: + case CPU_DOWN_FAILED: + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: + mutex_lock(&pwr_throttl_cpu_lock); + err = power_throttle_add_dev(dev); + mutex_unlock(&pwr_throttl_cpu_lock); + WARN_ON(err); + break; + case CPU_UP_CANCELED: + case CPU_UP_CANCELED_FROZEN: + case CPU_DEAD: + case CPU_DEAD_FROZEN: + case CPU_DOWN_PREPARE: + mutex_lock(&pwr_throttl_cpu_lock); + power_throttle_remove_dev(dev); + mutex_unlock(&pwr_throttl_cpu_lock); + break; + } + return err ? NOTIFY_BAD : NOTIFY_OK; +} + +static struct notifier_block power_throttle_cpu_notifier = { + .notifier_call = power_throttle_cpu_callback, +}; + +static __init int power_throtl_init(void) +{ + unsigned int cpu = 0; + int err = 0; + + if (CVMX_PTH_AVAILABLE) { +#ifdef CONFIG_HOTPLUG_CPU + register_hotcpu_notifier(&power_throttle_cpu_notifier); + mutex_lock(&pwr_throttl_cpu_lock); +#endif + /* connect live CPUs to sysfs */ + for_each_online_cpu(cpu) { + err = power_throttle_add_dev(get_cpu_device(cpu)); + WARN_ON(err); + cvmx_init_throttle_feedback(cpu); + } +#ifdef CONFIG_HOTPLUG_CPU + mutex_unlock(&pwr_throttl_cpu_lock); +#endif + return err; + } + return 0; +} +device_initcall(power_throtl_init); -- 1.6.3.3.340.g77d18 From linus.walleij@linaro.org Thu Jul 5 15:02:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jul 2012 15:03:00 +0200 (CEST) Received: from mail-qc0-f177.google.com ([209.85.216.177]:65235 "EHLO mail-qc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903749Ab2GENCy (ORCPT ); Thu, 5 Jul 2012 15:02:54 +0200 Received: by qcsu28 with SMTP id u28so4892310qcs.36 for ; Thu, 05 Jul 2012 06:02:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:x-gm-message-state; bh=/qYkC7e4rYfHVxaB+eaVms3QGaOzRsDJgknvOpVz1oQ=; b=lbrKOASYnFw4a8tLYt/RFG6v/FNqTWwIdc0cyhe3cYZJHuW/aXDJCXd9vAJ/u3gWxF BfLcUaCOJpHv52l2yUaanMMTHDFkMwWb5iMeAFHcNE9/btRSximlRSIgTSB8vZLm1eMu vPLigeGuVN5estU+sjEnh1C3QSX0FZ/0CDw7lGMhhv6xIWYx1m9DZ0K9nFOj/A43meWp h5+d+Wb7XW+sd8DHxW5jzix69nQEGjnXpB051i8XR2fraa77gQTiG4gq3vabVHwmqOw1 u2d57ckAyUUlcKJMho4prDlCovy9Pp4EoH3dI7vE0+CHZXxoP0GQOqvb0KJFSnIrJ/zA NZZA== MIME-Version: 1.0 Received: by 10.229.115.12 with SMTP id g12mr12847685qcq.58.1341493368305; Thu, 05 Jul 2012 06:02:48 -0700 (PDT) Received: by 10.229.234.81 with HTTP; Thu, 5 Jul 2012 06:02:48 -0700 (PDT) In-Reply-To: <1340011706-32281-1-git-send-email-stigge@antcom.de> References: <1340011706-32281-1-git-send-email-stigge@antcom.de> Date: Thu, 5 Jul 2012 15:02:48 +0200 Message-ID: Subject: Re: [PATCH] mips: pci-lantiq: Fix check for valid gpio From: Linus Walleij To: Roland Stigge Cc: ralf@linux-mips.org, blogic@openwrt.org, jkosina@suse.cz, standby24x7@gmail.com, bhelgaas@google.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, grant.likely@secretlab.ca, linus.walleij@stericsson.com Content-Type: text/plain; charset=ISO-8859-1 X-Gm-Message-State: ALoCoQkYSOUb6Zsliupfl21hw9R+wN/s0kRhV8zobhMc3Q6IZcgTyr22RltbsIbcZxIg56xqrsAa X-archive-position: 33876 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linus.walleij@linaro.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 290 Lines: 11 On Mon, Jun 18, 2012 at 11:28 AM, Roland Stigge wrote: > This patch fixes two checks for valid gpio number, formerly (wrongly) > considering zero as invalid, now using gpio_is_valid(). > > Signed-off-by: Roland Stigge Applied. Thanks, Linus Walleij From codeblue@inbox.lv Thu Jul 5 18:02:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jul 2012 18:02:40 +0200 (CEST) Received: from shark4.inbox.lv ([89.111.3.84]:40911 "EHLO shark4.inbox.lv" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903735Ab2GEQCg (ORCPT ); Thu, 5 Jul 2012 18:02:36 +0200 Received: from mail.inbox.lv (pop [10.0.1.110]) by shark4-plain.inbox.lv (Postfix) with ESMTP id B19DC25353 for ; Thu, 5 Jul 2012 19:02:29 +0300 (EEST) Received: from inbox.lv (unknown [77.125.137.216]) (Authenticated sender: codeblue@inbox.lv) by mail.inbox.lv (Postfix) with ESMTPSA id 71D902A92A for ; Thu, 5 Jul 2012 19:02:26 +0300 (EEST) Date: Thu, 5 Jul 2012 16:02:22 +0000 From: Code Blue To: linux-mips@linux-mips.org Subject: Please recommend distro for Lemote Fuloong Message-ID: <20120705160222.GJ25225@inbox.lv> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-Virus-Scanned: OK X-archive-position: 33877 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: codeblue@inbox.lv Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 791 Lines: 18 Hi, I just received a Lemote Fuloong Mini and I installed OpenBSD on it. I would like to dual boot Linux but I am having a hard time finding the right distro. I know Lemote and MIPS people are doing a lot of work and submitting patches to the Linux kernel and binutils and I am sure many other areas. Can anyone please recommend a Linux distro that will come with (or can install) a recent kernel so I can take advantage of all this hard work people are doing? Of course I will need a tarball or USB installer since the Fuloong doesn't have an optical drive. Thank you. -- _ ASCII ribbon campaign ( ) Please follow up to the mailing list against HTML e-mail X and proprietary / \ Mutt.org attachments Code Blue or Go Home! From suprasad.desai@gmail.com Fri Jul 6 12:26:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jul 2012 12:26:29 +0200 (CEST) Received: from mail-wi0-f171.google.com ([209.85.212.171]:52884 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903548Ab2GFK0Z (ORCPT ); Fri, 6 Jul 2012 12:26:25 +0200 Received: by wibhq4 with SMTP id hq4so515363wib.6 for ; Fri, 06 Jul 2012 03:26:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=Q46MwWBCkV2SJzJzwn5Eenfn+2DZYEMz54e9nl3KusE=; b=pw+BZe+gMhud2yGJcGbMkgccNJ5TP85yxyWsC/Yz51VtvBN5i56xt234FI8I3h1AUT CjC19kSerspnxth99bjHFKE7r5fd10p4W5URI1Nv/JDpIFS3xvP89H9LpNU2Hx7DBJaX uLZhwUoB3oDzJvs6V1Jo5uhcmgtGRE/t8FZxS455wNwq2CC2sJGmg2K7w4HK8SEukkfO 6lgSTVpwVPss6XOg6luu0QZBVxEUbnzfcuXBtWbBJgX+ikq9L6GiuytpcwGuAm7UqkVd R8yWMzT+Q8gmQcswlNsAwzdtahUnc2esWvbQCgyhDcXHM8irItL9POec2mvbzvJAVJme ZAgw== MIME-Version: 1.0 Received: by 10.216.80.212 with SMTP id k62mr7592044wee.18.1341570380074; Fri, 06 Jul 2012 03:26:20 -0700 (PDT) Received: by 10.194.60.20 with HTTP; Fri, 6 Jul 2012 03:26:20 -0700 (PDT) Date: Fri, 6 Jul 2012 15:56:20 +0530 Message-ID: Subject: Bypass "find_busiest_queue" in VSMP (SMVP) mode From: Suprasad Mutalik Desai To: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=00504502d296f20cf404c426b1a2 X-archive-position: 33878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: suprasad.desai@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2354 Lines: 57 --00504502d296f20cf404c426b1a2 Content-Type: text/plain; charset=ISO-8859-1 Hi All, Currently i am running SMVP mode (2 VPEs each having one TC) on MIPS 34Kc . W.r.t load balancing logic, load_balance --> find_busiest_group (find the busiest group in the domain) --> find_busiest_queue (find the busiest runqueue among the cpus in group) In SMVP mode, each VPE is referred as groups and these VPEs (groups) have *ONLY* one TC (CPU) so do we still need to run "find_busiest_queue" to get the busiest runqueue among the cpus of a particular group . Instead of "find_busiest_queue" , can we use below code in "linux-2.6.32.42/kernel/sched.c" , +#ifdef CONFIG_MIPS_MT_SMP + cpu = cpumask_first(sched_group_cpus(group)) / * get the first CPU in the busiest group */ + busiest = cpu_rq (cpu) /* assign the runqueue of the cpu to busiest */ +#else busiest = find_busiest_queue(group, idle, imbalance, cpus); +#endif Please let me know your views . Thanks and Regards, Suprasad. --00504502d296f20cf404c426b1a2 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Hi All,

Currently i am running SMVP mode (2 VPEs each having one TC)= on MIPS 34Kc .=A0

W.r.t load balancing logic,
load_balance --&g= t; find_busiest_group (find the busiest group in the domain) --> find_bu= siest_queue (find the busiest runqueue among the cpus in group)

In SMVP mode, each VPE is referred as groups and these VPEs (groups) ha= ve *ONLY* one TC (CPU) so do we still need to run "find_busiest_queue&= quot; to get the busiest runqueue among the cpus of a particular group .
Instead of "find_busiest_queue" , can we use below code in &q= uot;linux-2.6.32.42/kernel/sched.c" ,

+#ifdef CONFIG_MIPS_MT_SM= P
+=A0=A0=A0=A0=A0=A0 cpu =3D cpumask_first(sched_group_cpus(group))=A0 = / * get the first CPU in the busiest group */
+=A0=A0=A0=A0=A0=A0 busiest =3D cpu_rq (cpu)=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* assign the runqueue of the cpu t= o busiest */
+#else
=A0=A0=A0=A0=A0=A0=A0 busiest =3D find_busiest_qu= eue(group, idle, imbalance, cpus);
+#endif

Please let me know you= r views .

Thanks and Regards,
Suprasad.
--00504502d296f20cf404c426b1a2-- From keguang.zhang@gmail.com Sat Jul 7 11:30:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Jul 2012 11:30:34 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:49663 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901166Ab2GGJaV (ORCPT ); Sat, 7 Jul 2012 11:30:21 +0200 Received: by pbbrq13 with SMTP id rq13so17888788pbb.36 for ; Sat, 07 Jul 2012 02:30:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=3ju8WvNY7xi2GYeY5hi8LsLpK3ktSZrCS5nbhLjRKCY=; b=BWI5kXjTmjV1D7iQrraGurGLWawmhYe1j9GeP2y7pPVE3Pd5oBGdRg9tUyMa8KJNp/ 5t37jIXJojFQr2NdB7F+H8qgPUWn7Ykt6892kP7WpKLIJ+qJql975zDVvrJTLQDSsljv Rk05s5g12SlZzzXYGf89EuLSGR8M7etpkRjFN0eA9ydGaCZu1E5hy00+VQ2toy2Ir4+N DfegJ6m6tt+SNz8rKZIz1d25uxeTnblGQKY3RqreiAJOPeaibpAcVImLkB1DQjJedqFl zazz8LfFOK75pyrFZNBvwZoD5oShaVDt+UOX/oyfUMdd82HJvnyunjrrNdrl7/7rPKOF 3ZRg== Received: by 10.66.83.200 with SMTP id s8mr51411331pay.10.1341653413704; Sat, 07 Jul 2012 02:30:13 -0700 (PDT) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id vz9sm23595458pbc.12.2012.07.07.02.30.06 (version=SSLv3 cipher=OTHER); Sat, 07 Jul 2012 02:30:12 -0700 (PDT) From: Kelvin Cheung To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ralf@linux-mips.org Cc: wuzhangjin@gmail.com, zhzhl555@gmail.com, Kelvin Cheung Subject: [PATCH V7 2/4] MIPS: Add board support for Loongson1B Date: Sat, 7 Jul 2012 17:29:58 +0800 Message-Id: <1341653400-24860-1-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 X-archive-position: 33879 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 27746 Lines: 1011 This patch adds basic platform devices for Loongson1B, including serial port, ethernet, usb, rtc and interrupt handler. Loongson1B UART is compatible with NS16550A. Loongson1B GMAC is built around Synopsys IP Core. Use normal descriptor instead of enhanced descriptor. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung --- V7(updated): 1.Remove 'ifdef' of platform devices. (Asked by Ralf) 2.Modify plat_stmmacenet_data accordingly due to the change of upstream. --- arch/mips/include/asm/mach-loongson1/irq.h | 73 ++++++++++ arch/mips/include/asm/mach-loongson1/loongson1.h | 44 ++++++ arch/mips/include/asm/mach-loongson1/platform.h | 23 +++ arch/mips/include/asm/mach-loongson1/prom.h | 24 +++ arch/mips/include/asm/mach-loongson1/regs-clk.h | 33 +++++ arch/mips/include/asm/mach-loongson1/regs-wdt.h | 22 +++ arch/mips/include/asm/mach-loongson1/war.h | 25 ++++ arch/mips/loongson1/common/clock.c | 165 ++++++++++++++++++++++ arch/mips/loongson1/common/irq.c | 147 +++++++++++++++++++ arch/mips/loongson1/common/platform.c | 124 ++++++++++++++++ arch/mips/loongson1/common/prom.c | 87 ++++++++++++ arch/mips/loongson1/common/reset.c | 45 ++++++ arch/mips/loongson1/common/setup.c | 29 ++++ arch/mips/loongson1/ls1b/board.c | 33 +++++ 14 files changed, 874 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h create mode 100644 arch/mips/include/asm/mach-loongson1/war.h create mode 100644 arch/mips/loongson1/common/clock.c create mode 100644 arch/mips/loongson1/common/irq.c create mode 100644 arch/mips/loongson1/common/platform.c create mode 100644 arch/mips/loongson1/common/prom.c create mode 100644 arch/mips/loongson1/common/reset.c create mode 100644 arch/mips/loongson1/common/setup.c create mode 100644 arch/mips/loongson1/ls1b/board.c diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h new file mode 100644 index 0000000..ccc42cc --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/irq.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * IRQ mappings for Loongson1. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_IRQ_H +#define __ASM_MACH_LOONGSON1_IRQ_H + +/* + * CPU core Interrupt Numbers + */ +#define MIPS_CPU_IRQ_BASE 0 +#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) + +#define SOFTINT0_IRQ MIPS_CPU_IRQ(0) +#define SOFTINT1_IRQ MIPS_CPU_IRQ(1) +#define INT0_IRQ MIPS_CPU_IRQ(2) +#define INT1_IRQ MIPS_CPU_IRQ(3) +#define INT2_IRQ MIPS_CPU_IRQ(4) +#define INT3_IRQ MIPS_CPU_IRQ(5) +#define INT4_IRQ MIPS_CPU_IRQ(6) +#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ + +#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) + +/* + * INT0~3 Interrupt Numbers + */ +#define LS1X_IRQ_BASE MIPS_CPU_IRQS +#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) + +#define LS1X_UART0_IRQ LS1X_IRQ(0, 2) +#define LS1X_UART1_IRQ LS1X_IRQ(0, 3) +#define LS1X_UART2_IRQ LS1X_IRQ(0, 4) +#define LS1X_UART3_IRQ LS1X_IRQ(0, 5) +#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) +#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) +#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) +#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) +#define LS1X_AC97_IRQ LS1X_IRQ(0, 10) +#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) +#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) +#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) +#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) +#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) +#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) +#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) +#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) +#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) +#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) +#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) +#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) +#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) +#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) +#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) + +#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) +#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) +#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) +#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) + +#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE) + +#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) + +#endif /* __ASM_MACH_LOONGSON1_IRQ_H */ diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h new file mode 100644 index 0000000..0440627 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/loongson1.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Register mappings for Loongson1. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H +#define __ASM_MACH_LOONGSON1_LOONGSON1_H + +#define DEFAULT_MEMSIZE 256 /* If no memsize provided */ + +/* Loongson1 Register Bases */ +#define LS1X_INTC_BASE 0x1fd01040 +#define LS1X_EHCI_BASE 0x1fe00000 +#define LS1X_OHCI_BASE 0x1fe08000 +#define LS1X_GMAC0_BASE 0x1fe10000 +#define LS1X_GMAC1_BASE 0x1fe20000 + +#define LS1X_UART0_BASE 0x1fe40000 +#define LS1X_UART1_BASE 0x1fe44000 +#define LS1X_UART2_BASE 0x1fe48000 +#define LS1X_UART3_BASE 0x1fe4c000 +#define LS1X_CAN0_BASE 0x1fe50000 +#define LS1X_CAN1_BASE 0x1fe54000 +#define LS1X_I2C0_BASE 0x1fe58000 +#define LS1X_I2C1_BASE 0x1fe68000 +#define LS1X_I2C2_BASE 0x1fe70000 +#define LS1X_PWM_BASE 0x1fe5c000 +#define LS1X_WDT_BASE 0x1fe5c060 +#define LS1X_RTC_BASE 0x1fe64000 +#define LS1X_AC97_BASE 0x1fe74000 +#define LS1X_NAND_BASE 0x1fe78000 +#define LS1X_CLK_BASE 0x1fe78030 + +#include +#include + +#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */ diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h new file mode 100644 index 0000000..2f17161 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/platform.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H +#define __ASM_MACH_LOONGSON1_PLATFORM_H + +#include + +extern struct platform_device ls1x_uart_device; +extern struct platform_device ls1x_eth0_device; +extern struct platform_device ls1x_ehci_device; +extern struct platform_device ls1x_rtc_device; + +void ls1x_serial_setup(void); + +#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h new file mode 100644 index 0000000..b871dc4 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/prom.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_PROM_H +#define __ASM_MACH_LOONGSON1_PROM_H + +#include +#include +#include + +/* environment arguments from bootloader */ +extern unsigned long memsize, highmemsize; + +/* loongson-specific command line, env and memory initialization */ +extern char *prom_getenv(char *name); +extern void __init prom_init_cmdline(void); + +#endif /* __ASM_MACH_LOONGSON1_PROM_H */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h new file mode 100644 index 0000000..5b9635a --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Loongson1 Clock Register Definitions. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H +#define __ASM_MACH_LOONGSON1_REGS_CLK_H + +#define LS1X_CLK_REG(x) \ + ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x))) + +#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) +#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) + +/* Clock PLL Divisor Register Bits */ +#define DIV_DC_EN (0x1 << 31) +#define DIV_DC (0x1f << 26) +#define DIV_CPU_EN (0x1 << 25) +#define DIV_CPU (0x1f << 20) +#define DIV_DDR_EN (0x1 << 19) +#define DIV_DDR (0x1f << 14) + +#define DIV_DC_SHIFT 26 +#define DIV_CPU_SHIFT 20 +#define DIV_DDR_SHIFT 14 + +#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h new file mode 100644 index 0000000..d339fe7 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Loongson1 Watchdog register definitions. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H +#define __ASM_MACH_LOONGSON1_REGS_WDT_H + +#define LS1X_WDT_REG(x) \ + ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x))) + +#define LS1X_WDT_EN LS1X_WDT_REG(0x0) +#define LS1X_WDT_SET LS1X_WDT_REG(0x4) +#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8) + +#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */ diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h new file mode 100644 index 0000000..e3680a8 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_LOONGSON1_WAR_H +#define __ASM_MACH_LOONGSON1_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_LOONGSON1_WAR_H */ diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c new file mode 100644 index 0000000..2d98fb0 --- /dev/null +++ b/arch/mips/loongson1/common/clock.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +struct clk *clk_get(struct device *dev, const char *name) +{ + struct clk *c; + struct clk *ret = NULL; + + mutex_lock(&clocks_mutex); + list_for_each_entry(c, &clocks, node) { + if (!strcmp(c->name, name)) { + ret = c; + break; + } + } + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL(clk_get); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +static void pll_clk_init(struct clk *clk) +{ + u32 pll; + + pll = __raw_readl(LS1X_CLK_PLL_FREQ); + clk->rate = (12 + (pll & 0x3f)) * 33 / 2 + + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2; + clk->rate *= 1000000; +} + +static void cpu_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU; + clk->rate = pll / (ctrl >> DIV_CPU_SHIFT); +} + +static void ddr_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR; + clk->rate = pll / (ctrl >> DIV_DDR_SHIFT); +} + +static void dc_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC; + clk->rate = pll / (ctrl >> DIV_DC_SHIFT); +} + +static struct clk_ops pll_clk_ops = { + .init = pll_clk_init, +}; + +static struct clk_ops cpu_clk_ops = { + .init = cpu_clk_init, +}; + +static struct clk_ops ddr_clk_ops = { + .init = ddr_clk_init, +}; + +static struct clk_ops dc_clk_ops = { + .init = dc_clk_init, +}; + +static struct clk pll_clk = { + .name = "pll", + .ops = &pll_clk_ops, +}; + +static struct clk cpu_clk = { + .name = "cpu", + .parent = &pll_clk, + .ops = &cpu_clk_ops, +}; + +static struct clk ddr_clk = { + .name = "ddr", + .parent = &pll_clk, + .ops = &ddr_clk_ops, +}; + +static struct clk dc_clk = { + .name = "dc", + .parent = &pll_clk, + .ops = &dc_clk_ops, +}; + +int clk_register(struct clk *clk) +{ + mutex_lock(&clocks_mutex); + list_add(&clk->node, &clocks); + if (clk->ops->init) + clk->ops->init(clk); + mutex_unlock(&clocks_mutex); + + return 0; +} +EXPORT_SYMBOL(clk_register); + +static struct clk *ls1x_clks[] = { + &pll_clk, + &cpu_clk, + &ddr_clk, + &dc_clk, +}; + +int __init ls1x_clock_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++) + clk_register(ls1x_clks[i]); + + return 0; +} + +void __init plat_time_init(void) +{ + struct clk *clk; + + /* Initialize LS1X clocks */ + ls1x_clock_init(); + + /* setup mips r4k timer */ + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get dc clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; +} diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/irq.c new file mode 100644 index 0000000..41bc8ff --- /dev/null +++ b/arch/mips/loongson1/common/irq.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include +#include + +#define LS1X_INTC_REG(n, x) \ + ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x))) + +#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0) +#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4) +#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8) +#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc) +#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10) +#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14) + +static void ls1x_irq_ack(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) + | (1 << bit), LS1X_INTC_INTCLR(n)); +} + +static void ls1x_irq_mask(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + & ~(1 << bit), LS1X_INTC_INTIEN(n)); +} + +static void ls1x_irq_mask_ack(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + & ~(1 << bit), LS1X_INTC_INTIEN(n)); + __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) + | (1 << bit), LS1X_INTC_INTCLR(n)); +} + +static void ls1x_irq_unmask(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + | (1 << bit), LS1X_INTC_INTIEN(n)); +} + +static struct irq_chip ls1x_irq_chip = { + .name = "LS1X-INTC", + .irq_ack = ls1x_irq_ack, + .irq_mask = ls1x_irq_mask, + .irq_mask_ack = ls1x_irq_mask_ack, + .irq_unmask = ls1x_irq_unmask, +}; + +static void ls1x_irq_dispatch(int n) +{ + u32 int_status, irq; + + /* Get pending sources, masked by current enables */ + int_status = __raw_readl(LS1X_INTC_INTISR(n)) & + __raw_readl(LS1X_INTC_INTIEN(n)); + + if (int_status) { + irq = LS1X_IRQ(n, __ffs(int_status)); + do_IRQ(irq); + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending; + + pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) + do_IRQ(TIMER_IRQ); + else if (pending & CAUSEF_IP2) + ls1x_irq_dispatch(0); /* INT0 */ + else if (pending & CAUSEF_IP3) + ls1x_irq_dispatch(1); /* INT1 */ + else if (pending & CAUSEF_IP4) + ls1x_irq_dispatch(2); /* INT2 */ + else if (pending & CAUSEF_IP5) + ls1x_irq_dispatch(3); /* INT3 */ + else if (pending & CAUSEF_IP6) + ls1x_irq_dispatch(4); /* INT4 */ + else + spurious_interrupt(); + +} + +struct irqaction cascade_irqaction = { + .handler = no_action, + .name = "cascade", + .flags = IRQF_NO_THREAD, +}; + +static void __init ls1x_irq_init(int base) +{ + int n; + + /* Disable interrupts and clear pending, + * setup all IRQs as high level triggered + */ + for (n = 0; n < 4; n++) { + __raw_writel(0x0, LS1X_INTC_INTIEN(n)); + __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n)); + __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n)); + /* set DMA0, DMA1 and DMA2 to edge trigger */ + __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n)); + } + + + for (n = base; n < LS1X_IRQS; n++) { + irq_set_chip_and_handler(n, &ls1x_irq_chip, + handle_level_irq); + } + + setup_irq(INT0_IRQ, &cascade_irqaction); + setup_irq(INT1_IRQ, &cascade_irqaction); + setup_irq(INT2_IRQ, &cascade_irqaction); + setup_irq(INT3_IRQ, &cascade_irqaction); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + ls1x_irq_init(LS1X_IRQ_BASE); +} diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/common/platform.c new file mode 100644 index 0000000..e92d59c --- /dev/null +++ b/arch/mips/loongson1/common/platform.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LS1X_UART(_id) \ + { \ + .mapbase = LS1X_UART ## _id ## _BASE, \ + .irq = LS1X_UART ## _id ## _IRQ, \ + .iotype = UPIO_MEM, \ + .flags = UPF_IOREMAP | UPF_FIXED_TYPE, \ + .type = PORT_16550A, \ + } + +static struct plat_serial8250_port ls1x_serial8250_port[] = { + LS1X_UART(0), + LS1X_UART(1), + LS1X_UART(2), + LS1X_UART(3), + {}, +}; + +struct platform_device ls1x_uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = ls1x_serial8250_port, + }, +}; + +void __init ls1x_serial_setup(void) +{ + struct clk *clk; + struct plat_serial8250_port *p; + + clk = clk_get(NULL, "dc"); + if (IS_ERR(clk)) + panic("unable to get dc clock, err=%ld", PTR_ERR(clk)); + + for (p = ls1x_serial8250_port; p->flags != 0; ++p) + p->uartclk = clk_get_rate(clk); +} + +/* Synopsys Ethernet GMAC */ +static struct resource ls1x_eth0_resources[] = { + [0] = { + .start = LS1X_GMAC0_BASE, + .end = LS1X_GMAC0_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "macirq", + .start = LS1X_GMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = { + .bus_id = 0, + .phy_mask = 0, +}; + +static struct plat_stmmacenet_data ls1x_eth_data = { + .bus_id = 0, + .phy_addr = -1, + .mdio_bus_data = &ls1x_mdio_bus_data, + .has_gmac = 1, + .tx_coe = 1, +}; + +struct platform_device ls1x_eth0_device = { + .name = "stmmaceth", + .id = 0, + .num_resources = ARRAY_SIZE(ls1x_eth0_resources), + .resource = ls1x_eth0_resources, + .dev = { + .platform_data = &ls1x_eth_data, + }, +}; + +/* USB EHCI */ +static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32); + +static struct resource ls1x_ehci_resources[] = { + [0] = { + .start = LS1X_EHCI_BASE, + .end = LS1X_EHCI_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = LS1X_EHCI_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ls1x_ehci_device = { + .name = "ls1x-ehci", + .id = -1, + .num_resources = ARRAY_SIZE(ls1x_ehci_resources), + .resource = ls1x_ehci_resources, + .dev = { + .dma_mask = &ls1x_ehci_dmamask, + }, +}; + +/* Real Time Clock */ +struct platform_device ls1x_rtc_device = { + .name = "ls1x-rtc", + .id = -1, +}; diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c new file mode 100644 index 0000000..1f8e49f --- /dev/null +++ b/arch/mips/loongson1/common/prom.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Modified from arch/mips/pnx833x/common/prom.c. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +unsigned long memsize, highmemsize; + +char *prom_getenv(char *envname) +{ + char **env = prom_envp; + int i; + + i = strlen(envname); + + while (*env) { + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') + return *env + i + 1; + env++; + } + + return 0; +} + +static inline unsigned long env_or_default(char *env, unsigned long dfl) +{ + char *str = prom_getenv(env); + return str ? simple_strtol(str, 0, 0) : dfl; +} + +void __init prom_init_cmdline(void) +{ + char *c = &(arcs_cmdline[0]); + int i; + + for (i = 1; i < prom_argc; i++) { + strcpy(c, prom_argv[i]); + c += strlen(prom_argv[i]); + if (i < prom_argc-1) + *c++ = ' '; + } + *c = 0; +} + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize = env_or_default("memsize", DEFAULT_MEMSIZE); + highmemsize = env_or_default("highmemsize", 0x0); +} + +void __init prom_free_prom_memory(void) +{ +} + +#define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset)) + +void __init prom_putchar(char c) +{ + int timeout; + + timeout = 1024; + + while (((readb(PORT(UART_LSR)) & UART_LSR_THRE) == 0) + && (timeout-- > 0)) + ; + + writeb(c, PORT(UART_TX)); +} diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c new file mode 100644 index 0000000..fb979a7 --- /dev/null +++ b/arch/mips/loongson1/common/reset.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include + +static void ls1x_restart(char *command) +{ + __raw_writel(0x1, LS1X_WDT_EN); + __raw_writel(0x5000000, LS1X_WDT_TIMER); + __raw_writel(0x1, LS1X_WDT_SET); +} + +static void ls1x_halt(void) +{ + while (1) { + if (cpu_wait) + cpu_wait(); + } +} + +static void ls1x_power_off(void) +{ + ls1x_halt(); +} + +static int __init ls1x_reboot_setup(void) +{ + _machine_restart = ls1x_restart; + _machine_halt = ls1x_halt; + pm_power_off = ls1x_power_off; + + return 0; +} + +arch_initcall(ls1x_reboot_setup); diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/common/setup.c new file mode 100644 index 0000000..62128cc --- /dev/null +++ b/arch/mips/loongson1/common/setup.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +void __init plat_mem_setup(void) +{ + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +} + +const char *get_system_type(void) +{ + unsigned int processor_id = (¤t_cpu_data)->processor_id; + + switch (processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON1B: + return "LOONGSON LS1B"; + default: + return "LOONGSON (unknown)"; + } +} diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c new file mode 100644 index 0000000..295b1be --- /dev/null +++ b/arch/mips/loongson1/ls1b/board.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +static struct platform_device *ls1b_platform_devices[] __initdata = { + &ls1x_uart_device, + &ls1x_eth0_device, + &ls1x_ehci_device, + &ls1x_rtc_device, +}; + +static int __init ls1b_platform_init(void) +{ + int err; + + ls1x_serial_setup(); + + err = platform_add_devices(ls1b_platform_devices, + ARRAY_SIZE(ls1b_platform_devices)); + return err; +} + +arch_initcall(ls1b_platform_init); -- 1.7.1 From keguang.zhang@gmail.com Sat Jul 7 11:30:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Jul 2012 11:30:57 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:49663 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903393Ab2GGJaY (ORCPT ); Sat, 7 Jul 2012 11:30:24 +0200 Received: by mail-pb0-f49.google.com with SMTP id rq13so17888788pbb.36 for ; Sat, 07 Jul 2012 02:30:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=E/+6Npb6c1lMdENGLTk3c2o9fCzoE8HiXHGWv6gfPsY=; b=B940LPf5ufJ2ycMpY19lYguMHAkDBf+/3Oz2yAMZ3Pbvuxc2NXtomHFBZKLok/8OGd xNy3w9KJdyCc132UB4pq37mCByd1z5sTVhwh4emuQtZEf9RR0PDqjJYC8hMYt26c+JaG zI0s+vnxVIkX2slRGcMtkyc7ufqwOAsmCYTbZsS+db10GnaBKnJcwiDz2fDutFr2gwyA qU9o3zF4d1WEPtBubgCHC3UFuqQdZLg1pZmYHd85cGA9/GOICiut97v4Oo2OBUWmF4a4 k8DuoLuqfVuTEG4XpL1l5MkE8sZjIZODwlQVr7DSHm/9PxjiBtFlkT3Q25KgU9B8e9O2 F7PQ== Received: by 10.68.201.195 with SMTP id kc3mr44363805pbc.33.1341653423481; Sat, 07 Jul 2012 02:30:23 -0700 (PDT) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id vz9sm23595458pbc.12.2012.07.07.02.30.19 (version=SSLv3 cipher=OTHER); Sat, 07 Jul 2012 02:30:22 -0700 (PDT) From: Kelvin Cheung To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ralf@linux-mips.org Cc: wuzhangjin@gmail.com, zhzhl555@gmail.com, Kelvin Cheung Subject: [PATCH V7 4/4] MIPS: Add defconfig for Loongson1B Date: Sat, 7 Jul 2012 17:30:00 +0800 Message-Id: <1341653400-24860-3-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1341653400-24860-1-git-send-email-keguang.zhang@gmail.com> References: <1341653400-24860-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 33880 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3560 Lines: 131 This patch adds defconfig for Loongson1B. Signed-off-by: Kelvin Cheung --- V7(updated): Add CONFIG_USB_ANNOUNCE_NEW_DEVICES in default configuration. --- arch/mips/configs/ls1b_defconfig | 109 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 109 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/ls1b_defconfig diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig new file mode 100644 index 0000000..80cff8b --- /dev/null +++ b/arch/mips/configs/ls1b_defconfig @@ -0,0 +1,109 @@ +CONFIG_MACH_LOONGSON1=y +CONFIG_PREEMPT=y +# CONFIG_SECCOMP is not set +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_SCSI=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=m +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_DA=y +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=8 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB_HID=m +CONFIG_HID_GENERIC=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_STORAGE=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_LOONGSON1=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +# CONFIG_EARLY_PRINTK is not set -- 1.7.1 From keguang.zhang@gmail.com Sat Jul 7 11:30:25 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Jul 2012 11:31:29 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:49439 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903520Ab2GGJaZ (ORCPT ); Sat, 7 Jul 2012 11:30:25 +0200 Received: by pbbrq13 with SMTP id rq13so17888931pbb.36 for ; Sat, 07 Jul 2012 02:30:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=80p4AWDn8gStwztO1Y57NIC1eU+Sr9lhkR8jhE+KrPc=; b=SpVkOcdtZdSWJAU7AiCEDvFYaPC7OguZTosqYLMjPh6I3ppMtAl+6r64HgdZLjGh1U nrvrj+hWO3PKMuRV22QEM9AajkRQN75QU8Y6TBqWrU8J7jGspVSdRKIkk6cUPmw9xhzi P5BGqoILm9q0j5+Abg5+/Zh6mUp7IOLzwvn+4fGy2l9V5gq4XgvDcy+5FSeN7GjfxhFo pzMmDTluHjmI4xkJs7woY+PIXsUjE2kkFwo0a7XDluGfrYsCHcN99VVAATY4s9aY+6ZC cW8rJh2I2Hb8yuWxXQm6WyslmV5GvssPYwVB6Y1czCFxJ/uN5es8LCW4ccRMdHeJlySh Tn8w== Received: by 10.66.81.3 with SMTP id v3mr32961092pax.62.1341653418642; Sat, 07 Jul 2012 02:30:18 -0700 (PDT) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id vz9sm23595458pbc.12.2012.07.07.02.30.14 (version=SSLv3 cipher=OTHER); Sat, 07 Jul 2012 02:30:17 -0700 (PDT) From: Kelvin Cheung To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ralf@linux-mips.org Cc: wuzhangjin@gmail.com, zhzhl555@gmail.com, Kelvin Cheung Subject: [PATCH V7 3/4] MIPS: Add Makefile and Kconfig for Loongson1B Date: Sat, 7 Jul 2012 17:29:59 +0800 Message-Id: <1341653400-24860-2-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1341653400-24860-1-git-send-email-keguang.zhang@gmail.com> References: <1341653400-24860-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 33881 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5266 Lines: 186 This patch adds Makefile and Kconfig related to Loongson1B. Signed-off-by: Kelvin Cheung --- V7(updated): Change the load address of kernel to 0xffffffff80100000. --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 31 +++++++++++++++++++++++++++++++ arch/mips/loongson1/Kconfig | 21 +++++++++++++++++++++ arch/mips/loongson1/Makefile | 11 +++++++++++ arch/mips/loongson1/Platform | 7 +++++++ arch/mips/loongson1/common/Makefile | 5 +++++ arch/mips/loongson1/ls1b/Makefile | 5 +++++ 7 files changed, 81 insertions(+), 0 deletions(-) create mode 100644 arch/mips/loongson1/Kconfig create mode 100644 arch/mips/loongson1/Makefile create mode 100644 arch/mips/loongson1/Platform create mode 100644 arch/mips/loongson1/common/Makefile create mode 100644 arch/mips/loongson1/ls1b/Makefile diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 5ce8029..d64786d 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -14,6 +14,7 @@ platforms += jz4740 platforms += lantiq platforms += lasat platforms += loongson +platforms += loongson1 platforms += mipssim platforms += mti-malta platforms += netlogic diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 08dfc79..61e1459 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -265,6 +265,17 @@ config MACH_LOONGSON Chinese Academy of Sciences (CAS) in the People's Republic of China. The chief architect is Professor Weiwu Hu. +config MACH_LOONGSON1 + bool "Loongson1 family of machines" + select SYS_SUPPORTS_ZBOOT + help + This enables the support of Loongson1 family of machines. + + Loongson1 is a family of 32-bit MIPS-compatible SoCs. + developed at Institute of Computing Technology (ICT), + Chinese Academy of Sciences (CAS) in the People's Republic + of China. + config MIPS_MALTA bool "MIPS Malta board" select ARCH_MAY_HAVE_PC_FDC @@ -838,6 +849,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/loongson1/Kconfig" source "arch/mips/netlogic/Kconfig" endmenu @@ -1219,6 +1231,14 @@ config CPU_LOONGSON2F have a similar programming interface with FPGA northbridge used in Loongson2E. +config CPU_LOONGSON1B + bool "Loongson 1B" + depends on SYS_HAS_CPU_LOONGSON1B + select CPU_LOONGSON1 + help + The Loongson 1B is a 32-bit SoC, which implements the MIPS32 + release 2 instruction set. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1548,6 +1568,14 @@ config CPU_LOONGSON2 select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM +config CPU_LOONGSON1 + bool + select CPU_MIPS32 + select CPU_MIPSR2 + select CPU_HAS_PREFETCH + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + config CPU_BMIPS bool select CPU_MIPS32 @@ -1566,6 +1594,9 @@ config SYS_HAS_CPU_LOONGSON2F select CPU_SUPPORTS_ADDRWINCFG if 64BIT select CPU_SUPPORTS_UNCACHED_ACCELERATED +config SYS_HAS_CPU_LOONGSON1B + bool + config SYS_HAS_CPU_MIPS32_R1 bool diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig new file mode 100644 index 0000000..237fa21 --- /dev/null +++ b/arch/mips/loongson1/Kconfig @@ -0,0 +1,21 @@ +if MACH_LOONGSON1 + +choice + prompt "Machine Type" + +config LOONGSON1_LS1B + bool "Loongson LS1B board" + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON1B + select DMA_NONCOHERENT + select BOOT_ELF32 + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + +endchoice + +endif # MACH_LOONGSON1 diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile new file mode 100644 index 0000000..e9123c2 --- /dev/null +++ b/arch/mips/loongson1/Makefile @@ -0,0 +1,11 @@ +# +# Common code for all Loongson1 based systems +# + +obj-$(CONFIG_MACH_LOONGSON1) += common/ + +# +# Loongson LS1B board +# + +obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/ diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform new file mode 100644 index 0000000..99bdefe --- /dev/null +++ b/arch/mips/loongson1/Platform @@ -0,0 +1,7 @@ +cflags-$(CONFIG_CPU_LOONGSON1) += \ + $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ + -Wa,-mips32r2 -Wa,--trap + +platform-$(CONFIG_MACH_LOONGSON1) += loongson1/ +cflags-$(CONFIG_MACH_LOONGSON1) += -I$(srctree)/arch/mips/include/asm/mach-loongson1 +load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000 diff --git a/arch/mips/loongson1/common/Makefile b/arch/mips/loongson1/common/Makefile new file mode 100644 index 0000000..b279770 --- /dev/null +++ b/arch/mips/loongson1/common/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for common code of loongson1 based machines. +# + +obj-y += clock.o irq.o platform.o prom.o reset.o setup.o diff --git a/arch/mips/loongson1/ls1b/Makefile b/arch/mips/loongson1/ls1b/Makefile new file mode 100644 index 0000000..891eac4 --- /dev/null +++ b/arch/mips/loongson1/ls1b/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for loongson1B based machines. +# + +obj-y += board.o -- 1.7.1 From miloody@gmail.com Sat Jul 7 12:46:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Jul 2012 12:46:14 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:64115 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903536Ab2GGKqL (ORCPT ); Sat, 7 Jul 2012 12:46:11 +0200 Received: by pbbrq13 with SMTP id rq13so17992104pbb.36 for ; Sat, 07 Jul 2012 03:46:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=oJJzLxk/hth57NsKmfLEIdZ8/cQGoSR5jz7JIRkPZ3U=; b=Mi66/lqepcnEk7WZDBN9cCPrl5JnVrE/kVfZ2zO4MxrAZTn0tTyuC2ysuMhAV7lV84 JwwJ9chWQJOaYRy4uWU6+TYbNfKxD/NEtfHGV2WqbGh0jhK5mIDkkWHftb3zykCNwxY2 SwZTN7Z6/Atwh/+CAsbUhRlV6hVauXOeLUzWO+UUUtgf6gW7MFL9Vifuyz+yTTqj/oeo WXgpwEs6O/k/p+sjYNuCJOz8GMjq/rz/KOqLpi5VWtD2uHNd237EbDPnD7kX3G6caYI1 edaeJpVJ6Q3fpvkwoJe/vGHpB8ofojg0GyQ5d5TbEjonoB3FWSxi7iZcjfLa/eaXuDVG 3rEQ== MIME-Version: 1.0 Received: by 10.68.221.74 with SMTP id qc10mr43793629pbc.31.1341657964685; Sat, 07 Jul 2012 03:46:04 -0700 (PDT) Received: by 10.68.240.41 with HTTP; Sat, 7 Jul 2012 03:46:04 -0700 (PDT) Date: Sat, 7 Jul 2012 18:46:04 +0800 Message-ID: Subject: some question about struct ktermios From: loody To: Linux MIPS Mailing List , Kernel Newbies , kernelnewbies@kernelnewbies.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33882 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 182 Lines: 8 Dear all "struct ktermios" is the struct used for terminal. Why the header file is put at arch/mips/include/asm/termbits.h Doesn't it should located at kernel/include? -- Regards From p.ittershagen@googlemail.com Sat Jul 7 12:54:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Jul 2012 12:54:26 +0200 (CEST) Received: from mail-wg0-f43.google.com ([74.125.82.43]:65136 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903536Ab2GGKyX (ORCPT ); Sat, 7 Jul 2012 12:54:23 +0200 Received: by wgbdr1 with SMTP id dr1so9194157wgb.24 for ; Sat, 07 Jul 2012 03:54:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=6uraLCkiggtfykfJXki+ig7UJeR8qNIKKAeguw6iaUw=; b=dA9Wt44Gd0fEqrzICG+Rlfm0f4NylLaqrv39hJNEzxYPIwX1TZBIqDmGEetOfz+kxP lRcx36HJlJiLHUOgsKwMdU6qWIAZCKRbqxKVxbR1NUq69xpYYY4Dvk2B9KnVYobYUQzx WYdJ1qIsnMOmSWLZkg5dIGS8iSVAxPjq7CWhPzhr0jEbYMDWu4WBGDb4QKpjPKZy0mSo KK3ZqguhzqaJL7f5wydRIryAYObl3h1bFjyHIQ1jg1uMu69L2s/FAex1DBzdWge0U0Mg g0E8aXejqzYA3Ano1PEaf3Lei/2JqieoL0COmCmCVWDd5+VYLTmR8hsmjyYJhXdAaV9b ReoQ== MIME-Version: 1.0 Received: by 10.180.20.239 with SMTP id q15mr14661517wie.13.1341658458076; Sat, 07 Jul 2012 03:54:18 -0700 (PDT) Received: by 10.194.59.106 with HTTP; Sat, 7 Jul 2012 03:54:18 -0700 (PDT) In-Reply-To: References: Date: Sat, 7 Jul 2012 12:54:18 +0200 X-Google-Sender-Auth: b9vIbuaWiO44RtCaQPsvbL0SbkM Message-ID: Subject: Re: some question about struct ktermios From: Philipp Ittershagen To: loody Cc: Linux MIPS Mailing List , Kernel Newbies , kernelnewbies@kernelnewbies.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 33883 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: p.ittershagen@googlemail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 385 Lines: 16 On Sat, Jul 7, 2012 at 12:46 PM, loody wrote: > Dear all > "struct ktermios" is the struct used for terminal. > Why the header file is put at arch/mips/include/asm/termbits.h > Doesn't it should located at kernel/include? That is the architecture-specific definition. The generic definition can be found at include/asm-generic/termbits.h Greetings, Philipp From cernekee@gmail.com Mon Jul 9 04:47:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jul 2012 04:48:04 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:45206 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1903438Ab2GICrz (ORCPT ); Mon, 9 Jul 2012 04:47:55 +0200 Received: (qmail 24390 invoked from network); 9 Jul 2012 02:47:51 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 9 Jul 2012 02:47:51 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sun, 08 Jul 2012 19:47:51 -0700 From: Kevin Cernekee To: ralf@linux-mips.org Cc: , , , Subject: [PATCH V2 2/7] MIPS: BCM63XX: Move DMA descriptor definition into common header file Date: Sun, 08 Jul 2012 19:41:18 -0700 Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 33884 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3203 Lines: 109 The "IUDMA" engine used by bcm63xx_enet is also used by other blocks, such as the USB 2.0 device. Move the definitions into a common file so that they do not need to be duplicated in each driver. Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h | 34 ++++++++++++++++++++++ drivers/net/ethernet/broadcom/bcm63xx_enet.h | 30 +------------------ 2 files changed, 35 insertions(+), 29 deletions(-) create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h V2: Move this into a separate, non-enet-related header file. I'll submit another patch to rename "enet" / "DMADESC" to "IUDMA" after Maxime's enetsw patches are merged. diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h new file mode 100644 index 0000000..358cf28 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h @@ -0,0 +1,34 @@ +#ifndef BCM63XX_IUDMA_H_ +#define BCM63XX_IUDMA_H_ + +#include + +/* + * rx/tx dma descriptor + */ +struct bcm_enet_desc { + u32 len_stat; + u32 address; +}; + +#define DMADESC_LENGTH_SHIFT 16 +#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) +#define DMADESC_OWNER_MASK (1 << 15) +#define DMADESC_EOP_MASK (1 << 14) +#define DMADESC_SOP_MASK (1 << 13) +#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) +#define DMADESC_WRAP_MASK (1 << 12) + +#define DMADESC_UNDER_MASK (1 << 9) +#define DMADESC_APPEND_CRC (1 << 8) +#define DMADESC_OVSIZE_MASK (1 << 4) +#define DMADESC_RXER_MASK (1 << 2) +#define DMADESC_CRC_MASK (1 << 1) +#define DMADESC_OV_MASK (1 << 0) +#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ + DMADESC_OVSIZE_MASK | \ + DMADESC_RXER_MASK | \ + DMADESC_CRC_MASK | \ + DMADESC_OV_MASK) + +#endif /* ! BCM63XX_IUDMA_H_ */ diff --git a/drivers/net/ethernet/broadcom/bcm63xx_enet.h b/drivers/net/ethernet/broadcom/bcm63xx_enet.h index 0e3048b..133d585 100644 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h @@ -10,6 +10,7 @@ #include #include #include +#include /* default number of descriptor */ #define BCMENET_DEF_RX_DESC 64 @@ -31,35 +32,6 @@ #define BCMENET_MAX_MTU 2046 /* - * rx/tx dma descriptor - */ -struct bcm_enet_desc { - u32 len_stat; - u32 address; -}; - -#define DMADESC_LENGTH_SHIFT 16 -#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) -#define DMADESC_OWNER_MASK (1 << 15) -#define DMADESC_EOP_MASK (1 << 14) -#define DMADESC_SOP_MASK (1 << 13) -#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) -#define DMADESC_WRAP_MASK (1 << 12) - -#define DMADESC_UNDER_MASK (1 << 9) -#define DMADESC_APPEND_CRC (1 << 8) -#define DMADESC_OVSIZE_MASK (1 << 4) -#define DMADESC_RXER_MASK (1 << 2) -#define DMADESC_CRC_MASK (1 << 1) -#define DMADESC_OV_MASK (1 << 0) -#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ - DMADESC_OVSIZE_MASK | \ - DMADESC_RXER_MASK | \ - DMADESC_CRC_MASK | \ - DMADESC_OV_MASK) - - -/* * MIB Counters register definitions */ #define ETH_MIB_TX_GD_OCTETS 0 -- 1.7.11.1 From cernekee@gmail.com Mon Jul 9 04:47:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jul 2012 04:48:32 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:45214 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1903471Ab2GICr5 (ORCPT ); Mon, 9 Jul 2012 04:47:57 +0200 Received: (qmail 24398 invoked from network); 9 Jul 2012 02:47:54 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 9 Jul 2012 02:47:54 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sun, 08 Jul 2012 19:47:54 -0700 From: Kevin Cernekee To: ralf@linux-mips.org Cc: , , , Subject: [PATCH V2 3/7] MIPS: BCM63XX: Add new IUDMA definitions needed for USBD Date: Sun, 08 Jul 2012 19:41:19 -0700 Message-Id: <8dea894598ce64bd8834a48e395dcd07@localhost> In-Reply-To: References: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 33885 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2642 Lines: 72 Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h | 4 ++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 12 ++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) V2: These go into bcm63xx_iudma.h now; see previous post. Add BUFHALT bit. Use ENETDMAC_* instead of ENETDMA_* where warranted (the constants are identical, name change only). diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h index 358cf28..a5bbff3 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h @@ -11,6 +11,7 @@ struct bcm_enet_desc { u32 address; }; +/* control */ #define DMADESC_LENGTH_SHIFT 16 #define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) #define DMADESC_OWNER_MASK (1 << 15) @@ -18,7 +19,10 @@ struct bcm_enet_desc { #define DMADESC_SOP_MASK (1 << 13) #define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) #define DMADESC_WRAP_MASK (1 << 12) +#define DMADESC_USB_NOZERO_MASK (1 << 1) +#define DMADESC_USB_ZERO_MASK (1 << 0) +/* status */ #define DMADESC_UNDER_MASK (1 << 9) #define DMADESC_APPEND_CRC (1 << 8) #define DMADESC_OVSIZE_MASK (1 << 4) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 4ccc2a7..7a10112 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -670,6 +670,12 @@ #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) +/* Global interrupt status */ +#define ENETDMA_GLB_IRQSTAT_REG (0x40) + +/* Global interrupt mask */ +#define ENETDMA_GLB_IRQMASK_REG (0x44) + /* Channel Configuration register */ #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) #define ENETDMA_CHANCFG_EN_SHIFT 0 @@ -709,9 +715,11 @@ /* Channel Configuration register */ #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) #define ENETDMAC_CHANCFG_EN_SHIFT 0 -#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) +#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 -#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) +#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) +#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 +#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) /* Interrupt Control/Status register */ #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) -- 1.7.11.1 From cernekee@gmail.com Mon Jul 9 04:47:59 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jul 2012 04:48:55 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:45220 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1903472Ab2GICr7 (ORCPT ); Mon, 9 Jul 2012 04:47:59 +0200 Received: (qmail 24406 invoked from network); 9 Jul 2012 02:47:56 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 9 Jul 2012 02:47:56 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sun, 08 Jul 2012 19:47:56 -0700 From: Kevin Cernekee To: ralf@linux-mips.org Cc: , , , Subject: [PATCH V2 6/7] MIPS: BCM63XX: Add register and IRQ definitions for USB 2.0 device Date: Sun, 08 Jul 2012 19:41:20 -0700 Message-Id: <4bd8d0a281e5678919fd10b90bb4472d@localhost> In-Reply-To: References: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 33886 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 16328 Lines: 395 Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 75 ++++++++++- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 147 ++++++++++++++++++++++ 2 files changed, 221 insertions(+), 1 deletion(-) V2: Rename USBDMA IRQs so they are closer to the ENET names. diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index c0e6333..1ac5704 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -120,6 +120,8 @@ enum bcm63xx_regs_set { RSET_OHCI0, RSET_OHCI_PRIV, RSET_USBH_PRIV, + RSET_USBD, + RSET_USBDMA, RSET_MPI, RSET_PCMCIA, RSET_PCIE, @@ -162,6 +164,8 @@ enum bcm63xx_regs_set { #define RSET_UDC_SIZE 256 #define RSET_OHCI_SIZE 256 #define RSET_EHCI_SIZE 256 +#define RSET_USBD_SIZE 256 +#define RSET_USBDMA_SIZE 1280 #define RSET_PCMCIA_SIZE 12 #define RSET_M2M_SIZE 256 #define RSET_ATM_SIZE 4096 @@ -183,10 +187,11 @@ enum bcm63xx_regs_set { #define BCM_6328_GPIO_BASE (0xb0000080) #define BCM_6328_SPI_BASE (0xdeadbeef) #define BCM_6328_UDC0_BASE (0xdeadbeef) -#define BCM_6328_USBDMA_BASE (0xdeadbeef) +#define BCM_6328_USBDMA_BASE (0xb000c000) #define BCM_6328_OHCI0_BASE (0xb0002600) #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6328_USBH_PRIV_BASE (0xb0002700) +#define BCM_6328_USBD_BASE (0xb0002400) #define BCM_6328_MPI_BASE (0xdeadbeef) #define BCM_6328_PCMCIA_BASE (0xdeadbeef) #define BCM_6328_PCIE_BASE (0xb0e40000) @@ -232,6 +237,7 @@ enum bcm63xx_regs_set { #define BCM_6338_OHCI0_BASE (0xdeadbeef) #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6338_USBD_BASE (0xdeadbeef) #define BCM_6338_MPI_BASE (0xfffe3160) #define BCM_6338_PCMCIA_BASE (0xdeadbeef) #define BCM_6338_PCIE_BASE (0xdeadbeef) @@ -286,6 +292,7 @@ enum bcm63xx_regs_set { #define BCM_6345_OHCI0_BASE (0xfffe2100) #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6345_USBD_BASE (0xdeadbeef) #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6345_DSL_BASE (0xdeadbeef) #define BCM_6345_UBUS_BASE (0xdeadbeef) @@ -319,9 +326,11 @@ enum bcm63xx_regs_set { #define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_SPI_BASE (0xfffe0c00) #define BCM_6348_UDC0_BASE (0xfffe1000) +#define BCM_6348_USBDMA_BASE (0xdeadbeef) #define BCM_6348_OHCI0_BASE (0xfffe1b00) #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6348_USBD_BASE (0xdeadbeef) #define BCM_6348_MPI_BASE (0xfffe2000) #define BCM_6348_PCMCIA_BASE (0xfffe2054) #define BCM_6348_PCIE_BASE (0xdeadbeef) @@ -362,9 +371,11 @@ enum bcm63xx_regs_set { #define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_SPI_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800) +#define BCM_6358_USBDMA_BASE (0xdeadbeef) #define BCM_6358_OHCI0_BASE (0xfffe1400) #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) +#define BCM_6358_USBD_BASE (0xdeadbeef) #define BCM_6358_MPI_BASE (0xfffe1000) #define BCM_6358_PCMCIA_BASE (0xfffe1054) #define BCM_6358_PCIE_BASE (0xdeadbeef) @@ -406,9 +417,11 @@ enum bcm63xx_regs_set { #define BCM_6368_GPIO_BASE (0xb0000080) #define BCM_6368_SPI_BASE (0xb0000800) #define BCM_6368_UDC0_BASE (0xdeadbeef) +#define BCM_6368_USBDMA_BASE (0xb0004800) #define BCM_6368_OHCI0_BASE (0xb0001600) #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6368_USBH_PRIV_BASE (0xb0001700) +#define BCM_6368_USBD_BASE (0xb0001400) #define BCM_6368_MPI_BASE (0xb0001000) #define BCM_6368_PCMCIA_BASE (0xb0001054) #define BCM_6368_PCIE_BASE (0xdeadbeef) @@ -458,6 +471,8 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ __GEN_RSET_BASE(__cpu, USBH_PRIV) \ + __GEN_RSET_BASE(__cpu, USBD) \ + __GEN_RSET_BASE(__cpu, USBDMA) \ __GEN_RSET_BASE(__cpu, MPI) \ __GEN_RSET_BASE(__cpu, PCMCIA) \ __GEN_RSET_BASE(__cpu, PCIE) \ @@ -499,6 +514,8 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ + [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \ + [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \ [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ @@ -569,6 +586,13 @@ enum bcm63xx_irq { IRQ_ENET_PHY, IRQ_OHCI0, IRQ_EHCI0, + IRQ_USBD, + IRQ_USBD_RXDMA0, + IRQ_USBD_TXDMA0, + IRQ_USBD_RXDMA1, + IRQ_USBD_TXDMA1, + IRQ_USBD_RXDMA2, + IRQ_USBD_TXDMA2, IRQ_ENET0_RXDMA, IRQ_ENET0_TXDMA, IRQ_ENET1_RXDMA, @@ -604,6 +628,13 @@ enum bcm63xx_irq { #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) +#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) #define BCM_6328_PCMCIA_IRQ 0 #define BCM_6328_ENET0_RXDMA_IRQ 0 #define BCM_6328_ENET0_TXDMA_IRQ 0 @@ -642,6 +673,13 @@ enum bcm63xx_irq { #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6338_OHCI0_IRQ 0 #define BCM_6338_EHCI0_IRQ 0 +#define BCM_6338_USBD_IRQ 0 +#define BCM_6338_USBD_RXDMA0_IRQ 0 +#define BCM_6338_USBD_TXDMA0_IRQ 0 +#define BCM_6338_USBD_RXDMA1_IRQ 0 +#define BCM_6338_USBD_TXDMA1_IRQ 0 +#define BCM_6338_USBD_RXDMA2_IRQ 0 +#define BCM_6338_USBD_TXDMA2_IRQ 0 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) #define BCM_6338_ENET1_RXDMA_IRQ 0 @@ -673,6 +711,13 @@ enum bcm63xx_irq { #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6345_OHCI0_IRQ 0 #define BCM_6345_EHCI0_IRQ 0 +#define BCM_6345_USBD_IRQ 0 +#define BCM_6345_USBD_RXDMA0_IRQ 0 +#define BCM_6345_USBD_TXDMA0_IRQ 0 +#define BCM_6345_USBD_RXDMA1_IRQ 0 +#define BCM_6345_USBD_TXDMA1_IRQ 0 +#define BCM_6345_USBD_RXDMA2_IRQ 0 +#define BCM_6345_USBD_TXDMA2_IRQ 0 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) #define BCM_6345_ENET1_RXDMA_IRQ 0 @@ -704,6 +749,13 @@ enum bcm63xx_irq { #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6348_EHCI0_IRQ 0 +#define BCM_6348_USBD_IRQ 0 +#define BCM_6348_USBD_RXDMA0_IRQ 0 +#define BCM_6348_USBD_TXDMA0_IRQ 0 +#define BCM_6348_USBD_RXDMA1_IRQ 0 +#define BCM_6348_USBD_TXDMA1_IRQ 0 +#define BCM_6348_USBD_RXDMA2_IRQ 0 +#define BCM_6348_USBD_TXDMA2_IRQ 0 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) @@ -735,6 +787,13 @@ enum bcm63xx_irq { #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_6358_USBD_IRQ 0 +#define BCM_6358_USBD_RXDMA0_IRQ 0 +#define BCM_6358_USBD_TXDMA0_IRQ 0 +#define BCM_6358_USBD_RXDMA1_IRQ 0 +#define BCM_6358_USBD_TXDMA1_IRQ 0 +#define BCM_6358_USBD_RXDMA2_IRQ 0 +#define BCM_6358_USBD_TXDMA2_IRQ 0 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) @@ -775,6 +834,13 @@ enum bcm63xx_irq { #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26) +#define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27) +#define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28) +#define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29) +#define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30) +#define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31) #define BCM_6368_PCMCIA_IRQ 0 #define BCM_6368_ENET0_RXDMA_IRQ 0 #define BCM_6368_ENET0_TXDMA_IRQ 0 @@ -815,6 +881,13 @@ extern const int *bcm63xx_irqs; [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ + [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ + [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \ + [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \ + [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \ + [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \ + [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \ + [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \ [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 29654ae..fa74a37 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -795,6 +795,12 @@ #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) +#define USBH_PRIV_UTMI_CTL_6368_REG 0x10 +#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 +#define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) +#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 +#define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) + #define USBH_PRIV_TEST_6358_REG 0x24 #define USBH_PRIV_TEST_6368_REG 0x14 @@ -803,6 +809,147 @@ #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) +/************************************************************************* + * _REG relative to RSET_USBD + *************************************************************************/ + +/* General control */ +#define USBD_CONTROL_REG 0x00 +#define USBD_CONTROL_TXZLENINS_SHIFT 14 +#define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT) +#define USBD_CONTROL_AUTO_CSRS_SHIFT 13 +#define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT) +#define USBD_CONTROL_RXZSCFG_SHIFT 12 +#define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT) +#define USBD_CONTROL_INIT_SEL_SHIFT 8 +#define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) +#define USBD_CONTROL_FIFO_RESET_SHIFT 6 +#define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) +#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 +#define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) +#define USBD_CONTROL_DONE_CSRS_SHIFT 0 +#define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) + +/* Strap options */ +#define USBD_STRAPS_REG 0x04 +#define USBD_STRAPS_APP_SELF_PWR_SHIFT 10 +#define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) +#define USBD_STRAPS_APP_DISCON_SHIFT 9 +#define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) +#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 +#define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) +#define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 +#define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) +#define USBD_STRAPS_APP_RAM_IF_SHIFT 7 +#define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT) +#define USBD_STRAPS_APP_8BITPHY_SHIFT 2 +#define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT) +#define USBD_STRAPS_SPEED_SHIFT 0 +#define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT) + +/* Stall control */ +#define USBD_STALL_REG 0x08 +#define USBD_STALL_UPDATE_SHIFT 7 +#define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT) +#define USBD_STALL_ENABLE_SHIFT 6 +#define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT) +#define USBD_STALL_EPNUM_SHIFT 0 +#define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT) + +/* General status */ +#define USBD_STATUS_REG 0x0c +#define USBD_STATUS_SOF_SHIFT 16 +#define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT) +#define USBD_STATUS_SPD_SHIFT 12 +#define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT) +#define USBD_STATUS_ALTINTF_SHIFT 8 +#define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT) +#define USBD_STATUS_INTF_SHIFT 4 +#define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT) +#define USBD_STATUS_CFG_SHIFT 0 +#define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT) + +/* Other events */ +#define USBD_EVENTS_REG 0x10 +#define USBD_EVENTS_USB_LINK_SHIFT 10 +#define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT) + +/* IRQ status */ +#define USBD_EVENT_IRQ_STATUS_REG 0x14 + +/* IRQ level (2 bits per IRQ event) */ +#define USBD_EVENT_IRQ_CFG_HI_REG 0x18 + +#define USBD_EVENT_IRQ_CFG_LO_REG 0x1c + +#define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1) +#define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x)) +#define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x)) +#define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x)) + +/* IRQ mask (1=unmasked) */ +#define USBD_EVENT_IRQ_MASK_REG 0x20 + +/* IRQ bits */ +#define USBD_EVENT_IRQ_USB_LINK 10 +#define USBD_EVENT_IRQ_SETCFG 9 +#define USBD_EVENT_IRQ_SETINTF 8 +#define USBD_EVENT_IRQ_ERRATIC_ERR 7 +#define USBD_EVENT_IRQ_SET_CSRS 6 +#define USBD_EVENT_IRQ_SUSPEND 5 +#define USBD_EVENT_IRQ_EARLY_SUSPEND 4 +#define USBD_EVENT_IRQ_SOF 3 +#define USBD_EVENT_IRQ_ENUM_ON 2 +#define USBD_EVENT_IRQ_SETUP 1 +#define USBD_EVENT_IRQ_USB_RESET 0 + +/* TX FIFO partitioning */ +#define USBD_TXFIFO_CONFIG_REG 0x40 +#define USBD_TXFIFO_CONFIG_END_SHIFT 16 +#define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) +#define USBD_TXFIFO_CONFIG_START_SHIFT 0 +#define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) + +/* RX FIFO partitioning */ +#define USBD_RXFIFO_CONFIG_REG 0x44 +#define USBD_RXFIFO_CONFIG_END_SHIFT 16 +#define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) +#define USBD_RXFIFO_CONFIG_START_SHIFT 0 +#define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) + +/* TX FIFO/endpoint configuration */ +#define USBD_TXFIFO_EPSIZE_REG 0x48 + +/* RX FIFO/endpoint configuration */ +#define USBD_RXFIFO_EPSIZE_REG 0x4c + +/* Endpoint<->DMA mappings */ +#define USBD_EPNUM_TYPEMAP_REG 0x50 +#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 +#define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) +#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 +#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) + +/* Misc per-endpoint settings */ +#define USBD_CSR_SETUPADDR_REG 0x80 +#define USBD_CSR_SETUPADDR_DEF 0xb550 + +#define USBD_CSR_EP_REG(x) (0x84 + (x) * 4) +#define USBD_CSR_EP_MAXPKT_SHIFT 19 +#define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT) +#define USBD_CSR_EP_ALTIFACE_SHIFT 15 +#define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT) +#define USBD_CSR_EP_IFACE_SHIFT 11 +#define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT) +#define USBD_CSR_EP_CFG_SHIFT 7 +#define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT) +#define USBD_CSR_EP_TYPE_SHIFT 5 +#define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT) +#define USBD_CSR_EP_DIR_SHIFT 4 +#define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT) +#define USBD_CSR_EP_LOG_SHIFT 0 +#define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT) + /************************************************************************* * _REG relative to RSET_MPI -- 1.7.11.1 From cernekee@gmail.com Mon Jul 9 04:48:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jul 2012 04:49:20 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:45228 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1903507Ab2GICsB (ORCPT ); Mon, 9 Jul 2012 04:48:01 +0200 Received: (qmail 24414 invoked from network); 9 Jul 2012 02:47:58 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 9 Jul 2012 02:47:58 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sun, 08 Jul 2012 19:47:58 -0700 From: Kevin Cernekee To: ralf@linux-mips.org Cc: , , , Subject: [PATCH V2 7/7] MIPS: BCM63XX: Create platform_device for USBD Date: Sun, 08 Jul 2012 19:41:21 -0700 Message-Id: In-Reply-To: References: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 33887 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5941 Lines: 198 Signed-off-by: Kevin Cernekee --- arch/mips/bcm63xx/Makefile | 2 +- arch/mips/bcm63xx/boards/board_bcm963xx.c | 10 +++ arch/mips/bcm63xx/dev-usb-usbd.c | 72 ++++++++++++++++++++++ .../asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h | 17 +++++ .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 5 ++ 5 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 arch/mips/bcm63xx/dev-usb-usbd.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h V2: Use the newly changed IRQ names. Use platform_device ID -1, as is customary on UDC drivers. diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 833af72..9bbb30a 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,6 +1,6 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \ - dev-spi.o dev-uart.o dev-wdt.o + dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index feb0525..ea4ea77 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #define PFX "board_bcm963xx: " @@ -42,6 +43,12 @@ static struct board_info __initdata board_96328avng = { .has_uart0 = 1, .has_pci = 1, + .has_usbd = 0, + + .usbd = { + .use_fullspeed = 0, + .port_no = 0, + }, .leds = { { @@ -888,6 +895,9 @@ int __init board_register_devices(void) !board_get_mac_address(board.enet1.mac_addr)) bcm63xx_enet_register(1, &board.enet1); + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + if (board.has_dsp) bcm63xx_dsp_register(&board.dsp); diff --git a/arch/mips/bcm63xx/dev-usb-usbd.c b/arch/mips/bcm63xx/dev-usb-usbd.c new file mode 100644 index 0000000..cfad216 --- /dev/null +++ b/arch/mips/bcm63xx/dev-usb-usbd.c @@ -0,0 +1,72 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2012 Kevin Cernekee + * Copyright (C) 2012 Broadcom Corporation + */ + +#include +#include +#include +#include +#include +#include + +static struct resource usbd_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 usbd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device bcm63xx_usbd_device = { + .name = "bcm63xx_udc", + .id = -1, + .num_resources = ARRAY_SIZE(usbd_resources), + .resource = usbd_resources, + .dev = { + .dma_mask = &usbd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +int __init bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd) +{ + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) + return 0; + + usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD); + usbd_resources[0].end = usbd_resources[0].start + RSET_USBD_SIZE - 1; + + usbd_resources[1].start = bcm63xx_regset_address(RSET_USBDMA); + usbd_resources[1].end = usbd_resources[1].start + RSET_USBDMA_SIZE - 1; + + usbd_resources[2].start = bcm63xx_get_irq_number(IRQ_USBD); + + usbd_resources[3].start = bcm63xx_get_irq_number(IRQ_USBD_RXDMA0); + usbd_resources[3].end = bcm63xx_get_irq_number(IRQ_USBD_TXDMA2); + + platform_device_add_data(&bcm63xx_usbd_device, pd, sizeof(*pd)); + + return platform_device_register(&bcm63xx_usbd_device); +} diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h new file mode 100644 index 0000000..5d6d698 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h @@ -0,0 +1,17 @@ +#ifndef BCM63XX_DEV_USB_USBD_H_ +#define BCM63XX_DEV_USB_USBD_H_ + +/* + * usb device platform data + */ +struct bcm63xx_usbd_platform_data { + /* board can only support full speed (USB 1.1) */ + int use_fullspeed; + + /* 0-based port index, for chips with >1 USB PHY */ + int port_no; +}; + +int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd); + +#endif /* BCM63XX_DEV_USB_USBD_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h index 474daaa..b0dd4bb 100644 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -5,6 +5,7 @@ #include #include #include +#include #include /* @@ -44,6 +45,7 @@ struct board_info { unsigned int has_pccard:1; unsigned int has_ohci0:1; unsigned int has_ehci0:1; + unsigned int has_usbd:1; unsigned int has_dsp:1; unsigned int has_uart0:1; unsigned int has_uart1:1; @@ -52,6 +54,9 @@ struct board_info { struct bcm63xx_enet_platform_data enet0; struct bcm63xx_enet_platform_data enet1; + /* USB config */ + struct bcm63xx_usbd_platform_data usbd; + /* DSP config */ struct bcm63xx_dsp_platform_data dsp; -- 1.7.11.1 From cernekee@gmail.com Mon Jul 9 04:58:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jul 2012 04:58:11 +0200 (CEST) Received: from mail-ee0-f49.google.com ([74.125.83.49]:33736 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903445Ab2GIC6I (ORCPT ); Mon, 9 Jul 2012 04:58:08 +0200 Received: by eekd17 with SMTP id d17so4090096eek.36 for ; Sun, 08 Jul 2012 19:58:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=lJ3JjJCQmZlCk8KRCTEeobL+XGb0gdxJbufjR0Q0Xg0=; b=EfyF4Quhsuy0laHS2Mp0drMjQwfqtG9a15uDCaSmp+TxnjstlVXlxJLKQ3rscveoch u4KCLr0Li4/ZZIGqaOHznR5NddFtie+ozvNm6/W9g9v4j7IjqJ0zFlYCM220k7y91CbJ atXkkGo9zA9jtkPVuipwrZxOBIpmE60GD6mDOoJ04NIR+BXdSj9tGoHt8Zajyym2dXOb Axygo7wrltjq1Jdp8i5uBRe3Wcvo2EOoxENosgdj+sRCESkauvTwQgDuv896KP5pgXQ7 vxKIaAU5tVTQq250RyYEVs52C9edih3rC662W+kz8KQfA9G9GNnUCezeqYYejO6H0a8O RyxA== MIME-Version: 1.0 Received: by 10.14.100.144 with SMTP id z16mr9084480eef.50.1341802682542; Sun, 08 Jul 2012 19:58:02 -0700 (PDT) Received: by 10.14.173.194 with HTTP; Sun, 8 Jul 2012 19:58:02 -0700 (PDT) In-Reply-To: <0f67eabbb0d5c59add27e42a08b94944@localhost> References: <0f67eabbb0d5c59add27e42a08b94944@localhost> Date: Sun, 8 Jul 2012 19:58:02 -0700 Message-ID: Subject: Re: [PATCH 0/7] Prerequisites for BCM63XX UDC driver From: Kevin Cernekee To: ralf@linux-mips.org Cc: ffainelli@freebox.fr, mbizon@freebox.fr, jonas.gorski@gmail.com, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 33888 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 320 Lines: 7 On Fri, Jun 22, 2012 at 10:14 PM, Kevin Cernekee wrote: > These patches are intended to lay the groundwork for a new USB Device > Controller (gadget UDC) driver. I have posted "V2" for 4 of the 7 patches. New bundle is here: http://patchwork.linux-mips.org/bundle/cernekee/bcm63xx-udc-prereq-v2/ From macro@linux-mips.org Wed Jul 11 02:05:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jul 2012 02:05:09 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:39075 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903700Ab2GKAFE (ORCPT ); Wed, 11 Jul 2012 02:05:04 +0200 Date: Wed, 11 Jul 2012 01:05:04 +0100 (BST) From: "Maciej W. Rozycki" To: =?ISO-8859-15?Q?Llu=EDs_Batlle_i_Rossell?= cc: linux-mips@linux-mips.org, tsbogend@alpha.franken.de Subject: Re: [PATCH] MIPS: Add emulation for fpureg-mem unaligned access In-Reply-To: <20120620190545.GV2039@vicerveza.homeunix.net> Message-ID: References: <20120615234641.6938B58FE7C@mail.viric.name> <20120616121513.GP2039@vicerveza.homeunix.net> <20120616124001.GQ2039@vicerveza.homeunix.net> <20120620190545.GV2039@vicerveza.homeunix.net> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=ISO-8859-15 Content-Transfer-Encoding: 8BIT X-archive-position: 33889 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1636 Lines: 36 On Wed, 20 Jun 2012, Lluís Batlle i Rossell wrote: > > > Well, I think I take my words back. Handling the ldc1/sdc1 cases in MIPS32 is > > > tricker than I thought first, because I can't use ldl/ldr or sdl/sdr there. > > > Given my ability with mips assembly, I leave the patch as is. I suggest that for 32-bit kernels you simply reuse the existing snippets from that function and handle ldc1/sdc1 with a pair of lwl/ldr or swl/swr pairs ordered as appropriate for the endianness selected -- that should be fairly easy. Also regardless of that, please make sure that your code handles the two possible settings of CP0 Status register's bit FR correctly, as the 32-bit halves of floating-point data are distributed differently across floating-point registers based on this bit's setting (check if an o32 and an n64 or n32 program gets these values right). > > why is there a reason for this ? Unaligned FPU access shouts to me simply > > broken code, go fix that. But maybe I'm wrong ? Since we're emulating these accesses at all I concur Lluís we should stay consistent across the whole instruction set. > Right, the patch allows broken code to run further, instead of fail straight. > The crash can be still achieved disabling the emulation of unaligned accesses > completely, through debugfs, for example. sysmips(MIPS_FIXADE, 0) is another way. > As Jonas reported, I think that maybe I should rework the patch for it to emit > sigbus instead of sigill on ldc1,ldc1 for mips32. Do I understand it right? Have you checked your code against a non-FPU processor (or with the "nofpu" kernel option) too? Maciej From jonas.gorski@gmail.com Thu Jul 12 10:58:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jul 2012 10:58:31 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:53389 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1902243Ab2GLI6Y (ORCPT ); Thu, 12 Jul 2012 10:58:24 +0200 Received: by obbta17 with SMTP id ta17so2944847obb.36 for ; Thu, 12 Jul 2012 01:58:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=MHWANTt7HFd7kn0Ndmbc50DEjV/ul8bkcB5GV3WypcY=; b=GGsXJb4wmqgukXuyhY+YG+LjxcEuFs1diR41PavwQrthepOBJtEK9HlDF5EjWuizEO RX7GazsSzzGvkMAWuH1/yd9DoJtVz9+xBLw6Uq1oSmsJd70T69s17T5MGa9rGaX5d5Bq Pn/t6JCyfHZHHExDhO1Wj6VMCK7cVHyfPEYe2hgED6vJQhdTemBg2iG3t39o901H2RuN /Cd2FFfJFVwkn6GYV5Z587mJOyTHYvlOFLzV4MvDHapVMzQ0Ivdqyk4uELCGDh8kz4fL P8dELcrkR58l7qY4us2gEw32gKIT+r8SMSQF+UOjBScC3v/9CI0NPL5w1ymngpkNGtmP xFLg== Received: by 10.182.51.69 with SMTP id i5mr29082295obo.42.1342083498641; Thu, 12 Jul 2012 01:58:18 -0700 (PDT) MIME-Version: 1.0 Received: by 10.76.94.235 with HTTP; Thu, 12 Jul 2012 01:57:58 -0700 (PDT) In-Reply-To: References: <0f67eabbb0d5c59add27e42a08b94944@localhost> From: Jonas Gorski Date: Thu, 12 Jul 2012 10:57:58 +0200 Message-ID: Subject: Re: [PATCH 0/7] Prerequisites for BCM63XX UDC driver To: Kevin Cernekee Cc: ralf@linux-mips.org, ffainelli@freebox.fr, mbizon@freebox.fr, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 33890 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 460 Lines: 12 On 9 July 2012 04:58, Kevin Cernekee wrote: > On Fri, Jun 22, 2012 at 10:14 PM, Kevin Cernekee wrote: >> These patches are intended to lay the groundwork for a new USB Device >> Controller (gadget UDC) driver. > > I have posted "V2" for 4 of the 7 patches. New bundle is here: > > http://patchwork.linux-mips.org/bundle/cernekee/bcm63xx-udc-prereq-v2/ These look good to me, and I have no further objections. Jonas From ffainelli@freebox.fr Thu Jul 12 11:43:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jul 2012 11:43:19 +0200 (CEST) Received: from zmc.proxad.net ([212.27.53.206]:33810 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903451Ab2GLJnN convert rfc822-to-8bit (ORCPT ); Thu, 12 Jul 2012 11:43:13 +0200 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id 753C89BA80B; Thu, 12 Jul 2012 11:43:13 +0200 (CEST) X-Virus-Scanned: amavisd-new at localhost Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3cVkBtxKVNKX; Thu, 12 Jul 2012 11:43:12 +0200 (CEST) Received: from lenovo.localnet (alphacore.org [94.143.118.29]) by zmc.proxad.net (Postfix) with ESMTPSA id 74A629BA528; Thu, 12 Jul 2012 11:43:12 +0200 (CEST) From: Florian Fainelli Organization: Freebox To: linux-mips@linux-mips.org Subject: Re: [PATCH 0/7] Prerequisites for BCM63XX UDC driver Date: Thu, 12 Jul 2012 11:43:07 +0200 User-Agent: KMail/1.13.7 (Linux/3.4-trunk-amd64; KDE/4.8.4; x86_64; ; ) Cc: Jonas Gorski , Kevin Cernekee , ralf@linux-mips.org, mbizon@freebox.fr References: <0f67eabbb0d5c59add27e42a08b94944@localhost> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Message-Id: <201207121143.08293.ffainelli@freebox.fr> X-archive-position: 33891 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ffainelli@freebox.fr Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 576 Lines: 16 Le jeudi 12 juillet 2012 10:57:58, Jonas Gorski a Ă©crit : > On 9 July 2012 04:58, Kevin Cernekee wrote: > > On Fri, Jun 22, 2012 at 10:14 PM, Kevin Cernekee wrote: > >> These patches are intended to lay the groundwork for a new USB Device > >> Controller (gadget UDC) driver. > > > > I have posted "V2" for 4 of the 7 patches. New bundle is here: > > > > http://patchwork.linux-mips.org/bundle/cernekee/bcm63xx-udc-prereq-v2/ > > These look good to me, and I have no further objections. Me neither, they look good. -- Florian From sjhill@mips.com Thu Jul 12 20:21:46 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jul 2012 20:21:52 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49832 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903839Ab2GLSVq (ORCPT ); Thu, 12 Jul 2012 20:21:46 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SpO1B-0004PU-Sg; Thu, 12 Jul 2012 13:21:37 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v5,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler. Date: Thu, 12 Jul 2012 13:21:31 -0500 Message-Id: <1342117291-30268-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33893 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2595 Lines: 80 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/uasm.h | 4 ++-- arch/mips/mm/uasm.c | 15 +++++++++++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 53db9d7..7e0bf17 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -66,8 +66,6 @@ Ip_u3u1u2(_addu); Ip_u3u1u2(_and); Ip_u2u1u3(_andi); Ip_u1u2s3(_bbit0); -Ip_u1u2s3(_bbit0); -Ip_u1u2s3(_bbit1); Ip_u1u2s3(_bbit1); Ip_u1u2s3(_beq); Ip_u1u2s3(_beql); @@ -92,6 +90,8 @@ Ip_u2u1u3(_dsrl); Ip_u2u1u3(_dsrl32); Ip_u3u1u2(_dsubu); Ip_0(_eret); +Ip_u2u1msbu3(_ext); +Ip_u2u1msbu3(_ins); Ip_u1(_j); Ip_u1(_jal); Ip_u1(_jr); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 5fa1851..f6ba16e 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -63,8 +63,8 @@ enum opcode { insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, - insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, - insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, + insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ll, + insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, @@ -113,6 +113,8 @@ static struct insn insn_table[] __uasminitdata = { { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, @@ -343,6 +345,13 @@ Ip_u2u1msbu3(op) \ } \ UASM_EXPORT_SYMBOL(uasm_i##op); +#define I_u2u1msbdu3(op) \ +Ip_u2u1msbu3(op) \ +{ \ + build_insn(buf, insn##op, b, a, d-1, c); \ +} \ +UASM_EXPORT_SYMBOL(uasm_i##op); + #define I_u1u2(op) \ Ip_u1u2(op) \ { \ @@ -396,6 +405,8 @@ I_u2u1u3(_drotr) I_u2u1u3(_drotr32) I_u3u1u2(_dsubu) I_0(_eret) +I_u2u1msbdu3(_ext) +I_u2u1msbu3(_ins) I_u1(_j) I_u1(_jal) I_u1(_jr) -- 1.7.11.1 From sjhill@mips.com Thu Jul 12 20:27:41 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jul 2012 20:27:45 +0200 (CEST) Received: from dns1.mips.com ([12.201.5.69]:49698 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903450Ab2GLS1l convert rfc822-to-8bit (ORCPT ); Thu, 12 Jul 2012 20:27:41 +0200 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id q6CIRXxI029951; Thu, 12 Jul 2012 11:27:33 -0700 Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchhub01.mips.com ([::1]) with mapi id 14.01.0270.001; Thu, 12 Jul 2012 11:27:14 -0700 From: "Hill, Steven" To: Sergei Shtylyov CC: "linux-mips@linux-mips.org" Subject: RE: [PATCH v4,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler. Thread-Topic: [PATCH v4,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler. Thread-Index: AQHNViX6NQwUfW+0XUuBvsFSkLeGqpcTwJeAgBJJqAo= Date: Thu, 12 Jul 2012 18:27:14 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B80114699ED9@exchdb03.mips.com> References: <1340994924-3922-1-git-send-email-sjhill@mips.com>,<4FEF5C29.50107@mvista.com> In-Reply-To: <4FEF5C29.50107@mvista.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: 1Tqaygz5P2idrI1ZkSNI6g== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 33894 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 276 Lines: 10 >> @@ -396,6 +405,8 @@ I_u2u1u3(_drotr) >> I_u2u1u3(_drotr32) >> I_u3u1u2(_dsubu) >> I_0(_eret) >> +I_u2u1mmsbu3(_ext) >> +I_u2u1msbu3(_ins) > > Not I_u2u1mmsbu3()? > No, the 'ins' instruction opcode layout is identical to the 'dins' instruction. Thus, it is correct. From kr-jiffy@yandex.ru Thu Jul 12 22:03:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jul 2012 22:03:39 +0200 (CEST) Received: from forward7.mail.yandex.net ([77.88.61.37]:49198 "EHLO forward7.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903847Ab2GLUDf (ORCPT ); Thu, 12 Jul 2012 22:03:35 +0200 Received: from web6e.yandex.ru (web6e.yandex.ru [77.88.60.75]) by forward7.mail.yandex.net (Yandex) with ESMTP id 400A61C1EAA for ; Fri, 13 Jul 2012 00:03:26 +0400 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1342123406; bh=Zu8Ei40mbe6//n/rloKV6uPg3wagyVcx7uAemWzyixM=; h=From:To:Subject:MIME-Version:Message-Id:Date: Content-Transfer-Encoding:Content-Type; b=mYMlugZU/UrO4ueN0Tr5wbz7H6pFhtverjWmsikZVbD7zjO+vTGbr1eSeaohJhuEO nGkNOSDZX37264r+Tvr6VFbeaG8bwm8nqZXPaIEchx8dcvZ3PAkT1f1orF+uhnjPEx fppbUOJJwuvhdaOeWKjRRQ8BLzDoiVurHpIGfhRw= Received: from 127.0.0.1 (localhost.localdomain [127.0.0.1]) by web6e.yandex.ru (Yandex) with ESMTP id 110AF2F80EA; Fri, 13 Jul 2012 00:03:26 +0400 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1342123406; bh=Zu8Ei40mbe6//n/rloKV6uPg3wagyVcx7uAemWzyixM=; h=From:To:Subject:MIME-Version:Message-Id:Date: Content-Transfer-Encoding:Content-Type; b=mYMlugZU/UrO4ueN0Tr5wbz7H6pFhtverjWmsikZVbD7zjO+vTGbr1eSeaohJhuEO nGkNOSDZX37264r+Tvr6VFbeaG8bwm8nqZXPaIEchx8dcvZ3PAkT1f1orF+uhnjPEx fppbUOJJwuvhdaOeWKjRRQ8BLzDoiVurHpIGfhRw= Received: from wimax-client.yota.ru (wimax-client.yota.ru [178.176.146.54]) by web6e.yandex.ru with HTTP; Fri, 13 Jul 2012 00:03:25 +0400 From: kr kr To: linux-mips@linux-mips.org Subject: [mips32r1 cpu] Advice needed: "Machine Check exception - caused by multiple matching entries in the TLB" MIME-Version: 1.0 Message-Id: <194011342123405@web6e.yandex.ru> Date: Fri, 13 Jul 2012 00:03:25 +0400 X-Mailer: Yamail [ http://yandex.ru ] 5.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-archive-position: 33895 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kr-jiffy@yandex.ru Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 7471 Lines: 154 Hi, I've been trying to run a custom board with mips32 custom cpu (Elvees multicore) with MIPS-I binaries, provided by Debian 'squeeze' release. So far, I've had "Kernel panic - not syncing: Caught Machine Check exception - caused by multiple matching entries in the TLB". With a buildroot fs built as mips32 the board runs just fine, with a buildroot fs built as mips-I I've had issues similar to debian MIPS-I fs. Have I been missing something very obvious? Is that a completely wrong settings for a MIPS32 cpu to run MIPS-I binaries? I've checked Malta's Cobalt's and Broadcom's kernel configs from Debian *.deb and looks my config settings are plausible, I mean I don't need to attempt to degrade cpu configuration to CPU_R3000 or do similar weird things? Nothing obviously wrong in my kernel config for a kernel intended to run MIPS-I binaries? My kernel config contains the next definitions: CONFIG_MULTICORE=y CONFIG_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_32BIT=y CONFIG_PAGE_SIZE_4KB=y #CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set CONFIG_SYS_SUPPORTS_MULTITHREADING=y # CONFIG_MIPS_VPE_LOADER is not set # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y Console output: [ 0.000000] Linux version 2.6.36-multicore (koivu@koivu) (gcc version 4.3.5 (Buildroot 2 011.05) ) #5 Fri Jul 6 22:55:20 MSK 2012 [ 0.000000] CPU revision is: 000a2001 (Elvees Multicore) [ 0.000000] FPU revision is: 00030001 [ 0.000000] MIPS clk frequency: 290 MHz, frequency multiplier: 58 [ 0.000000] MPORT clk frequency: 100 MHz, frequency multiplier: 20 [ 0.000000] Multicore specific initialisation complete [ 0.000000] Determined physical RAM map: [ 0.000000] memory: 04000000 @ 00000000 (usable) [ 0.000000] Initrd not found or empty - disabling initrd [ 0.000000] Zone PFN ranges: [ 0.000000] Normal 0x00000000 -> 0x00004000 [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[1] active PFN ranges [ 0.000000] 0: 0x00000000 -> 0x00004000 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16240 [ 0.000000] Kernel command line: console=ttyS0,115200N8 root=/dev/ram0 [ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes) [ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Memory: 60224k/65536k available (1349k kernel code, 5312k reserved, 214k dat a, 2928k init, 0k highmem) [ 0.000000] NR_IRQS:105 [ 0.000000] console [ttyS0] enabled [ 0.004000] Calibrating delay loop... 10.49 BogoMIPS (lpj=20992) [ 0.080000] pid_max: default: 32768 minimum: 301 [ 0.084000] Mount-cache hash table entries: 512 [ 0.160000] Multicore AMBA bus registered [ 0.176000] bio: create slab at 0 [ 0.184000] Switching to clocksource MIPS [ 4.436000] msgmni has been set to 117 [ 4.444000] io scheduler noop registered [ 4.448000] io scheduler deadline registered (default) [ 7.944000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 7.964000] serial8250: ttyS0 at MMIO 0xb82f3000 (irq = 13) is a 16550 [ 7.976000] serial8250: ttyS1 at MMIO 0xb82f3800 (irq = 14) is a 16550 [ 8.536000] brd: module loaded [ 8.804000] loop: module loaded [ 9.028000] Freeing unused kernel memory: 2928k freed Initializing random number generator... done. Please press Enter to activate this console. [ 12.560000] Got mcheck at 0044f6a8 [ 12.560000] Cpu 0 [ 12.560000] $ 0 : 00000000 3000fc00 00000000 004eb02c [ 12.560000] $ 4 : 00000001 00000004 004eb02c 00000000 [ 12.560000] $ 8 : 00000000 00000000 8002b6c8 fffffffc [ 12.560000] $12 : fffffffc 00000807 00000800 0044952c [ 12.560000] $16 : 004c1958 0000005c 7ffdf3e8 7ffdf440 [ 12.560000] $20 : 00000001 004f0000 ffffffff 004f0000 [ 12.560000] $24 : 00000163 004eb02c [ 12.560000] $28 : 004f0df0 7ffdf240 004c1934 0044f090 [ 12.560000] Hi : 0000025b [ 12.560000] Lo : 00035a4f [ 12.560000] epc : 0044f6a8 0x44f6a8 [ 12.560000] Not tainted [ 12.560000] ra : 0044f090 0x44f090 [ 12.560000] Status: 2020fc13 USER EXL IE [ 12.560000] Cause : 10000060 [ 12.560000] PrId : 000a2001 (Elvees Multicore) [ 12.560000] Index : 5 [ 12.560000] Pagemask: 0 [ 12.560000] EntryHi : 0044e046 [ 12.560000] EntryLo0: 00000000 [ 12.560000] EntryLo1: 000f7c42 [ 12.560000] [ 12.560000] Index: 0 pgmask=4kb va=2ac38000 asid=46 [ 12.560000] [pa=03eab000 c=3 d=0 v=1 g=0] [pa=03eac000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 1 pgmask=4kb va=00448000 asid=46 [ 12.560000] [pa=00000000 c=3 d=0 v=0 g=0] [pa=03deb000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 2 pgmask=4kb va=2ac3c000 asid=46 [ 12.560000] [pa=03eaf000 c=3 d=0 v=1 g=0] [pa=03eb0000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 3 pgmask=4kb va=2ac3a000 asid=46 [ 12.560000] [pa=03ead000 c=3 d=0 v=1 g=0] [pa=03eae000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 4 pgmask=4kb va=00444000 asid=46 [ 12.560000] [pa=03de6000 c=3 d=0 v=1 g=0] [pa=03de7000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 5 pgmask=4kb va=00446000 asid=46 [ 12.560000] [pa=03de8000 c=3 d=0 v=1 g=0] [pa=00000000 c=3 d=0 v=0 g=0] [ 12.560000] Index: 6 pgmask=4kb va=00440000 asid=46 [ 12.560000] [pa=00000000 c=3 d=0 v=0 g=0] [pa=03de3000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 7 pgmask=4kb va=004ec000 asid=46 [ 12.560000] [pa=00454000 c=3 d=1 v=1 g=0] [pa=00441000 c=3 d=1 v=1 g=0] [ 12.560000] Index: 8 pgmask=4kb va=004c0000 asid=46 [ 12.560000] [pa=03e62000 c=3 d=0 v=1 g=0] [pa=03e63000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 9 pgmask=4kb va=0044e000 asid=46 [ 12.560000] [pa=00000000 c=3 d=0 v=0 g=0] [pa=03df1000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 10 pgmask=4kb va=2ac74000 asid=46 [ 12.560000] [pa=03ee7000 c=3 d=0 v=1 g=0] [pa=03ee8000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 11 pgmask=4kb va=7ffde000 asid=46 [ 12.560000] [pa=00458000 c=3 d=1 v=1 g=0] [pa=0109d000 c=3 d=1 v=1 g=0] [ 12.560000] Index: 12 pgmask=4kb va=0040a000 asid=46 [ 12.560000] [pa=03dac000 c=3 d=0 v=1 g=0] [pa=00000000 c=3 d=0 v=0 g=0] [ 12.560000] Index: 13 pgmask=4kb va=2ac80000 asid=46 [ 12.560000] [pa=00000000 c=3 d=0 v=0 g=0] [pa=03ef4000 c=3 d=0 v=1 g=0] [ 12.560000] Index: 14 pgmask=4kb va=004ea000 asid=46 [ 12.560000] [pa=00000000 c=3 d=0 v=0 g=0] [pa=0049c000 c=3 d=1 v=1 g=0] [ 12.560000] Index: 15 pgmask=4kb va=004e8000 asid=46 [ 12.560000] [pa=00450000 c=3 d=1 v=1 g=0] [pa=0109f000 c=3 d=1 v=1 g=0] [ 12.560000] [ 12.560000] [ 12.560000] Code: afa00104 10000235 00000000 <8f85804c> 00000000 8ca50000 00000000 afa50128 8fb90128 [ 12.560000] Kernel panic - not syncing: Caught Machine Check exception - caused by multiple matching entries in the TLB. TIA, Yuri From br1@einfach.org Thu Jul 12 22:54:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jul 2012 22:54:26 +0200 (CEST) Received: from postler.einfach.org ([86.59.21.13]:49211 "EHLO postler.einfach.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903841Ab2GLUyU (ORCPT ); Thu, 12 Jul 2012 22:54:20 +0200 Received: from localhost.localdomain (82.Red-83-44-208.dynamicIP.rima-tde.net [83.44.208.82]) by postler.einfach.org (Postfix) with ESMTPSA id C38A521421EB; Thu, 12 Jul 2012 22:54:13 +0200 (CEST) From: Bruno Randolf To: linux-mips@linux-mips.org Cc: manuel.lauss@googlemail.com, ralf@linux-mips.org, florian@openwrt.org, br1@einfach.org Subject: [PATCH] mtx-1: add udelay to mtx1_pci_idsel Date: Thu, 12 Jul 2012 21:54:05 +0100 Message-Id: <1342126445-13408-1-git-send-email-br1@einfach.org> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 33896 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: br1@einfach.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2041 Lines: 52 Without this udelay(1) PCI idsel does not work correctly on the "singleboard" (T-Mobile Surfbox) for the MiniPCI device. The result is that PCI configuration fails and the MiniPCI card is not detected correctly. Instead of PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] pci_bus 0000:00: root bus resource [io 0x1000-0xffff] pci 0000:00:03.0: BAR 0: assigned [mem 0x40000000-0x4000ffff] pci 0000:00:00.0: BAR 0: assigned [mem 0x40010000-0x40010fff] pci 0000:00:00.1: BAR 0: assigned [mem 0x40011000-0x40011fff] We see only the CardBus device: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] pci_bus 0000:00: root bus resource [io 0x1000-0xffff] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x40000fff] pci 0000:00:00.1: BAR 0: assigned [mem 0x40001000-0x40001fff] Later the device driver shows this error: ath5k 0000:00:03.0: cannot remap PCI memory region ath5k: probe of 0000:00:03.0 failed with error -5 I assume that the logic chip which usually supresses the signal to the CardBus card has some settling time and without the delay it would still let the Cardbus interfere with the response from the MiniPCI card. What I cannot explain is why this behaviour shows up now and not in earlier kernel versions before. Maybe older PCI code was slower? Signed-off-by: Bruno Randolf --- arch/mips/alchemy/board-mtx1.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c index 295f1a9..e107a2f 100644 --- a/arch/mips/alchemy/board-mtx1.c +++ b/arch/mips/alchemy/board-mtx1.c @@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int assert) * adapter on the mtx-1 "singleboard" variant. It triggers a custom * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. */ + udelay(1); + if (assert && devsel != 0) /* Suppress signal to Cardbus */ alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ -- 1.7.9.5 From mattst88@gmail.com Fri Jul 13 01:53:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 01:53:13 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:56941 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903849Ab2GLXxI (ORCPT ); Fri, 13 Jul 2012 01:53:08 +0200 Received: by yenr9 with SMTP id r9so3305178yen.36 for ; Thu, 12 Jul 2012 16:53:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=PNrp57piZKjv1LuTOp16EqSw/5JGtlptl7VLa13/3hA=; b=kyY99pAK/NXZoeADpNnnMmDt73DjzSSU619CMBO7bt782CI3xarAFZM3OJ1Ekb2bzt EB+g1cgpDwUOfCe8RsrAdSZ+kGEBWSBwxM7+rxk/5JNuPeVxJdahx+/wQ0tjPquNHmhk 8gq2agddtfMz4fzQeuBIakDdmM/BbSHPqcLNsztiHmyUuibXYxaOEA0FgSjWdGKJhr5Y uh6zTD6wrPi+LInYfZQ0vzO4lAkCFNcBZI0quLHCXkl8jAIFA5DVZTCOYWY0DsETx44U uwmVWgn1xp+9hs2S6nOWwoLhmvApQnSJHmJkmiwMUgzAUbYh7BrpJ8PB+nyVIGh6ayqD LGmw== Received: by 10.66.79.8 with SMTP id f8mr274629pax.81.1342137182002; Thu, 12 Jul 2012 16:53:02 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.138.233 with HTTP; Thu, 12 Jul 2012 16:52:41 -0700 (PDT) In-Reply-To: <20120705160222.GJ25225@inbox.lv> References: <20120705160222.GJ25225@inbox.lv> From: Matt Turner Date: Thu, 12 Jul 2012 16:52:41 -0700 Message-ID: Subject: Re: Please recommend distro for Lemote Fuloong To: Code Blue Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33897 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1115 Lines: 28 On Thu, Jul 5, 2012 at 9:02 AM, Code Blue wrote: > Hi, > > I just received a Lemote Fuloong Mini and I installed OpenBSD on it. I would > like to dual boot Linux but I am having a hard time finding the right distro. > > I know Lemote and MIPS people are doing a lot of work and submitting patches > to the Linux kernel and binutils and I am sure many other areas. Can anyone > please recommend a Linux distro that will come with (or can install) a > recent kernel so I can take advantage of all this hard work people are > doing? Of course I will need a tarball or USB installer since the Fuloong > doesn't have an optical drive. Thank you. > > -- > _ > ASCII ribbon campaign ( ) Please follow up to the mailing list > against HTML e-mail X > and proprietary / \ Mutt.org > attachments Code Blue or Go Home! > Gentoo. Join the #gentoo-mips IRC channel and ping 'blueness' since he's built some very nice install stages and netboot images. Also, we provide multilib installations with o32, n32, and n64 base libraries (n32 is default). From joe@perches.com Fri Jul 13 07:33:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 07:33:46 +0200 (CEST) Received: from perches-mx.perches.com ([206.117.179.246]:46696 "EHLO labridge.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1902104Ab2GMFdm (ORCPT ); Fri, 13 Jul 2012 07:33:42 +0200 Received: from [96.240.34.65] (account joe@perches.com HELO joe-laptop.perches.com) by labridge.com (CommuniGate Pro SMTP 5.0.14) with ESMTPA id 19369765; Thu, 12 Jul 2012 22:33:38 -0700 From: Joe Perches To: David Miller , netdev@vger.kernel.org, linux-usb@vger.kernel.org, wimax@linuxwimax.org, linux-wireless@vger.kernel.org, users@rt2x00.serialmonkey.com, linux-s390@vger.kernel.org Cc: Johannes Berg , uclinux-dist-devel@blackfin.uclinux.org, linux-kernel@vger.kernel.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, e1000-devel@lists.sourceforge.net Subject: [PATCH net-next 0/8] etherdevice: Rename random_ether_addr to eth_random_addr Date: Thu, 12 Jul 2012 22:33:04 -0700 Message-Id: X-Mailer: git-send-email 1.7.8.111.gad25c.dirty In-Reply-To: <1341968967.13724.23.camel@joe2Laptop> References: <1341968967.13724.23.camel@joe2Laptop> X-archive-position: 33898 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3006 Lines: 59 net-next commit ad7eee98be ("etherdevice: introduce eth_broadcast_addr") added a new style API. Rename random_ether_addr to eth_random_addr to create some API symmetry. Joe Perches (8): etherdevice: Rename random_ether_addr to eth_random_addr ethernet: Use eth_random_addr net: usb: Use eth_random_addr wireless: Use eth_random_addr drivers/net: Use eth_random_addr s390: Use eth_random_addr usb: Use eth_random_addr arch: Use eth_random_addr arch/blackfin/mach-bf537/boards/stamp.c | 2 +- arch/c6x/kernel/soc.c | 2 +- arch/mips/ar7/platform.c | 4 ++-- arch/mips/powertv/powertv_setup.c | 6 +++--- arch/um/drivers/net_kern.c | 2 +- drivers/net/ethernet/atheros/atl1c/atl1c_hw.c | 2 +- drivers/net/ethernet/atheros/atlx/atl1.c | 2 +- drivers/net/ethernet/atheros/atlx/atl2.c | 2 +- drivers/net/ethernet/ethoc.c | 2 +- drivers/net/ethernet/intel/igb/igb_main.c | 4 ++-- drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c | 2 +- drivers/net/ethernet/lantiq_etop.c | 2 +- drivers/net/ethernet/micrel/ks8851.c | 2 +- drivers/net/ethernet/micrel/ks8851_mll.c | 2 +- drivers/net/ethernet/smsc/smsc911x.c | 2 +- drivers/net/ethernet/ti/cpsw.c | 2 +- drivers/net/ethernet/tile/tilegx.c | 2 +- drivers/net/ethernet/wiznet/w5100.c | 2 +- drivers/net/ethernet/wiznet/w5300.c | 2 +- drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 2 +- drivers/net/tun.c | 2 +- drivers/net/usb/smsc75xx.c | 2 +- drivers/net/usb/smsc95xx.c | 2 +- drivers/net/usb/usbnet.c | 2 +- drivers/net/wimax/i2400m/driver.c | 2 +- drivers/net/wireless/adm8211.c | 2 +- drivers/net/wireless/p54/eeprom.c | 2 +- drivers/net/wireless/rt2x00/rt2400pci.c | 2 +- drivers/net/wireless/rt2x00/rt2500pci.c | 2 +- drivers/net/wireless/rt2x00/rt2500usb.c | 2 +- drivers/net/wireless/rt2x00/rt2800lib.c | 2 +- drivers/net/wireless/rt2x00/rt61pci.c | 2 +- drivers/net/wireless/rt2x00/rt73usb.c | 2 +- drivers/net/wireless/rtl818x/rtl8180/dev.c | 2 +- drivers/net/wireless/rtl818x/rtl8187/dev.c | 2 +- drivers/s390/net/qeth_l2_main.c | 2 +- drivers/s390/net/qeth_l3_main.c | 2 +- drivers/usb/atm/xusbatm.c | 4 ++-- drivers/usb/gadget/u_ether.c | 2 +- include/linux/etherdevice.h | 14 ++++++++------ 40 files changed, 52 insertions(+), 50 deletions(-) -- 1.7.8.111.gad25c.dirty From joe@perches.com Fri Jul 13 07:35:13 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 07:35:19 +0200 (CEST) Received: from perches-mx.perches.com ([206.117.179.246]:44841 "EHLO labridge.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1902233Ab2GMFfN (ORCPT ); Fri, 13 Jul 2012 07:35:13 +0200 Received: from [96.240.34.65] (account joe@perches.com HELO joe-laptop.perches.com) by labridge.com (CommuniGate Pro SMTP 5.0.14) with ESMTPA id 19369785; Thu, 12 Jul 2012 22:35:11 -0700 From: Joe Perches To: David Miller , linux-kernel@vger.kernel.org Cc: Johannes Berg , Mike Frysinger , Mark Salter , Aurelien Jacquiot , Ralf Baechle , Jeff Dike , Richard Weinberger , uclinux-dist-devel@blackfin.uclinux.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net Subject: [PATCH net-next 8/8] arch: Use eth_random_addr Date: Thu, 12 Jul 2012 22:33:12 -0700 Message-Id: <14a91278564bb5a263c561a7f1bd10ea6386d90a.1342157022.git.joe@perches.com> X-Mailer: git-send-email 1.7.8.111.gad25c.dirty In-Reply-To: <1341968967.13724.23.camel@joe2Laptop> References: <1341968967.13724.23.camel@joe2Laptop> In-Reply-To: References: X-archive-position: 33899 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3872 Lines: 102 Convert the existing uses of random_ether_addr to the new eth_random_addr. Signed-off-by: Joe Perches --- arch/blackfin/mach-bf537/boards/stamp.c | 2 +- arch/c6x/kernel/soc.c | 2 +- arch/mips/ar7/platform.c | 4 ++-- arch/mips/powertv/powertv_setup.c | 6 +++--- arch/um/drivers/net_kern.c | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index c9d9473..5ed654a 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -873,7 +873,7 @@ static struct adf702x_platform_data adf7021_platform_data = { }; static inline void adf702x_mac_init(void) { - random_ether_addr(adf7021_platform_data.mac_addr); + eth_random_addr(adf7021_platform_data.mac_addr); } #else static inline void adf702x_mac_init(void) {} diff --git a/arch/c6x/kernel/soc.c b/arch/c6x/kernel/soc.c index 0748c94..3ac7408 100644 --- a/arch/c6x/kernel/soc.c +++ b/arch/c6x/kernel/soc.c @@ -80,7 +80,7 @@ int soc_mac_addr(unsigned int index, u8 *addr) if (have_fuse_mac) memcpy(addr, c6x_fuse_mac, 6); else - random_ether_addr(addr); + eth_random_addr(addr); } /* adjust for specific EMAC device */ diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 1a24d31..1bbc24b 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -310,10 +310,10 @@ static void __init cpmac_get_mac(int instance, unsigned char *dev_addr) &dev_addr[4], &dev_addr[5]) != 6) { pr_warning("cannot parse mac address, " "using random address\n"); - random_ether_addr(dev_addr); + eth_random_addr(dev_addr); } } else - random_ether_addr(dev_addr); + eth_random_addr(dev_addr); } /***************************************************************************** diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c index 3933c37..820b848 100644 --- a/arch/mips/powertv/powertv_setup.c +++ b/arch/mips/powertv/powertv_setup.c @@ -254,7 +254,7 @@ early_param("rfmac", rfmac_param); * Generates an Ethernet MAC address that is highly likely to be unique for * this particular system on a network with other systems of the same type. * - * The problem we are solving is that, when random_ether_addr() is used to + * The problem we are solving is that, when eth_random_addr() is used to * generate MAC addresses at startup, there isn't much entropy for the random * number generator to use and the addresses it produces are fairly likely to * be the same as those of other identical systems on the same local network. @@ -269,7 +269,7 @@ early_param("rfmac", rfmac_param); * Still, this does give us something to work with. * * The approach we take is: - * 1. If we can't get the RF MAC Address, just call random_ether_addr. + * 1. If we can't get the RF MAC Address, just call eth_random_addr. * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24 * bits of the new address. This is very likely to be unique, except for * the current box. @@ -299,7 +299,7 @@ void platform_random_ether_addr(u8 addr[ETH_ALEN]) if (!have_rfmac) { pr_warning("rfmac not available on command line; " "generating random MAC address\n"); - random_ether_addr(addr); + eth_random_addr(addr); } else { diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c index 0d60c56..458d324 100644 --- a/arch/um/drivers/net_kern.c +++ b/arch/um/drivers/net_kern.c @@ -339,7 +339,7 @@ static int setup_etheraddr(char *str, unsigned char *addr, char *name) random: printk(KERN_INFO "Choosing a random ethernet address for device %s\n", name); - random_ether_addr(addr); + eth_random_addr(addr); return 1; } -- 1.7.8.111.gad25c.dirty From jonas.gorski@gmail.com Fri Jul 13 09:59:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 09:59:28 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:34252 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903439Ab2GMH7W (ORCPT ); Fri, 13 Jul 2012 09:59:22 +0200 Received: by bkcji2 with SMTP id ji2so2802728bkc.36 for ; Fri, 13 Jul 2012 00:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=OBy3lEWbECer/IAkfViMyphRAJJDD3ncB3OQGMe3A6g=; b=bBZ8rcV2h5dPn+6uxBlHNDXU0p2AhmB5sdI2tbgOXKsb9kfsZoXcEvKcwF99qZU/rC SJRRCvkGlTo/VJVIIcn56I8zohbgzStHNKVwAfrIIRDcNuEVLmr+obSOYG1v8WXPfBty 1IkiXMN55DM/hBMaa1y7SIs0/wIkL5sgJ16xIAmBEezZkq9QGDcfIpOR3CTvS3Y3URQ4 7mLM92OlaDduWplxQfFD4fPu0WQMppiEo9e0KPi9Xacb2WTJDJVdHEgBg94wi5vIi9LT myMsL9CnsyZqE8SRjPJCEXP549tosJdpNno/lM8aVHB+bG8lTPd070GWnLs6OUjMHbfB N/0g== Received: by 10.204.157.156 with SMTP id b28mr111108bkx.27.1342166357150; Fri, 13 Jul 2012 00:59:17 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-145-009.pools.arcor-ip.net. [88.73.145.9]) by mx.google.com with ESMTPS id o4sm4150114bkv.15.2012.07.13.00.59.15 (version=SSLv3 cipher=OTHER); Fri, 13 Jul 2012 00:59:16 -0700 (PDT) From: Jonas Gorski To: linux-kernel@vger.kernel.org Cc: Andrew Morton , Viresh Kumar , Russell King , linux-mips@linux-mips.org, Ralf Baechle , Florian Fainelli , Maxime Bizon Subject: [PATCH] MIPS: BCM63XX: select HAVE_CLK Date: Fri, 13 Jul 2012 09:58:35 +0200 Message-Id: <1342166315-17765-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 33900 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1145 Lines: 40 BCM63XX implements the clk interface, but does not advertise it. Signed-off-by: Jonas Gorski --- This fixes a build failure in linux-next caused by 5afae362dc79cb8b6b3965422d13d118c63d4ee4 ("clk: Add non CONFIG_HAVE_CLK routines"): CC arch/mips/bcm63xx/clk.o arch/mips/bcm63xx/clk.c:285:5: error: redefinition of 'clk_enable' include/linux/clk.h:294:19: note: previous definition of 'clk_enable' was here and so on (I think you have already seen one of these). @Andrew: This patch should apply cleanly to any tree, so maybe you could add it to your patch series in front of the mentioned patch, to keep bisectability for bcm63xx. @Ralf: I hope it is okay for you that this goes through a different tree. arch/mips/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 09ab87e..80d9199 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -122,6 +122,7 @@ config BCM63XX select SYS_HAS_EARLY_PRINTK select SWAP_IO_SPACE select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK help Support for BCM63XX based boards -- 1.7.2.5 From viresh.kumar2@arm.com Fri Jul 13 10:30:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 10:30:56 +0200 (CEST) Received: from service88.mimecast.com ([195.130.217.12]:35334 "EHLO service88.mimecast.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903258Ab2GMIat convert rfc822-to-8bit (ORCPT ); Fri, 13 Jul 2012 10:30:49 +0200 Received: from emea-cam-gw1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) (Using TLS) by service88.mimecast.com; Fri, 13 Jul 2012 09:30:47 +0100 Received: from [10.1.215.139] (10.1.2.13) by emea-cam-gw1.Emea.Arm.com (10.1.248.203) with Microsoft SMTP Server id 8.2.254.0; Fri, 13 Jul 2012 09:31:49 +0100 Message-ID: <4FFFDCB2.3030700@arm.com> Date: Fri, 13 Jul 2012 09:30:42 +0100 From: viresh kumar User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:13.0) Gecko/20120615 Thunderbird/13.0.1 MIME-Version: 1.0 To: Jonas Gorski CC: "linux-kernel@vger.kernel.org" , Andrew Morton , Viresh Kumar , Russell King , "linux-mips@linux-mips.org" , Ralf Baechle , Florian Fainelli , Maxime Bizon Subject: Re: [PATCH] MIPS: BCM63XX: select HAVE_CLK References: <1342166315-17765-1-git-send-email-jonas.gorski@gmail.com> In-Reply-To: <1342166315-17765-1-git-send-email-jonas.gorski@gmail.com> X-MC-Unique: 112071309304701002 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: 8BIT X-archive-position: 33901 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: viresh.kumar2@arm.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1652 Lines: 47 On 13/07/12 08:58, Jonas Gorski wrote: > BCM63XX implements the clk interface, but does not advertise it. > > Signed-off-by: Jonas Gorski > --- > > This fixes a build failure in linux-next caused by > 5afae362dc79cb8b6b3965422d13d118c63d4ee4 ("clk: Add non CONFIG_HAVE_CLK > routines"): > > CC arch/mips/bcm63xx/clk.o > arch/mips/bcm63xx/clk.c:285:5: error: redefinition of 'clk_enable' > include/linux/clk.h:294:19: note: previous definition of 'clk_enable' was here > > and so on (I think you have already seen one of these). > > @Andrew: This patch should apply cleanly to any tree, so maybe you > could add it to your patch series in front of the mentioned > patch, to keep bisectability for bcm63xx. > > @Ralf: I hope it is okay for you that this goes through a different > tree. > > arch/mips/Kconfig | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 09ab87e..80d9199 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -122,6 +122,7 @@ config BCM63XX > select SYS_HAS_EARLY_PRINTK > select SWAP_IO_SPACE > select ARCH_REQUIRE_GPIOLIB > + select HAVE_CLK > help > Support for BCM63XX based boards Reviewed-by: Viresh Kumar -- Viresh -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From jonas.gorski@gmail.com Fri Jul 13 10:31:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 10:31:40 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:57814 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903258Ab2GMIbg (ORCPT ); Fri, 13 Jul 2012 10:31:36 +0200 Received: by bkcji2 with SMTP id ji2so2818019bkc.36 for ; Fri, 13 Jul 2012 01:31:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=T+E/ZyUwcH5fCod53kOijkGcdS51XYTrG5TnRKoTBJg=; b=WrnpEKNcaRfFoSpGvsM4Az/fp/C2EfXuUgzqzPX08rgnVPPrUU7KdKAcSrj9eJKGMw gzUnDdlNphSHSpWcyIq6t11LRTXPtVAmd5ShSP21jEhwOXU4ZCzrZp0bNMlyCJmqQFfJ CK0fYFQqRWTXRSV4K7gxR6TikJR5jnvn97WXesAQgkWwCEhEsbG5lOQhlm1ya6WjSco9 VyB5hFNP4a73USSxgbBxCOEseUwqsddDl/LaEA9GZwA50s3NQwY2di61pHmiunpnDImT aORjkprotMjF5R6MlZF/vt1keSbvFj2NlWNVFQQd+vFzXCNwE/yrckXkenMb6eRGx/BX mXeg== Received: by 10.204.155.69 with SMTP id r5mr150002bkw.49.1342168290653; Fri, 13 Jul 2012 01:31:30 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-145-009.pools.arcor-ip.net. [88.73.145.9]) by mx.google.com with ESMTPS id gq2sm4211293bkc.13.2012.07.13.01.31.28 (version=SSLv3 cipher=OTHER); Fri, 13 Jul 2012 01:31:29 -0700 (PDT) From: Jonas Gorski To: linux-mips@linux-mips.org Cc: Ralf Baechle , Florian Fainelli , Maxime Bizon , Kevin Cernekee Subject: [PATCH] MIPS: BCM63XX: remove bogus ENETSW_TXDMA interrupts from BCM6328 Date: Fri, 13 Jul 2012 10:30:46 +0200 Message-Id: <1342168246-18012-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 33902 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1622 Lines: 37 These were erroneously copied from BCM6368. BCM6328 does not expose the ENETSW_TXDMA interrupts, and BCM_6328_HIGH_IRQ_BASE + 7 is actually used for the second UART. Signed-off-by: Jonas Gorski --- Ralf, since there are no users for these (non) interrupts yet, I'll leave it at your discretion if you want to keep it as a separate patch or merge it into 02a0111daed3103368123596b9960d10986c0f7a ("MIPS: BCM63XX: Add basic BCM6328 support"). arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index e104ddb..9cc1b9f 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -615,10 +615,10 @@ enum bcm63xx_irq { #define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) #define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) #define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) -#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4) -#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5) -#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6) -#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) +#define BCM_6328_ENETSW_TXDMA0_IRQ 0 +#define BCM_6328_ENETSW_TXDMA1_IRQ 0 +#define BCM_6328_ENETSW_TXDMA2_IRQ 0 +#define BCM_6328_ENETSW_TXDMA3_IRQ 0 #define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) #define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) -- 1.7.2.5 From jonas.gorski@gmail.com Fri Jul 13 10:47:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 10:47:32 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:61696 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903467Ab2GMIr2 (ORCPT ); Fri, 13 Jul 2012 10:47:28 +0200 Received: by bkcji2 with SMTP id ji2so2825809bkc.36 for ; Fri, 13 Jul 2012 01:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=n8j2xw9EImNzeTWcJOfDWmqw07zetSwtRMbb3nXMHHo=; b=seIZIGcbZIrmWn6l0iekJ10H6yQA2gZef3v4Z+Ko2lz/wbI6lJyZ9qhAqQMcPCQ5Q1 8P8/H9c5OA6RQfDYHan7/ZhG2T33yej1n2TXXYIJinml+yKv346G3XyxJT/sdaj9D2Z+ ot1pUppo9HzQUEF3W835e7owT6NUUgUeXwIddBGqDH8Ufi7U9OVsoagWAAD8vQhTMnM4 YaJz6E5lIVfwj1KsU0/FRVvZsq1ScpcFy5FRSg4YmF1V9JQciZ9+SpZhpmQbDDmJPzHg tkvD3EZK3NkOPR1lTyj0AbeZXdNbqZxJky1o3ARWC2r4rNCpizSIkC8tVGq273232xQi 2BkQ== Received: by 10.205.136.3 with SMTP id ii3mr154113bkc.101.1342169243083; Fri, 13 Jul 2012 01:47:23 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-145-009.pools.arcor-ip.net. [88.73.145.9]) by mx.google.com with ESMTPS id hg13sm4243506bkc.7.2012.07.13.01.47.21 (version=SSLv3 cipher=OTHER); Fri, 13 Jul 2012 01:47:22 -0700 (PDT) From: Jonas Gorski To: linux-mips@linux-mips.org Cc: Ralf Baechle , Florian Fainelli , Maxime Bizon , Kevin Cernekee Subject: [PATCH 0/3] MIPS: BCM63XX: small fixes from the BCM6368 patches Date: Fri, 13 Jul 2012 10:46:02 +0200 Message-Id: <1342169165-18382-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 33903 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 786 Lines: 21 "MIPS: BCM63XX: add external irq support for non 6348 CPUs" and "MIPS: BCM63XX: add support for bcm6368 CPU" received an update, but the update never made it into the tree. Since they can't be updated now, but there were real fixes in them I decided to split them up into sensible patches and add a proper commit log for them. Maxime Bizon (3): MIPS: BCM63XX: add external irq support for BCM6345 MIPS: BCM63XX: don't write to the chipid register on reboot MIPS: BCM63XX: use a switch for external irq config arch/mips/bcm63xx/irq.c | 22 ++++++++++++++++---- arch/mips/bcm63xx/setup.c | 6 +++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 1 + 3 files changed, 24 insertions(+), 5 deletions(-) -- 1.7.2.5 From jonas.gorski@gmail.com Fri Jul 13 10:47:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 10:47:56 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:54946 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903474Ab2GMIra (ORCPT ); Fri, 13 Jul 2012 10:47:30 +0200 Received: by bkcji2 with SMTP id ji2so2825825bkc.36 for ; Fri, 13 Jul 2012 01:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=qTJAs01VSMmr5k+FyJOoO25VGprtdyTTVdKB4fsS6DI=; b=tzoRxTEQOkVhFVdcXoI1adSu1A324wirdesk7uL/qgYk+ESeO5OEJkfraKmpzL2kkY Yi9d40sX8E81rOeKWWWtqQ0jMg66DOGdr/7kMCwmC6KZ1uyFQCHT+9KPqoyZ+9vFk7k2 33ZMMzmCu+OPcRwgK0yTW7Q+Ux/jGDuF8PP3m5Za8NvI50AMxZK3YJyAuvW5cfu8YMBX OVtfPywLatJ5H1xc5JoFysMvBkrJvNJYhNUhf/BjhuPQJCucJzvTCxJCDsPUWGpvVrLV vUkMMaI0CIquHYlcE66XdRaIi4waCCocuqRXMEXeE98414wt+H8CziurTmXlOHQLN6d2 i32A== Received: by 10.204.130.10 with SMTP id q10mr156633bks.90.1342169244788; Fri, 13 Jul 2012 01:47:24 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-145-009.pools.arcor-ip.net. [88.73.145.9]) by mx.google.com with ESMTPS id hg13sm4243506bkc.7.2012.07.13.01.47.23 (version=SSLv3 cipher=OTHER); Fri, 13 Jul 2012 01:47:23 -0700 (PDT) From: Jonas Gorski To: linux-mips@linux-mips.org Cc: Ralf Baechle , Florian Fainelli , Maxime Bizon , Kevin Cernekee Subject: [PATCH 1/3] MIPS: BCM63XX: add external irq support for BCM6345 Date: Fri, 13 Jul 2012 10:46:03 +0200 Message-Id: <1342169165-18382-2-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1342169165-18382-1-git-send-email-jonas.gorski@gmail.com> References: <1342169165-18382-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33904 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2481 Lines: 72 From: Maxime Bizon Add the missing definitions for BCM6345. Signed-off-by: Maxime Bizon Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/irq.c | 8 ++++++-- arch/mips/bcm63xx/setup.c | 3 +++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 1 + 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 18e051a..d40169f 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -56,8 +56,8 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #define is_ext_irq_cascaded 0 #define ext_irq_start 0 #define ext_irq_end 0 -#define ext_irq_count 0 -#define ext_irq_cfg_reg1 0 +#define ext_irq_count 4 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345 #define ext_irq_cfg_reg2 0 #endif #ifdef CONFIG_BCM63XX_CPU_6348 @@ -143,11 +143,15 @@ static void bcm63xx_init_irq(void) irq_stat_addr += PERF_IRQSTAT_6338_REG; irq_mask_addr += PERF_IRQMASK_6338_REG; irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; break; case BCM6345_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6345_REG; irq_mask_addr += PERF_IRQMASK_6345_REG; irq_bits = 32; + ext_irq_count = 4; + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; break; case BCM6348_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6348_REG; diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index 0e74a13..bd83836 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -74,6 +74,9 @@ void bcm63xx_machine_reboot(void) case BCM6338_CPU_ID: perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; break; + case BCM6345_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345; + break; case BCM6348_CPU_ID: perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348; break; diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 4ccc2a7..75f162d 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -161,6 +161,7 @@ /* External Interrupt Configuration register */ #define PERF_EXTIRQ_CFG_REG_6328 0x18 #define PERF_EXTIRQ_CFG_REG_6338 0x14 +#define PERF_EXTIRQ_CFG_REG_6345 0x14 #define PERF_EXTIRQ_CFG_REG_6348 0x14 #define PERF_EXTIRQ_CFG_REG_6358 0x14 #define PERF_EXTIRQ_CFG_REG_6368 0x18 -- 1.7.2.5 From jonas.gorski@gmail.com Fri Jul 13 10:47:31 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 10:48:19 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:63991 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903481Ab2GMIrb (ORCPT ); Fri, 13 Jul 2012 10:47:31 +0200 Received: by bkcji2 with SMTP id ji2so2825838bkc.36 for ; Fri, 13 Jul 2012 01:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=XRP8s9bp9IpjPfAmln11Q2TXKl+uJAi2FqSiCyCltPE=; b=hQhyHuUfORxg/CGSH2Bxl1FMffaF9blZjldTGbcxPtV8IGaTmgU8ydTOPeqq7ccl2T t+MzAZbRqwIioA20Lxb7X1mB1aHDoBpbvCUBJg4DcujRVQRB9thUUN0FRGSOfacf8PmY FromeYhcqpEuZ5L3ASlW+5cqtyGbBU0cI5s1z2O3P9oqWh7d+Z7VGltnGU7lDyZ8Redt rQ2K3r69DK/3rKpg3XUSk2VixvPiCh42wluzj/Ypd+I0JLPdBMvaDIXz9FhZuujFge4M BNSEc0wHa/lpsXSMBzVzn3Zt2tQRtJdQ2vx4i2B9frxLbKuR+ukAZNe0vR5vTvureDcc tjQg== Received: by 10.204.154.74 with SMTP id n10mr181638bkw.60.1342169246362; Fri, 13 Jul 2012 01:47:26 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-145-009.pools.arcor-ip.net. [88.73.145.9]) by mx.google.com with ESMTPS id hg13sm4243506bkc.7.2012.07.13.01.47.24 (version=SSLv3 cipher=OTHER); Fri, 13 Jul 2012 01:47:25 -0700 (PDT) From: Jonas Gorski To: linux-mips@linux-mips.org Cc: Ralf Baechle , Florian Fainelli , Maxime Bizon , Kevin Cernekee Subject: [PATCH 2/3] MIPS: BCM63XX: don't write to the chipid register on reboot Date: Fri, 13 Jul 2012 10:46:04 +0200 Message-Id: <1342169165-18382-3-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1342169165-18382-1-git-send-email-jonas.gorski@gmail.com> References: <1342169165-18382-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33905 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 676 Lines: 27 From: Maxime Bizon While harmless, it is bad style to do so. Signed-off-by: Maxime Bizon Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/setup.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index bd83836..314231b 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -86,6 +86,9 @@ void bcm63xx_machine_reboot(void) } for (i = 0; i < 2; i++) { + if (!perf_regs[i]) + break; + reg = bcm_perf_readl(perf_regs[i]); if (BCMCPU_IS_6348()) { reg &= ~EXTIRQ_CFG_MASK_ALL_6348; -- 1.7.2.5 From jonas.gorski@gmail.com Fri Jul 13 10:47:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 10:48:43 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:50181 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903610Ab2GMIrd (ORCPT ); Fri, 13 Jul 2012 10:47:33 +0200 Received: by bkcji2 with SMTP id ji2so2825853bkc.36 for ; Fri, 13 Jul 2012 01:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=7fIoExIxF/X7rOHeZHnEdPF7vheRp9RUMIDq1RTSBCE=; b=y7jmscREAE0x05/QSKOoRJnmDIRL4FA8lco3i6LZygxW2OEDkoZWb/UeAtkPpo/Izh aUXzYl59H9TJ2qHi1UxI3Pjo/mGbUoDuEo7UAxTeHCVly6GfmEPTZCc3zHDEaBz8V9zv HJXcqSoY8kmQhGvmxGFV3bVS0OKN5LdU6pMZ05H4RrBImsqEvzd228M2HrBV5WfoT346 cEbf4ShCokoGYoRfSin0Bw+t8hYOF7kaczeIjylfUoY94hy8enGnvZA+gL7OaljAxy/q GlSXSQ4YTeZT2Ym5XBRP45MyeNaqHlm+2GYmslrD/mJ5znbH3r+06uFweSySaU6OTPX/ wqWA== Received: by 10.204.152.152 with SMTP id g24mr146323bkw.104.1342169247988; Fri, 13 Jul 2012 01:47:27 -0700 (PDT) Received: from shaker64.lan (dslb-088-073-145-009.pools.arcor-ip.net. [88.73.145.9]) by mx.google.com with ESMTPS id hg13sm4243506bkc.7.2012.07.13.01.47.26 (version=SSLv3 cipher=OTHER); Fri, 13 Jul 2012 01:47:27 -0700 (PDT) From: Jonas Gorski To: linux-mips@linux-mips.org Cc: Ralf Baechle , Florian Fainelli , Maxime Bizon , Kevin Cernekee Subject: [PATCH 3/3] MIPS: BCM63XX: use a switch for external irq config Date: Fri, 13 Jul 2012 10:46:05 +0200 Message-Id: <1342169165-18382-4-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1342169165-18382-1-git-send-email-jonas.gorski@gmail.com> References: <1342169165-18382-1-git-send-email-jonas.gorski@gmail.com> X-archive-position: 33906 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1441 Lines: 54 From: Maxime Bizon Makes the code a bit more readable and easier to add support for new chips. Signed-off-by: Maxime Bizon Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/irq.c | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index d40169f..da24c2b 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -438,7 +438,8 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, reg = bcm_perf_readl(regaddr); irq %= 4; - if (BCMCPU_IS_6348()) { + switch (bcm63xx_get_cpu_id()) { + case BCM6348_CPU_ID: if (levelsense) reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); else @@ -451,9 +452,13 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); else reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); - } + break; - if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { + case BCM6328_CPU_ID: + case BCM6338_CPU_ID: + case BCM6345_CPU_ID: + case BCM6358_CPU_ID: + case BCM6368_CPU_ID: if (levelsense) reg |= EXTIRQ_CFG_LEVELSENSE(irq); else @@ -466,6 +471,9 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, reg |= EXTIRQ_CFG_BOTHEDGE(irq); else reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); + break; + default: + BUG(); } bcm_perf_writel(reg, regaddr); -- 1.7.2.5 From codeblue@inbox.lv Fri Jul 13 12:54:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 12:54:22 +0200 (CEST) Received: from shark3.inbox.lv ([89.111.3.83]:32990 "EHLO shark3.inbox.lv" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1902755Ab2GMKyS (ORCPT ); Fri, 13 Jul 2012 12:54:18 +0200 Received: from mail.inbox.lv (pop [10.0.1.110]) by shark3-plain.inbox.lv (Postfix) with ESMTP id 13B87EEFD for ; Fri, 13 Jul 2012 13:54:13 +0300 (EEST) Received: from inbox.lv (unknown [77.125.145.41]) (Authenticated sender: codeblue@inbox.lv) by mail.inbox.lv (Postfix) with ESMTPSA id 4045D18546 for ; Fri, 13 Jul 2012 13:54:10 +0300 (EEST) Date: Fri, 13 Jul 2012 10:54:06 +0000 From: John Long To: linux-mips@linux-mips.org Subject: Re: Please recommend distro for Lemote Fuloong Message-ID: <20120713105406.GA30449@inbox.lv> References: <20120705160222.GJ25225@inbox.lv> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Virus-Scanned: OK X-archive-position: 33907 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: codeblue@inbox.lv Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Status: RO Content-Length: 1182 Lines: 25 On Thu, Jul 12, 2012 at 04:52:41PM -0700, Matt Turner wrote: > On Thu, Jul 5, 2012 at 9:02 AM, Code Blue wrote: > > Hi, > > > > I just received a Lemote Fuloong Mini and I installed OpenBSD on it. I would > > like to dual boot Linux but I am having a hard time finding the right distro. > > > > I know Lemote and MIPS people are doing a lot of work and submitting patches > > to the Linux kernel and binutils and I am sure many other areas. Can anyone > > please recommend a Linux distro that will come with (or can install) a > > recent kernel so I can take advantage of all this hard work people are > > doing? Of course I will need a tarball or USB installer since the Fuloong > > doesn't have an optical drive. Thank you. > > Gentoo. > > Join the #gentoo-mips IRC channel and ping 'blueness' since he's built > some very nice install stages and netboot images. > > Also, we provide multilib installations with o32, n32, and n64 base > libraries (n32 is default). Thanks a lot for the info. For now I have repartitioned the drive and used all of it for OpenBSD. I hope to get another identical box in the next few months and then I will look into Gentoo. From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:26 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:24:34 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2885 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903498Ab2GMQY0 (ORCPT ); Fri, 13 Jul 2012 18:24:26 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:13 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:24:10 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id B25879F9F5; Fri, 13 Jul 2012 09:24:10 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:10 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 01/12] MIPS: Netlogic: Fix indentation of smpboot.S Date: Fri, 13 Jul 2012 21:53:14 +0530 Message-ID: <1342196605-4260-2-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94FB3NK5403875-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33909 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Status: RO Content-Length: 1538 Lines: 66 Fix whitespace issue introduced in the last merge, and while there use tabs consistently in assembly after opcode. No change in logic. Signed-off-by: Jayachandran C --- arch/mips/netlogic/common/smpboot.S | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index a58f498..7badf38 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -67,7 +67,7 @@ li t2, ~0xe /* S1RCM */ and t1, t1, t2 #endif - mtcr t1, t0 + mtcr t1, t0 #ifdef XLP_AX_WORKAROUND li t0, SCHED_DEFEATURE @@ -82,7 +82,7 @@ */ .macro xlp_flush_l1_dcache li t0, LSU_DEBUG_DATA0 - li t1, LSU_DEBUG_ADDR + li t1, LSU_DEBUG_ADDR li t2, 0 /* index */ li t3, 0x200 /* loop count, 512 sets */ 1: @@ -95,13 +95,13 @@ andi v1, 0x1 /* wait for write_active == 0 */ bnez v1, 2b nop - mtcr zero, t0 + mtcr zero, t0 ori v1, v0, 0x7 /* way1 | write_enable | write_active */ - mtcr v1, t1 + mtcr v1, t1 3: - mfcr v1, t1 - andi v1, 0x1 /* wait for write_active == 0 */ - bnez v1, 3b + mfcr v1, t1 + andi v1, 0x1 /* wait for write_active == 0 */ + bnez v1, 3b nop addi t2, 1 bne t3, t2, 1b @@ -193,9 +193,9 @@ EXPORT(nlm_boot_siblings) bnez v1, 2f nop - li t0, MMU_SETUP - li t1, 0 - mtcr t1, t0 + li t0, MMU_SETUP + li t1, 0 + mtcr t1, t0 _ehb 2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:25:00 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:1446 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903684Ab2GMQY1 (ORCPT ); Fri, 13 Jul 2012 18:24:27 +0200 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:25 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:23:28 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 636B29F9F5; Fri, 13 Jul 2012 09:24:08 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:07 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 00/12] Netlogic XLR/XLP updates. Date: Fri, 13 Jul 2012 21:53:13 +0530 Message-ID: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94F73MK9921326-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33910 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2384 Lines: 58 Fixes and updates for the Netlogic XLP code, this should apply cleanly on top of the current linux-next tree. Patch 1 (Netlogic: Fix indentation of smpboot.S) and patch 3 (Netlogic: merge of.c into setup.c) are fixups to the merge fallout in linux-next. Regards, JC. Ganesan Ramalingam (1): MIPS: Netlogic: DTS file for XLP boards Jayachandran C (9): MIPS: Netlogic: Fix indentation of smpboot.S MIPS: Netlogic: Fix low-level flush on core wakeup MIPS: Netlogic: merge of.c into setup.c MIPS: Netlogic: remove cpu_has_dc_aliases define for XLP MIPS: PCI: Fix for byte swap for Netlogic XLP MIPS: Netlogic: early console fix MIPS: Netlogic: Move serial ports to device tree MIPS: Netlogic: Add support for built in DTB MIPS: Netlogic: XLP defconfig update Madhusudan Bhat (1): MIPS: oprofile: Support for XLR/XLS processors Zi Shen Lim (1): MIPS: perf: Add XLP support for hardware perf. arch/mips/Kconfig | 3 +- arch/mips/configs/nlm_xlp_defconfig | 133 +++++++++++++------- .../asm/mach-netlogic/cpu-feature-overrides.h | 1 - arch/mips/kernel/perf_event_mipsxx.c | 124 ++++++++++++++++++ arch/mips/netlogic/Kconfig | 15 +++ arch/mips/netlogic/Makefile | 1 + arch/mips/netlogic/common/earlycons.c | 2 +- arch/mips/netlogic/common/smpboot.S | 22 ++-- arch/mips/netlogic/dts/Makefile | 4 + arch/mips/netlogic/dts/xlp_evp.dts | 124 ++++++++++++++++++ arch/mips/netlogic/xlp/Makefile | 3 +- arch/mips/netlogic/xlp/of.c | 34 ----- arch/mips/netlogic/xlp/platform.c | 108 ---------------- arch/mips/netlogic/xlp/setup.c | 32 ++++- arch/mips/oprofile/Makefile | 1 + arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 28 +++++ arch/mips/pci/pci-xlp.c | 5 +- 18 files changed, 437 insertions(+), 204 deletions(-) create mode 100644 arch/mips/netlogic/dts/Makefile create mode 100644 arch/mips/netlogic/dts/xlp_evp.dts delete mode 100644 arch/mips/netlogic/xlp/of.c delete mode 100644 arch/mips/netlogic/xlp/platform.c -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:25:24 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2901 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903698Ab2GMQY1 (ORCPT ); Fri, 13 Jul 2012 18:24:27 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:15 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:24:13 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id F04599F9FA; Fri, 13 Jul 2012 09:24:12 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:12 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 02/12] MIPS: Netlogic: Fix low-level flush on core wakeup Date: Fri, 13 Jul 2012 21:53:15 +0530 Message-ID: <1342196605-4260-3-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94F93NK5403908-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33911 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 771 Lines: 27 The L1D cache flush needs to be done for more iterations to ensure that the cache is clean before waking up threads. This change is experimental, but should not have any negative impact. Signed-off-by: Jayachandran C --- arch/mips/netlogic/common/smpboot.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index 7badf38..8c13cd9 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -84,7 +84,7 @@ li t0, LSU_DEBUG_DATA0 li t1, LSU_DEBUG_ADDR li t2, 0 /* index */ - li t3, 0x200 /* loop count, 512 sets */ + li t3, 0x1000 /* loop count */ 1: sll v0, t2, 5 mtcr zero, t0 -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:32 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:25:48 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2885 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903718Ab2GMQYc (ORCPT ); Fri, 13 Jul 2012 18:24:32 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:24 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:23:42 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 252499F9F5; Fri, 13 Jul 2012 09:24:22 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:21 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 06/12] MIPS: Netlogic: early console fix Date: Fri, 13 Jul 2012 21:53:19 +0530 Message-ID: <1342196605-4260-7-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94F63NK5403962-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33912 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 756 Lines: 25 In prom_putchar(), wait for just the TX empty bit to clear in the UART LSR. Signed-off-by: Jayachandran C --- arch/mips/netlogic/common/earlycons.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c index f193f7b..53b200a5 100644 --- a/arch/mips/netlogic/common/earlycons.c +++ b/arch/mips/netlogic/common/earlycons.c @@ -54,7 +54,7 @@ void prom_putchar(char c) #elif defined(CONFIG_CPU_XLR) uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); #endif - while (nlm_read_reg(uartbase, UART_LSR) == 0) + while ((nlm_read_reg(uartbase, UART_LSR) & 0x20) == 0) ; nlm_write_reg(uartbase, UART_TX, c); } -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:26:11 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:1468 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903714Ab2GMQYd (ORCPT ); Fri, 13 Jul 2012 18:24:33 +0200 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:31 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:23:35 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 460B89F9F5; Fri, 13 Jul 2012 09:24:15 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:14 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 03/12] MIPS: Netlogic: merge of.c into setup.c Date: Fri, 13 Jul 2012 21:53:16 +0530 Message-ID: <1342196605-4260-4-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94093MK9921388-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33913 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2838 Lines: 105 Move the function device_tree_init() from netlogic/xlp/of.c to setup.c, and remove the wrapper functions reserve_mem_mach() and free_mem_mach(). Remove file netlogic/xlp/of.c, and the Makefile entry for it. Signed-off-by: Jayachandran C --- arch/mips/netlogic/xlp/Makefile | 1 - arch/mips/netlogic/xlp/of.c | 34 ---------------------------------- arch/mips/netlogic/xlp/setup.c | 20 ++++++++++++++++++++ 3 files changed, 20 insertions(+), 35 deletions(-) delete mode 100644 arch/mips/netlogic/xlp/of.c diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index 6b4b972..5bd24b6 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,4 +1,3 @@ obj-y += setup.o platform.o nlm_hal.o -obj-$(CONFIG_OF) += of.o obj-$(CONFIG_SMP) += wakeup.o obj-$(CONFIG_USB) += usb-init.o diff --git a/arch/mips/netlogic/xlp/of.c b/arch/mips/netlogic/xlp/of.c deleted file mode 100644 index 8e3921c..0000000 --- a/arch/mips/netlogic/xlp/of.c +++ /dev/null @@ -1,34 +0,0 @@ -#include -#include -#include -#include -#include - -static int __init reserve_mem_mach(unsigned long addr, unsigned long size) -{ - return reserve_bootmem(addr, size, BOOTMEM_DEFAULT); -} - -void __init free_mem_mach(unsigned long addr, unsigned long size) -{ - return free_bootmem(addr, size); -} - -void __init device_tree_init(void) -{ - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_mem_mach(base, size); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_mem_mach(base, size); -} diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 3dec9f2..0d2d679 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -112,6 +113,25 @@ void __init prom_init(void) #endif } +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); + + /* free the space reserved for the dt blob */ + free_bootmem(base, size); +} + static struct of_device_id __initdata xlp_ids[] = { { .compatible = "simple-bus", }, {}, -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:26:34 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2885 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903722Ab2GMQYh (ORCPT ); Fri, 13 Jul 2012 18:24:37 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:29 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:23:47 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 0A4F39F9F5; Fri, 13 Jul 2012 09:24:27 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:26 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 08/12] MIPS: Netlogic: Move serial ports to device tree Date: Fri, 13 Jul 2012 21:53:21 +0530 Message-ID: <1342196605-4260-9-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E940B3NK5403974-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33914 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5546 Lines: 170 Add the serial ports to the device tree and remove the platform code for adding them. Signed-off-by: Jayachandran C --- arch/mips/netlogic/dts/xlp_evp.dts | 21 +++++++ arch/mips/netlogic/xlp/Makefile | 2 +- arch/mips/netlogic/xlp/platform.c | 108 ------------------------------------ 3 files changed, 22 insertions(+), 109 deletions(-) delete mode 100644 arch/mips/netlogic/xlp/platform.c diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts index 86a29ca..e14f423 100644 --- a/arch/mips/netlogic/dts/xlp_evp.dts +++ b/arch/mips/netlogic/dts/xlp_evp.dts @@ -22,6 +22,27 @@ compatible = "simple-bus"; ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG 1 0 0 0x16000000 0x01000000>; // GBU chipselects + + serial0: serial@30000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x30100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + serial1: serial@31000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x31100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <18>; + }; i2c0: ocores@32000 { compatible = "opencores,i2c-ocores"; #address-cells = <1>; diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile index 5bd24b6..a84d6ed 100644 --- a/arch/mips/netlogic/xlp/Makefile +++ b/arch/mips/netlogic/xlp/Makefile @@ -1,3 +1,3 @@ -obj-y += setup.o platform.o nlm_hal.o +obj-y += setup.o nlm_hal.o obj-$(CONFIG_SMP) += wakeup.o obj-$(CONFIG_USB) += usb-init.o diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c deleted file mode 100644 index 2c510d5..0000000 --- a/arch/mips/netlogic/xlp/platform.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset) -{ - return nlm_read_reg(p->iobase, offset); -} - -static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value) -{ - nlm_write_reg(p->iobase, offset, value); -} - -#define PORT(_irq) \ - { \ - .irq = _irq, \ - .regshift = 2, \ - .iotype = UPIO_MEM32, \ - .flags = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\ - UPF_BOOT_AUTOCONF), \ - .uartclk = XLP_IO_CLK, \ - .type = PORT_16550A, \ - .serial_in = nlm_xlp_uart_in, \ - .serial_out = nlm_xlp_uart_out, \ - } - -static struct plat_serial8250_port xlp_uart_data[] = { - PORT(PIC_UART_0_IRQ), - PORT(PIC_UART_1_IRQ), - {}, -}; - -static struct platform_device uart_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = xlp_uart_data, - }, -}; - -static int __init nlm_platform_uart_init(void) -{ - unsigned long mmio; - - mmio = (unsigned long)nlm_get_uart_regbase(0, 0); - xlp_uart_data[0].iobase = mmio; - xlp_uart_data[0].membase = (void __iomem *)mmio; - xlp_uart_data[0].mapbase = mmio; - - mmio = (unsigned long)nlm_get_uart_regbase(0, 1); - xlp_uart_data[1].iobase = mmio; - xlp_uart_data[1].membase = (void __iomem *)mmio; - xlp_uart_data[1].mapbase = mmio; - - return platform_device_register(&uart_device); -} - -arch_initcall(nlm_platform_uart_init); -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:26:59 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2298 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903725Ab2GMQYi (ORCPT ); Fri, 13 Jul 2012 18:24:38 +0200 Received: from [10.9.200.131] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:02 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:24:17 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 951A89F9F5; Fri, 13 Jul 2012 09:24:17 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:16 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 04/12] MIPS: Netlogic: remove cpu_has_dc_aliases define for XLP Date: Fri, 13 Jul 2012 21:53:17 +0530 Message-ID: <1342196605-4260-5-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94EC4989490099-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33915 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 915 Lines: 28 On XLP, the dcache size depends on the number of enabled threads in core. There are no dcache aliases if the pagesize is large enough or if enough threads are enabled in the core. Remove the #define for cpu_has_dc_aliases and leave it to be computed at runtime. Signed-off-by: Jayachandran C --- .../asm/mach-netlogic/cpu-feature-overrides.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h index d193fb6..966db4b 100644 --- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -48,7 +48,6 @@ #define cpu_has_userlocal 1 #define cpu_has_mips32r2 1 #define cpu_has_mips64r2 1 -#define cpu_has_dc_aliases 1 #else #error "Unknown Netlogic CPU" #endif -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:27:24 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2342 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903726Ab2GMQYk (ORCPT ); Fri, 13 Jul 2012 18:24:40 +0200 Received: from [10.9.200.133] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:09 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:23:45 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id C39849F9F6; Fri, 13 Jul 2012 09:24:24 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:24 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Ganesan Ramalingam" , "Jayachandran C" Subject: [PATCH 07/12] MIPS: Netlogic: DTS file for XLP boards Date: Fri, 13 Jul 2012 21:53:20 +0530 Message-ID: <1342196605-4260-8-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94E74989490133-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33916 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2826 Lines: 125 From: Ganesan Ramalingam Add a basic DTS file netlogic/dts/nlm_xlp.dts which contains memory, i2c devices, NOR flash and command line arguments. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/netlogic/dts/xlp_evp.dts | 103 ++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 arch/mips/netlogic/dts/xlp_evp.dts diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts new file mode 100644 index 0000000..86a29ca --- /dev/null +++ b/arch/mips/netlogic/dts/xlp_evp.dts @@ -0,0 +1,103 @@ +/* + * XLP8XX Device Tree Source for EVP boards + */ + +/dts-v1/; +/ { + model = "netlogic,XLP-EVP"; + compatible = "netlogic,xlp"; + #address-cells = <2>; + #size-cells = <2>; + + memory { + device_type = "memory"; + reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M + 0 0x20000000 0 0xa0000000 // 2560M at 512M + 0 0xe0000000 1 0x00000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG + 1 0 0 0x16000000 0x01000000>; // GBU chipselects + i2c0: ocores@32000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x32100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <30>; + }; + i2c1: ocores@33000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x33100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <31>; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + + dtt@4c { + compatible = "national,lm90"; + reg = <0x4c>; + }; + }; + pic: pic@4000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0 0x4000 0x200>; + }; + + nor_flash@1,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + reg = <1 0 0x1000000>; + + partition@0 { + label = "x-loader"; + reg = <0x0 0x100000>; /* 1M */ + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; /* 1M */ + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; /* 5M */ + }; + + partition@700000 { + label = "rootfs"; + reg = <0x700000 0x800000>; /* 8M */ + }; + + partition@f00000 { + label = "env"; + reg = <0xf00000 0x100000>; /* 1M */ + read-only; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; + }; +}; -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:27:49 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2901 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903731Ab2GMQYm (ORCPT ); Fri, 13 Jul 2012 18:24:42 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:37 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:24:34 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id DCB999F9F5; Fri, 13 Jul 2012 09:24:34 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:34 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Zi Shen Lim" , "Jayachandran C" Subject: [PATCH 11/12] MIPS: perf: Add XLP support for hardware perf. Date: Fri, 13 Jul 2012 21:53:24 +0530 Message-ID: <1342196605-4260-12-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94033NK5404014-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33917 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6087 Lines: 182 From: Zi Shen Lim Signed-off-by: Zi Shen Lim Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 2 +- arch/mips/kernel/perf_event_mipsxx.c | 124 ++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d80ed42..3c7714a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2164,7 +2164,7 @@ config NODES_SHIFT config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON) + depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP) default y help Enable hardware performance counter support for perf events. If diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 2f28d3b..15cbbc3 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -829,6 +829,16 @@ static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, }; +static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, + [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */ + [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ + [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */ + [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ + [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, +}; + /* 24K/34K/1004K cores can share the same cache event map. */ static const struct mips_perf_event mipsxxcore_cache_map [PERF_COUNT_HW_CACHE_MAX] @@ -1158,6 +1168,100 @@ static const struct mips_perf_event octeon_cache_map }, }; +static const struct mips_perf_event xlp_cache_map + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { +[C(L1D)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */ + [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */ + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ + [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ + [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */ + [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */ + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ + [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(DTLB)] = { + /* + * Only general DTLB misses are counted use the same event for + * read and write. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(BPU)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +}; + #ifdef CONFIG_MIPS_MT_SMP static void check_and_calc_range(struct perf_event *event, const struct mips_perf_event *pev) @@ -1499,6 +1603,20 @@ static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) return &raw_event; } +static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config) +{ + unsigned int raw_id = config & 0xff; + + /* Only 1-63 are defined */ + if ((raw_id < 0x01) || (raw_id > 0x3f)) + return ERR_PTR(-EOPNOTSUPP); + + raw_event.cntr_mask = CNTR_ALL; + raw_event.event_id = raw_id; + + return &raw_event; +} + static int __init init_hw_perf_events(void) { @@ -1572,6 +1690,12 @@ init_hw_perf_events(void) mipspmu.cache_event_map = &octeon_cache_map; mipspmu.map_raw_event = octeon_pmu_map_raw_event; break; + case CPU_XLP: + mipspmu.name = "xlp"; + mipspmu.general_event_map = &xlp_event_map; + mipspmu.cache_event_map = &xlp_cache_map; + mipspmu.map_raw_event = xlp_pmu_map_raw_event; + break; default: pr_cont("Either hardware does not support performance " "counters, or not yet implemented.\n"); -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:28:15 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2885 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903729Ab2GMQYm (ORCPT ); Fri, 13 Jul 2012 18:24:42 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:34 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:24:32 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 37CC69F9F5; Fri, 13 Jul 2012 09:24:32 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:31 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Madhusudan Bhat" , "Jayachandran C" Subject: [PATCH 10/12] MIPS: oprofile: Support for XLR/XLS processors Date: Fri, 13 Jul 2012 21:53:23 +0530 Message-ID: <1342196605-4260-11-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E940C3NK5404007-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33918 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3851 Lines: 122 From: Madhusudan Bhat Add support for XLR and XLS processors in MIPS Oprofile code. These processors are multi-threaded and have two counters per core. Each counter can track either all the events in the core (global mode), or events in just one thread. We use the counters in the global mode, and use only the first thread in each core to handle the configuration etc. Signed-off-by: Madhusudan Bhat Signed-off-by: Jayachandran C --- arch/mips/oprofile/Makefile | 1 + arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 1208c28..65f5237 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -12,5 +12,6 @@ oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o +oprofile-$(CONFIG_CPU_XLR) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index f80480a..abd5a02 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -91,6 +91,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_R10000: case CPU_R12000: case CPU_R14000: + case CPU_XLR: lmodel = &op_model_mipsxx_ops; break; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 28ea1a4..7862546 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -31,8 +31,22 @@ #define M_COUNTER_OVERFLOW (1UL << 31) +/* Netlogic XLR specific, count events in all threads in a core */ +#define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13) + static int (*save_perf_irq)(void); +/* + * XLR has only one set of counters per core. Designate the + * first hardware thread in the core for setup and init. + * Skip CPUs with non-zero hardware thread id (4 hwt per core) + */ +#ifdef CONFIG_CPU_XLR +#define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0) +#else +#define oprofile_skip_cpu(c) 0 +#endif + #ifdef CONFIG_MIPS_MT_SMP static int cpu_has_mipsmt_pertccounters; #define WHAT (M_TC_EN_VPE | \ @@ -152,6 +166,8 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr) reg.control[i] |= M_PERFCTL_USER; if (ctr[i].exl) reg.control[i] |= M_PERFCTL_EXL; + if (current_cpu_type() == CPU_XLR) + reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS; reg.counter[i] = 0x80000000 - ctr[i].count; } } @@ -162,6 +178,9 @@ static void mipsxx_cpu_setup(void *args) { unsigned int counters = op_model_mipsxx_ops.num_counters; + if (oprofile_skip_cpu(smp_processor_id())) + return; + switch (counters) { case 4: w_c0_perfctrl3(0); @@ -183,6 +202,9 @@ static void mipsxx_cpu_start(void *args) { unsigned int counters = op_model_mipsxx_ops.num_counters; + if (oprofile_skip_cpu(smp_processor_id())) + return; + switch (counters) { case 4: w_c0_perfctrl3(WHAT | reg.control[3]); @@ -200,6 +222,9 @@ static void mipsxx_cpu_stop(void *args) { unsigned int counters = op_model_mipsxx_ops.num_counters; + if (oprofile_skip_cpu(smp_processor_id())) + return; + switch (counters) { case 4: w_c0_perfctrl3(0); @@ -372,6 +397,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/loongson1"; break; + case CPU_XLR: + op_model_mipsxx_ops.cpu_type = "mips/xlr"; + break; + default: printk(KERN_ERR "Profiling unsupported for this CPU\n"); -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:28:40 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2344 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903727Ab2GMQYm (ORCPT ); Fri, 13 Jul 2012 18:24:42 +0200 Received: from [10.9.200.133] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:14 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:23:49 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 99C529F9F5; Fri, 13 Jul 2012 09:24:29 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:28 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 09/12] MIPS: Netlogic: Add support for built in DTB Date: Fri, 13 Jul 2012 21:53:22 +0530 Message-ID: <1342196605-4260-10-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94F84989490169-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33919 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3065 Lines: 103 Provide a config option to embed a device tree for XLP evaluation boards. This DTB will be used if the firmware does not pass in a device tree pointer. Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 1 + arch/mips/netlogic/Kconfig | 15 +++++++++++++++ arch/mips/netlogic/Makefile | 1 + arch/mips/netlogic/dts/Makefile | 4 ++++ arch/mips/netlogic/xlp/setup.c | 12 +++++++++++- 5 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 arch/mips/netlogic/dts/Makefile diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 61e1459..d80ed42 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -827,6 +827,7 @@ config NLM_XLP_BOARD select ZONE_DMA if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK + select USE_OF help This board is based on Netlogic XLP Processor. Say Y here if you have a XLP based board. diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig index 75bec44..8059eb7 100644 --- a/arch/mips/netlogic/Kconfig +++ b/arch/mips/netlogic/Kconfig @@ -1,2 +1,17 @@ +if NLM_XLP_BOARD || NLM_XLR_BOARD + +if NLM_XLP_BOARD +config DT_XLP_EVP + bool "Built-in device tree for XLP EVP/SVP boards" + default y + help + Add an FDT blob for XLP EVP and SVP boards into the kernel. + This DTB will be used if the firmware does not pass in a DTB + pointer to the kernel. The corresponding DTS file is at + arch/mips/netlogic/dts/xlp_evp.dts +endif + config NLM_COMMON bool + +endif diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile index 36d169b..7602d13 100644 --- a/arch/mips/netlogic/Makefile +++ b/arch/mips/netlogic/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_NLM_COMMON) += common/ obj-$(CONFIG_CPU_XLR) += xlr/ obj-$(CONFIG_CPU_XLP) += xlp/ +obj-$(CONFIG_CPU_XLP) += dts/ diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile new file mode 100644 index 0000000..67ae3fe --- /dev/null +++ b/arch/mips/netlogic/dts/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o + +$(obj)/%.dtb: $(obj)/%.dts + $(call if_changed,dtc) diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 0d2d679..d899709 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -57,6 +57,7 @@ unsigned long nlm_common_ebase = 0x0; /* default to uniprocessor */ uint32_t nlm_coremask = 1, nlm_cpumask = 1; int nlm_threads_per_core = 1; +extern u32 __dtb_start[]; static void nlm_linux_exit(void) { @@ -97,9 +98,18 @@ void __init prom_init(void) { void *fdtp; - fdtp = (void *)(long)fw_arg0; xlp_mmu_init(); nlm_hal_init(); + + /* + * If no FDT pointer is passed in, use the built-in FDT. + * device_tree_init() does not handle CKSEG0 pointers in + * 64-bit, so convert pointer. + */ + fdtp = (void *)(long)fw_arg0; + if (!fdtp) + fdtp = __dtb_start; + fdtp = phys_to_virt(__pa(fdtp)); early_init_devtree(fdtp); nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:29:05 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2300 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903724Ab2GMQYn (ORCPT ); Fri, 13 Jul 2012 18:24:43 +0200 Received: from [10.9.200.131] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:04 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:24:19 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id E1C819F9F5; Fri, 13 Jul 2012 09:24:19 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:19 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 05/12] MIPS: PCI: Fix for byte swap for Netlogic XLP Date: Fri, 13 Jul 2012 21:53:18 +0530 Message-ID: <1342196605-4260-6-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94E24989490114-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33920 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1295 Lines: 38 The last 12 bits of the PCIe hardware swap size and limit registers are significant, while the same bits of the bridge PCIe registers are 0. So, to program limits correctly, we need to set the last 12 bits of the value read from the bridge limit registers to 1 before writing to the PCIe limit registers. Signed-off-by: Jayachandran C --- arch/mips/pci/pci-xlp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 3e177e9..140557a 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -213,13 +213,14 @@ static int xlp_enable_pci_bswap(void) nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, reg); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, + reg | 0xfff); reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); } return 0; } -- 1.7.9.5 From jayachandranc@netlogicmicro.com Fri Jul 13 18:24:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:29:35 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:2298 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903732Ab2GMQYp (ORCPT ); Fri, 13 Jul 2012 18:24:45 +0200 Received: from [10.9.200.133] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 09:23:22 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 09:23:57 -0700 Received: from hqcas02.netlogicmicro.com (unknown [10.65.50.15]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 4A57E9F9F6; Fri, 13 Jul 2012 09:24:37 -0700 (PDT) Received: from jayachandranc.netlogicmicro.com (10.7.0.77) by hqcas02.netlogicmicro.com (10.65.50.15) with Microsoft SMTP Server id 14.1.339.1; Fri, 13 Jul 2012 09:24:36 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 12/12] MIPS: Netlogic: XLP defconfig update Date: Fri, 13 Jul 2012 21:53:25 +0530 Message-ID: <1342196605-4260-13-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 X-Originating-IP: [10.7.0.77] X-WSS-ID: 7C1E94F04989490206-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33921 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8085 Lines: 294 Enable more devices and options for XLP default configuration: - Serial ports from FDT - NOR Flash support and partitions from FDT - PCI and PCI bus support and devices - SATA, e1000e, sky2 - I2C ocores controller and devices - ds1374, lm90 - Misc options such as RTC, partition formats etc. Signed-off-by: Jayachandran C --- arch/mips/configs/nlm_xlp_defconfig | 133 ++++++++++++++++++++++++----------- 1 file changed, 90 insertions(+), 43 deletions(-) diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig index 28c6b27..43b67a7 100644 --- a/arch/mips/configs/nlm_xlp_defconfig +++ b/arch/mips/configs/nlm_xlp_defconfig @@ -1,14 +1,12 @@ CONFIG_NLM_XLP_BOARD=y CONFIG_64BIT=y +CONFIG_PAGE_SIZE_16KB=y +# CONFIG_HW_PERF_EVENTS is not set CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 CONFIG_SMP=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y # CONFIG_SECCOMP is not set -CONFIG_USE_OF=y CONFIG_EXPERIMENTAL=y -CONFIG_CROSS_COMPILE="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -19,13 +17,13 @@ CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_CGROUPS=y CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y -CONFIG_INITRAMFS_COMPRESSION_LZMA=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set @@ -35,6 +33,29 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +CONFIG_ACORN_PARTITION_ICS=y +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_PCI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=y CONFIG_MIPS32_COMPAT=y @@ -170,7 +191,6 @@ CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m @@ -186,7 +206,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -197,7 +216,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m @@ -248,9 +266,6 @@ CONFIG_IPDDP_ENCAP=y CONFIG_IPDDP_DECAP=y CONFIG_X25=m CONFIG_LAPB=m -CONFIG_ECONET=m -CONFIG_ECONET_AUNUDP=y -CONFIG_ECONET_NATIVE=y CONFIG_WAN_ROUTER=m CONFIG_PHONET=m CONFIG_IEEE802154=m @@ -297,11 +312,21 @@ CONFIG_NET_ACT_SIMP=m CONFIG_NET_ACT_SKBEDIT=m CONFIG_DCB=y CONFIG_NET_PKTGEN=m -# CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m @@ -310,7 +335,6 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_CDROM_PKTCDVD=y CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y CONFIG_SCSI_TGT=m CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m @@ -337,6 +361,48 @@ CONFIG_SCSI_DH_EMC=m CONFIG_SCSI_DH_ALUA=m CONFIG_SCSI_OSD_INITIATOR=m CONFIG_SCSI_OSD_ULD=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_SIL24=y +# CONFIG_ATA_SFF is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_E1000E=y +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_SKY2=y +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m @@ -360,16 +426,23 @@ CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_OF_PLATFORM=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_RAW_DRIVER=m -# CONFIG_HWMON is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_OCORES=y +CONFIG_SENSORS_LM90=y +CONFIG_THERMAL=y # CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1374=y CONFIG_UIO=y CONFIG_UIO_PDRV=m CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -381,15 +454,10 @@ CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y CONFIG_GFS2_FS=m -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_OCFS2_FS=m CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_NILFS2_FS=m CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=y CONFIG_CUSE=m @@ -415,6 +483,7 @@ CONFIG_HFSPLUS_FS=m CONFIG_BEFS_FS=m CONFIG_BFS_FS=m CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=y CONFIG_CRAMFS=m CONFIG_SQUASHFS=m CONFIG_VXFS_FS=m @@ -427,7 +496,6 @@ CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_EXOFS_FS=m CONFIG_NFS_FS=m -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_NFS_FSCACHE=y @@ -450,25 +518,6 @@ CONFIG_NCPFS_NLS=y CONFIG_NCPFS_EXTRAS=y CONFIG_CODA_FS=m CONFIG_AFS_FS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_ACORN_PARTITION=y -CONFIG_ACORN_PARTITION_ICS=y -CONFIG_ACORN_PARTITION_RISCIX=y -CONFIG_OSF_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_ATARI_PARTITION=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_SGI_PARTITION=y -CONFIG_ULTRIX_PARTITION=y -CONFIG_SUN_PARTITION=y -CONFIG_KARMA_PARTITION=y -CONFIG_EFI_PARTITION=y -CONFIG_SYSV68_PARTITION=y CONFIG_NLS=y CONFIG_NLS_DEFAULT="cp437" CONFIG_NLS_CODEPAGE_437=m @@ -518,12 +567,10 @@ CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_SCHED_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_KGDB=y CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK=y CONFIG_LSM_MMAP_MIN_ADDR=0 CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y -- 1.7.9.5 From florian@openwrt.org Fri Jul 13 18:30:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 18:30:11 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:65290 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903718Ab2GMQaF (ORCPT ); Fri, 13 Jul 2012 18:30:05 +0200 Received: by eaaf11 with SMTP id f11so1171393eaa.36 for ; Fri, 13 Jul 2012 09:29:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:organization:user-agent :in-reply-to:references:mime-version:content-transfer-encoding :content-type; bh=ud6MvCWpfZnqLNmei4I2J1EUEYzFmj12TdTXOwU9jnY=; b=eU/180dLXqELSzX/F87ZGTUYH1Q6KItr4I24JTO28psvYA5bY/mSPnRNOsFOj7r135 aQUfVOLMWCgccDCLU0hclx057gqbjfN70LVjLY0b2O4lyl7t7vGHli1HVDTLGo78lZn+ wSBoVk74YLY/T6Jbt0t/1lXJchPbK5C/2Fu5p7Lb28Ay2sTgsDOzn52hLgfZid3mFd9Y qhkLIMWI8pmLjCRzOgVWMDbVKNqJx2UOMMgACRKyh5u8PIdWLeOhzX+sZ3Nkp/7uOlNs 4hv4877m1T7TjJoBf+39sUmfH+UVXTwEes6Px8hhhl+BIB5QAtjFWcTaNGUIMf6JLJPm EcoA== Received: by 10.14.101.138 with SMTP id b10mr516908eeg.56.1342196999619; Fri, 13 Jul 2012 09:29:59 -0700 (PDT) Received: from flexo.localnet (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id u56sm26747934eef.7.2012.07.13.09.29.54 (version=SSLv3 cipher=OTHER); Fri, 13 Jul 2012 09:29:55 -0700 (PDT) From: Florian Fainelli To: linux-mips@linux-mips.org Cc: Jayachandran C , ralf@linux-mips.org Subject: Re: [PATCH 06/12] MIPS: Netlogic: early console fix Date: Fri, 13 Jul 2012 18:27:07 +0200 Message-ID: <2602396.OWAlsVeLic@flexo> Organization: OpenWrt User-Agent: KMail/4.8.4 (Linux/3.2.0-24-generic; KDE/4.8.4; x86_64; ; ) In-Reply-To: <1342196605-4260-7-git-send-email-jayachandranc@netlogicmicro.com> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> <1342196605-4260-7-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="utf-8" X-archive-position: 33922 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 859 Lines: 25 On Friday 13 July 2012 21:53:19 Jayachandran C wrote: > In prom_putchar(), wait for just the TX empty bit to clear in the > UART LSR. > > Signed-off-by: Jayachandran C > --- > arch/mips/netlogic/common/earlycons.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c > index f193f7b..53b200a5 100644 > --- a/arch/mips/netlogic/common/earlycons.c > +++ b/arch/mips/netlogic/common/earlycons.c > @@ -54,7 +54,7 @@ void prom_putchar(char c) > #elif defined(CONFIG_CPU_XLR) > uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); > #endif > - while (nlm_read_reg(uartbase, UART_LSR) == 0) > + while ((nlm_read_reg(uartbase, UART_LSR) & 0x20) == 0) > ; You could use use UART_LSR_THRE here instead of 0x20. -- Florian From alcooperx@gmail.com Fri Jul 13 22:46:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 22:46:21 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:3906 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903724Ab2GMUqL (ORCPT ); Fri, 13 Jul 2012 22:46:11 +0200 Received: from [10.9.200.131] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 13:45:12 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 13:45:55 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 212689F9F7; Fri, 13 Jul 2012 13:45:55 -0700 (PDT) From: "Al Cooper" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org cc: "Al Cooper" Subject: [PATCH 2/5] MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt) Date: Fri, 13 Jul 2012 16:44:51 -0400 Message-ID: <1342212294-23014-2-git-send-email-alcooperx@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> References: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C1E57523MK9973571-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33923 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3049 Lines: 86 The PCI (Program Counter Interrupt) bit in the "cause" register is mandatory for MIPS32R2 cores, but has also been added to some R1 cores (BMIPS5000). This change adds a cpu feature bit to make it easier to check for and use this feature. Signed-off-by: Al Cooper --- arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/include/asm/mipsregs.h | 2 ++ arch/mips/kernel/cpu-probe.c | 5 ++++- arch/mips/kernel/perf_event_mipsxx.c | 2 +- 5 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7..55db8e1 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -252,4 +252,8 @@ #define cpu_hwrena_impl_bits 0 #endif +#ifndef cpu_has_perf_cntr_intr_bit +#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) +#endif + #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f21b7c0..783e598 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -319,6 +319,7 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ +#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7f87d82..2b83c36 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -458,6 +458,8 @@ #define CAUSEF_IP7 (_ULCAST_(1) << 15) #define CAUSEB_IV 23 #define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_PCI 26 +#define CAUSEF_PCI (_ULCAST_(1) << 26) #define CAUSEB_CE 28 #define CAUSEF_CE (_ULCAST_(3) << 28) #define CAUSEB_TI 30 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1b51046..7ae3895 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1186,8 +1186,11 @@ __cpuinit void cpu_probe(void) } } - if (cpu_has_mips_r2) + if (cpu_has_mips_r2) { c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; + /* R2 has Performance Counter Interrupt indicator */ + c->options |= MIPS_CPU_PCI; + } else c->srsets = 1; diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 8451f04..4ee1111 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1158,7 +1158,7 @@ static int mipsxx_pmu_handle_shared_irq(void) int handled = IRQ_NONE; struct pt_regs *regs; - if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) + if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI)) return handled; /* * First we pause the local counters, so that when we are locked -- 1.7.6 From alcooperx@gmail.com Fri Jul 13 22:46:12 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 22:46:42 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:3912 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903726Ab2GMUqM (ORCPT ); Fri, 13 Jul 2012 22:46:12 +0200 Received: from [10.9.200.131] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 13:45:12 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 13:45:56 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id CD7B49F9F5; Fri, 13 Jul 2012 13:45:55 -0700 (PDT) From: "Al Cooper" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org cc: "Al Cooper" Subject: [PATCH 3/5] MIPS: perf: Remove unnecessary #ifdef Date: Fri, 13 Jul 2012 16:44:52 -0400 Message-ID: <1342212294-23014-3-git-send-email-alcooperx@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> References: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C1E57523MK9973575-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33924 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1201 Lines: 34 The #ifdef for CONFIG_HW_PERF_EVENTS is not needed because the Makefile will only compile the module if this config option is set. This means that the code under #else would never be compiled. This may have been done to leave the original broken code around for reference, but the FIXME comment above the code already shows the broken code. Signed-off-by: Al Cooper --- arch/mips/kernel/perf_event_mipsxx.c | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 4ee1111..19253d7 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -139,13 +139,8 @@ static DEFINE_RWLOCK(pmuint_rwlock); * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. */ -#if defined(CONFIG_HW_PERF_EVENTS) #define vpe_id() (cpu_has_mipsmt_pertccounters ? \ 0 : smp_processor_id()) -#else -#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ - 0 : cpu_data[smp_processor_id()].vpe_id) -#endif /* Copied from op_model_mipsxx.c */ static unsigned int vpe_shift(void) -- 1.7.6 From alcooperx@gmail.com Fri Jul 13 22:46:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 22:47:09 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:1339 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903719Ab2GMUqS (ORCPT ); Fri, 13 Jul 2012 22:46:18 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 13:44:59 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 13:45:56 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 732999F9F6; Fri, 13 Jul 2012 13:45:56 -0700 (PDT) From: "Al Cooper" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org cc: "Al Cooper" Subject: [PATCH 4/5] MIPS: perf: Split the Kconfig option CONFIG_MIPS_MT_SMP Date: Fri, 13 Jul 2012 16:44:53 -0400 Message-ID: <1342212294-23014-4-git-send-email-alcooperx@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> References: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C1E57413NK5453383-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33925 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3237 Lines: 108 Split the Kconfig option CONFIG_MIPS_MT_SMP into CONFIG_MIPS_MT_SMP and CONFIG_MIPS_PERF_SHARED_TC_COUNTERS so some of the code used for performance counters that are shared between threads can be used for MIPS cores that are not MT_SMP. Signed-off-by: Al Cooper --- arch/mips/Kconfig | 4 ++++ arch/mips/kernel/perf_event_mipsxx.c | 16 ++++++++-------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 61e1459..bced05c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1898,6 +1898,7 @@ config MIPS_MT_SMP select SYS_SUPPORTS_SCHED_SMT if SMP select SYS_SUPPORTS_SMP select SMP_UP + select MIPS_PERF_SHARED_TC_COUNTERS help This is a kernel model which is known a VSMP but lately has been marketesed into SMVP. @@ -2248,6 +2249,9 @@ config NR_CPUS performance should round up your number of processors to the next power of two. +config MIPS_PERF_SHARED_TC_COUNTERS + bool + # # Timer Interrupt Frequency Configuration # diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 19253d7..cb21308 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -130,7 +130,7 @@ static struct mips_pmu mipspmu; #define M_PERFCTL_EVENT_MASK 0xfe0 -#ifdef CONFIG_MIPS_MT_SMP +#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS static int cpu_has_mipsmt_pertccounters; static DEFINE_RWLOCK(pmuint_rwlock); @@ -156,10 +156,10 @@ static unsigned int counters_total_to_per_cpu(unsigned int counters) return counters >> vpe_shift(); } -#else /* !CONFIG_MIPS_MT_SMP */ +#else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */ #define vpe_id() 0 -#endif /* CONFIG_MIPS_MT_SMP */ +#endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */ static void resume_local_counters(void); static void pause_local_counters(void); @@ -503,7 +503,7 @@ static void mipspmu_read(struct perf_event *event) static void mipspmu_enable(struct pmu *pmu) { -#ifdef CONFIG_MIPS_MT_SMP +#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS write_unlock(&pmuint_rwlock); #endif resume_local_counters(); @@ -523,7 +523,7 @@ static void mipspmu_enable(struct pmu *pmu) static void mipspmu_disable(struct pmu *pmu) { pause_local_counters(); -#ifdef CONFIG_MIPS_MT_SMP +#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS write_lock(&pmuint_rwlock); #endif } @@ -1163,7 +1163,7 @@ static int mipsxx_pmu_handle_shared_irq(void) * See also mipsxx_pmu_start(). */ pause_local_counters(); -#ifdef CONFIG_MIPS_MT_SMP +#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS read_lock(&pmuint_rwlock); #endif @@ -1195,7 +1195,7 @@ static int mipsxx_pmu_handle_shared_irq(void) if (handled == IRQ_HANDLED) irq_work_run(); -#ifdef CONFIG_MIPS_MT_SMP +#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS read_unlock(&pmuint_rwlock); #endif resume_local_counters(); @@ -1362,7 +1362,7 @@ init_hw_perf_events(void) return -ENODEV; } -#ifdef CONFIG_MIPS_MT_SMP +#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19); if (!cpu_has_mipsmt_pertccounters) counters = counters_total_to_per_cpu(counters); -- 1.7.6 From alcooperx@gmail.com Fri Jul 13 22:46:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 22:47:33 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:1344 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903727Ab2GMUqS (ORCPT ); Fri, 13 Jul 2012 22:46:18 +0200 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 13:45:03 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 13:45:57 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 29DDF9F9F5; Fri, 13 Jul 2012 13:45:57 -0700 (PDT) From: "Al Cooper" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org cc: "Al Cooper" Subject: [PATCH 5/5] MIPS: perf: Add perf functionality for BMIPS5000 Date: Fri, 13 Jul 2012 16:44:54 -0400 Message-ID: <1342212294-23014-5-git-send-email-alcooperx@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> References: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7C1E57453NK5453393-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33926 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6215 Lines: 196 Add hardware performance counter support to kernel "perf" code for BMIPS5000. The BMIPS5000 performance counters are similar to MIPS MTI cores, so the changes were mostly made in perf_event_mipsxx.c which is typically for MTI cores. Signed-off-by: Al Cooper --- arch/mips/kernel/perf_event_mipsxx.c | 103 +++++++++++++++++++++++++++++++++- 1 files changed, 102 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index cb21308..a9b995d 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -28,6 +28,8 @@ #include /* For perf_irq */ #define MIPS_MAX_HWEVENTS 4 +#define MIPS_TCS_PER_COUNTER 2 +#define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1) struct cpu_hw_events { /* Array of events on this cpu. */ @@ -108,13 +110,20 @@ static struct mips_pmu mipspmu; #define M_PERFCTL_INTERRUPT_ENABLE (1 << 4) #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) + +#ifdef CONFIG_CPU_BMIPS5000 +#define M_PERFCTL_MT_EN(filter) 0 +#else /* !CONFIG_CPU_BMIPS5000 */ #define M_PERFCTL_MT_EN(filter) ((filter) << 20) +#endif /* CONFIG_CPU_BMIPS5000 */ + #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) #define M_TC_EN_VPE M_PERFCTL_MT_EN(1) #define M_TC_EN_TC M_PERFCTL_MT_EN(2) #define M_PERFCTL_TCID(tcid) ((tcid) << 22) #define M_PERFCTL_WIDE (1 << 30) #define M_PERFCTL_MORE (1 << 31) +#define M_PERFCTL_TC (1 << 30) #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ M_PERFCTL_KERNEL | \ @@ -135,12 +144,17 @@ static int cpu_has_mipsmt_pertccounters; static DEFINE_RWLOCK(pmuint_rwlock); +#if defined(CONFIG_CPU_BMIPS5000) +#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ + 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK)) +#else /* * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. */ #define vpe_id() (cpu_has_mipsmt_pertccounters ? \ - 0 : smp_processor_id()) + 0 : smp_processor_id()) +#endif /* Copied from op_model_mipsxx.c */ static unsigned int vpe_shift(void) @@ -334,6 +348,11 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) (evt->config_base & M_PERFCTL_CONFIG_MASK) | /* Make sure interrupt enabled. */ M_PERFCTL_INTERRUPT_ENABLE; + if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) + /* enable the counter for the calling thread */ + cpuc->saved_ctrl[idx] |= + (1 << (12 + vpe_id())) | M_PERFCTL_TC; + /* * We do not actually let the counter run. Leave it until start(). */ @@ -814,6 +833,13 @@ static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, }; +static const struct mips_perf_event bmips5000_event_map + [PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T }, + [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, + [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, +}; + /* 24K/34K/1004K cores can share the same cache event map. */ static const struct mips_perf_event mipsxxcore_cache_map [PERF_COUNT_HW_CACHE_MAX] @@ -966,6 +992,65 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map }, }; +/* BMIPS5000 */ +static const struct mips_perf_event bmips5000_cache_map + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { +[C(L1D)] = { + /* + * Like some other architectures (e.g. ARM), the performance + * counters don't differentiate between read and write + * accesses/misses, so this isn't strictly correct, but it's the + * best we can do. Writes and reads get combined. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 12, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 12, CNTR_ODD, T }, + }, +}, +[C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 10, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 10, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T }, + /* + * Note that MIPS has only "hit" events countable for + * the prefetch operation. + */ + }, +}, +[C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, + [C(RESULT_MISS)] = { 28, CNTR_ODD, P }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, + [C(RESULT_MISS)] = { 28, CNTR_ODD, P }, + }, +}, +[C(BPU)] = { + /* Using the same code for *HW_BRANCH* */ + [C(OP_READ)] = { + [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, + }, +}, +}; + static const struct mips_perf_event octeon_cache_map [PERF_COUNT_HW_CACHE_MAX] @@ -1240,6 +1325,11 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47) #endif +/* BMIPS5000 */ +#define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \ + ((b) == 0 || (b) == 1) + + /* * User can use 0-255 raw events, where 0-127 for the events of even * counters, and 128-255 for odd counters. Note that bit 7 is used to @@ -1310,6 +1400,12 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) raw_event.range = T; #endif break; + case CPU_BMIPS5000: + if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id)) + raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; + else + raw_event.cntr_mask = + raw_id > 127 ? CNTR_ODD : CNTR_EVEN; } return &raw_event; @@ -1421,6 +1517,11 @@ init_hw_perf_events(void) mipspmu.cache_event_map = &octeon_cache_map; mipspmu.map_raw_event = octeon_pmu_map_raw_event; break; + case CPU_BMIPS5000: + mipspmu.name = "BMIPS5000"; + mipspmu.general_event_map = &bmips5000_event_map; + mipspmu.cache_event_map = &bmips5000_cache_map; + break; default: pr_cont("Either hardware does not support performance " "counters, or not yet implemented.\n"); -- 1.7.6 From alcooperx@gmail.com Fri Jul 13 22:46:20 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Jul 2012 22:47:59 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:4926 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903729Ab2GMUqU (ORCPT ); Fri, 13 Jul 2012 22:46:20 +0200 Received: from [10.9.200.133] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Fri, 13 Jul 2012 13:44:39 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Fri, 13 Jul 2012 13:45:15 -0700 Received: from stbsrv-and-2.and.broadcom.com ( stbsrv-and-2.and.broadcom.com [10.32.128.96]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 6C1859F9F5; Fri, 13 Jul 2012 13:45:54 -0700 (PDT) From: "Al Cooper" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org cc: "Al Cooper" Subject: [PATCH 1/5] MIPS: perf: Change the "mips_perf_event" table unsupported indicator. Date: Fri, 13 Jul 2012 16:44:50 -0400 Message-ID: <1342212294-23014-1-git-send-email-alcooperx@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: References: MIME-Version: 1.0 X-WSS-ID: 7C1E573D4989539313-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33927 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alcooperx@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10693 Lines: 324 Change the indicator from 0xffffffff in the "event_id" member to zero in the "cntr_mask" member. This removes the need to initialize entries that are unsupported. This also solves a problem where the number of entries in the table was increased based on a globel enum used for all platforms, but the new unsupported entries were not added for mips. This was leaving new table entries of all zeros that we not marked UNSUPPORTED. Signed-off-by: Al Cooper --- arch/mips/kernel/perf_event_mipsxx.c | 154 +--------------------------------- 1 files changed, 4 insertions(+), 150 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 2f28d3b..8451f04 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -78,7 +78,6 @@ struct mips_perf_event { static struct mips_perf_event raw_event; static DEFINE_MUTEX(raw_event_mutex); -#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff #define C(x) PERF_COUNT_HW_CACHE_##x struct mips_pmu { @@ -664,13 +663,10 @@ static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) static const struct mips_perf_event *mipspmu_map_general_event(int idx) { - const struct mips_perf_event *pev; - - pev = ((*mipspmu.general_event_map)[idx].event_id == - UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) : - &(*mipspmu.general_event_map)[idx]); - return pev; + if ((*mipspmu.general_event_map)[idx].cntr_mask == 0) + return ERR_PTR(-EOPNOTSUPP); + return &(*mipspmu.general_event_map)[idx]; } static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) @@ -695,7 +691,7 @@ static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) [cache_op] [cache_result]); - if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID) + if (pev->cntr_mask == 0) return ERR_PTR(-EOPNOTSUPP); return pev; @@ -800,11 +796,8 @@ static const struct mips_perf_event mipsxxcore_event_map [PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, - [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, - [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, - [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, }; /* 74K core has different branch event code. */ @@ -812,11 +805,8 @@ static const struct mips_perf_event mipsxx74Kcore_event_map [PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, - [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, - [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, - [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, }; static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { @@ -849,10 +839,6 @@ static const struct mips_perf_event mipsxxcore_cache_map [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(L1I)] = { [C(OP_READ)] = { @@ -869,7 +855,6 @@ static const struct mips_perf_event mipsxxcore_cache_map * Note that MIPS has only "hit" events countable for * the prefetch operation. */ - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, }, }, [C(LL)] = { @@ -881,10 +866,6 @@ static const struct mips_perf_event mipsxxcore_cache_map [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(DTLB)] = { [C(OP_READ)] = { @@ -895,10 +876,6 @@ static const struct mips_perf_event mipsxxcore_cache_map [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(ITLB)] = { [C(OP_READ)] = { @@ -909,10 +886,6 @@ static const struct mips_perf_event mipsxxcore_cache_map [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(BPU)] = { /* Using the same code for *HW_BRANCH* */ @@ -924,24 +897,6 @@ static const struct mips_perf_event mipsxxcore_cache_map [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, -}, -[C(NODE)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, }; @@ -965,10 +920,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(L1I)] = { [C(OP_READ)] = { @@ -985,7 +936,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map * Note that MIPS has only "hit" events countable for * the prefetch operation. */ - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, }, }, [C(LL)] = { @@ -997,25 +947,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, -}, -[C(DTLB)] = { - /* 74K core does not have specific DTLB events. */ - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(ITLB)] = { [C(OP_READ)] = { @@ -1026,10 +957,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(BPU)] = { /* Using the same code for *HW_BRANCH* */ @@ -1041,24 +968,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, -}, -[C(NODE)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, }; @@ -1074,39 +983,14 @@ static const struct mips_perf_event octeon_cache_map }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, }, }, [C(L1I)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, -}, -[C(LL)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, }, }, [C(DTLB)] = { @@ -1115,46 +999,16 @@ static const struct mips_perf_event octeon_cache_map * read and write. */ [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, [C(ITLB)] = { [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, -}, -[C(BPU)] = { - /* Using the same code for *HW_BRANCH* */ - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, - }, }, }; -- 1.7.6 From cernekee@gmail.com Sat Jul 14 21:11:10 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 14 Jul 2012 21:11:19 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:33853 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1903495Ab2GNTLK (ORCPT ); Sat, 14 Jul 2012 21:11:10 +0200 Received: (qmail 29864 invoked from network); 14 Jul 2012 19:11:05 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 14 Jul 2012 19:11:05 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 14 Jul 2012 12:11:05 -0700 From: Kevin Cernekee To: ralf@linux-mips.org Cc: , , , Subject: [PATCH V3 7/7] MIPS: BCM63XX: Create platform_device for USBD Date: Sat, 14 Jul 2012 12:01:09 -0700 Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 33928 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6075 Lines: 196 Signed-off-by: Kevin Cernekee --- arch/mips/bcm63xx/Makefile | 2 +- arch/mips/bcm63xx/boards/board_bcm963xx.c | 10 ++++ arch/mips/bcm63xx/dev-usb-usbd.c | 65 ++++++++++++++++++++++ .../asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h | 17 ++++++ .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 5 ++ 5 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 arch/mips/bcm63xx/dev-usb-usbd.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h V3: Jonas pointed out that one of the newer platforms does not use consecutive IRQ numbers for the IUDMA interrupts. So we will have to eventually pass in individual IRQ resources, instead of a range. Might as well do this up front to avoid hassles later. I will roll this into a new bundle: http://patchwork.linux-mips.org/bundle/cernekee/bcm63xx-udc-prereq-v3/ diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 833af72..9bbb30a 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,6 +1,6 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \ - dev-spi.o dev-uart.o dev-wdt.o + dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index feb0525..ea4ea77 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #define PFX "board_bcm963xx: " @@ -42,6 +43,12 @@ static struct board_info __initdata board_96328avng = { .has_uart0 = 1, .has_pci = 1, + .has_usbd = 0, + + .usbd = { + .use_fullspeed = 0, + .port_no = 0, + }, .leds = { { @@ -888,6 +895,9 @@ int __init board_register_devices(void) !board_get_mac_address(board.enet1.mac_addr)) bcm63xx_enet_register(1, &board.enet1); + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + if (board.has_dsp) bcm63xx_dsp_register(&board.dsp); diff --git a/arch/mips/bcm63xx/dev-usb-usbd.c b/arch/mips/bcm63xx/dev-usb-usbd.c new file mode 100644 index 0000000..508bd9d --- /dev/null +++ b/arch/mips/bcm63xx/dev-usb-usbd.c @@ -0,0 +1,65 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2012 Kevin Cernekee + * Copyright (C) 2012 Broadcom Corporation + */ + +#include +#include +#include +#include +#include +#include + +#define NUM_MMIO 2 +#define NUM_IRQ 7 + +static struct resource usbd_resources[NUM_MMIO + NUM_IRQ]; + +static u64 usbd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device bcm63xx_usbd_device = { + .name = "bcm63xx_udc", + .id = -1, + .num_resources = ARRAY_SIZE(usbd_resources), + .resource = usbd_resources, + .dev = { + .dma_mask = &usbd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +int __init bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd) +{ + const int irq_list[NUM_IRQ] = { IRQ_USBD, + IRQ_USBD_RXDMA0, IRQ_USBD_TXDMA0, + IRQ_USBD_RXDMA1, IRQ_USBD_TXDMA1, + IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 }; + int i; + + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) + return 0; + + usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD); + usbd_resources[0].end = usbd_resources[0].start + RSET_USBD_SIZE - 1; + usbd_resources[0].flags = IORESOURCE_MEM; + + usbd_resources[1].start = bcm63xx_regset_address(RSET_USBDMA); + usbd_resources[1].end = usbd_resources[1].start + RSET_USBDMA_SIZE - 1; + usbd_resources[1].flags = IORESOURCE_MEM; + + for (i = 0; i < NUM_IRQ; i++) { + struct resource *r = &usbd_resources[NUM_MMIO + i]; + + r->start = r->end = bcm63xx_get_irq_number(irq_list[i]); + r->flags = IORESOURCE_IRQ; + } + + platform_device_add_data(&bcm63xx_usbd_device, pd, sizeof(*pd)); + + return platform_device_register(&bcm63xx_usbd_device); +} diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h new file mode 100644 index 0000000..5d6d698 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h @@ -0,0 +1,17 @@ +#ifndef BCM63XX_DEV_USB_USBD_H_ +#define BCM63XX_DEV_USB_USBD_H_ + +/* + * usb device platform data + */ +struct bcm63xx_usbd_platform_data { + /* board can only support full speed (USB 1.1) */ + int use_fullspeed; + + /* 0-based port index, for chips with >1 USB PHY */ + int port_no; +}; + +int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd); + +#endif /* BCM63XX_DEV_USB_USBD_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h index 474daaa..b0dd4bb 100644 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -5,6 +5,7 @@ #include #include #include +#include #include /* @@ -44,6 +45,7 @@ struct board_info { unsigned int has_pccard:1; unsigned int has_ohci0:1; unsigned int has_ehci0:1; + unsigned int has_usbd:1; unsigned int has_dsp:1; unsigned int has_uart0:1; unsigned int has_uart1:1; @@ -52,6 +54,9 @@ struct board_info { struct bcm63xx_enet_platform_data enet0; struct bcm63xx_enet_platform_data enet1; + /* USB config */ + struct bcm63xx_usbd_platform_data usbd; + /* DSP config */ struct bcm63xx_dsp_platform_data dsp; -- 1.7.11.1 From vapier@gentoo.org Sun Jul 15 23:51:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Jul 2012 23:51:51 +0200 (CEST) Received: from smtp.gentoo.org ([140.211.166.183]:43199 "EHLO smtp.gentoo.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903414Ab2GOVvm (ORCPT ); Sun, 15 Jul 2012 23:51:42 +0200 Received: from vapier.localnet (localhost [127.0.0.1]) by smtp.gentoo.org (Postfix) with ESMTP id DF5001B4026; Sun, 15 Jul 2012 21:51:32 +0000 (UTC) From: Mike Frysinger Organization: wh0rd.org To: Joe Perches Subject: Re: [PATCH net-next 8/8] arch: Use eth_random_addr Date: Sun, 15 Jul 2012 17:51:29 -0400 User-Agent: KMail/1.13.7 (Linux/3.4.4; KDE/4.6.5; x86_64; ; ) Cc: David Miller , linux-kernel@vger.kernel.org, Johannes Berg , Mark Salter , Aurelien Jacquiot , Ralf Baechle , Jeff Dike , Richard Weinberger , uclinux-dist-devel@blackfin.uclinux.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net References: <1341968967.13724.23.camel@joe2Laptop> <14a91278564bb5a263c561a7f1bd10ea6386d90a.1342157022.git.joe@perches.com> In-Reply-To: <14a91278564bb5a263c561a7f1bd10ea6386d90a.1342157022.git.joe@perches.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart2984557.iEo3zAiUsd"; protocol="application/pgp-signature"; micalg=pgp-sha1 Content-Transfer-Encoding: 7bit Message-Id: <201207151751.32715.vapier@gentoo.org> X-archive-position: 33929 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vapier@gentoo.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1435 Lines: 39 --nextPart2984557.iEo3zAiUsd Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Friday 13 July 2012 01:33:12 Joe Perches wrote: > Convert the existing uses of random_ether_addr to > the new eth_random_addr. >=20 > Signed-off-by: Joe Perches > --- > arch/blackfin/mach-bf537/boards/stamp.c | 2 +- Acked-by: Mike Frysinger =2Dmike --nextPart2984557.iEo3zAiUsd Content-Type: application/pgp-signature; name=signature.asc Content-Description: This is a digitally signed message part. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.17 (GNU/Linux) iQIcBAABAgAGBQJQAztkAAoJEEFjO5/oN/WBdAEP/2504DMXVeLawf3QYL83Ybgk JdSLiVaZvOSvNibDqyWKFczikUDAKeJBBSUYdHht10Jo6By/EHzslxnK+y22yoE9 bN0Y9bI+7WpOjischyUg7iZzDEOx+sKWK0TooVv15wu68flAy8AY6PnpxKA2+//e x28CnNgrc0DbKqTg2FnDtzgZzkOpp1zX/Zdku+oJLBxo6VEBmgVZb8D5Aydoc5fD se81hN0yVigA85WfYDt1MaQhf6dc4rauPCEby1NGaB5EAdqy2p1wRsCLCGoIOZsV PIEQUfAiNWICF1kkO1QBhmotPTGSWPHo5Iw+DWuud0h7JK5/KQWtYwLcBmSGYlJ3 fRqzQaI9tmqcXW6sWXT1qPA2pHVGninJ9sJKehdy6dmK7nZqE5KV3B26ntRxUqFB tnSKUVaMPFJOlaBCEOi/eKZHEBeLHatev/qYqj7rF3dURWkhmTqDPJy59rgs+sHv /YitzpASRvl7M0mKm2RpNtO6/fYK5AO3yr7mfnZ4psXpKutEiMPkEZ13m4Fbp4mW tbh65jfkrOHuY02IvTXwqb9Cpl4dzYYEBCBCgD6p6mmXGcT0moBgCiDHF5vKbJMc +8eKfqsXOz+P3jf1cGGkoSgVZtWKkfm7TX4gfB3+xBXhVQe8k+ljAcNbGuC5M5Mj VoGCFnUMFIONUUj71+wZ =85OH -----END PGP SIGNATURE----- --nextPart2984557.iEo3zAiUsd-- From jayachandranc@netlogicmicro.com Mon Jul 16 12:03:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jul 2012 12:03:25 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:4610 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903526Ab2GPKDQ (ORCPT ); Mon, 16 Jul 2012 12:03:16 +0200 Received: from [10.9.200.131] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 16 Jul 2012 03:02:11 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Mon, 16 Jul 2012 03:02:55 -0700 Received: from hqcas01.netlogicmicro.com (unknown [10.65.50.14]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id E4C6A9FA01; Mon, 16 Jul 2012 03:02:52 -0700 (PDT) Received: from jc-virtual-machine.netlogicmicro.com (10.7.2.153) by hqcas01.netlogicmicro.com (10.65.50.14) with Microsoft SMTP Server id 14.1.339.1; Mon, 16 Jul 2012 03:02:52 -0700 From: "Jayachandran C" To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Florian Fainelli" , "Jayachandran C" Subject: [PATCH UPDATED 06/12] MIPS: Netlogic: early console fix Date: Mon, 16 Jul 2012 15:33:37 +0530 Message-ID: <1342433017-24485-1-git-send-email-jayachandranc@netlogicmicro.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <2602396.OWAlsVeLic@flexo> References: <2602396.OWAlsVeLic@flexo> MIME-Version: 1.0 X-Originating-IP: [10.7.2.153] X-WSS-ID: 7C1D39293MK10332603-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 33930 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 871 Lines: 28 In prom_putchar(), wait for just the TX empty bit to clear in the UART LSR. Signed-off-by: Jayachandran C --- [Updated to use UART_LSR_THRE instead of 0x20, as suggested by Florian Fainelli ] arch/mips/netlogic/common/earlycons.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c index f193f7b..53b200a5 100644 --- a/arch/mips/netlogic/common/earlycons.c +++ b/arch/mips/netlogic/common/earlycons.c @@ -54,7 +54,7 @@ void prom_putchar(char c) #elif defined(CONFIG_CPU_XLR) uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); #endif - while (nlm_read_reg(uartbase, UART_LSR) == 0) + while ((nlm_read_reg(uartbase, UART_LSR) & UART_LSR_THRE) == 0) ; nlm_write_reg(uartbase, UART_TX, c); } -- 1.7.9.5 From balbi@ti.com Mon Jul 16 12:17:37 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jul 2012 12:17:42 +0200 (CEST) Received: from na3sys009aog122.obsmtp.com ([74.125.149.147]:60366 "EHLO na3sys009aog122.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903532Ab2GPKRh (ORCPT ); Mon, 16 Jul 2012 12:17:37 +0200 Received: from mail-lb0-f171.google.com ([209.85.217.171]) (using TLSv1) by na3sys009aob122.postini.com ([74.125.148.12]) with SMTP ID DSNKUAPqPpZIugspY9/IFfme6w2htcl/FL+y@postini.com; Mon, 16 Jul 2012 03:17:36 PDT Received: by lbom4 with SMTP id m4so10012606lbo.30 for ; Mon, 16 Jul 2012 03:17:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=/Uo6LuP+FGiibM/GDZc1+nkVkUVMwsxgVERPna4Bpiw=; b=OP/KDvvCpzWNFZYXu0yeTmfaXn7mkd+zZyQ2prZnTR0vOvIgpAXj7neGUH4U3ZDXDz QyMu3gghYnmI9PGajz1SGHARcWdcynxcecENNeEAsG4Xd9+P+5gDOexlObIlOnipb1k2 z0Raez4PdWjDfhl1/F9uEfCBjLnPeIbdq3ejibplfmMC3w1mKG//1jr+7TsVluvsbjZg DnFUPbqC666p7hk+6ZzFOzCGofGWTHfPkqpO55h6ROgaR6vJzb72++uRur3TBj+RXZIz YwwOgkGd8D7DcdCJnSDgxPzkN4c3ABevlLoBrTDJffU91QAxg/XZKxMgfiOuHVNyhQVs Po+g== Received: by 10.112.100.234 with SMTP id fb10mr5053663lbb.12.1342433853229; Mon, 16 Jul 2012 03:17:33 -0700 (PDT) Received: from localhost (cs78217178.pp.htv.fi. [62.78.217.178]) by mx.google.com with ESMTPS id k4sm3399886lbb.12.2012.07.16.03.17.31 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 16 Jul 2012 03:17:32 -0700 (PDT) Date: Mon, 16 Jul 2012 13:14:38 +0300 From: Felipe Balbi To: Joe Perches Cc: David Miller , netdev@vger.kernel.org, linux-usb@vger.kernel.org, wimax@linuxwimax.org, linux-wireless@vger.kernel.org, users@rt2x00.serialmonkey.com, linux-s390@vger.kernel.org, Johannes Berg , uclinux-dist-devel@blackfin.uclinux.org, linux-kernel@vger.kernel.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, e1000-devel@lists.sourceforge.net Subject: Re: [PATCH net-next 0/8] etherdevice: Rename random_ether_addr to eth_random_addr Message-ID: <20120716101437.GC22638@arwen.pp.htv.fi> Reply-To: balbi@ti.com References: <1341968967.13724.23.camel@joe2Laptop> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="KN5l+BnMqAQyZLvT" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQlI281oS/5cegB+ZPeeUZzNPB3MPYWG+M71Nxn1Qr0zHcUuUk6ILnKXg2Eu0+iIKOiSr6kh X-archive-position: 33931 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: balbi@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4725 Lines: 102 --KN5l+BnMqAQyZLvT Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jul 12, 2012 at 10:33:04PM -0700, Joe Perches wrote: > net-next commit ad7eee98be ("etherdevice: introduce eth_broadcast_addr") > added a new style API. Rename random_ether_addr to eth_random_addr to > create some API symmetry. >=20 > Joe Perches (8): > etherdevice: Rename random_ether_addr to eth_random_addr if you're really renaming the function, then this patch alone will break all of the below users. That should all be a single patch, I'm afraid. > ethernet: Use eth_random_addr > net: usb: Use eth_random_addr > wireless: Use eth_random_addr > drivers/net: Use eth_random_addr > s390: Use eth_random_addr > usb: Use eth_random_addr > arch: Use eth_random_addr >=20 > arch/blackfin/mach-bf537/boards/stamp.c | 2 +- > arch/c6x/kernel/soc.c | 2 +- > arch/mips/ar7/platform.c | 4 ++-- > arch/mips/powertv/powertv_setup.c | 6 +++--- > arch/um/drivers/net_kern.c | 2 +- > drivers/net/ethernet/atheros/atl1c/atl1c_hw.c | 2 +- > drivers/net/ethernet/atheros/atlx/atl1.c | 2 +- > drivers/net/ethernet/atheros/atlx/atl2.c | 2 +- > drivers/net/ethernet/ethoc.c | 2 +- > drivers/net/ethernet/intel/igb/igb_main.c | 4 ++-- > drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c | 2 +- > drivers/net/ethernet/lantiq_etop.c | 2 +- > drivers/net/ethernet/micrel/ks8851.c | 2 +- > drivers/net/ethernet/micrel/ks8851_mll.c | 2 +- > drivers/net/ethernet/smsc/smsc911x.c | 2 +- > drivers/net/ethernet/ti/cpsw.c | 2 +- > drivers/net/ethernet/tile/tilegx.c | 2 +- > drivers/net/ethernet/wiznet/w5100.c | 2 +- > drivers/net/ethernet/wiznet/w5300.c | 2 +- > drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 2 +- > drivers/net/tun.c | 2 +- > drivers/net/usb/smsc75xx.c | 2 +- > drivers/net/usb/smsc95xx.c | 2 +- > drivers/net/usb/usbnet.c | 2 +- > drivers/net/wimax/i2400m/driver.c | 2 +- > drivers/net/wireless/adm8211.c | 2 +- > drivers/net/wireless/p54/eeprom.c | 2 +- > drivers/net/wireless/rt2x00/rt2400pci.c | 2 +- > drivers/net/wireless/rt2x00/rt2500pci.c | 2 +- > drivers/net/wireless/rt2x00/rt2500usb.c | 2 +- > drivers/net/wireless/rt2x00/rt2800lib.c | 2 +- > drivers/net/wireless/rt2x00/rt61pci.c | 2 +- > drivers/net/wireless/rt2x00/rt73usb.c | 2 +- > drivers/net/wireless/rtl818x/rtl8180/dev.c | 2 +- > drivers/net/wireless/rtl818x/rtl8187/dev.c | 2 +- > drivers/s390/net/qeth_l2_main.c | 2 +- > drivers/s390/net/qeth_l3_main.c | 2 +- > drivers/usb/atm/xusbatm.c | 4 ++-- > drivers/usb/gadget/u_ether.c | 2 +- > include/linux/etherdevice.h | 14 ++++++++------ > 40 files changed, 52 insertions(+), 50 deletions(-) >=20 > --=20 > 1.7.8.111.gad25c.dirty >=20 > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ --=20 balbi --KN5l+BnMqAQyZLvT Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBAgAGBQJQA+mNAAoJEIaOsuA1yqRE+ksP/Alli7QgsqKkod+QSJZRmYS6 wJJT+g2ZqoMatSweM3ZCXzeGMBspr3j0TtRqcLxugkaNullhyfqLmyXAW3FQIboF Aw40vVRTZSjTmecHJB53QVMZ+u+lGKu7u5YAvF+ixof9AXZYPppTEghxHdCtdKou SpkRsOgw+DwgftlGma27DAiAGTSuV59c74NiOmpCazv2w/TSNF63AkNEfyUH9Cqv nT7M89z7BJDGoUKKULpN/wKlCl6qWNEtOWShjAmkmhYJBnsIMGEX+w5/4RO8ABOK p82KlsEl0+Ze5dZGJ1sy64Cs9a50dqIrDcPHtnKwACZqwj9SI6uQSpa9spX5qlqA 64CQzBaudcBcLKzeXlzvOfZmbVbPIXd/wtFXlbYCKGd2Gl+3F211yL7fzd++3RDR 0bIm5vjUjf/c6830awVc6JRUtnLsEzdNnwpNPlm9oCSu5p7TwEGQkhblI7TyYRNV /Xl5sPiSmIlHfV073zXco8CyuXdHnAUdY7Ujg98KXcXds7AxDd3R4wRa9KykGyVf Vb4TZ5Rk2bXaFOnfqAT2+aGOGyox/504ud1KVdBvLFc4VLkv4/DN1syiNjDtORu3 Ls+uNzP85uB5c5p49fvM56Mwjzfql47PRKi86OdPebfFCKmLGoVi8k2aHioTvCMO 7qp9s0cYaXJREqb3n+Yb =EBK7 -----END PGP SIGNATURE----- --KN5l+BnMqAQyZLvT-- From davem@davemloft.net Mon Jul 16 12:29:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jul 2012 12:29:15 +0200 (CEST) Received: from shards.monkeyblade.net ([149.20.54.216]:33926 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903548Ab2GPK3J (ORCPT ); Mon, 16 Jul 2012 12:29:09 +0200 Received: from localhost (74-93-104-98-Washington.hfc.comcastbusiness.net [74.93.104.98]) by shards.monkeyblade.net (Postfix) with ESMTPSA id 99A255823BF; Mon, 16 Jul 2012 03:29:05 -0700 (PDT) Date: Mon, 16 Jul 2012 03:29:01 -0700 (PDT) Message-Id: <20120716.032901.1657058688119342783.davem@davemloft.net> To: balbi@ti.com Cc: joe@perches.com, netdev@vger.kernel.org, linux-usb@vger.kernel.org, wimax@linuxwimax.org, linux-wireless@vger.kernel.org, users@rt2x00.serialmonkey.com, linux-s390@vger.kernel.org, johannes@sipsolutions.net, uclinux-dist-devel@blackfin.uclinux.org, linux-kernel@vger.kernel.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, e1000-devel@lists.sourceforge.net Subject: Re: [PATCH net-next 0/8] etherdevice: Rename random_ether_addr to eth_random_addr From: David Miller In-Reply-To: <20120716101437.GC22638@arwen.pp.htv.fi> References: <1341968967.13724.23.camel@joe2Laptop> <20120716101437.GC22638@arwen.pp.htv.fi> X-Mailer: Mew version 6.5 on Emacs 24.0.97 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-archive-position: 33932 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 422 Lines: 11 From: Felipe Balbi Date: Mon, 16 Jul 2012 13:14:38 +0300 > if you're really renaming the function, then this patch alone will break > all of the below users. That should all be a single patch, I'm afraid. It would help if you actually read his patches before saying what they might or might not do. He provides a macro in the first patch that provides the old name, and this will get removed at the end. From balbi@ti.com Mon Jul 16 13:15:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jul 2012 13:15:21 +0200 (CEST) Received: from na3sys009aog108.obsmtp.com ([74.125.149.199]:53443 "EHLO na3sys009aog108.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903548Ab2GPLPR (ORCPT ); Mon, 16 Jul 2012 13:15:17 +0200 Received: from mail-lb0-f174.google.com ([209.85.217.174]) (using TLSv1) by na3sys009aob108.postini.com ([74.125.148.12]) with SMTP ID DSNKUAP3wsB6RbkrCEeJ6zWZedPpDvauIVCl@postini.com; Mon, 16 Jul 2012 04:15:16 PDT Received: by lbbgm6 with SMTP id gm6so8554746lbb.19 for ; Mon, 16 Jul 2012 04:15:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=4Nxc50hDjmlE0B9OFABYwNOKRjpH2v3yEdfjJQGgbeg=; b=DVTB146YjkmLTMxVrTSOLF3PGO/JJoM/dYKS1WkLDTDAQth1akHYKrPrrF+5qZp/FE OWbBtcVdij3RXCkHF+Ch7M32xk4ah++dtPq3KLaFOcsmMAW6f0vdZ8hb28Qf7oXBCiIx cNd8+gQM4di0qhslfEG0G7IgJVaSRgsBomAJlKRX79dcHaGiC7GUm6xY+/tyT3ikil0W EF812ztbaDJQXGwW4VNkFqAJUr7QP+GTZMMa5I719vk/C05b5QkPQfDvllKNmSL70Aj8 b8j6/SluLVtWLB2QmfmPJtCNEhH6qe2yan085BkSR6mZJRExbMrpeHQEEUjI5NgUCFat pceg== Received: by 10.112.49.100 with SMTP id t4mr5147527lbn.10.1342437313388; Mon, 16 Jul 2012 04:15:13 -0700 (PDT) Received: from localhost (cs78217178.pp.htv.fi. [62.78.217.178]) by mx.google.com with ESMTPS id k4sm3432692lbb.12.2012.07.16.04.15.11 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 16 Jul 2012 04:15:12 -0700 (PDT) Date: Mon, 16 Jul 2012 14:12:19 +0300 From: Felipe Balbi To: David Miller Cc: balbi@ti.com, joe@perches.com, netdev@vger.kernel.org, linux-usb@vger.kernel.org, wimax@linuxwimax.org, linux-wireless@vger.kernel.org, users@rt2x00.serialmonkey.com, linux-s390@vger.kernel.org, johannes@sipsolutions.net, uclinux-dist-devel@blackfin.uclinux.org, linux-kernel@vger.kernel.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, e1000-devel@lists.sourceforge.net Subject: Re: [PATCH net-next 0/8] etherdevice: Rename random_ether_addr to eth_random_addr Message-ID: <20120716111218.GA4913@arwen.pp.htv.fi> Reply-To: balbi@ti.com References: <1341968967.13724.23.camel@joe2Laptop> <20120716101437.GC22638@arwen.pp.htv.fi> <20120716.032901.1657058688119342783.davem@davemloft.net> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="dDRMvlgZJXvWKvBx" Content-Disposition: inline In-Reply-To: <20120716.032901.1657058688119342783.davem@davemloft.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQnMJ33PKAEcNd0WYHeSC+yllUkh+96DZC7WFKCCIw/39uWbsz+bbMSloN/xFw/MMEV2/syb X-archive-position: 33933 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: balbi@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1888 Lines: 54 --dDRMvlgZJXvWKvBx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Mon, Jul 16, 2012 at 03:29:01AM -0700, David Miller wrote: > From: Felipe Balbi > Date: Mon, 16 Jul 2012 13:14:38 +0300 >=20 > > if you're really renaming the function, then this patch alone will break > > all of the below users. That should all be a single patch, I'm afraid. >=20 > It would help if you actually read his patches before saying what they > might or might not do. >=20 > He provides a macro in the first patch that provides the old name, > and this will get removed at the end. that's why I put an "if" there. The subject was misleading and I really couldn't bother going search for the patch on the mail archives. Anyway, if nothing will be broken then for drivers/usb/gadget/: Acked-by: Felipe Balbi --=20 balbi --dDRMvlgZJXvWKvBx Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBAgAGBQJQA/cSAAoJEIaOsuA1yqRECgMP/11LX6hhvLwodK9V12dXWUI8 n4rD9q+ipGtPf/S551hE9jkkp4yCPUromRhx5hgbmaDJ23ZbqHpRR3fNNHSGpH1W xSdS7vdtqWxpt7LUqczpgbjstrFqDYEt5idkuUsQ3QRZEZ5NgeTigWYEiIpf6uPQ qy1YgtmJZlPJKskiH+8YdDGHgL3vI8iypfk7GBVwBYp7ozl7LyqM62mpbSMPxQGr uAx/FEFC2o31p/B81WkGzFiq2vc7oy+c+IvfWre+mI7X6+AyiAGR719CI0V7umQD iMK/yrncbbuBCEsCdLN446kkRocFYX/IDiykTYHc2/V4WDxJO8wYH0gTSdMJOxDG fsxrUS9RUAb0vyGRaUvTMHKhQdo5ijBhkWHvoL7jjyqaCEvYqarRDhqZq6uW6t9E AVNxmUriH7Iflw1BiRJk03IO3/dFOY2b5yCTmSwklNdXuuL52biuRe3PIK1mDli9 F2sr5xj/VuT66HNTbOI4tFH53yhakkYjSffVK8xs2GuBvsTr1RiLBQT2YK3yU77Z Pk798mAkIhUhlZh998YRlJHtqs9JkyeHIHTuSt7Zj/FJmWaDLfjMAa18knsuFAFg tYnpnP3mtGE12FeXQ0rGcnqrsqWjIy8NKnNjf9DqNc/DwmjnyL/UMsN0J+m9/uaF kyn8nJ4loji/LHjMvX2g =BzOs -----END PGP SIGNATURE----- --dDRMvlgZJXvWKvBx-- From davem@davemloft.net Mon Jul 16 13:17:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jul 2012 13:17:33 +0200 (CEST) Received: from shards.monkeyblade.net ([149.20.54.216]:34302 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903556Ab2GPLR3 (ORCPT ); Mon, 16 Jul 2012 13:17:29 +0200 Received: from localhost (74-93-104-98-Washington.hfc.comcastbusiness.net [74.93.104.98]) by shards.monkeyblade.net (Postfix) with ESMTPSA id 1D550582423; Mon, 16 Jul 2012 04:17:29 -0700 (PDT) Date: Mon, 16 Jul 2012 04:17:23 -0700 (PDT) Message-Id: <20120716.041723.349766690942695703.davem@davemloft.net> To: balbi@ti.com Cc: joe@perches.com, netdev@vger.kernel.org, linux-usb@vger.kernel.org, wimax@linuxwimax.org, linux-wireless@vger.kernel.org, users@rt2x00.serialmonkey.com, linux-s390@vger.kernel.org, johannes@sipsolutions.net, uclinux-dist-devel@blackfin.uclinux.org, linux-kernel@vger.kernel.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, e1000-devel@lists.sourceforge.net Subject: Re: [PATCH net-next 0/8] etherdevice: Rename random_ether_addr to eth_random_addr From: David Miller In-Reply-To: <20120716111218.GA4913@arwen.pp.htv.fi> References: <20120716101437.GC22638@arwen.pp.htv.fi> <20120716.032901.1657058688119342783.davem@davemloft.net> <20120716111218.GA4913@arwen.pp.htv.fi> X-Mailer: Mew version 6.5 on Emacs 24.0.97 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-archive-position: 33934 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 274 Lines: 10 From: Felipe Balbi Date: Mon, 16 Jul 2012 14:12:19 +0300 > Acked-by: Felipe Balbi You need to provide this in a reply to the patch you actually want to ACK, so that the patch tracking system attaches your ACK to the proper patch. Thank you. From msalter@redhat.com Mon Jul 16 14:57:23 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jul 2012 14:57:29 +0200 (CEST) Received: from mx1.redhat.com ([209.132.183.28]:60293 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903532Ab2GPM5X (ORCPT ); Mon, 16 Jul 2012 14:57:23 +0200 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q6GCufFZ011115 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 16 Jul 2012 08:56:41 -0400 Received: from [10.3.113.83] (ovpn-113-83.phx2.redhat.com [10.3.113.83]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q6GCuabC023828; Mon, 16 Jul 2012 08:56:37 -0400 Subject: Re: [PATCH net-next 8/8] arch: Use eth_random_addr From: Mark Salter To: Joe Perches Cc: David Miller , linux-kernel@vger.kernel.org, Johannes Berg , Mike Frysinger , Aurelien Jacquiot , Ralf Baechle , Jeff Dike , Richard Weinberger , uclinux-dist-devel@blackfin.uclinux.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net Date: Mon, 16 Jul 2012 08:56:36 -0400 In-Reply-To: <14a91278564bb5a263c561a7f1bd10ea6386d90a.1342157022.git.joe@perches.com> References: <1341968967.13724.23.camel@joe2Laptop> <14a91278564bb5a263c561a7f1bd10ea6386d90a.1342157022.git.joe@perches.com> Organization: Red Hat, Inc Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-ID: <1342443401.2880.2.camel@deneb.redhat.com> Mime-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-archive-position: 33935 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: msalter@redhat.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 341 Lines: 12 On Thu, 2012-07-12 at 22:33 -0700, Joe Perches wrote: > Convert the existing uses of random_ether_addr to > the new eth_random_addr. > > Signed-off-by: Joe Perches > --- > arch/blackfin/mach-bf537/boards/stamp.c | 2 +- > arch/c6x/kernel/soc.c | 2 +- Acked-by: Mark Salter From ralf@linux-mips.org Mon Jul 16 16:20:21 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jul 2012 16:20:29 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:46140 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903725Ab2GPOUV (ORCPT ); Mon, 16 Jul 2012 16:20:21 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6GEKAkC012991; Mon, 16 Jul 2012 16:20:10 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6GEK0EF012958; Mon, 16 Jul 2012 16:20:00 +0200 Date: Mon, 16 Jul 2012 16:20:00 +0200 From: Ralf Baechle To: Joe Perches Cc: David Miller , linux-kernel@vger.kernel.org, Johannes Berg , Mike Frysinger , Mark Salter , Aurelien Jacquiot , Jeff Dike , Richard Weinberger , uclinux-dist-devel@blackfin.uclinux.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net Subject: Re: [PATCH net-next 8/8] arch: Use eth_random_addr Message-ID: <20120716141959.GA12338@linux-mips.org> References: <14a91278564bb5a263c561a7f1bd10ea6386d90a.1342157022.git.joe@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <14a91278564bb5a263c561a7f1bd10ea6386d90a.1342157022.git.joe@perches.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33936 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 583 Lines: 19 On Thu, Jul 12, 2012 at 10:33:12PM -0700, Joe Perches wrote: > Convert the existing uses of random_ether_addr to > the new eth_random_addr. > > Signed-off-by: Joe Perches > --- > arch/blackfin/mach-bf537/boards/stamp.c | 2 +- > arch/c6x/kernel/soc.c | 2 +- > arch/mips/ar7/platform.c | 4 ++-- > arch/mips/powertv/powertv_setup.c | 6 +++--- > arch/um/drivers/net_kern.c | 2 +- > 5 files changed, 8 insertions(+), 8 deletions(-) Acked-by: Ralf Baechle Thanks, Ralf From geert@linux-m68k.org Mon Jul 16 21:27:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Jul 2012 21:27:25 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:63492 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903549Ab2GPT1S (ORCPT ); Mon, 16 Jul 2012 21:27:18 +0200 Received: by yenr9 with SMTP id r9so5834428yen.36 for ; Mon, 16 Jul 2012 12:27:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=RXDeBqqf4ud4rDmEXMl0crGcBy7+YyIbTm8EiwtuzEc=; b=jU1e99sp+SI2KFrEz0mpfay+IsZfP3JFcWdc3O4T68eeegNtf0menKsXkDoiloqAMv ulWuI166AhOsxV3UfiOAb3noKzBrYoT8+uPDE0+9uasO2qZY01Vnw8gpYyN0kRPv8Eot lYwHL50ACQbkn1aetrLWqc8bbVIYQLkzvzWVa1hvI6M4MgLRSKxOXrPZEstbuDKhWF0n OVJoRTZrqGImhtWq5BrmkiQYe0lhBDbGGz/PS9PzvRva5aAZYiQL89JGg+vCGjCFgS/k kzl4NreAEGsEW1akUGsvig62blxsn7cr6vwB9O8ErSJgT9aN7iFKVTtG5Jdk4DkK+7p1 M3jA== MIME-Version: 1.0 Received: by 10.50.135.1 with SMTP id po1mr5981152igb.67.1342466832162; Mon, 16 Jul 2012 12:27:12 -0700 (PDT) Received: by 10.231.135.1 with HTTP; Mon, 16 Jul 2012 12:27:12 -0700 (PDT) In-Reply-To: <4FE4B13E.10709@caviumnetworks.com> References: <1339962373-3224-1-git-send-email-geert@linux-m68k.org> <20120620152759.2caceb8c.yuasa@linux-mips.org> <20120620161249.GB29196@linux-mips.org> <4FE4B13E.10709@caviumnetworks.com> Date: Mon, 16 Jul 2012 21:27:12 +0200 X-Google-Sender-Auth: 3zRs9Ed7_W2rWDcGqS4JdQG_7r4 Message-ID: Subject: Re: [PATCH] MIPS: fix bug.h MIPS build regression From: Geert Uytterhoeven To: David Daney Cc: Ralf Baechle , Yoichi Yuasa , Paul Mundt , linux-kernel@vger.kernel.org, Linuxppc-dev , Linux MIPS Mailing List , Linux-sh list , Chris Zankel Content-Type: text/plain; charset=UTF-8 X-archive-position: 33937 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 814 Lines: 29 On Fri, Jun 22, 2012 at 7:54 PM, David Daney wrote: > On 06/20/2012 09:12 AM, Ralf Baechle wrote: >> >> On Wed, Jun 20, 2012 at 03:27:59PM +0900, Yoichi Yuasa wrote: >> >>> Commit: 3777808873b0c49c5cf27e44c948dfb02675d578 breaks all MIPS builds. >> >> >> Thanks, fix applied. >> > > Where was it applied? > > It doesn't show up in linux-next for 20120622, which is where it is needed. It's also desperately needed in mainline for 3.5. Ralf? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From davem@davemloft.net Tue Jul 17 07:39:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Jul 2012 07:39:59 +0200 (CEST) Received: from shards.monkeyblade.net ([149.20.54.216]:43723 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903419Ab2GQFjx (ORCPT ); Tue, 17 Jul 2012 07:39:53 +0200 Received: from localhost (74-93-104-98-Washington.hfc.comcastbusiness.net [74.93.104.98]) by shards.monkeyblade.net (Postfix) with ESMTPSA id 2268B583610; Mon, 16 Jul 2012 22:39:50 -0700 (PDT) Date: Mon, 16 Jul 2012 22:39:47 -0700 (PDT) Message-Id: <20120716.223947.963699777040428903.davem@davemloft.net> To: joe@perches.com Cc: netdev@vger.kernel.org, linux-usb@vger.kernel.org, wimax@linuxwimax.org, linux-wireless@vger.kernel.org, users@rt2x00.serialmonkey.com, linux-s390@vger.kernel.org, johannes@sipsolutions.net, uclinux-dist-devel@blackfin.uclinux.org, linux-kernel@vger.kernel.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, e1000-devel@lists.sourceforge.net Subject: Re: [PATCH net-next 0/8] etherdevice: Rename random_ether_addr to eth_random_addr From: David Miller In-Reply-To: References: <1341968967.13724.23.camel@joe2Laptop> X-Mailer: Mew version 6.5 on Emacs 24.0.97 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-archive-position: 33938 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 280 Lines: 8 From: Joe Perches Date: Thu, 12 Jul 2012 22:33:04 -0700 > net-next commit ad7eee98be ("etherdevice: introduce eth_broadcast_addr") > added a new style API. Rename random_ether_addr to eth_random_addr to > create some API symmetry. Series applied, thanks Joe. From geert@linux-m68k.org Wed Jul 18 10:35:53 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Jul 2012 10:36:00 +0200 (CEST) Received: from mail-gg0-f177.google.com ([209.85.161.177]:60423 "EHLO mail-gg0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903472Ab2GRIfx (ORCPT ); Wed, 18 Jul 2012 10:35:53 +0200 Received: by ggcs5 with SMTP id s5so1400315ggc.36 for ; Wed, 18 Jul 2012 01:35:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=na1NQxt2XM3cbFALyGTwx0Fe8cwqocyn6p7xm1O1XRI=; b=YEU7FF1QoCDwcxDXySSxOtkEsxGNdiolObCSyMBkwDsMUP00Fs0iDaRlVD3/0pU+u6 QZaS5EieMlW5n1AKKH0/WrpfemQM813Vny+IIiF+bWf18TL+0tysO0sQcrXYdb3WZKYB WehB5hoKZhZxriOBjIIFSSUivSF5WiQwTnoY+VXo2/gU6X6fv9EFirjpy6Y7kjQKy6Hc 1WzCsAsZDT2gIPr3Iw0wyKlII1ci1QaMVAK8iHwkgqB3A3L0vryItt+hbGtPqf1NBjQw 36OMf73naawoIZSm1be1yxP9aCTTMmeXE1kBWuz0LXwTjynMCWbJdt3RlGWYc4lYc0Rn VhOA== MIME-Version: 1.0 Received: by 10.50.135.1 with SMTP id po1mr1108998igb.67.1342600546627; Wed, 18 Jul 2012 01:35:46 -0700 (PDT) Received: by 10.231.135.1 with HTTP; Wed, 18 Jul 2012 01:35:46 -0700 (PDT) In-Reply-To: References: <1339962373-3224-1-git-send-email-geert@linux-m68k.org> <20120620152759.2caceb8c.yuasa@linux-mips.org> <20120620161249.GB29196@linux-mips.org> <4FE4B13E.10709@caviumnetworks.com> Date: Wed, 18 Jul 2012 10:35:46 +0200 X-Google-Sender-Auth: Lzm0-Z199Mg_WHoF2uOaDRblHeE Message-ID: Subject: Re: [PATCH] MIPS: fix bug.h MIPS build regression From: Geert Uytterhoeven To: David Daney , Andrew Morton Cc: Ralf Baechle , Yoichi Yuasa , Paul Mundt , linux-kernel@vger.kernel.org, Linuxppc-dev , Linux MIPS Mailing List , Linux-sh list , Chris Zankel Content-Type: text/plain; charset=UTF-8 X-archive-position: 33939 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 963 Lines: 33 On Mon, Jul 16, 2012 at 9:27 PM, Geert Uytterhoeven wrote: > On Fri, Jun 22, 2012 at 7:54 PM, David Daney wrote: >> On 06/20/2012 09:12 AM, Ralf Baechle wrote: >>> >>> On Wed, Jun 20, 2012 at 03:27:59PM +0900, Yoichi Yuasa wrote: >>> >>>> Commit: 3777808873b0c49c5cf27e44c948dfb02675d578 breaks all MIPS builds. >>> >>> >>> Thanks, fix applied. >>> >> >> Where was it applied? >> >> It doesn't show up in linux-next for 20120622, which is where it is needed. > > It's also desperately needed in mainline for 3.5. > > Ralf? Andrew? This prevents any green MIPS builds. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From akpm@linux-foundation.org Wed Jul 18 23:07:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Jul 2012 23:07:56 +0200 (CEST) Received: from mail.linuxfoundation.org ([140.211.169.12]:54930 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903605Ab2GRVHr (ORCPT ); Wed, 18 Jul 2012 23:07:47 +0200 Received: from akpm.mtv.corp.google.com (216-239-45-4.google.com [216.239.45.4]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id 4B1FC88A; Wed, 18 Jul 2012 21:07:39 +0000 (UTC) Date: Wed, 18 Jul 2012 14:07:38 -0700 From: Andrew Morton To: Geert Uytterhoeven Cc: David Daney , Ralf Baechle , Yoichi Yuasa , Paul Mundt , linux-kernel@vger.kernel.org, Linuxppc-dev , Linux MIPS Mailing List , Linux-sh list , Chris Zankel Subject: Re: [PATCH] MIPS: fix bug.h MIPS build regression Message-Id: <20120718140738.ca6f8f5a.akpm@linux-foundation.org> In-Reply-To: References: <1339962373-3224-1-git-send-email-geert@linux-m68k.org> <20120620152759.2caceb8c.yuasa@linux-mips.org> <20120620161249.GB29196@linux-mips.org> <4FE4B13E.10709@caviumnetworks.com> X-Mailer: Sylpheed 3.0.2 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 33940 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 863 Lines: 30 On Wed, 18 Jul 2012 10:35:46 +0200 Geert Uytterhoeven wrote: > On Mon, Jul 16, 2012 at 9:27 PM, Geert Uytterhoeven > wrote: > > On Fri, Jun 22, 2012 at 7:54 PM, David Daney wrote: > >> On 06/20/2012 09:12 AM, Ralf Baechle wrote: > >>> > >>> On Wed, Jun 20, 2012 at 03:27:59PM +0900, Yoichi Yuasa wrote: > >>> > >>>> Commit: 3777808873b0c49c5cf27e44c948dfb02675d578 breaks all MIPS builds. > >>> > >>> > >>> Thanks, fix applied. > >>> > >> > >> Where was it applied? > >> > >> It doesn't show up in linux-next for 20120622, which is where it is needed. > > > > It's also desperately needed in mainline for 3.5. > > > > Ralf? > > Andrew? This prevents any green MIPS builds. > The patch is already in linux-next via Ralf's tree. Perhaps he nodded off - I'll send it at Linus right now. From oliver.kowalke@gmx.de Thu Jul 19 21:15:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Jul 2012 21:15:12 +0200 (CEST) Received: from mailout-de.gmx.net ([213.165.64.22]:39272 "HELO mailout-de.gmx.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1903650Ab2GSTPI (ORCPT ); Thu, 19 Jul 2012 21:15:08 +0200 Received: (qmail invoked by alias); 19 Jul 2012 19:15:03 -0000 Received: from p579D32F1.dip.t-dialin.net (EHLO [192.168.1.11]) [87.157.50.241] by mail.gmx.net (mp034) with SMTP; 19 Jul 2012 21:15:03 +0200 X-Authenticated: #25097877 X-Provags-ID: V01U2FsdGVkX19fepNFQhlfJpjxRsf1u9qdTGRcna+6PcdOqwWt/a vJQFnpoYrpnuqF Message-ID: <50085CB4.3030205@gmx.de> Date: Thu, 19 Jul 2012 21:15:00 +0200 From: Oliver Kowalke User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:13.0) Gecko/20120615 Thunderbird/13.0.1 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: development board? Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Y-GMX-Trusted: 0 X-archive-position: 33941 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: oliver.kowalke@gmx.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 325 Lines: 8 Hi, I'm searching for an development board with a MIPS processor - 1GB RAM would be nice but 10/100MBit ethernet is required. Unfortunately I can't find only ARM boards (100-150 USD). Could you recommend me a MIPS board for development (I don't want to have an old Indigo, O2 or Octane). thank you and best regards, Oliver From macro@linux-mips.org Thu Jul 19 23:01:09 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Jul 2012 23:01:17 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:41369 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903568Ab2GSVBJ (ORCPT ); Thu, 19 Jul 2012 23:01:09 +0200 Date: Thu, 19 Jul 2012 22:01:08 +0100 (BST) From: "Maciej W. Rozycki" To: Matt Turner cc: Jean Delvare , linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Guenter Roeck Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts In-Reply-To: Message-ID: References: <1313710991-3596-1-git-send-email-mattst88@gmail.com> <20110903103036.161616a5@endymion.delvare> <20111031105354.4b888e44@endymion.delvare> <20120110153834.531664db@endymion.delvare> <20120331082346.26cc95cb@endymion.delvare> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 33942 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 827 Lines: 20 On Sat, 30 Jun 2012, Matt Turner wrote: > I'm not going to have time to do this. :( > > I had another look at the code, and I'm not sure I really understand > it well enough to address your concerns. I'll try then, as soon as I can. > Good thing there are only about three users with this motherboard. Really? I've thought Debian used them for MIPS distribution builds if nobody else. AFAIK, ten years on and these systems (I mean the whole family) are still about the only ones reasonably widely available that provide performance decent enough for native use these days (yes, I did make serious use of an R3k DECstation natively once -- waiting for a GCC bootstrap to complete after the expected four weeks of computing time only to see it choke on a Makefile typo three weeks into was all but fun). Maciej From ralf@linux-mips.org Fri Jul 20 11:16:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Jul 2012 11:16:10 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:58909 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903645Ab2GTJQF (ORCPT ); Fri, 20 Jul 2012 11:16:05 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6K9G4Gn021221; Fri, 20 Jul 2012 11:16:04 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6K9G2Pd021220; Fri, 20 Jul 2012 11:16:02 +0200 Date: Fri, 20 Jul 2012 11:16:02 +0200 From: Ralf Baechle To: kr kr Cc: linux-mips@linux-mips.org Subject: Re: [mips32r1 cpu] Advice needed: "Machine Check exception - caused by multiple matching entries in the TLB" Message-ID: <20120720091602.GA15546@linux-mips.org> References: <194011342123405@web6e.yandex.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <194011342123405@web6e.yandex.ru> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33943 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 651 Lines: 14 On Fri, Jul 13, 2012 at 12:03:25AM +0400, kr kr wrote: > [ 12.560000] Kernel panic - not syncing: Caught Machine Check exception - caused by multiple matching entries in the TLB. Running userland should never result in crashing the kernel except if programs directly touch I/O hardware an do stupid things or abuse their root priviledges.. This type of crash specifically has in the past been produced by incorrect hazard barriers but also CPU hardware bugs so you may want to review the kernel code against a CPU datasheet and errata documentation. As always with hardware that is only supported out of tree we can't be too helpful ... Ralf From codeblue@inbox.lv Fri Jul 20 13:38:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Jul 2012 13:38:40 +0200 (CEST) Received: from shark2.inbox.lv ([89.111.3.82]:40002 "EHLO shark2.inbox.lv" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903469Ab2GTLig (ORCPT ); Fri, 20 Jul 2012 13:38:36 +0200 Received: from mail.inbox.lv (pop [10.0.1.110]) by shark2-plain.inbox.lv (Postfix) with ESMTP id 1FA17C01C for ; Fri, 20 Jul 2012 14:38:29 +0300 (EEST) Received: from inbox.lv (unknown [77.125.145.41]) (Authenticated sender: codeblue@inbox.lv) by mail.inbox.lv (Postfix) with ESMTPSA id BD4C51963C for ; Fri, 20 Jul 2012 14:38:24 +0300 (EEST) Date: Fri, 20 Jul 2012 11:38:17 +0000 From: John Long To: linux-mips@linux-mips.org Subject: Re: development board? Message-ID: <20120720113817.GA14576@inbox.lv> References: <50085CB4.3030205@gmx.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50085CB4.3030205@gmx.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-Virus-Scanned: OK X-archive-position: 33944 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: codeblue@inbox.lv Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 1189 Lines: 28 On Thu, Jul 19, 2012 at 09:15:00PM +0200, Oliver Kowalke wrote: > Hi, > I'm searching for an development board with a MIPS processor - 1GB > RAM would be nice but 10/100MBit ethernet is required. > Unfortunately I can't find only ARM boards (100-150 USD). > Could you recommend me a MIPS board for development (I don't want to > have an old Indigo, O2 or Octane). > thank you and best regards, > Oliver Hi, I am emailing you from my Lemote Fuloong. It is an 800 MHz MIPS-III+ box. It has 512M of RAM and comes in a nice enclosure. List price is about $190 but I have seen some invitations on various mailing lists from Lemote for developer discounts. http://www.lemote.com/en If this is too expensive or you really prefer a dev board instead of an SBC then what about MIPS Malta? They don't list the price on their site but it is supposed to be a good board with good doc and I believe various BSD support it in addition to Linux. http://www.mips.com/products/development-kits/ -- ASCII ribbon campaign ( ) Powered by Lemote Fuloong against HTML e-mail X Loongson MIPS and OpenBSD and proprietary / \ http://www.mutt.org attachments Code Blue or Go Home! From ralf@linux-mips.org Fri Jul 20 14:00:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Jul 2012 14:00:16 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:33572 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903608Ab2GTMAI (ORCPT ); Fri, 20 Jul 2012 14:00:08 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6KC06rr029900; Fri, 20 Jul 2012 14:00:06 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6KC05nc029897; Fri, 20 Jul 2012 14:00:05 +0200 Date: Fri, 20 Jul 2012 14:00:05 +0200 From: Ralf Baechle To: John Long Cc: linux-mips@linux-mips.org Subject: Re: development board? Message-ID: <20120720120005.GC15546@linux-mips.org> References: <50085CB4.3030205@gmx.de> <20120720113817.GA14576@inbox.lv> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120720113817.GA14576@inbox.lv> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33945 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 740 Lines: 15 On Fri, Jul 20, 2012 at 11:38:17AM +0000, John Long wrote: > If this is too expensive or you really prefer a dev board instead of an SBC > then what about MIPS Malta? They don't list the price on their site but it > is supposed to be a good board with good doc and I believe various BSD > support it in addition to Linux. > http://www.mips.com/products/development-kits/ The Malta is very expensive and also is a very old design. On top of that a Malta is just an ATX-format base board which needs a CPU card. A typical CPU card contains one or two of the biggest FPGAs money can buy so the CPU itself can be replaced by loading a bitfile. That is very appealing to hardware developers but the FPGA dictate a very juicy price. Ralf From geert@linux-m68k.org Fri Jul 20 20:38:18 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Jul 2012 20:38:22 +0200 (CEST) Received: from mail-gh0-f177.google.com ([209.85.160.177]:45332 "EHLO mail-gh0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903749Ab2GTSiS (ORCPT ); Fri, 20 Jul 2012 20:38:18 +0200 Received: by ghbf11 with SMTP id f11so4605410ghb.36 for ; Fri, 20 Jul 2012 11:38:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=SzHJQa5QdLG5kknwCbcecVjwR89k0CMoMYL+8oL2Mq0=; b=GOSQwXJQ3PH5Cd7wGdbWdoUR1KCsPeKak+Yg39zj2EUZq95olGFc1vBYzPTRA6iTPY 1aeSrr3DVxckIjR76kGMHZ+SCxZsUZUffqYy4zd2losPf3HA2p6fehBIwC9Z1+S22Yp4 wnwiXn1PpqjeFxxJTBHwmoyGbx15MuWK2R5CqPBtQSFCRIYOYgCXwfIDbcO5HB7BtfIM dy1mjjGxEnkrhukdXoXZtiufxs0WCnHlEKxH+Xah49W1jhHp4FS2QY/uuWG5LL017u7N MQZTyAVNpWy5rPmB/blrBImR9pfUxV+7StJBEdx/tAll9QfjUuqPaYx7bjQ4S1251HYb d8eA== MIME-Version: 1.0 Received: by 10.50.178.33 with SMTP id cv1mr1944954igc.1.1342809491607; Fri, 20 Jul 2012 11:38:11 -0700 (PDT) Received: by 10.231.135.1 with HTTP; Fri, 20 Jul 2012 11:38:11 -0700 (PDT) In-Reply-To: <20120713121053.0637219f@pyramind.ukuu.org.uk> References: <20120713141345.f71b7c01f720d616d74721dd@canb.auug.org.au> <20120713121053.0637219f@pyramind.ukuu.org.uk> Date: Fri, 20 Jul 2012 20:38:11 +0200 X-Google-Sender-Auth: WmGuH-U86p9zNLpFIA2TZy7dA-4 Message-ID: Subject: Re: linux-next: build failure after merge of the tty tree From: Geert Uytterhoeven To: Alan Cox , David Daney Cc: Stephen Rothwell , Greg KH , linux-next@vger.kernel.org, linux-kernel@vger.kernel.org, Linux MIPS Mailing List Content-Type: text/plain; charset=UTF-8 X-archive-position: 33946 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1582 Lines: 36 Hi Alan, David, On Fri, Jul 13, 2012 at 1:10 PM, Alan Cox wrote: > On Fri, 13 Jul 2012 14:13:45 +1000 > Stephen Rothwell wrote: >> After merging the tty tree, today's linux-next build (x86_64 allmodconfig) >> failed like this: >> >> drivers/char/mwave/mwavedd.c: In function 'register_serial_portandirq': >> drivers/char/mwave/mwavedd.c:472:2: error: implicit declaration of function 'serial8250_register_port' [-Werror=implicit-function-declaration] >> cc1: some warnings being treated as errors >> drivers/misc/ibmasm/uart.c: In function 'ibmasm_register_uart': >> drivers/misc/ibmasm/uart.c:57:2: error: implicit declaration of function 'serial8250_register_port' [-Werror=implicit-function-declaration] >> cc1: some warnings being treated as errors >> >> Caused by commit 2655a2c76f80 ("8250: use the 8250 register interface not >> the legacy one"). Grep is your friend. > > My fault on that one not GregKH's. I'll wrap that into the updated patch > series. I thought I had them all but I forgot to grep off in drivers/misc. Today's build failed because there's a new user in the MIPS tree: arch/mips/cavium-octeon/serial.c http://kisskb.ellerman.id.au/kisskb/buildresult/6739341/ Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From alan@lxorguk.ukuu.org.uk Fri Jul 20 22:51:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Jul 2012 22:51:53 +0200 (CEST) Received: from lxorguk.ukuu.org.uk ([81.2.110.251]:52708 "EHLO lxorguk.ukuu.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903748Ab2GTUvt (ORCPT ); Fri, 20 Jul 2012 22:51:49 +0200 Received: from pyramind.ukuu.org.uk (earthlight.etchedpixels.co.uk [81.2.110.250]) by lxorguk.ukuu.org.uk (8.14.5/8.14.1) with ESMTP id q6KLOqZt015797; Fri, 20 Jul 2012 22:24:57 +0100 Received: from pyramind.ukuu.org.uk (localhost [127.0.0.1]) by pyramind.ukuu.org.uk (8.14.5/8.14.5) with ESMTP id q6KKtHRs012699; Fri, 20 Jul 2012 21:55:17 +0100 Date: Fri, 20 Jul 2012 21:55:16 +0100 From: Alan Cox To: Geert Uytterhoeven Cc: David Daney , Stephen Rothwell , Greg KH , linux-next@vger.kernel.org, linux-kernel@vger.kernel.org, Linux MIPS Mailing List Subject: Re: linux-next: build failure after merge of the tty tree Message-ID: <20120720215516.03abd164@pyramind.ukuu.org.uk> In-Reply-To: References: <20120713141345.f71b7c01f720d616d74721dd@canb.auug.org.au> <20120713121053.0637219f@pyramind.ukuu.org.uk> X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.8; x86_64-redhat-linux-gnu) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAFVBMVEWysKsSBQMIAwIZCwj///8wIhxoRDXH9QHCAAABeUlEQVQ4jaXTvW7DIBAAYCQTzz2hdq+rdg494ZmBeE5KYHZjm/d/hJ6NfzBJpp5kRb5PHJwvMPMk2L9As5Y9AmYRBL+HAyJKeOU5aHRhsAAvORQ+UEgAvgddj/lwAXndw2laEDqA4x6KEBhjYRCg9tBFCOuJFxg2OKegbWjbsRTk8PPhKPD7HcRxB7cqhgBRp9Dcqs+B8v4CQvFdqeot3Kov6hBUn0AJitrzY+sgUuiA8i0r7+B3AfqKcN6t8M6HtqQ+AOoELCikgQSbgabKaJW3kn5lBs47JSGDhhLKDUh1UMipwwinMYPTBuIBjEclSaGZUk9hDlTb5sUTYN2SFFQuPe4Gox1X0FZOufjgBiV1Vls7b+GvK3SU4wfmcGo9rPPQzgIabfj4TYQo15k3bTHX9RIw/kniir5YbtJF4jkFG+dsDK1IgE413zAthU/vR2HVMmFUPIHTvF6jWCpFaGw/A3qWgnbxpSm9MSmY5b3pM1gvNc/gQfwBsGwF0VCtxZgAAAAASUVORK5CYII= Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 33947 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 420 Lines: 11 > Today's build failed because there's a new user in the MIPS tree: > arch/mips/cavium-octeon/serial.c > > http://kisskb.ellerman.id.au/kisskb/buildresult/6739341/ The version in the tree I have registers a platform device rather than calling into 8250 directly. That appears to be rather better mannered than whatever you are building. If someone has moved from the platform device could they kindly explain *why* ? From geert@linux-m68k.org Fri Jul 20 23:06:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Jul 2012 23:06:54 +0200 (CEST) Received: from mail-gh0-f177.google.com ([209.85.160.177]:55179 "EHLO mail-gh0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903748Ab2GTVGu (ORCPT ); Fri, 20 Jul 2012 23:06:50 +0200 Received: by ghbf11 with SMTP id f11so4743526ghb.36 for ; Fri, 20 Jul 2012 14:06:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=6w1VWgyiw+m9RsZKkVDy62tHKRq0zeow6FE9nzKpKAg=; b=eX5hZnlJjzxETvNN0+WXAwsfH/tVXNYz/mNrurIAKWCP0NLJFhQPx3C7xgihiMQP+M e6kANOPPVNhOptkDYLF36htZW8du3o38HxP2vJ4AKxdek5Is5Eqyo9f8/mx6JRmtyoFP dJHm2O1jvAAQNd1eQYW9HkNQ8gd8N1xXsrYsdmznbgT7vQOsKMhpppBWua6mIfvOew3t dKJcQQAhzs+4qvSSyVea66TfikZlWqDnCuYiThItJswPs+4yqg+cpYblxXwrm49TnmlQ YryC/wITTUM8kJl720vaWIiDSMhG5w9VdZS+vVPGa9GGOQ+XMjodV1tGYBkWwnIKh+b0 2kzg== MIME-Version: 1.0 Received: by 10.50.94.133 with SMTP id dc5mr9352614igb.16.1342818404325; Fri, 20 Jul 2012 14:06:44 -0700 (PDT) Received: by 10.231.135.1 with HTTP; Fri, 20 Jul 2012 14:06:44 -0700 (PDT) In-Reply-To: <20120720215516.03abd164@pyramind.ukuu.org.uk> References: <20120713141345.f71b7c01f720d616d74721dd@canb.auug.org.au> <20120713121053.0637219f@pyramind.ukuu.org.uk> <20120720215516.03abd164@pyramind.ukuu.org.uk> Date: Fri, 20 Jul 2012 23:06:44 +0200 X-Google-Sender-Auth: jTxq8avEmrgzCrGCx1FUtEagvy4 Message-ID: Subject: Re: linux-next: build failure after merge of the tty tree From: Geert Uytterhoeven To: Alan Cox Cc: David Daney , Stephen Rothwell , Greg KH , linux-next@vger.kernel.org, linux-kernel@vger.kernel.org, Linux MIPS Mailing List Content-Type: text/plain; charset=UTF-8 X-archive-position: 33948 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 989 Lines: 28 Hi Alan, On Fri, Jul 20, 2012 at 10:55 PM, Alan Cox wrote: >> Today's build failed because there's a new user in the MIPS tree: >> arch/mips/cavium-octeon/serial.c >> >> http://kisskb.ellerman.id.au/kisskb/buildresult/6739341/ > > The version in the tree I have registers a platform device rather than > calling into 8250 directly. That appears to be rather better mannered > than whatever you are building. > > If someone has moved from the platform device could they kindly explain > *why* ? commit 7c507e6fe36d8e8f67a06d1f81ddde4d8ecf739f ("MIPS: Octeon: Use device tree to register serial ports.") in linux-next. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From blogic@openwrt.org Sun Jul 22 08:56:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jul 2012 08:56:35 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:55366 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1902755Ab2GVG41 (ORCPT ); Sun, 22 Jul 2012 08:56:27 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 1/5] MIPS: lantiq: fix interface clock and PCI control register offset Date: Sun, 22 Jul 2012 08:55:57 +0200 Message-Id: <1342940161-1421-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33949 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4085 Lines: 140 The XRX200 based SoC have a different register offset for the interface clock and PCI control registers. This patch detects the SoC and sets the register offset at runtime. This make PCI work on the VR9 SoC. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/sysctrl.c | 49 ++++++++++++++++++++++---------------- 1 files changed, 28 insertions(+), 21 deletions(-) diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 83780f7..befbb76 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -20,10 +20,12 @@ /* clock control register */ #define CGU_IFCCR 0x0018 +#define CGU_IFCCR_VR9 0x0024 /* system clock register */ #define CGU_SYS 0x0010 /* pci control register */ #define CGU_PCICR 0x0034 +#define CGU_PCICR_VR9 0x0038 /* ephy configuration register */ #define CGU_EPHY 0x10 /* power control register */ @@ -80,6 +82,9 @@ static void __iomem *pmu_membase; void __iomem *ltq_cgu_membase; void __iomem *ltq_ebu_membase; +static u32 ifccr = CGU_IFCCR; +static u32 pcicr = CGU_PCICR; + /* legacy function kept alive to ease clkdev transition */ void ltq_pmu_enable(unsigned int module) { @@ -103,14 +108,14 @@ EXPORT_SYMBOL(ltq_pmu_disable); /* enable a hw clock */ static int cgu_enable(struct clk *clk) { - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR); + ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); return 0; } /* disable a hw clock */ static void cgu_disable(struct clk *clk) { - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR); + ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); } /* enable a clock gate */ @@ -138,22 +143,22 @@ static void pmu_disable(struct clk *clk) /* the pci enable helper */ static int pci_enable(struct clk *clk) { - unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); + unsigned int val = ltq_cgu_r32(ifccr); /* set bus clock speed */ if (of_machine_is_compatible("lantiq,ar9")) { - ifccr &= ~0x1f00000; + val &= ~0x1f00000; if (clk->rate == CLOCK_33M) - ifccr |= 0xe00000; + val |= 0xe00000; else - ifccr |= 0x700000; /* 62.5M */ + val |= 0x700000; /* 62.5M */ } else { - ifccr &= ~0xf00000; + val &= ~0xf00000; if (clk->rate == CLOCK_33M) - ifccr |= 0x800000; + val |= 0x800000; else - ifccr |= 0x400000; /* 62.5M */ + val |= 0x400000; /* 62.5M */ } - ltq_cgu_w32(ifccr, CGU_IFCCR); + ltq_cgu_w32(val, ifccr); pmu_enable(clk); return 0; } @@ -161,18 +166,16 @@ static int pci_enable(struct clk *clk) /* enable the external clock as a source */ static int pci_ext_enable(struct clk *clk) { - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16), - CGU_IFCCR); - ltq_cgu_w32((1 << 30), CGU_PCICR); + ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr); + ltq_cgu_w32((1 << 30), pcicr); return 0; } /* disable the external clock as a source */ static void pci_ext_disable(struct clk *clk) { - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), - CGU_IFCCR); - ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR); + ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr); + ltq_cgu_w32((1 << 31) | (1 << 30), pcicr); } /* enable a clockout source */ @@ -184,11 +187,11 @@ static int clkout_enable(struct clk *clk) for (i = 0; i < 4; i++) { if (clk->rates[i] == clk->rate) { int shift = 14 - (2 * clk->module); - unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); + unsigned int val = ltq_cgu_r32(ifccr); - ifccr &= ~(3 << shift); - ifccr |= i << shift; - ltq_cgu_w32(ifccr, CGU_IFCCR); + val &= ~(3 << shift); + val |= i << shift; + ltq_cgu_w32(val, ifccr); return 0; } } @@ -336,8 +339,12 @@ void __init ltq_soc_init(void) clkdev_add_clkout(); /* add the soc dependent clocks */ - if (!of_machine_is_compatible("lantiq,vr9")) + if (of_machine_is_compatible("lantiq,vr9")) { + ifccr = CGU_IFCCR_VR9; + pcicr = CGU_PCICR_VR9; + } else { clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE); + } if (!of_machine_is_compatible("lantiq,ase")) { clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1); -- 1.7.9.1 From blogic@openwrt.org Sun Jul 22 08:56:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jul 2012 08:56:59 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:55368 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903258Ab2GVG41 (ORCPT ); Sun, 22 Jul 2012 08:56:27 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay Date: Sun, 22 Jul 2012 08:55:58 +0200 Message-Id: <1342940161-1421-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1342940161-1421-1-git-send-email-blogic@openwrt.org> References: <1342940161-1421-1-git-send-email-blogic@openwrt.org> X-archive-position: 33950 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2006 Lines: 57 The PCI core has a register that allows us to set the nanosecond delay of the PCI clock lane. This patch adds a helper function to allow setting this value. Signed-off-by: John Crispin --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +++ arch/mips/lantiq/xway/sysctrl.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 6a2df70..0c2d67d 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -87,5 +87,8 @@ extern __iomem void *ltq_cgu_membase; extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); +/* allow pci driver to set the pci clk delay */ +void ltq_pci_set_delay(u32 delay); + #endif /* CONFIG_SOC_TYPE_XWAY */ #endif /* _LTQ_XWAY_H__ */ diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index befbb76..91bb435 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -41,6 +41,10 @@ /* power status register */ #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) +/* pci delay is 6 bit wide and 18 bit into the register*/ +#define PCI_DLY_MASK 0x3f +#define PCI_DLY_SHIFT 18 + /* clock gates that we can en/disable */ #define PMU_USB0_P BIT(0) #define PMU_PCI BIT(4) @@ -258,6 +262,16 @@ static void clkdev_add_pci(void) clkdev_add(&clk_ext->cl); } +/* allow PCI driver to specify the clock delay. This is a 6 bit value */ +void ltq_pci_set_delay(u32 delay) +{ + u32 val = ltq_cgu_r32(pcicr); + + val &= ~(PCI_DLY_MASK << PCI_DLY_SHIFT); + val |= (delay & PCI_DLY_MASK) << PCI_DLY_SHIFT; + ltq_cgu_w32(val, pcicr); +} + /* xway socs can generate clocks on gpio pins */ static unsigned long valid_clkout_rates[4][5] = { {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, -- 1.7.9.1 From blogic@openwrt.org Sun Jul 22 08:56:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jul 2012 08:57:33 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:55370 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903413Ab2GVG42 (ORCPT ); Sun, 22 Jul 2012 08:56:28 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 3/5] MIPS: lantiq: make use of new PCI clock helper Date: Sun, 22 Jul 2012 08:55:59 +0200 Message-Id: <1342940161-1421-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1342940161-1421-1-git-send-email-blogic@openwrt.org> References: <1342940161-1421-1-git-send-email-blogic@openwrt.org> X-archive-position: 33951 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1124 Lines: 36 Make use of the new helper function that allows us to set the PCI clock delay inside the PCI driver. Signed-off-by: John Crispin --- arch/mips/pci/pci-lantiq.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 075d87a..dae4349 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -98,7 +98,7 @@ static inline u32 ltq_calc_bar11mask(void) static int __devinit ltq_pci_startup(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; - const __be32 *req_mask, *bus_clk; + const __be32 *req_mask, *bus_clk, *delay; u32 temp_buffer; /* get our clocks */ @@ -127,6 +127,11 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev) else clk_disable(clk_external); + /* pci ckl delay is a 6 bit value */ + delay = of_get_property(node, "lantiq,delay", NULL); + if (delay) + ltq_pci_set_delay(*delay); + /* setup reset gpio used by pci */ reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); if (gpio_is_valid(reset_gpio)) -- 1.7.9.1 From blogic@openwrt.org Sun Jul 22 08:56:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jul 2012 08:58:04 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:55372 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903417Ab2GVG43 (ORCPT ); Sun, 22 Jul 2012 08:56:29 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 4/5] MIPS: lantiq: adds device_tree_init function Date: Sun, 22 Jul 2012 08:56:00 +0200 Message-Id: <1342940161-1421-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1342940161-1421-1-git-send-email-blogic@openwrt.org> References: <1342940161-1421-1-git-send-email-blogic@openwrt.org> X-archive-position: 33952 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1435 Lines: 58 Add a lantiq specific version of device_tree_init. The generic MIPS version was removed by. commit 594e966bc412d64eec9282d28ce511bdd62fea39 Author: David Daney Date: Thu Jul 5 18:12:38 2012 +0200 MIPS: Prune some target specific code out of prom.c Signed-off-by: John Crispin --- arch/mips/lantiq/prom.c | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 05a3364..e537099 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -8,7 +8,10 @@ #include #include +#include #include +#include + #include #include @@ -74,6 +77,25 @@ void __init plat_mem_setup(void) __dt_setup_arch(bph); } +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); + + /* free the space reserved for the dt blob */ + free_bootmem(base, size); +} + void __init prom_init(void) { /* call the soc specific detetcion code and get it to fill soc_info */ -- 1.7.9.1 From blogic@openwrt.org Sun Jul 22 08:56:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jul 2012 08:58:29 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:55374 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903439Ab2GVG43 (ORCPT ); Sun, 22 Jul 2012 08:56:29 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH 5/5] MIPS: lantiq: platform specific CLK fixup Date: Sun, 22 Jul 2012 08:56:01 +0200 Message-Id: <1342940161-1421-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1342940161-1421-1-git-send-email-blogic@openwrt.org> References: <1342940161-1421-1-git-send-email-blogic@openwrt.org> X-archive-position: 33953 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 687 Lines: 27 As we use CLKDEV_LOOKUP but dont have support for COMMON_CLK yet, we need to provide our own version of of_clk_get_from_provider(). Signed-off-by: John Crispin --- arch/mips/lantiq/clk.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index d3bcc33..ce2f129 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -135,6 +135,11 @@ void clk_deactivate(struct clk *clk) } EXPORT_SYMBOL(clk_deactivate); +struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) +{ + return NULL; +} + static inline u32 get_counter_resolution(void) { u32 res; -- 1.7.9.1 From sshtylyov@mvista.com Sun Jul 22 18:05:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jul 2012 18:05:52 +0200 (CEST) Received: from mail-lb0-f177.google.com ([209.85.217.177]:55498 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903474Ab2GVQFo (ORCPT ); Sun, 22 Jul 2012 18:05:44 +0200 Received: by lbbgg6 with SMTP id gg6so7299661lbb.36 for ; Sun, 22 Jul 2012 09:05:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=KB/4yX0raSZ+EgCIhPLBcvEiLSv/mY5gsQNiZNeLuqM=; b=mg6789Rt51jpoFyhb314o9aUxIMIeJnYSoUoBJQA3bgoG5+Kho4bRc3Vh2JwUklzGZ RjqjDOcQPzRLj1s/b7Yp7n8Plr61nEplAQpHnRfOYSSpz7EOD+KT2rPbyGD5+NxRNufG VbyX1yTzTPi+ZOhrmY2+oWcJqJ9gORcdvgTnwQHpSmkXt1CiiR9bZNfudkid3MryPolf sD6+UooDE+wtA43b52xRCtTbih8HcnqVnSsaDA5smP9lblNXIF609ZiXWfE2FeLMNkw/ n0j8leAGlDFGjFQRDeiBpeznntPkkpWwqqgmWcpsHQfyCL3P39VcniObsrpOK5VRWt46 D2Og== Received: by 10.152.112.138 with SMTP id iq10mr13579173lab.13.1342973139044; Sun, 22 Jul 2012 09:05:39 -0700 (PDT) Received: from [192.168.2.2] (ppp91-79-65-231.pppoe.mtu-net.ru. [91.79.65.231]) by mx.google.com with ESMTPS id n7sm2290759lbk.10.2012.07.22.09.05.36 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 22 Jul 2012 09:05:37 -0700 (PDT) Message-ID: <500C2498.1010609@mvista.com> Date: Sun, 22 Jul 2012 20:04:40 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:14.0) Gecko/20120713 Thunderbird/14.0 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay References: <1342940161-1421-1-git-send-email-blogic@openwrt.org> <1342940161-1421-2-git-send-email-blogic@openwrt.org> In-Reply-To: <1342940161-1421-2-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQl3/JdrpNDmueqMZ2FtT4j3eIE+wV8h3pKKtwSZbc4xrNnhJ4/Kcy7r9UA69Qx5GFcTzHKy X-archive-position: 33954 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 899 Lines: 35 Hello. On 22-07-2012 10:55, John Crispin wrote: > The PCI core has a register that allows us to set the nanosecond delay of the > PCI clock lane. This patch adds a helper function to allow setting this value. > Signed-off-by: John Crispin [...] > diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c > index befbb76..91bb435 100644 > --- a/arch/mips/lantiq/xway/sysctrl.c > +++ b/arch/mips/lantiq/xway/sysctrl.c [...] > @@ -258,6 +262,16 @@ static void clkdev_add_pci(void) > clkdev_add(&clk_ext->cl); > } > > +/* allow PCI driver to specify the clock delay. This is a 6 bit value */ WHy make it 'u32' then? > +void ltq_pci_set_delay(u32 delay) > +{ > + u32 val = ltq_cgu_r32(pcicr); > + > + val &= ~(PCI_DLY_MASK << PCI_DLY_SHIFT); > + val |= (delay & PCI_DLY_MASK) << PCI_DLY_SHIFT; > + ltq_cgu_w32(val, pcicr); > +} > + WBR, Sergei From blogic@openwrt.org Sun Jul 22 18:09:16 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Jul 2012 18:09:23 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:44052 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903467Ab2GVQJQ (ORCPT ); Sun, 22 Jul 2012 18:09:16 +0200 Message-ID: <500C2598.906@openwrt.org> Date: Sun, 22 Jul 2012 18:08:56 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111114 Icedove/3.1.16 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay References: <1342940161-1421-1-git-send-email-blogic@openwrt.org> <1342940161-1421-2-git-send-email-blogic@openwrt.org> <500C2498.1010609@mvista.com> In-Reply-To: <500C2498.1010609@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33955 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 168 Lines: 9 Hi Sergei, >> +/* allow PCI driver to specify the clock delay. This is a 6 bit >> value */ > > WHy make it 'u32' then? yep, let me change it to u8 ... Thanks, John From kr-jiffy@yandex.ru Mon Jul 23 19:22:35 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Jul 2012 19:22:40 +0200 (CEST) Received: from forward20.mail.yandex.net ([95.108.253.145]:60185 "EHLO forward20.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903706Ab2GWRWf (ORCPT ); Mon, 23 Jul 2012 19:22:35 +0200 Received: from web3g.yandex.ru (web3g.yandex.ru [95.108.252.103]) by forward20.mail.yandex.net (Yandex) with ESMTP id 37B661042C7E; Mon, 23 Jul 2012 21:22:29 +0400 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1343064149; bh=ciB0e/Tov2bVNZ6oW4S1LZLVJTSmkpxKNVlkcWFi7pk=; h=From:To:Cc:In-Reply-To:References:Subject:MIME-Version:Message-Id: Date:Content-Transfer-Encoding:Content-Type; b=v5JT6S31us1gvPNHIMhRShXODqSt4WWsd7NILhsw5gHDUdh6LqK5iqszKvYoQ+Joi aw7tGZrMh9roTo3FDiss39JrV0F/sw3qFMTizo4+VNZpKJOJkz1h2GrFvOmi9ndump oXviv+7OSmNDVhk6Nx6JDOVdEhnOKtAdwrDLMTa8= Received: from 127.0.0.1 (localhost.localdomain [127.0.0.1]) by web3g.yandex.ru (Yandex) with ESMTP id CFC31208802C; Mon, 23 Jul 2012 21:22:28 +0400 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1343064149; bh=ciB0e/Tov2bVNZ6oW4S1LZLVJTSmkpxKNVlkcWFi7pk=; h=From:To:Cc:In-Reply-To:References:Subject:Date; b=b6yBI0VBjeF9c1tgZTL6A6K6xh34b2NCjjPozLmTZBMmKYYBdNlt2CwH6wpWcr9ZB 1/LWJwcBKvs+LFZMDD2aswHMpk3C/7LNQi2x65AJc2s1gO9T+rORiBjiAdGH5g2RMi DCgOCPsj3PrDfyypPCVmO5vA/pijHj+3n8l3jcUo= Received: from wimax-client.yota.ru (wimax-client.yota.ru [178.176.237.110]) by web3g.yandex.ru with HTTP; Mon, 23 Jul 2012 21:22:28 +0400 From: kr kr To: Ralf Baechle Cc: "linux-mips@linux-mips.org" In-Reply-To: <20120720091602.GA15546@linux-mips.org> References: <194011342123405@web6e.yandex.ru> <20120720091602.GA15546@linux-mips.org> Subject: Re: [mips32r1 cpu] Advice needed: "Machine Check exception - caused by multiple matching entries in the TLB" MIME-Version: 1.0 Message-Id: <189641343064148@web3g.yandex.ru> Date: Mon, 23 Jul 2012 21:22:28 +0400 X-Mailer: Yamail [ http://yandex.ru ] 5.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=koi8-r X-archive-position: 33956 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kr-jiffy@yandex.ru Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 967 Lines: 20 20.07.2012, 13:16, "Ralf Baechle" : > On Fri, Jul 13, 2012 at 12:03:25AM +0400, kr kr wrote: > >> š[ šš12.560000] Kernel panic - not syncing: Caught Machine Check exception - caused by multiple matching entries in the TLB. > > Running userland should never result in crashing the kernel except if > programs directly touch I/O hardware an do stupid things or abuse their > root priviledges.. > > This type of crash specifically has in the past been produced by incorrect > hazard barriers but also CPU hardware bugs so you may want to review the > kernel code against a CPU datasheet and errata documentation. šAs always > with hardware that is only supported out of tree we can't be too helpful ... > > ššRalf Ok, thank you. But, in case of, say, Malta, we don't need to turn on (or turn off) some special CONFIG_* options in order to make it run MIPS-I binaries (which Debian provides), whereas MIPS32 binaries are native for the board? Yuri From minchan@kernel.org Tue Jul 24 03:10:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 03:10:39 +0200 (CEST) Received: from LGEMRELSE1Q.lge.com ([156.147.1.111]:44694 "EHLO LGEMRELSE1Q.lge.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903712Ab2GXBK1 (ORCPT ); Tue, 24 Jul 2012 03:10:27 +0200 X-AuditID: 9c93016f-b7b08ae00000790d-e8-500df5f6575e Received: from localhost.localdomain ( [10.177.220.67]) by LGEMRELSE1Q.lge.com (Symantec Brightmail Gateway) with SMTP id CA.2D.30989.7F5FD005; Tue, 24 Jul 2012 10:10:16 +0900 (KST) From: Minchan Kim To: Andrew Morton Cc: Tejun Heo , Yinghai Lu , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Minchan Kim , Ralf Baechle , linux-mips@linux-mips.org Subject: [PATCH 1/3] mips: zero out pg_data_t when it's allocated Date: Tue, 24 Jul 2012 10:10:33 +0900 Message-Id: <1343092235-13399-1-git-send-email-minchan@kernel.org> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: AAAAAA== X-archive-position: 33957 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: minchan@kernel.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 938 Lines: 26 This patch is ready for next patch which try to remove zero-out of pg_data_t in core MM part. At a glance, all archs except this part already have done it so this patch makes consistent with other archs. Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Signed-off-by: Minchan Kim --- arch/mips/sgi-ip27/ip27-memory.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c index b105eca..cd8fcab 100644 --- a/arch/mips/sgi-ip27/ip27-memory.c +++ b/arch/mips/sgi-ip27/ip27-memory.c @@ -401,6 +401,7 @@ static void __init node_mem_init(cnodeid_t node) * Allocate the node data structures on the node first. */ __node_data[node] = __va(slot_freepfn << PAGE_SHIFT); + memset(__node_data[node], 0, PAGE_SIZE); NODE_DATA(node)->bdata = &bootmem_node_data[node]; NODE_DATA(node)->node_start_pfn = start_pfn; -- 1.7.9.5 From blogic@openwrt.org Tue Jul 24 08:30:14 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 08:30:22 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:35743 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1902244Ab2GXGaO (ORCPT ); Tue, 24 Jul 2012 08:30:14 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH V2 2/5] MIPS: lantiq: add helper to set PCI clock delay Date: Tue, 24 Jul 2012 08:29:46 +0200 Message-Id: <1343111386-9584-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33958 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2077 Lines: 60 The PCI core has a register that allows us to set the nanosecond delay of the PCI clock lane. This patch adds a helper function to allow setting this value. Signed-off-by: John Crispin --- Changes in V2 * use u8 rather than u32 for the 6 bit delay value .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +++ arch/mips/lantiq/xway/sysctrl.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 6a2df70..1de5d82 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -87,5 +87,8 @@ extern __iomem void *ltq_cgu_membase; extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); +/* allow pci driver to set the pci clk delay */ +void ltq_pci_set_delay(u8 delay); + #endif /* CONFIG_SOC_TYPE_XWAY */ #endif /* _LTQ_XWAY_H__ */ diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index befbb76..79887af 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -41,6 +41,10 @@ /* power status register */ #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) +/* pci delay is 6 bit wide and 18 bit into the register*/ +#define PCI_DLY_MASK 0x3f +#define PCI_DLY_SHIFT 18 + /* clock gates that we can en/disable */ #define PMU_USB0_P BIT(0) #define PMU_PCI BIT(4) @@ -258,6 +262,16 @@ static void clkdev_add_pci(void) clkdev_add(&clk_ext->cl); } +/* allow PCI driver to specify the clock delay. This is a 6 bit value */ +void ltq_pci_set_delay(u8 delay) +{ + u32 val = ltq_cgu_r32(pcicr); + + val &= ~(PCI_DLY_MASK << PCI_DLY_SHIFT); + val |= ((u32)(delay & PCI_DLY_MASK)) << PCI_DLY_SHIFT; + ltq_cgu_w32(val, pcicr); +} + /* xway socs can generate clocks on gpio pins */ static unsigned long valid_clkout_rates[4][5] = { {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, -- 1.7.9.1 From blogic@openwrt.org Tue Jul 24 08:57:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 08:57:15 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:47943 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903414Ab2GXG5I (ORCPT ); Tue, 24 Jul 2012 08:57:08 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH] MIPS: lantiq: explicitly enable clkout generation Date: Tue, 24 Jul 2012 08:56:41 +0200 Message-Id: <1343113001-12896-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.9.1 X-archive-position: 33959 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 832 Lines: 28 Previously we relied on the bootloader to have enabled this bit. However some bootloaders seem to not enable this for us. Signed-off-by: John Crispin --- arch/mips/lantiq/xway/sysctrl.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 79887af..8863cca 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -191,10 +191,12 @@ static int clkout_enable(struct clk *clk) for (i = 0; i < 4; i++) { if (clk->rates[i] == clk->rate) { int shift = 14 - (2 * clk->module); + int enable = 7 - clk->module; unsigned int val = ltq_cgu_r32(ifccr); val &= ~(3 << shift); val |= i << shift; + val |= enable; ltq_cgu_w32(val, ifccr); return 0; } -- 1.7.9.1 From dhillf@gmail.com Tue Jul 24 15:04:40 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 15:04:47 +0200 (CEST) Received: from mail-vc0-f177.google.com ([209.85.220.177]:62388 "EHLO mail-vc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903752Ab2GXNEk convert rfc822-to-8bit (ORCPT ); Tue, 24 Jul 2012 15:04:40 +0200 Received: by vcbfl13 with SMTP id fl13so6013005vcb.36 for ; Tue, 24 Jul 2012 06:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=SRTp+gUeIdYfIYTIEbhSwj6FZpPF/NX6hqjFNTJY3fw=; b=tdKk0YvYXVD9xrGE3bKlHKGoSEjqleUVNSBeSz2UoasA6Vfe28kcT9UgsYP+A173bN vXdN8O8gFbNLqpg4hZCyAW7YXkYG7TX+pOEM556jTfgB6POCDv9SvuCxxVvhyOIdL4JP 7Nvh1mKCA7Ru8VkbEvyQjLPq02CnKbQJX+tfWLHW2V7P2ebxExvyOabURy/GjHsyGHop f76wgWLg6N00NKkeAoo3aoKt5TA5dgCiia5lKi3Au4erm7AIW5sp2yhEDkQK58kneA9l KUhJlo/t4a1m8P7hlccaGawpprJ25Od+PXsxaLgB/yatGDlKgVwli/J6sUHEZVUdRm6k 8AiA== MIME-Version: 1.0 Received: by 10.52.180.230 with SMTP id dr6mr13431220vdc.130.1343135073536; Tue, 24 Jul 2012 06:04:33 -0700 (PDT) Received: by 10.220.1.210 with HTTP; Tue, 24 Jul 2012 06:04:32 -0700 (PDT) In-Reply-To: <1342922751.65328.YahooMailNeo@web120106.mail.ne1.yahoo.com> References: <1342922751.65328.YahooMailNeo@web120106.mail.ne1.yahoo.com> Date: Tue, 24 Jul 2012 21:04:32 +0800 Message-ID: Subject: Re: Direct I/O bug in kernel From: Hillf Danton To: Victor Meyerson Cc: "linux-mips@linux-mips.org" , Ralf Baechle , LKML Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 33960 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3822 Lines: 73 On Sun, Jul 22, 2012 at 10:05 AM, Victor Meyerson wrote: > Hi, > > I recently found a bug related to direct io in post 3.3 linux kernels. Fortunately, my hardware (a Cobalt Qube2) is supported by the vanilla kernel so I did not need additional patch sets to get the machine to boot. I ran git bisect on the main tree[1] and tested the various bisect results until git reported the first bad commit. After several bisects and many reboots, git reported that [2] was the first bad commit. > > In testing this I came up with a repeatable process. Unfortunately, I do not have any other MIPS hardware to test this on and I believe that based on the commit in question that it is MIPS related. My procedure is as follows: > > 1) Create a random file to be used on the two kernels (one before the commit, and one that includes the commit) > $ dd if=/dev/urandom of=random-file bs=512 count=30720 > 30720+0 records in > 30720+0 records out > 15728640 bytes (16 MB) copied, 60.7035 s, 259 kB/s > $ chmod -w random-file > > 2) Reboot to the kernel before the commit and run dd with direct io. Repeat. > $ uname -a > Linux horadric 3.2.0-dirty #2 Fri Jul 13 06:20:22 PDT 2012 mips64 Nevada V10.0 FPU V10.0 Cobalt Qube2 GNU/Linux > $ dd if=random-file of=portion-of-random-3.2.0 bs=512 count=20480 iflag=direct > 20480+0 records in > 20480+0 records out > 10485760 bytes (10 MB) copied, 42.3636 s, 248 kB/s > $ reboot > $ dd if=random-file of=portion-of-random-3.2.0-2 bs=512 count=20480 iflag=direct > 20480+0 records in > 20480+0 records out > 10485760 bytes (10 MB) copied, 42.5252 s, 247 kB/s > > 3) Reboot to the kernel with the commit and run dd with direct io. Repeat. > $ uname -a > Linux horadric 3.2.0-rc4-00003-gb1c10be-dirty #15 Fri Jul 20 15:05:13 PDT 2012 mips64 Nevada V10.0 FPU V10.0 Cobalt Qube2 GNU/Linux > $ dd if=random-file of=portion-of-random-3.2.0-rc4 bs=512 count=20480 iflag=direct > 20480+0 records in > 20480+0 records out > 10485760 bytes (10 MB) copied, 40.6226 s, 258 kB/s > $ reboot > $ dd if=random-file of=portion-of-random-3.2.0-rc4-2 bs=512 count=20480 iflag=direct > 20480+0 records in > 20480+0 records out > 10485760 bytes (10 MB) copied, 40.8856 s, 256 kB/s > Hi Victor, Create files with dd if=random-file of=portion-of-random-3.2.0-rc4 bs=8k count=1280 iflag=direct dd if=random-file of=portion-of-random-3.2.0-rc4-2 bs=8k count=1280 iflag=direct without reboot(why reboot needed?), then see the changes in checksums. Thanks Hillf > 4) Compare checksums of the resulting files. > $ sha256sum portion-of-random-3.2.0* > c98a6e949b36448842a21f68e7c6a5daff1f161e1eb3e3529176cf56bf5af89e portion-of-random-3.2.0 > c98a6e949b36448842a21f68e7c6a5daff1f161e1eb3e3529176cf56bf5af89e portion-of-random-3.2.0-2 > dca27da87a78580b8a34bbff2790ae80d3aa880d5d00fc2126f109d6fff9e056 portion-of-random-3.2.0-rc4 > 703cf02d4fa90679d4a75900e7e5a3b8c3000a65bfc475610b10f17bb88bedbc portion-of-random-3.2.0-rc4-2 > > Notice how the last two files have different checksums between themselves and even different from the first two files. This lead me to believe that there is a problem with direct io. All the files are the same size and should include the same portion of the random file created in step 1). > > My configuration is the Cobalt Qube2 with a 64-bit kernel and an n32 userspace. Hopefully someone with a much more deeper understanding of the kernel can confirm and provide a fix for this (assuming one has not been created yet). > > Thanks. Let me know if there is any additional information that may help with the investigation. > > Victor > > > [1] http://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > [2] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=b1c10bea620f79109b5cc9935267bea4f6f29ac6 From ralf@linux-mips.org Tue Jul 24 16:58:44 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 16:58:48 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:53044 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903482Ab2GXO6o (ORCPT ); Tue, 24 Jul 2012 16:58:44 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6OEwhCG010259; Tue, 24 Jul 2012 16:58:43 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6OEwgsq010258; Tue, 24 Jul 2012 16:58:42 +0200 Date: Tue, 24 Jul 2012 16:58:42 +0200 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 05/12] MIPS: PCI: Fix for byte swap for Netlogic XLP Message-ID: <20120724145842.GA9721@linux-mips.org> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> <1342196605-4260-6-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1342196605-4260-6-git-send-email-jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33961 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 76 Lines: 4 Folded into https://patchwork.linux-mips.org/patch/3760/. Thanks, Ralf From ralf@linux-mips.org Tue Jul 24 16:59:36 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 16:59:40 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:53199 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903773Ab2GXO7g (ORCPT ); Tue, 24 Jul 2012 16:59:36 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6OExZTD010278; Tue, 24 Jul 2012 16:59:35 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6OExYc8010277; Tue, 24 Jul 2012 16:59:34 +0200 Date: Tue, 24 Jul 2012 16:59:34 +0200 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 02/12] MIPS: Netlogic: Fix low-level flush on core wakeup Message-ID: <20120724145934.GB9721@linux-mips.org> References: <1342196605-4260-1-git-send-email-jayachandranc@netlogicmicro.com> <1342196605-4260-3-git-send-email-jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1342196605-4260-3-git-send-email-jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33962 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 75 Lines: 3 Folded into https://patchwork.linux-mips.org/patch/3755/. Thanks, Ralf From br1@einfach.org Tue Jul 24 17:13:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 17:13:43 +0200 (CEST) Received: from postler.einfach.org ([86.59.21.13]:55365 "EHLO postler.einfach.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903748Ab2GXPNj (ORCPT ); Tue, 24 Jul 2012 17:13:39 +0200 Received: from [192.168.2.106] (217.Red-88-23-52.staticIP.rima-tde.net [88.23.52.217]) by postler.einfach.org (Postfix) with ESMTPSA id 36FE721421EB; Tue, 24 Jul 2012 17:13:31 +0200 (CEST) Message-ID: <500EBB99.5050209@einfach.org> Date: Tue, 24 Jul 2012 16:13:29 +0100 From: Bruno Randolf User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Bruno Randolf CC: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org, florian@openwrt.org Subject: Re: [PATCH] mtx-1: add udelay to mtx1_pci_idsel References: <1342126445-13408-1-git-send-email-br1@einfach.org> In-Reply-To: <1342126445-13408-1-git-send-email-br1@einfach.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 33963 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: br1@einfach.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2313 Lines: 60 Hello? Any feedback? I know the description is not very good, but this patch is necessary for PCI to work on the Surfbox. Thanks, bruno On 07/12/2012 09:54 PM, Bruno Randolf wrote: > Without this udelay(1) PCI idsel does not work correctly on the "singleboard" > (T-Mobile Surfbox) for the MiniPCI device. The result is that PCI configuration > fails and the MiniPCI card is not detected correctly. Instead of > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0xffff] > pci 0000:00:03.0: BAR 0: assigned [mem 0x40000000-0x4000ffff] > pci 0000:00:00.0: BAR 0: assigned [mem 0x40010000-0x40010fff] > pci 0000:00:00.1: BAR 0: assigned [mem 0x40011000-0x40011fff] > > We see only the CardBus device: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0xffff] > pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x40000fff] > pci 0000:00:00.1: BAR 0: assigned [mem 0x40001000-0x40001fff] > > Later the device driver shows this error: > > ath5k 0000:00:03.0: cannot remap PCI memory region > ath5k: probe of 0000:00:03.0 failed with error -5 > > I assume that the logic chip which usually supresses the signal to the CardBus > card has some settling time and without the delay it would still let the > Cardbus interfere with the response from the MiniPCI card. > > What I cannot explain is why this behaviour shows up now and not in earlier > kernel versions before. Maybe older PCI code was slower? > > Signed-off-by: Bruno Randolf > --- > arch/mips/alchemy/board-mtx1.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c > index 295f1a9..e107a2f 100644 > --- a/arch/mips/alchemy/board-mtx1.c > +++ b/arch/mips/alchemy/board-mtx1.c > @@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int assert) > * adapter on the mtx-1 "singleboard" variant. It triggers a custom > * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. > */ > + udelay(1); > + > if (assert && devsel != 0) > /* Suppress signal to Cardbus */ > alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ > From manuel.lauss@gmail.com Tue Jul 24 17:21:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 17:21:30 +0200 (CEST) Received: from mail-gg0-f177.google.com ([209.85.161.177]:53642 "EHLO mail-gg0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903514Ab2GXPVY (ORCPT ); Tue, 24 Jul 2012 17:21:24 +0200 Received: by ggcs5 with SMTP id s5so7192786ggc.36 for ; Tue, 24 Jul 2012 08:21:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=15oK9MPuWtYG3mNnowdCBBWCiuCAtO1/40oFE15+/MQ=; b=B5uBUbK+HttuqVxHN6FsLn7coK4rKYeQGSqsP1Boy5jPOZ6tbbEvLv709HWtx9XdCN MBn3pwUm6MlkuSMAmHyXeyF1foeHaa+TkCrcytnbaPNVdooXurxqlCYO89M+hRPTftM+ uT4TQO3iEcpUBpVKWWhlZq1hYUNpQxz2EloxhXwhLwWDxz8VSiSGR4xb4Dct+/Wk3EnZ I38UAv3cqISBrEz786K6/FeIFjw75QXoD6pQFoyMrtZoVVJ4FQcyFIa0zzwbwysWhuck EM3Hl9HRRX2W6Loi9BQHjzdZ5t6rznJUZZx1LDntXU/SGavfVqZ562LzjVSTepkq++Dw aHbA== Received: by 10.236.197.5 with SMTP id s5mr19248392yhn.114.1343143278293; Tue, 24 Jul 2012 08:21:18 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.92.208 with HTTP; Tue, 24 Jul 2012 08:20:37 -0700 (PDT) In-Reply-To: <500EBB99.5050209@einfach.org> References: <1342126445-13408-1-git-send-email-br1@einfach.org> <500EBB99.5050209@einfach.org> From: Manuel Lauss Date: Tue, 24 Jul 2012 17:20:37 +0200 Message-ID: Subject: Re: [PATCH] mtx-1: add udelay to mtx1_pci_idsel To: Bruno Randolf Cc: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org, florian@openwrt.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33964 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2634 Lines: 75 On Tue, Jul 24, 2012 at 5:13 PM, Bruno Randolf wrote: > Hello? Any feedback? > > I know the description is not very good, but this patch is necessary for PCI > to work on the Surfbox. > > Thanks, > bruno > > > On 07/12/2012 09:54 PM, Bruno Randolf wrote: >> >> Without this udelay(1) PCI idsel does not work correctly on the >> "singleboard" >> (T-Mobile Surfbox) for the MiniPCI device. The result is that PCI >> configuration >> fails and the MiniPCI card is not detected correctly. Instead of >> >> PCI host bridge to bus 0000:00 >> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >> pci 0000:00:03.0: BAR 0: assigned [mem 0x40000000-0x4000ffff] >> pci 0000:00:00.0: BAR 0: assigned [mem 0x40010000-0x40010fff] >> pci 0000:00:00.1: BAR 0: assigned [mem 0x40011000-0x40011fff] >> >> We see only the CardBus device: >> >> PCI host bridge to bus 0000:00 >> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >> pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x40000fff] >> pci 0000:00:00.1: BAR 0: assigned [mem 0x40001000-0x40001fff] >> >> Later the device driver shows this error: >> >> ath5k 0000:00:03.0: cannot remap PCI memory region >> ath5k: probe of 0000:00:03.0 failed with error -5 >> >> I assume that the logic chip which usually supresses the signal to the >> CardBus >> card has some settling time and without the delay it would still let the >> Cardbus interfere with the response from the MiniPCI card. >> >> What I cannot explain is why this behaviour shows up now and not in >> earlier >> kernel versions before. Maybe older PCI code was slower? >> >> Signed-off-by: Bruno Randolf >> --- >> arch/mips/alchemy/board-mtx1.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/mips/alchemy/board-mtx1.c >> b/arch/mips/alchemy/board-mtx1.c >> index 295f1a9..e107a2f 100644 >> --- a/arch/mips/alchemy/board-mtx1.c >> +++ b/arch/mips/alchemy/board-mtx1.c >> @@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int >> assert) >> * adapter on the mtx-1 "singleboard" variant. It triggers a >> custom >> * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL >> signals. >> */ >> + udelay(1); >> + >> if (assert && devsel != 0) >> /* Suppress signal to Cardbus */ >> alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ >> Why don't you increase the delay value in the udelay() immediately following this part? Manuel From keguang.zhang@gmail.com Tue Jul 24 17:24:47 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 17:25:06 +0200 (CEST) Received: from mail-vb0-f49.google.com ([209.85.212.49]:36970 "EHLO mail-vb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903509Ab2GXPYr (ORCPT ); Tue, 24 Jul 2012 17:24:47 +0200 Received: by vbbfo1 with SMTP id fo1so6162857vbb.36 for ; Tue, 24 Jul 2012 08:24:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=iKaGGX7fqP6xW1eiqV3hPpSDMwsVlfXxPcfuy/Y3l+c=; b=vkLj/Sr2MN0YeQfPdEytrwZCiDnjbxlr5RA/d2TbysipFhQrWybyBt2m53NkMAQ2ou 4MnVKkvPV9NdUocne3bCewC8zz/YD1R6rzsvdiJm/0ZjtiVyCfIJVzQf1J9IawQB+EOn H9mcfO0M/5L0aLd+Q7pzDb8MyVHcZhD5JDUM40iP+fpRzusUOTqiPO67cDLvjemiRL8X 25ofceIIGdMOzLzQRW4ZqQmzv57iAn9QKKoyX9YysQH3gTSb6mxzoSu1j3UyWbAPfIYT Q1lzah7RV2gYEM51mtzwdsWqex8qpnbmnrh6mQFBetRGzGXsI9v4LMIqibDwSevQUnAw ppXg== Received: by 10.52.68.165 with SMTP id x5mr13885203vdt.2.1343143481219; Tue, 24 Jul 2012 08:24:41 -0700 (PDT) MIME-Version: 1.0 Received: by 10.220.204.200 with HTTP; Tue, 24 Jul 2012 08:24:20 -0700 (PDT) In-Reply-To: <1341653400-24860-1-git-send-email-keguang.zhang@gmail.com> References: <1341653400-24860-1-git-send-email-keguang.zhang@gmail.com> From: Kelvin Cheung Date: Tue, 24 Jul 2012 23:24:20 +0800 Message-ID: Subject: Re: [PATCH V7 2/4] MIPS: Add board support for Loongson1B To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ralf@linux-mips.org Cc: wuzhangjin@gmail.com, zhzhl555@gmail.com, Kelvin Cheung Content-Type: multipart/alternative; boundary=20cf307f309614995004c594f6b6 X-archive-position: 33965 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 78397 Lines: 2300 --20cf307f309614995004c594f6b6 Content-Type: text/plain; charset=ISO-8859-1 Hi Ralf, I have submitted "V7 (updated)" for 3 of the 4 patches. And patch 1 is unchanged. New bundle is here: http://patchwork.linux-mips.org/bundle/kelvin/Loongson1B%20support 2012/7/7 Kelvin Cheung > This patch adds basic platform devices for Loongson1B, > including serial port, ethernet, usb, rtc and interrupt handler. > > Loongson1B UART is compatible with NS16550A. > Loongson1B GMAC is built around Synopsys IP Core. > > Use normal descriptor instead of enhanced descriptor. > Thanks to Giuseppe for updating the normal descriptor > in stmmac driver. > > Thanks to Zhao Zhang for implementing the RTC driver. > > Signed-off-by: Kelvin Cheung > > --- > V7(updated): > 1.Remove 'ifdef' of platform devices. (Asked by Ralf) > 2.Modify plat_stmmacenet_data accordingly due to the change > of upstream. > --- > arch/mips/include/asm/mach-loongson1/irq.h | 73 ++++++++++ > arch/mips/include/asm/mach-loongson1/loongson1.h | 44 ++++++ > arch/mips/include/asm/mach-loongson1/platform.h | 23 +++ > arch/mips/include/asm/mach-loongson1/prom.h | 24 +++ > arch/mips/include/asm/mach-loongson1/regs-clk.h | 33 +++++ > arch/mips/include/asm/mach-loongson1/regs-wdt.h | 22 +++ > arch/mips/include/asm/mach-loongson1/war.h | 25 ++++ > arch/mips/loongson1/common/clock.c | 165 > ++++++++++++++++++++++ > arch/mips/loongson1/common/irq.c | 147 > +++++++++++++++++++ > arch/mips/loongson1/common/platform.c | 124 ++++++++++++++++ > arch/mips/loongson1/common/prom.c | 87 ++++++++++++ > arch/mips/loongson1/common/reset.c | 45 ++++++ > arch/mips/loongson1/common/setup.c | 29 ++++ > arch/mips/loongson1/ls1b/board.c | 33 +++++ > 14 files changed, 874 insertions(+), 0 deletions(-) > create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h > create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h > create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h > create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h > create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h > create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h > create mode 100644 arch/mips/include/asm/mach-loongson1/war.h > create mode 100644 arch/mips/loongson1/common/clock.c > create mode 100644 arch/mips/loongson1/common/irq.c > create mode 100644 arch/mips/loongson1/common/platform.c > create mode 100644 arch/mips/loongson1/common/prom.c > create mode 100644 arch/mips/loongson1/common/reset.c > create mode 100644 arch/mips/loongson1/common/setup.c > create mode 100644 arch/mips/loongson1/ls1b/board.c > > diff --git a/arch/mips/include/asm/mach-loongson1/irq.h > b/arch/mips/include/asm/mach-loongson1/irq.h > new file mode 100644 > index 0000000..ccc42cc > --- /dev/null > +++ b/arch/mips/include/asm/mach-loongson1/irq.h > @@ -0,0 +1,73 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * IRQ mappings for Loongson1. > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > + > +#ifndef __ASM_MACH_LOONGSON1_IRQ_H > +#define __ASM_MACH_LOONGSON1_IRQ_H > + > +/* > + * CPU core Interrupt Numbers > + */ > +#define MIPS_CPU_IRQ_BASE 0 > +#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) > + > +#define SOFTINT0_IRQ MIPS_CPU_IRQ(0) > +#define SOFTINT1_IRQ MIPS_CPU_IRQ(1) > +#define INT0_IRQ MIPS_CPU_IRQ(2) > +#define INT1_IRQ MIPS_CPU_IRQ(3) > +#define INT2_IRQ MIPS_CPU_IRQ(4) > +#define INT3_IRQ MIPS_CPU_IRQ(5) > +#define INT4_IRQ MIPS_CPU_IRQ(6) > +#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu > timer */ > + > +#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) > + > +/* > + * INT0~3 Interrupt Numbers > + */ > +#define LS1X_IRQ_BASE MIPS_CPU_IRQS > +#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) > + > +#define LS1X_UART0_IRQ LS1X_IRQ(0, 2) > +#define LS1X_UART1_IRQ LS1X_IRQ(0, 3) > +#define LS1X_UART2_IRQ LS1X_IRQ(0, 4) > +#define LS1X_UART3_IRQ LS1X_IRQ(0, 5) > +#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) > +#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) > +#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) > +#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) > +#define LS1X_AC97_IRQ LS1X_IRQ(0, 10) > +#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) > +#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) > +#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) > +#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) > +#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) > +#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) > +#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) > +#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) > +#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) > +#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) > +#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) > +#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) > +#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) > +#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) > +#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) > + > +#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) > +#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) > +#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) > +#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) > + > +#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE) > + > +#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) > + > +#endif /* __ASM_MACH_LOONGSON1_IRQ_H */ > diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h > b/arch/mips/include/asm/mach-loongson1/loongson1.h > new file mode 100644 > index 0000000..0440627 > --- /dev/null > +++ b/arch/mips/include/asm/mach-loongson1/loongson1.h > @@ -0,0 +1,44 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * Register mappings for Loongson1. > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > + > +#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H > +#define __ASM_MACH_LOONGSON1_LOONGSON1_H > + > +#define DEFAULT_MEMSIZE 256 /* If no memsize > provided */ > + > +/* Loongson1 Register Bases */ > +#define LS1X_INTC_BASE 0x1fd01040 > +#define LS1X_EHCI_BASE 0x1fe00000 > +#define LS1X_OHCI_BASE 0x1fe08000 > +#define LS1X_GMAC0_BASE 0x1fe10000 > +#define LS1X_GMAC1_BASE 0x1fe20000 > + > +#define LS1X_UART0_BASE 0x1fe40000 > +#define LS1X_UART1_BASE 0x1fe44000 > +#define LS1X_UART2_BASE 0x1fe48000 > +#define LS1X_UART3_BASE 0x1fe4c000 > +#define LS1X_CAN0_BASE 0x1fe50000 > +#define LS1X_CAN1_BASE 0x1fe54000 > +#define LS1X_I2C0_BASE 0x1fe58000 > +#define LS1X_I2C1_BASE 0x1fe68000 > +#define LS1X_I2C2_BASE 0x1fe70000 > +#define LS1X_PWM_BASE 0x1fe5c000 > +#define LS1X_WDT_BASE 0x1fe5c060 > +#define LS1X_RTC_BASE 0x1fe64000 > +#define LS1X_AC97_BASE 0x1fe74000 > +#define LS1X_NAND_BASE 0x1fe78000 > +#define LS1X_CLK_BASE 0x1fe78030 > + > +#include > +#include > + > +#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */ > diff --git a/arch/mips/include/asm/mach-loongson1/platform.h > b/arch/mips/include/asm/mach-loongson1/platform.h > new file mode 100644 > index 0000000..2f17161 > --- /dev/null > +++ b/arch/mips/include/asm/mach-loongson1/platform.h > @@ -0,0 +1,23 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > + > +#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H > +#define __ASM_MACH_LOONGSON1_PLATFORM_H > + > +#include > + > +extern struct platform_device ls1x_uart_device; > +extern struct platform_device ls1x_eth0_device; > +extern struct platform_device ls1x_ehci_device; > +extern struct platform_device ls1x_rtc_device; > + > +void ls1x_serial_setup(void); > + > +#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */ > diff --git a/arch/mips/include/asm/mach-loongson1/prom.h > b/arch/mips/include/asm/mach-loongson1/prom.h > new file mode 100644 > index 0000000..b871dc4 > --- /dev/null > +++ b/arch/mips/include/asm/mach-loongson1/prom.h > @@ -0,0 +1,24 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#ifndef __ASM_MACH_LOONGSON1_PROM_H > +#define __ASM_MACH_LOONGSON1_PROM_H > + > +#include > +#include > +#include > + > +/* environment arguments from bootloader */ > +extern unsigned long memsize, highmemsize; > + > +/* loongson-specific command line, env and memory initialization */ > +extern char *prom_getenv(char *name); > +extern void __init prom_init_cmdline(void); > + > +#endif /* __ASM_MACH_LOONGSON1_PROM_H */ > diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h > b/arch/mips/include/asm/mach-loongson1/regs-clk.h > new file mode 100644 > index 0000000..5b9635a > --- /dev/null > +++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h > @@ -0,0 +1,33 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * Loongson1 Clock Register Definitions. > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H > +#define __ASM_MACH_LOONGSON1_REGS_CLK_H > + > +#define LS1X_CLK_REG(x) \ > + ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x))) > + > +#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) > +#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) > + > +/* Clock PLL Divisor Register Bits */ > +#define DIV_DC_EN (0x1 << 31) > +#define DIV_DC (0x1f << 26) > +#define DIV_CPU_EN (0x1 << 25) > +#define DIV_CPU (0x1f << 20) > +#define DIV_DDR_EN (0x1 << 19) > +#define DIV_DDR (0x1f << 14) > + > +#define DIV_DC_SHIFT 26 > +#define DIV_CPU_SHIFT 20 > +#define DIV_DDR_SHIFT 14 > + > +#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */ > diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h > b/arch/mips/include/asm/mach-loongson1/regs-wdt.h > new file mode 100644 > index 0000000..d339fe7 > --- /dev/null > +++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h > @@ -0,0 +1,22 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * Loongson1 Watchdog register definitions. > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H > +#define __ASM_MACH_LOONGSON1_REGS_WDT_H > + > +#define LS1X_WDT_REG(x) \ > + ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x))) > + > +#define LS1X_WDT_EN LS1X_WDT_REG(0x0) > +#define LS1X_WDT_SET LS1X_WDT_REG(0x4) > +#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8) > + > +#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */ > diff --git a/arch/mips/include/asm/mach-loongson1/war.h > b/arch/mips/include/asm/mach-loongson1/war.h > new file mode 100644 > index 0000000..e3680a8 > --- /dev/null > +++ b/arch/mips/include/asm/mach-loongson1/war.h > @@ -0,0 +1,25 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General > Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle > + */ > +#ifndef __ASM_MACH_LOONGSON1_WAR_H > +#define __ASM_MACH_LOONGSON1_WAR_H > + > +#define R4600_V1_INDEX_ICACHEOP_WAR 0 > +#define R4600_V1_HIT_CACHEOP_WAR 0 > +#define R4600_V2_HIT_CACHEOP_WAR 0 > +#define R5432_CP0_INTERRUPT_WAR 0 > +#define BCM1250_M3_WAR 0 > +#define SIBYTE_1956_WAR 0 > +#define MIPS4K_ICACHE_REFILL_WAR 0 > +#define MIPS_CACHE_SYNC_WAR 0 > +#define TX49XX_ICACHE_INDEX_INV_WAR 0 > +#define RM9000_CDEX_SMP_WAR 0 > +#define ICACHE_REFILLS_WORKAROUND_WAR 0 > +#define R10000_LLSC_WAR 0 > +#define MIPS34K_MISSED_ITLB_WAR 0 > + > +#endif /* __ASM_MACH_LOONGSON1_WAR_H */ > diff --git a/arch/mips/loongson1/common/clock.c > b/arch/mips/loongson1/common/clock.c > new file mode 100644 > index 0000000..2d98fb0 > --- /dev/null > +++ b/arch/mips/loongson1/common/clock.c > @@ -0,0 +1,165 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +static LIST_HEAD(clocks); > +static DEFINE_MUTEX(clocks_mutex); > + > +struct clk *clk_get(struct device *dev, const char *name) > +{ > + struct clk *c; > + struct clk *ret = NULL; > + > + mutex_lock(&clocks_mutex); > + list_for_each_entry(c, &clocks, node) { > + if (!strcmp(c->name, name)) { > + ret = c; > + break; > + } > + } > + mutex_unlock(&clocks_mutex); > + > + return ret; > +} > +EXPORT_SYMBOL(clk_get); > + > +unsigned long clk_get_rate(struct clk *clk) > +{ > + return clk->rate; > +} > +EXPORT_SYMBOL(clk_get_rate); > + > +static void pll_clk_init(struct clk *clk) > +{ > + u32 pll; > + > + pll = __raw_readl(LS1X_CLK_PLL_FREQ); > + clk->rate = (12 + (pll & 0x3f)) * 33 / 2 > + + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2; > + clk->rate *= 1000000; > +} > + > +static void cpu_clk_init(struct clk *clk) > +{ > + u32 pll, ctrl; > + > + pll = clk_get_rate(clk->parent); > + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU; > + clk->rate = pll / (ctrl >> DIV_CPU_SHIFT); > +} > + > +static void ddr_clk_init(struct clk *clk) > +{ > + u32 pll, ctrl; > + > + pll = clk_get_rate(clk->parent); > + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR; > + clk->rate = pll / (ctrl >> DIV_DDR_SHIFT); > +} > + > +static void dc_clk_init(struct clk *clk) > +{ > + u32 pll, ctrl; > + > + pll = clk_get_rate(clk->parent); > + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC; > + clk->rate = pll / (ctrl >> DIV_DC_SHIFT); > +} > + > +static struct clk_ops pll_clk_ops = { > + .init = pll_clk_init, > +}; > + > +static struct clk_ops cpu_clk_ops = { > + .init = cpu_clk_init, > +}; > + > +static struct clk_ops ddr_clk_ops = { > + .init = ddr_clk_init, > +}; > + > +static struct clk_ops dc_clk_ops = { > + .init = dc_clk_init, > +}; > + > +static struct clk pll_clk = { > + .name = "pll", > + .ops = &pll_clk_ops, > +}; > + > +static struct clk cpu_clk = { > + .name = "cpu", > + .parent = &pll_clk, > + .ops = &cpu_clk_ops, > +}; > + > +static struct clk ddr_clk = { > + .name = "ddr", > + .parent = &pll_clk, > + .ops = &ddr_clk_ops, > +}; > + > +static struct clk dc_clk = { > + .name = "dc", > + .parent = &pll_clk, > + .ops = &dc_clk_ops, > +}; > + > +int clk_register(struct clk *clk) > +{ > + mutex_lock(&clocks_mutex); > + list_add(&clk->node, &clocks); > + if (clk->ops->init) > + clk->ops->init(clk); > + mutex_unlock(&clocks_mutex); > + > + return 0; > +} > +EXPORT_SYMBOL(clk_register); > + > +static struct clk *ls1x_clks[] = { > + &pll_clk, > + &cpu_clk, > + &ddr_clk, > + &dc_clk, > +}; > + > +int __init ls1x_clock_init(void) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++) > + clk_register(ls1x_clks[i]); > + > + return 0; > +} > + > +void __init plat_time_init(void) > +{ > + struct clk *clk; > + > + /* Initialize LS1X clocks */ > + ls1x_clock_init(); > + > + /* setup mips r4k timer */ > + clk = clk_get(NULL, "cpu"); > + if (IS_ERR(clk)) > + panic("unable to get dc clock, err=%ld", PTR_ERR(clk)); > + > + mips_hpt_frequency = clk_get_rate(clk) / 2; > +} > diff --git a/arch/mips/loongson1/common/irq.c > b/arch/mips/loongson1/common/irq.c > new file mode 100644 > index 0000000..41bc8ff > --- /dev/null > +++ b/arch/mips/loongson1/common/irq.c > @@ -0,0 +1,147 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#include > +#include > +#include > + > +#include > +#include > + > +#define LS1X_INTC_REG(n, x) \ > + ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + > (x))) > + > +#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0) > +#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4) > +#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8) > +#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc) > +#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10) > +#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14) > + > +static void ls1x_irq_ack(struct irq_data *d) > +{ > + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; > + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; > + > + __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) > + | (1 << bit), LS1X_INTC_INTCLR(n)); > +} > + > +static void ls1x_irq_mask(struct irq_data *d) > +{ > + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; > + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; > + > + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) > + & ~(1 << bit), LS1X_INTC_INTIEN(n)); > +} > + > +static void ls1x_irq_mask_ack(struct irq_data *d) > +{ > + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; > + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; > + > + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) > + & ~(1 << bit), LS1X_INTC_INTIEN(n)); > + __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) > + | (1 << bit), LS1X_INTC_INTCLR(n)); > +} > + > +static void ls1x_irq_unmask(struct irq_data *d) > +{ > + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; > + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; > + > + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) > + | (1 << bit), LS1X_INTC_INTIEN(n)); > +} > + > +static struct irq_chip ls1x_irq_chip = { > + .name = "LS1X-INTC", > + .irq_ack = ls1x_irq_ack, > + .irq_mask = ls1x_irq_mask, > + .irq_mask_ack = ls1x_irq_mask_ack, > + .irq_unmask = ls1x_irq_unmask, > +}; > + > +static void ls1x_irq_dispatch(int n) > +{ > + u32 int_status, irq; > + > + /* Get pending sources, masked by current enables */ > + int_status = __raw_readl(LS1X_INTC_INTISR(n)) & > + __raw_readl(LS1X_INTC_INTIEN(n)); > + > + if (int_status) { > + irq = LS1X_IRQ(n, __ffs(int_status)); > + do_IRQ(irq); > + } > +} > + > +asmlinkage void plat_irq_dispatch(void) > +{ > + unsigned int pending; > + > + pending = read_c0_cause() & read_c0_status() & ST0_IM; > + > + if (pending & CAUSEF_IP7) > + do_IRQ(TIMER_IRQ); > + else if (pending & CAUSEF_IP2) > + ls1x_irq_dispatch(0); /* INT0 */ > + else if (pending & CAUSEF_IP3) > + ls1x_irq_dispatch(1); /* INT1 */ > + else if (pending & CAUSEF_IP4) > + ls1x_irq_dispatch(2); /* INT2 */ > + else if (pending & CAUSEF_IP5) > + ls1x_irq_dispatch(3); /* INT3 */ > + else if (pending & CAUSEF_IP6) > + ls1x_irq_dispatch(4); /* INT4 */ > + else > + spurious_interrupt(); > + > +} > + > +struct irqaction cascade_irqaction = { > + .handler = no_action, > + .name = "cascade", > + .flags = IRQF_NO_THREAD, > +}; > + > +static void __init ls1x_irq_init(int base) > +{ > + int n; > + > + /* Disable interrupts and clear pending, > + * setup all IRQs as high level triggered > + */ > + for (n = 0; n < 4; n++) { > + __raw_writel(0x0, LS1X_INTC_INTIEN(n)); > + __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n)); > + __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n)); > + /* set DMA0, DMA1 and DMA2 to edge trigger */ > + __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n)); > + } > + > + > + for (n = base; n < LS1X_IRQS; n++) { > + irq_set_chip_and_handler(n, &ls1x_irq_chip, > + handle_level_irq); > + } > + > + setup_irq(INT0_IRQ, &cascade_irqaction); > + setup_irq(INT1_IRQ, &cascade_irqaction); > + setup_irq(INT2_IRQ, &cascade_irqaction); > + setup_irq(INT3_IRQ, &cascade_irqaction); > +} > + > +void __init arch_init_irq(void) > +{ > + mips_cpu_irq_init(); > + ls1x_irq_init(LS1X_IRQ_BASE); > +} > diff --git a/arch/mips/loongson1/common/platform.c > b/arch/mips/loongson1/common/platform.c > new file mode 100644 > index 0000000..e92d59c > --- /dev/null > +++ b/arch/mips/loongson1/common/platform.c > @@ -0,0 +1,124 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define LS1X_UART(_id) \ > + { \ > + .mapbase = LS1X_UART ## _id ## _BASE, \ > + .irq = LS1X_UART ## _id ## _IRQ, \ > + .iotype = UPIO_MEM, \ > + .flags = UPF_IOREMAP | UPF_FIXED_TYPE, \ > + .type = PORT_16550A, \ > + } > + > +static struct plat_serial8250_port ls1x_serial8250_port[] = { > + LS1X_UART(0), > + LS1X_UART(1), > + LS1X_UART(2), > + LS1X_UART(3), > + {}, > +}; > + > +struct platform_device ls1x_uart_device = { > + .name = "serial8250", > + .id = PLAT8250_DEV_PLATFORM, > + .dev = { > + .platform_data = ls1x_serial8250_port, > + }, > +}; > + > +void __init ls1x_serial_setup(void) > +{ > + struct clk *clk; > + struct plat_serial8250_port *p; > + > + clk = clk_get(NULL, "dc"); > + if (IS_ERR(clk)) > + panic("unable to get dc clock, err=%ld", PTR_ERR(clk)); > + > + for (p = ls1x_serial8250_port; p->flags != 0; ++p) > + p->uartclk = clk_get_rate(clk); > +} > + > +/* Synopsys Ethernet GMAC */ > +static struct resource ls1x_eth0_resources[] = { > + [0] = { > + .start = LS1X_GMAC0_BASE, > + .end = LS1X_GMAC0_BASE + SZ_64K - 1, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .name = "macirq", > + .start = LS1X_GMAC0_IRQ, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = { > + .bus_id = 0, > + .phy_mask = 0, > +}; > + > +static struct plat_stmmacenet_data ls1x_eth_data = { > + .bus_id = 0, > + .phy_addr = -1, > + .mdio_bus_data = &ls1x_mdio_bus_data, > + .has_gmac = 1, > + .tx_coe = 1, > +}; > + > +struct platform_device ls1x_eth0_device = { > + .name = "stmmaceth", > + .id = 0, > + .num_resources = ARRAY_SIZE(ls1x_eth0_resources), > + .resource = ls1x_eth0_resources, > + .dev = { > + .platform_data = &ls1x_eth_data, > + }, > +}; > + > +/* USB EHCI */ > +static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32); > + > +static struct resource ls1x_ehci_resources[] = { > + [0] = { > + .start = LS1X_EHCI_BASE, > + .end = LS1X_EHCI_BASE + SZ_32K - 1, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = LS1X_EHCI_IRQ, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +struct platform_device ls1x_ehci_device = { > + .name = "ls1x-ehci", > + .id = -1, > + .num_resources = ARRAY_SIZE(ls1x_ehci_resources), > + .resource = ls1x_ehci_resources, > + .dev = { > + .dma_mask = &ls1x_ehci_dmamask, > + }, > +}; > + > +/* Real Time Clock */ > +struct platform_device ls1x_rtc_device = { > + .name = "ls1x-rtc", > + .id = -1, > +}; > diff --git a/arch/mips/loongson1/common/prom.c > b/arch/mips/loongson1/common/prom.c > new file mode 100644 > index 0000000..1f8e49f > --- /dev/null > +++ b/arch/mips/loongson1/common/prom.c > @@ -0,0 +1,87 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * Modified from arch/mips/pnx833x/common/prom.c. > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#include > +#include > + > +#include > +#include > + > +int prom_argc; > +char **prom_argv, **prom_envp; > +unsigned long memsize, highmemsize; > + > +char *prom_getenv(char *envname) > +{ > + char **env = prom_envp; > + int i; > + > + i = strlen(envname); > + > + while (*env) { > + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') > + return *env + i + 1; > + env++; > + } > + > + return 0; > +} > + > +static inline unsigned long env_or_default(char *env, unsigned long dfl) > +{ > + char *str = prom_getenv(env); > + return str ? simple_strtol(str, 0, 0) : dfl; > +} > + > +void __init prom_init_cmdline(void) > +{ > + char *c = &(arcs_cmdline[0]); > + int i; > + > + for (i = 1; i < prom_argc; i++) { > + strcpy(c, prom_argv[i]); > + c += strlen(prom_argv[i]); > + if (i < prom_argc-1) > + *c++ = ' '; > + } > + *c = 0; > +} > + > +void __init prom_init(void) > +{ > + prom_argc = fw_arg0; > + prom_argv = (char **)fw_arg1; > + prom_envp = (char **)fw_arg2; > + > + prom_init_cmdline(); > + > + memsize = env_or_default("memsize", DEFAULT_MEMSIZE); > + highmemsize = env_or_default("highmemsize", 0x0); > +} > + > +void __init prom_free_prom_memory(void) > +{ > +} > + > +#define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset)) > + > +void __init prom_putchar(char c) > +{ > + int timeout; > + > + timeout = 1024; > + > + while (((readb(PORT(UART_LSR)) & UART_LSR_THRE) == 0) > + && (timeout-- > 0)) > + ; > + > + writeb(c, PORT(UART_TX)); > +} > diff --git a/arch/mips/loongson1/common/reset.c > b/arch/mips/loongson1/common/reset.c > new file mode 100644 > index 0000000..fb979a7 > --- /dev/null > +++ b/arch/mips/loongson1/common/reset.c > @@ -0,0 +1,45 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#include > +#include > +#include > + > +#include > + > +static void ls1x_restart(char *command) > +{ > + __raw_writel(0x1, LS1X_WDT_EN); > + __raw_writel(0x5000000, LS1X_WDT_TIMER); > + __raw_writel(0x1, LS1X_WDT_SET); > +} > + > +static void ls1x_halt(void) > +{ > + while (1) { > + if (cpu_wait) > + cpu_wait(); > + } > +} > + > +static void ls1x_power_off(void) > +{ > + ls1x_halt(); > +} > + > +static int __init ls1x_reboot_setup(void) > +{ > + _machine_restart = ls1x_restart; > + _machine_halt = ls1x_halt; > + pm_power_off = ls1x_power_off; > + > + return 0; > +} > + > +arch_initcall(ls1x_reboot_setup); > diff --git a/arch/mips/loongson1/common/setup.c > b/arch/mips/loongson1/common/setup.c > new file mode 100644 > index 0000000..62128cc > --- /dev/null > +++ b/arch/mips/loongson1/common/setup.c > @@ -0,0 +1,29 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#include > + > +#include > + > +void __init plat_mem_setup(void) > +{ > + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); > +} > + > +const char *get_system_type(void) > +{ > + unsigned int processor_id = (¤t_cpu_data)->processor_id; > + > + switch (processor_id & PRID_REV_MASK) { > + case PRID_REV_LOONGSON1B: > + return "LOONGSON LS1B"; > + default: > + return "LOONGSON (unknown)"; > + } > +} > diff --git a/arch/mips/loongson1/ls1b/board.c > b/arch/mips/loongson1/ls1b/board.c > new file mode 100644 > index 0000000..295b1be > --- /dev/null > +++ b/arch/mips/loongson1/ls1b/board.c > @@ -0,0 +1,33 @@ > +/* > + * Copyright (c) 2011 Zhang, Keguang > + * > + * This program is free software; you can redistribute it and/or modify > it > + * under the terms of the GNU General Public License as published by > the > + * Free Software Foundation; either version 2 of the License, or (at > your > + * option) any later version. > + */ > + > +#include > + > +#include > +#include > + > +static struct platform_device *ls1b_platform_devices[] __initdata = { > + &ls1x_uart_device, > + &ls1x_eth0_device, > + &ls1x_ehci_device, > + &ls1x_rtc_device, > +}; > + > +static int __init ls1b_platform_init(void) > +{ > + int err; > + > + ls1x_serial_setup(); > + > + err = platform_add_devices(ls1b_platform_devices, > + ARRAY_SIZE(ls1b_platform_devices)); > + return err; > +} > + > +arch_initcall(ls1b_platform_init); > -- > 1.7.1 > > -- Best Regards! Kelvin --20cf307f309614995004c594f6b6 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Hi Ralf,

I have submitted "V7 (updated)" for 3 of the 4 pa= tches.
And patch 1 is unchanged.
New bundle is here:
http://patchwork.linux-mips.org/bundle/kelvin/Loongson1B%20support=

2012/7/7 Kelvin Cheung <= ;keguang.zhang= @gmail.com>
This patch adds basic platform devices for Loongson1B,
including serial port, ethernet, usb, rtc and interrupt handler.

Loongson1B UART is compatible with NS16550A.
Loongson1B GMAC is built around Synopsys IP Core.

Use normal descriptor instead of enhanced descriptor.
Thanks to Giuseppe for updating the normal descriptor
in stmmac driver.

Thanks to Zhao Zhang for implementing the RTC driver.

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>

---
V7(updated):
=A0 =A0 =A0 =A0 1.Remove 'ifdef' of platform devices. (Asked by Ral= f)
=A0 =A0 =A0 =A0 2.Modify plat_stmmacenet_data accordingly due to the change=
=A0 =A0 =A0 =A0 =A0 of upstream.
---
=A0arch/mips/include/asm/mach-loongson1/irq.h =A0 =A0 =A0 | =A0 73 ++++++++= ++
=A0arch/mips/include/asm/mach-loongson1/loongson1.h | =A0 44 ++++++
=A0arch/mips/include/asm/mach-loongson1/platform.h =A0| =A0 23 +++
=A0arch/mips/include/asm/mach-loongson1/prom.h =A0 =A0 =A0| =A0 24 +++
=A0arch/mips/include/asm/mach-loongson1/regs-clk.h =A0| =A0 33 +++++
=A0arch/mips/include/asm/mach-loongson1/regs-wdt.h =A0| =A0 22 +++
=A0arch/mips/include/asm/mach-loongson1/war.h =A0 =A0 =A0 | =A0 25 ++++
=A0arch/mips/loongson1/common/clock.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0165 = ++++++++++++++++++++++
=A0arch/mips/loongson1/common/irq.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A014= 7 +++++++++++++++++++
=A0arch/mips/loongson1/common/platform.c =A0 =A0 =A0 =A0 =A0 =A0| =A0124 ++= ++++++++++++++
=A0arch/mips/loongson1/common/prom.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 8= 7 ++++++++++++
=A0arch/mips/loongson1/common/reset.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 45 = ++++++
=A0arch/mips/loongson1/common/setup.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 29 = ++++
=A0arch/mips/loongson1/ls1b/board.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 3= 3 +++++
=A014 files changed, 874 insertions(+), 0 deletions(-)
=A0create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h
=A0create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h
=A0create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h
=A0create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h
=A0create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h
=A0create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h
=A0create mode 100644 arch/mips/include/asm/mach-loongson1/war.h
=A0create mode 100644 arch/mips/loongson1/common/clock.c
=A0create mode 100644 arch/mips/loongson1/common/irq.c
=A0create mode 100644 arch/mips/loongson1/common/platform.c
=A0create mode 100644 arch/mips/loongson1/common/prom.c
=A0create mode 100644 arch/mips/loongson1/common/reset.c
=A0create mode 100644 arch/mips/loongson1/common/setup.c
=A0create mode 100644 arch/mips/loongson1/ls1b/board.c

diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include= /asm/mach-loongson1/irq.h
new file mode 100644
index 0000000..ccc42cc
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * IRQ mappings for Loongson1.
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_IRQ_H
+#define __ASM_MACH_LOONGSON1_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A00
+#define MIPS_CPU_IRQ(x) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(MI= PS_CPU_IRQ_BASE + (x))
+
+#define SOFTINT0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MIPS_CPU_IRQ(0) +#define SOFTINT1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MIPS_CPU_IRQ(1) +#define INT0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MIPS_CPU_IRQ(= 2)
+#define INT1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MIPS_CPU_IRQ(= 3)
+#define INT2_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MIPS_CPU_IRQ(= 4)
+#define INT3_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MIPS_CPU_IRQ(= 5)
+#define INT4_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MIPS_CPU_IRQ(= 6)
+#define TIMER_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0MIPS_CPU_IRQ(= 7) =A0 =A0 =A0 =A0 /* cpu timer */
+
+#define MIPS_CPU_IRQS =A0 =A0 =A0 =A0 =A0(MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_I= RQ_BASE)
+
+/*
+ * INT0~3 Interrupt Numbers
+ */
+#define LS1X_IRQ_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0MIPS_CPU_IRQS
+#define LS1X_IRQ(n, x) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (LS1X_IRQ_BASE + (n= << 5) + (x))
+
+#define LS1X_UART0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_IRQ(0, 2)
+#define LS1X_UART1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_IRQ(0, 3)
+#define LS1X_UART2_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_IRQ(0, 4)
+#define LS1X_UART3_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_IRQ(0, 5)
+#define LS1X_CAN0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 6) +#define LS1X_CAN1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 7) +#define LS1X_SPI0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 8) +#define LS1X_SPI1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 9) +#define LS1X_AC97_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 10) +#define LS1X_DMA0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 13) +#define LS1X_DMA1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 14) +#define LS1X_DMA2_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 15) +#define LS1X_PWM0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 17) +#define LS1X_PWM1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 18) +#define LS1X_PWM2_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 19) +#define LS1X_PWM3_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 20) +#define LS1X_RTC_INT0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 21)
+#define LS1X_RTC_INT1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 22)
+#define LS1X_RTC_INT2_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 23)
+#define LS1X_TOY_INT0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 24)
+#define LS1X_TOY_INT1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 25)
+#define LS1X_TOY_INT2_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 26)
+#define LS1X_RTC_TICK_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 27)
+#define LS1X_TOY_TICK_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(0, 28)
+
+#define LS1X_EHCI_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(1, 0) +#define LS1X_OHCI_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_IRQ(1, 1) +#define LS1X_GMAC0_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_IRQ(1, 2)
+#define LS1X_GMAC1_IRQ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_IRQ(1, 3)
+
+#define LS1X_IRQS =A0 =A0 =A0 =A0 =A0 =A0 =A0(LS1X_IRQ(4, 31) + 1 - LS1X_I= RQ_BASE)
+
+#define NR_IRQS =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(MIPS_CPU_I= RQS + LS1X_IRQS)
+
+#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/i= nclude/asm/mach-loongson1/loongson1.h
new file mode 100644
index 0000000..0440627
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Register mappings for Loongson1.
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
+#define __ASM_MACH_LOONGSON1_LOONGSON1_H
+
+#define DEFAULT_MEMSIZE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0256= =A0 =A0 /* If no memsize provided */
+
+/* Loongson1 Register Bases */
+#define LS1X_INTC_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fd01040
+#define LS1X_EHCI_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe00000
+#define LS1X_OHCI_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe08000
+#define LS1X_GMAC0_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1= fe10000
+#define LS1X_GMAC1_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1= fe20000
+
+#define LS1X_UART0_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1= fe40000
+#define LS1X_UART1_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1= fe44000
+#define LS1X_UART2_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1= fe48000
+#define LS1X_UART3_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1= fe4c000
+#define LS1X_CAN0_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe50000
+#define LS1X_CAN1_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe54000
+#define LS1X_I2C0_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe58000
+#define LS1X_I2C1_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe68000
+#define LS1X_I2C2_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe70000
+#define LS1X_PWM_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1fe5c000
+#define LS1X_WDT_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1fe5c060
+#define LS1X_RTC_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1fe64000
+#define LS1X_AC97_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe74000
+#define LS1X_NAND_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x1fe78000
+#define LS1X_CLK_BASE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x1fe78030
+
+#include <regs-clk.h>
+#include <regs-wdt.h>
+
+#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/in= clude/asm/mach-loongson1/platform.h
new file mode 100644
index 0000000..2f17161
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H
+#define __ASM_MACH_LOONGSON1_PLATFORM_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device ls1x_uart_device;
+extern struct platform_device ls1x_eth0_device;
+extern struct platform_device ls1x_ehci_device;
+extern struct platform_device ls1x_rtc_device;
+
+void ls1x_serial_setup(void);
+
+#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/includ= e/asm/mach-loongson1/prom.h
new file mode 100644
index 0000000..b871dc4
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/prom.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_PROM_H
+#define __ASM_MACH_LOONGSON1_PROM_H
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+/* environment arguments from bootloader */
+extern unsigned long memsize, highmemsize;
+
+/* loongson-specific command line, env and memory initialization */
+extern char *prom_getenv(char *name);
+extern void __init prom_init_cmdline(void);
+
+#endif /* __ASM_MACH_LOONGSON1_PROM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/in= clude/asm/mach-loongson1/regs-clk.h
new file mode 100644
index 0000000..5b9635a
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson1 Clock Register Definitions.
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
+#define __ASM_MACH_LOONGSON1_REGS_CLK_H
+
+#define LS1X_CLK_REG(x) \
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x= )))
+
+#define LS1X_CLK_PLL_FREQ =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_CLK_REG(0x0)
+#define LS1X_CLK_PLL_DIV =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_CLK_REG(0x4)
+
+/* Clock PLL Divisor Register Bits */
+#define DIV_DC_EN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(0x1 <<= 31)
+#define DIV_DC =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (0x1f <&= lt; 26)
+#define DIV_CPU_EN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (0x1 << 2= 5)
+#define DIV_CPU =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0(0x1f << 20)
+#define DIV_DDR_EN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (0x1 << 1= 9)
+#define DIV_DDR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0(0x1f << 14)
+
+#define DIV_DC_SHIFT =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 26
+#define DIV_CPU_SHIFT =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A020
+#define DIV_DDR_SHIFT =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A014
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/in= clude/asm/mach-loongson1/regs-wdt.h
new file mode 100644
index 0000000..d339fe7
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson1 Watchdog register definitions.
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
+#define __ASM_MACH_LOONGSON1_REGS_WDT_H
+
+#define LS1X_WDT_REG(x) \
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x= )))
+
+#define LS1X_WDT_EN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LS1X_WDT_REG(0x= 0)
+#define LS1X_WDT_SET =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_WDT_REG(0x4)=
+#define LS1X_WDT_TIMER =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LS1X_WDT_REG(0x8) +
+#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include= /asm/mach-loongson1/war.h
new file mode 100644
index 0000000..e3680a8
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Pub= lic
+ * License. =A0See the file "COPYING" in the main directory of t= his archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_LOONGSON1_WAR_H
+#define __ASM_MACH_LOONGSON1_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR =A0 =A00
+#define R4600_V1_HIT_CACHEOP_WAR =A0 =A0 =A0 0
+#define R4600_V2_HIT_CACHEOP_WAR =A0 =A0 =A0 0
+#define R5432_CP0_INTERRUPT_WAR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00
+#define BCM1250_M3_WAR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0
+#define SIBYTE_1956_WAR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00 +#define MIPS4K_ICACHE_REFILL_WAR =A0 =A0 =A0 0
+#define MIPS_CACHE_SYNC_WAR =A0 =A0 =A0 =A0 =A0 =A00
+#define TX49XX_ICACHE_INDEX_INV_WAR =A0 =A00
+#define RM9000_CDEX_SMP_WAR =A0 =A0 =A0 =A0 =A0 =A00
+#define ICACHE_REFILLS_WORKAROUND_WAR =A00
+#define R10000_LLSC_WAR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00 +#define MIPS34K_MISSED_ITLB_WAR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00
+
+#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/commo= n/clock.c
new file mode 100644
index 0000000..2d98fb0
--- /dev/null
+++ b/arch/mips/loongson1/common/clock.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm/clock.h>
+#include <asm/time.h>
+
+#include <loongson1.h>
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+struct clk *clk_get(struct device *dev, const char *name)
+{
+ =A0 =A0 =A0 struct clk *c;
+ =A0 =A0 =A0 struct clk *ret =3D NULL;
+
+ =A0 =A0 =A0 mutex_lock(&clocks_mutex);
+ =A0 =A0 =A0 list_for_each_entry(c, &clocks, node) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!strcmp(c->name, name)) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ret =3D c;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
+ =A0 =A0 =A0 }
+ =A0 =A0 =A0 mutex_unlock(&clocks_mutex);
+
+ =A0 =A0 =A0 return ret;
+}
+EXPORT_SYMBOL(clk_get);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ =A0 =A0 =A0 return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+static void pll_clk_init(struct clk *clk)
+{
+ =A0 =A0 =A0 u32 pll;
+
+ =A0 =A0 =A0 pll =3D __raw_readl(LS1X_CLK_PLL_FREQ);
+ =A0 =A0 =A0 clk->rate =3D (12 + (pll & 0x3f)) * 33 / 2
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 + ((pll >> 8) & 0x3= ff) * 33 / 1024 / 2;
+ =A0 =A0 =A0 clk->rate *=3D 1000000;
+}
+
+static void cpu_clk_init(struct clk *clk)
+{
+ =A0 =A0 =A0 u32 pll, ctrl;
+
+ =A0 =A0 =A0 pll =3D clk_get_rate(clk->parent);
+ =A0 =A0 =A0 ctrl =3D __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
+ =A0 =A0 =A0 clk->rate =3D pll / (ctrl >> DIV_CPU_SHIFT);
+}
+
+static void ddr_clk_init(struct clk *clk)
+{
+ =A0 =A0 =A0 u32 pll, ctrl;
+
+ =A0 =A0 =A0 pll =3D clk_get_rate(clk->parent);
+ =A0 =A0 =A0 ctrl =3D __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
+ =A0 =A0 =A0 clk->rate =3D pll / (ctrl >> DIV_DDR_SHIFT);
+}
+
+static void dc_clk_init(struct clk *clk)
+{
+ =A0 =A0 =A0 u32 pll, ctrl;
+
+ =A0 =A0 =A0 pll =3D clk_get_rate(clk->parent);
+ =A0 =A0 =A0 ctrl =3D __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
+ =A0 =A0 =A0 clk->rate =3D pll / (ctrl >> DIV_DC_SHIFT);
+}
+
+static struct clk_ops pll_clk_ops =3D {
+ =A0 =A0 =A0 .init =A0 =3D pll_clk_init,
+};
+
+static struct clk_ops cpu_clk_ops =3D {
+ =A0 =A0 =A0 .init =A0 =3D cpu_clk_init,
+};
+
+static struct clk_ops ddr_clk_ops =3D {
+ =A0 =A0 =A0 .init =A0 =3D ddr_clk_init,
+};
+
+static struct clk_ops dc_clk_ops =3D {
+ =A0 =A0 =A0 .init =A0 =3D dc_clk_init,
+};
+
+static struct clk pll_clk =3D {
+ =A0 =A0 =A0 .name =A0 =3D "pll",
+ =A0 =A0 =A0 .ops =A0 =A0=3D &pll_clk_ops,
+};
+
+static struct clk cpu_clk =3D {
+ =A0 =A0 =A0 .name =A0 =3D "cpu",
+ =A0 =A0 =A0 .parent =3D &pll_clk,
+ =A0 =A0 =A0 .ops =A0 =A0=3D &cpu_clk_ops,
+};
+
+static struct clk ddr_clk =3D {
+ =A0 =A0 =A0 .name =A0 =3D "ddr",
+ =A0 =A0 =A0 .parent =3D &pll_clk,
+ =A0 =A0 =A0 .ops =A0 =A0=3D &ddr_clk_ops,
+};
+
+static struct clk dc_clk =3D {
+ =A0 =A0 =A0 .name =A0 =3D "dc",
+ =A0 =A0 =A0 .parent =3D &pll_clk,
+ =A0 =A0 =A0 .ops =A0 =A0=3D &dc_clk_ops,
+};
+
+int clk_register(struct clk *clk)
+{
+ =A0 =A0 =A0 mutex_lock(&clocks_mutex);
+ =A0 =A0 =A0 list_add(&clk->node, &clocks);
+ =A0 =A0 =A0 if (clk->ops->init)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk->ops->init(clk);
+ =A0 =A0 =A0 mutex_unlock(&clocks_mutex);
+
+ =A0 =A0 =A0 return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+static struct clk *ls1x_clks[] =3D {
+ =A0 =A0 =A0 &pll_clk,
+ =A0 =A0 =A0 &cpu_clk,
+ =A0 =A0 =A0 &ddr_clk,
+ =A0 =A0 =A0 &dc_clk,
+};
+
+int __init ls1x_clock_init(void)
+{
+ =A0 =A0 =A0 int i;
+
+ =A0 =A0 =A0 for (i =3D 0; i < ARRAY_SIZE(ls1x_clks); i++)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk_register(ls1x_clks[i]);
+
+ =A0 =A0 =A0 return 0;
+}
+
+void __init plat_time_init(void)
+{
+ =A0 =A0 =A0 struct clk *clk;
+
+ =A0 =A0 =A0 /* Initialize LS1X clocks */
+ =A0 =A0 =A0 ls1x_clock_init();
+
+ =A0 =A0 =A0 /* setup mips r4k timer */
+ =A0 =A0 =A0 clk =3D clk_get(NULL, "cpu");
+ =A0 =A0 =A0 if (IS_ERR(clk))
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 panic("unable to get dc clock, err=3D%ld= ", PTR_ERR(clk));
+
+ =A0 =A0 =A0 mips_hpt_frequency =3D clk_get_rate(clk) / 2;
+}
diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/= irq.c
new file mode 100644
index 0000000..41bc8ff
--- /dev/null
+++ b/arch/mips/loongson1/common/irq.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/irq_cpu.h>
+
+#include <loongson1.h>
+#include <irq.h>
+
+#define LS1X_INTC_REG(n, x) \
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (= n * 0x18) + (x)))
+
+#define LS1X_INTC_INTISR(n) =A0 =A0 =A0 =A0 =A0 =A0LS1X_INTC_REG(n, 0x0) +#define LS1X_INTC_INTIEN(n) =A0 =A0 =A0 =A0 =A0 =A0LS1X_INTC_REG(n, 0x4) +#define LS1X_INTC_INTSET(n) =A0 =A0 =A0 =A0 =A0 =A0LS1X_INTC_REG(n, 0x8) +#define LS1X_INTC_INTCLR(n) =A0 =A0 =A0 =A0 =A0 =A0LS1X_INTC_REG(n, 0xc) +#define LS1X_INTC_INTPOL(n) =A0 =A0 =A0 =A0 =A0 =A0LS1X_INTC_REG(n, 0x10)<= br> +#define LS1X_INTC_INTEDGE(n) =A0 =A0 =A0 =A0 =A0 LS1X_INTC_REG(n, 0x14) +
+static void ls1x_irq_ack(struct irq_data *d)
+{
+ =A0 =A0 =A0 unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f;<= br> + =A0 =A0 =A0 unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; +
+ =A0 =A0 =A0 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | (1 << bit), LS1X_INTC= _INTCLR(n));
+}
+
+static void ls1x_irq_mask(struct irq_data *d)
+{
+ =A0 =A0 =A0 unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f;<= br> + =A0 =A0 =A0 unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; +
+ =A0 =A0 =A0 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 & ~(1 << bit), LS1X= _INTC_INTIEN(n));
+}
+
+static void ls1x_irq_mask_ack(struct irq_data *d)
+{
+ =A0 =A0 =A0 unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f;<= br> + =A0 =A0 =A0 unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; +
+ =A0 =A0 =A0 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 & ~(1 << bit), LS1X= _INTC_INTIEN(n));
+ =A0 =A0 =A0 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | (1 << bit), LS1X_INTC= _INTCLR(n));
+}
+
+static void ls1x_irq_unmask(struct irq_data *d)
+{
+ =A0 =A0 =A0 unsigned int bit =3D (d->irq - LS1X_IRQ_BASE) & 0x1f;<= br> + =A0 =A0 =A0 unsigned int n =3D (d->irq - LS1X_IRQ_BASE) >> 5; +
+ =A0 =A0 =A0 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | (1 << bit), LS1X_INTC= _INTIEN(n));
+}
+
+static struct irq_chip ls1x_irq_chip =3D {
+ =A0 =A0 =A0 .name =A0 =A0 =A0 =A0 =A0 =3D "LS1X-INTC",
+ =A0 =A0 =A0 .irq_ack =A0 =A0 =A0 =A0=3D ls1x_irq_ack,
+ =A0 =A0 =A0 .irq_mask =A0 =A0 =A0 =3D ls1x_irq_mask,
+ =A0 =A0 =A0 .irq_mask_ack =A0 =3D ls1x_irq_mask_ack,
+ =A0 =A0 =A0 .irq_unmask =A0 =A0 =3D ls1x_irq_unmask,
+};
+
+static void ls1x_irq_dispatch(int n)
+{
+ =A0 =A0 =A0 u32 int_status, irq;
+
+ =A0 =A0 =A0 /* Get pending sources, masked by current enables */
+ =A0 =A0 =A0 int_status =3D __raw_readl(LS1X_INTC_INTISR(n)) &
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 __raw_readl(LS1X_INTC_INTIEN(= n));
+
+ =A0 =A0 =A0 if (int_status) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 irq =3D LS1X_IRQ(n, __ffs(int_status));
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 do_IRQ(irq);
+ =A0 =A0 =A0 }
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ =A0 =A0 =A0 unsigned int pending;
+
+ =A0 =A0 =A0 pending =3D read_c0_cause() & read_c0_status() & ST0_= IM;
+
+ =A0 =A0 =A0 if (pending & CAUSEF_IP7)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 do_IRQ(TIMER_IRQ);
+ =A0 =A0 =A0 else if (pending & CAUSEF_IP2)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ls1x_irq_dispatch(0); /* INT0 */
+ =A0 =A0 =A0 else if (pending & CAUSEF_IP3)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ls1x_irq_dispatch(1); /* INT1 */
+ =A0 =A0 =A0 else if (pending & CAUSEF_IP4)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ls1x_irq_dispatch(2); /* INT2 */
+ =A0 =A0 =A0 else if (pending & CAUSEF_IP5)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ls1x_irq_dispatch(3); /* INT3 */
+ =A0 =A0 =A0 else if (pending & CAUSEF_IP6)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ls1x_irq_dispatch(4); /* INT4 */
+ =A0 =A0 =A0 else
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 spurious_interrupt();
+
+}
+
+struct irqaction cascade_irqaction =3D {
+ =A0 =A0 =A0 .handler =3D no_action,
+ =A0 =A0 =A0 .name =3D "cascade",
+ =A0 =A0 =A0 .flags =3D IRQF_NO_THREAD,
+};
+
+static void __init ls1x_irq_init(int base)
+{
+ =A0 =A0 =A0 int n;
+
+ =A0 =A0 =A0 /* Disable interrupts and clear pending,
+ =A0 =A0 =A0 =A0* setup all IRQs as high level triggered
+ =A0 =A0 =A0 =A0*/
+ =A0 =A0 =A0 for (n =3D 0; n < 4; n++) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 __raw_writel(0x0, LS1X_INTC_INTIEN(n));
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n))= ;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n))= ;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* set DMA0, DMA1 and DMA2 to edge trigger */=
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTE= DGE(n));
+ =A0 =A0 =A0 }
+
+
+ =A0 =A0 =A0 for (n =3D base; n < LS1X_IRQS; n++) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 irq_set_chip_and_handler(n, &ls1x_irq_chi= p,
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0handle_level_irq);
+ =A0 =A0 =A0 }
+
+ =A0 =A0 =A0 setup_irq(INT0_IRQ, &cascade_irqaction);
+ =A0 =A0 =A0 setup_irq(INT1_IRQ, &cascade_irqaction);
+ =A0 =A0 =A0 setup_irq(INT2_IRQ, &cascade_irqaction);
+ =A0 =A0 =A0 setup_irq(INT3_IRQ, &cascade_irqaction);
+}
+
+void __init arch_init_irq(void)
+{
+ =A0 =A0 =A0 mips_cpu_irq_init();
+ =A0 =A0 =A0 ls1x_irq_init(LS1X_IRQ_BASE);
+}
diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/co= mmon/platform.c
new file mode 100644
index 0000000..e92d59c
--- /dev/null
+++ b/arch/mips/loongson1/common/platform.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/phy.h>
+#include <linux/serial_8250.h>
+#include <linux/stmmac.h>
+#include <asm-generic/sizes.h>
+
+#include <loongson1.h>
+
+#define LS1X_UART(_id) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
+ =A0 =A0 =A0 { =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .mapbase =A0 =A0 =A0 =A0=3D LS1X_UART ## _id = ## _BASE, =A0 =A0\
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .irq =A0 =A0 =A0 =A0 =A0 =A0=3D LS1X_UART ## = _id ## _IRQ, =A0 =A0 \
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .iotype =A0 =A0 =A0 =A0 =3D UPIO_MEM, =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .flags =A0 =A0 =A0 =A0 =A0=3D UPF_IOREMAP | U= PF_FIXED_TYPE, \
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .type =A0 =A0 =A0 =A0 =A0 =3D PORT_16550A, = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
+ =A0 =A0 =A0 }
+
+static struct plat_serial8250_port ls1x_serial8250_port[] =3D {
+ =A0 =A0 =A0 LS1X_UART(0),
+ =A0 =A0 =A0 LS1X_UART(1),
+ =A0 =A0 =A0 LS1X_UART(2),
+ =A0 =A0 =A0 LS1X_UART(3),
+ =A0 =A0 =A0 {},
+};
+
+struct platform_device ls1x_uart_device =3D {
+ =A0 =A0 =A0 .name =A0 =A0 =A0 =A0 =A0 =3D "serial8250",
+ =A0 =A0 =A0 .id =A0 =A0 =A0 =A0 =A0 =A0 =3D PLAT8250_DEV_PLATFORM,
+ =A0 =A0 =A0 .dev =A0 =A0 =A0 =A0 =A0 =A0=3D {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .platform_data =3D ls1x_serial8250_port,
+ =A0 =A0 =A0 },
+};
+
+void __init ls1x_serial_setup(void)
+{
+ =A0 =A0 =A0 struct clk *clk;
+ =A0 =A0 =A0 struct plat_serial8250_port *p;
+
+ =A0 =A0 =A0 clk =3D clk_get(NULL, "dc");
+ =A0 =A0 =A0 if (IS_ERR(clk))
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 panic("unable to get dc clock, err=3D%ld= ", PTR_ERR(clk));
+
+ =A0 =A0 =A0 for (p =3D ls1x_serial8250_port; p->flags !=3D 0; ++p)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 p->uartclk =3D clk_get_rate(clk);
+}
+
+/* Synopsys Ethernet GMAC */
+static struct resource ls1x_eth0_resources[] =3D {
+ =A0 =A0 =A0 [0] =3D {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .start =A0=3D LS1X_GMAC0_BASE,
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .end =A0 =A0=3D LS1X_GMAC0_BASE + SZ_64K - 1,=
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .flags =A0=3D IORESOURCE_MEM,
+ =A0 =A0 =A0 },
+ =A0 =A0 =A0 [1] =3D {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .name =A0 =3D "macirq",
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .start =A0=3D LS1X_GMAC0_IRQ,
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .flags =A0=3D IORESOURCE_IRQ,
+ =A0 =A0 =A0 },
+};
+
+static struct stmmac_mdio_bus_data ls1x_mdio_bus_data =3D {
+ =A0 =A0 =A0 .bus_id =A0 =A0 =A0 =A0 =3D 0,
+ =A0 =A0 =A0 .phy_mask =A0 =A0 =A0 =3D 0,
+};
+
+static struct plat_stmmacenet_data ls1x_eth_data =3D {
+ =A0 =A0 =A0 .bus_id =A0 =A0 =A0 =A0 =3D 0,
+ =A0 =A0 =A0 .phy_addr =A0 =A0 =A0 =3D -1,
+ =A0 =A0 =A0 .mdio_bus_data =A0=3D &ls1x_mdio_bus_data,
+ =A0 =A0 =A0 .has_gmac =A0 =A0 =A0 =3D 1,
+ =A0 =A0 =A0 .tx_coe =A0 =A0 =A0 =A0 =3D 1,
+};
+
+struct platform_device ls1x_eth0_device =3D {
+ =A0 =A0 =A0 .name =A0 =A0 =A0 =A0 =A0 =3D "stmmaceth",
+ =A0 =A0 =A0 .id =A0 =A0 =A0 =A0 =A0 =A0 =3D 0,
+ =A0 =A0 =A0 .num_resources =A0=3D ARRAY_SIZE(ls1x_eth0_resources),
+ =A0 =A0 =A0 .resource =A0 =A0 =A0 =3D ls1x_eth0_resources,
+ =A0 =A0 =A0 .dev =A0 =A0 =A0 =A0 =A0 =A0=3D {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .platform_data =3D &ls1x_eth_data,
+ =A0 =A0 =A0 },
+};
+
+/* USB EHCI */
+static u64 ls1x_ehci_dmamask =3D DMA_BIT_MASK(32);
+
+static struct resource ls1x_ehci_resources[] =3D {
+ =A0 =A0 =A0 [0] =3D {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .start =A0=3D LS1X_EHCI_BASE,
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .end =A0 =A0=3D LS1X_EHCI_BASE + SZ_32K - 1,<= br> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 .flags =A0=3D IORESOURCE_MEM,
+ =A0 =A0 =A0 },
+ =A0 =A0 =A0 [1] =3D {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .start =A0=3D LS1X_EHCI_IRQ,
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .flags =A0=3D IORESOURCE_IRQ,
+ =A0 =A0 =A0 },
+};
+
+struct platform_device ls1x_ehci_device =3D {
+ =A0 =A0 =A0 .name =A0 =A0 =A0 =A0 =A0 =3D "ls1x-ehci",
+ =A0 =A0 =A0 .id =A0 =A0 =A0 =A0 =A0 =A0 =3D -1,
+ =A0 =A0 =A0 .num_resources =A0=3D ARRAY_SIZE(ls1x_ehci_resources),
+ =A0 =A0 =A0 .resource =A0 =A0 =A0 =3D ls1x_ehci_resources,
+ =A0 =A0 =A0 .dev =A0 =A0 =A0 =A0 =A0 =A0=3D {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 .dma_mask =3D &ls1x_ehci_dmamask,
+ =A0 =A0 =A0 },
+};
+
+/* Real Time Clock */
+struct platform_device ls1x_rtc_device =3D {
+ =A0 =A0 =A0 .name =A0 =A0 =A0 =A0 =A0 =3D "ls1x-rtc",
+ =A0 =A0 =A0 .id =A0 =A0 =A0 =A0 =A0 =A0 =3D -1,
+};
diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common= /prom.c
new file mode 100644
index 0000000..1f8e49f
--- /dev/null
+++ b/arch/mips/loongson1/common/prom.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Modified from arch/mips/pnx833x/common/prom.c.
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/bootinfo.h>
+
+#include <loongson1.h>
+#include <prom.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+unsigned long memsize, highmemsize;
+
+char *prom_getenv(char *envname)
+{
+ =A0 =A0 =A0 char **env =3D prom_envp;
+ =A0 =A0 =A0 int i;
+
+ =A0 =A0 =A0 i =3D strlen(envname);
+
+ =A0 =A0 =A0 while (*env) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (strncmp(envname, *env, i) =3D=3D 0 &&= amp; *(*env+i) =3D=3D '=3D')
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 return *env + i + 1;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 env++;
+ =A0 =A0 =A0 }
+
+ =A0 =A0 =A0 return 0;
+}
+
+static inline unsigned long env_or_default(char *env, unsigned long dfl) +{
+ =A0 =A0 =A0 char *str =3D prom_getenv(env);
+ =A0 =A0 =A0 return str ? simple_strtol(str, 0, 0) : dfl;
+}
+
+void __init prom_init_cmdline(void)
+{
+ =A0 =A0 =A0 char *c =3D &(arcs_cmdline[0]);
+ =A0 =A0 =A0 int i;
+
+ =A0 =A0 =A0 for (i =3D 1; i < prom_argc; i++) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 strcpy(c, prom_argv[i]);
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 c +=3D strlen(prom_argv[i]);
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (i < prom_argc-1)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 *c++ =3D ' ';
+ =A0 =A0 =A0 }
+ =A0 =A0 =A0 *c =3D 0;
+}
+
+void __init prom_init(void)
+{
+ =A0 =A0 =A0 prom_argc =3D fw_arg0;
+ =A0 =A0 =A0 prom_argv =3D (char **)fw_arg1;
+ =A0 =A0 =A0 prom_envp =3D (char **)fw_arg2;
+
+ =A0 =A0 =A0 prom_init_cmdline();
+
+ =A0 =A0 =A0 memsize =3D env_or_default("memsize", DEFAULT_MEMSI= ZE);
+ =A0 =A0 =A0 highmemsize =3D env_or_default("highmemsize", 0x0);=
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+#define PORT(offset) =A0 (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset))
+
+void __init prom_putchar(char c)
+{
+ =A0 =A0 =A0 int timeout;
+
+ =A0 =A0 =A0 timeout =3D 1024;
+
+ =A0 =A0 =A0 while (((readb(PORT(UART_LSR)) & UART_LSR_THRE) =3D=3D 0)=
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 && (timeout-- > 0)= )
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 ;
+
+ =A0 =A0 =A0 writeb(c, PORT(UART_TX));
+}
diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/commo= n/reset.c
new file mode 100644
index 0000000..fb979a7
--- /dev/null
+++ b/arch/mips/loongson1/common/reset.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+#include <asm/reboot.h>
+
+#include <loongson1.h>
+
+static void ls1x_restart(char *command)
+{
+ =A0 =A0 =A0 __raw_writel(0x1, LS1X_WDT_EN);
+ =A0 =A0 =A0 __raw_writel(0x5000000, LS1X_WDT_TIMER);
+ =A0 =A0 =A0 __raw_writel(0x1, LS1X_WDT_SET);
+}
+
+static void ls1x_halt(void)
+{
+ =A0 =A0 =A0 while (1) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (cpu_wait)
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cpu_wait();
+ =A0 =A0 =A0 }
+}
+
+static void ls1x_power_off(void)
+{
+ =A0 =A0 =A0 ls1x_halt();
+}
+
+static int __init ls1x_reboot_setup(void)
+{
+ =A0 =A0 =A0 _machine_restart =3D ls1x_restart;
+ =A0 =A0 =A0 _machine_halt =3D ls1x_halt;
+ =A0 =A0 =A0 pm_power_off =3D ls1x_power_off;
+
+ =A0 =A0 =A0 return 0;
+}
+
+arch_initcall(ls1x_reboot_setup);
diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/commo= n/setup.c
new file mode 100644
index 0000000..62128cc
--- /dev/null
+++ b/arch/mips/loongson1/common/setup.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#include <asm/bootinfo.h>
+
+#include <prom.h>
+
+void __init plat_mem_setup(void)
+{
+ =A0 =A0 =A0 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);<= br> +}
+
+const char *get_system_type(void)
+{
+ =A0 =A0 =A0 unsigned int processor_id =3D (&current_cpu_data)->pro= cessor_id;
+
+ =A0 =A0 =A0 switch (processor_id & PRID_REV_MASK) {
+ =A0 =A0 =A0 case PRID_REV_LOONGSON1B:
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 return "LOONGSON LS1B";
+ =A0 =A0 =A0 default:
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 return "LOONGSON (unknown)";
+ =A0 =A0 =A0 }
+}
diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/bo= ard.c
new file mode 100644
index 0000000..295b1be
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/board.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute =A0it and/or modify= it
+ * under =A0the terms of =A0the GNU General =A0Public License as published= by the
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (at= your
+ * option) any later version.
+ */
+
+#include <platform.h>
+
+#include <linux/serial_8250.h>
+#include <loongson1.h>
+
+static struct platform_device *ls1b_platform_devices[] __initdata =3D { + =A0 =A0 =A0 &ls1x_uart_device,
+ =A0 =A0 =A0 &ls1x_eth0_device,
+ =A0 =A0 =A0 &ls1x_ehci_device,
+ =A0 =A0 =A0 &ls1x_rtc_device,
+};
+
+static int __init ls1b_platform_init(void)
+{
+ =A0 =A0 =A0 int err;
+
+ =A0 =A0 =A0 ls1x_serial_setup();
+
+ =A0 =A0 =A0 err =3D platform_add_devices(ls1b_platform_devices,
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ARRAY_= SIZE(ls1b_platform_devices));
+ =A0 =A0 =A0 return err;
+}
+
+arch_initcall(ls1b_platform_init);
--
1.7.1




--
Best Rega= rds!
Kelvin



--20cf307f309614995004c594f6b6-- From br1@einfach.org Tue Jul 24 17:25:43 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 17:25:48 +0200 (CEST) Received: from postler.einfach.org ([86.59.21.13]:55372 "EHLO postler.einfach.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903773Ab2GXPZn (ORCPT ); Tue, 24 Jul 2012 17:25:43 +0200 Received: from [192.168.2.106] (217.Red-88-23-52.staticIP.rima-tde.net [88.23.52.217]) by postler.einfach.org (Postfix) with ESMTPSA id 881BE21421EB; Tue, 24 Jul 2012 17:25:37 +0200 (CEST) Message-ID: <500EBE6F.5030208@einfach.org> Date: Tue, 24 Jul 2012 16:25:35 +0100 From: Bruno Randolf User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Manuel Lauss CC: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org, florian@openwrt.org Subject: Re: [PATCH] mtx-1: add udelay to mtx1_pci_idsel References: <1342126445-13408-1-git-send-email-br1@einfach.org> <500EBB99.5050209@einfach.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 33966 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: br1@einfach.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2891 Lines: 81 On 07/24/2012 04:20 PM, Manuel Lauss wrote: > On Tue, Jul 24, 2012 at 5:13 PM, Bruno Randolf wrote: >> Hello? Any feedback? >> >> I know the description is not very good, but this patch is necessary for PCI >> to work on the Surfbox. >> >> Thanks, >> bruno >> >> >> On 07/12/2012 09:54 PM, Bruno Randolf wrote: >>> >>> Without this udelay(1) PCI idsel does not work correctly on the >>> "singleboard" >>> (T-Mobile Surfbox) for the MiniPCI device. The result is that PCI >>> configuration >>> fails and the MiniPCI card is not detected correctly. Instead of >>> >>> PCI host bridge to bus 0000:00 >>> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >>> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >>> pci 0000:00:03.0: BAR 0: assigned [mem 0x40000000-0x4000ffff] >>> pci 0000:00:00.0: BAR 0: assigned [mem 0x40010000-0x40010fff] >>> pci 0000:00:00.1: BAR 0: assigned [mem 0x40011000-0x40011fff] >>> >>> We see only the CardBus device: >>> >>> PCI host bridge to bus 0000:00 >>> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >>> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >>> pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x40000fff] >>> pci 0000:00:00.1: BAR 0: assigned [mem 0x40001000-0x40001fff] >>> >>> Later the device driver shows this error: >>> >>> ath5k 0000:00:03.0: cannot remap PCI memory region >>> ath5k: probe of 0000:00:03.0 failed with error -5 >>> >>> I assume that the logic chip which usually supresses the signal to the >>> CardBus >>> card has some settling time and without the delay it would still let the >>> Cardbus interfere with the response from the MiniPCI card. >>> >>> What I cannot explain is why this behaviour shows up now and not in >>> earlier >>> kernel versions before. Maybe older PCI code was slower? >>> >>> Signed-off-by: Bruno Randolf >>> --- >>> arch/mips/alchemy/board-mtx1.c | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/arch/mips/alchemy/board-mtx1.c >>> b/arch/mips/alchemy/board-mtx1.c >>> index 295f1a9..e107a2f 100644 >>> --- a/arch/mips/alchemy/board-mtx1.c >>> +++ b/arch/mips/alchemy/board-mtx1.c >>> @@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int >>> assert) >>> * adapter on the mtx-1 "singleboard" variant. It triggers a >>> custom >>> * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL >>> signals. >>> */ >>> + udelay(1); >>> + >>> if (assert && devsel != 0) >>> /* Suppress signal to Cardbus */ >>> alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ >>> > > Why don't you increase the delay value in the udelay() immediately following > this part? Yes that would be logical and was my first try. Unfortunately it does not work. It's weird, but the delay needs to be before as well. bruno From manuel.lauss@gmail.com Tue Jul 24 17:37:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 17:37:12 +0200 (CEST) Received: from mail-yw0-f49.google.com ([209.85.213.49]:40048 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903773Ab2GXPhE (ORCPT ); Tue, 24 Jul 2012 17:37:04 +0200 Received: by yhjj52 with SMTP id j52so7242636yhj.36 for ; Tue, 24 Jul 2012 08:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=oszyrvpLbtyymrJWYojdfquT31F6+AbqEd7llvr2IH0=; b=cDemOVWpfeZZmLO64TkIW2PLbSQi9+M+o2540HrVjS6LT9+9ah8UYH6uem78+3Ha59 Lw09mxEbvcgZxmJ29T4tIPzlwIWVDY2axeeLI6f1m6GAuRxfeOcYkcEctZVNInJV0lUg ttB8vfouuVm6c8ntTV9cwRxv9PZtaO1mBiHz1p5Q8yxyxGyjL/X9z9e1DNuvHPJeJ6FJ 4JUQdzuMA5/WDe7lolDYMxwmEAJSr4KucJy9DsMbcGVkMICDnuRTXo7VPB6ZR1zohxzh wDshotxAUIozPZdbyTHuEzLENcTMRx5qNGcsm6U9S2Jzy9B+q1+bjZDa3QkEYmm2unnv h/BA== Received: by 10.101.176.15 with SMTP id d15mr1875574anp.65.1343144218290; Tue, 24 Jul 2012 08:36:58 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.92.208 with HTTP; Tue, 24 Jul 2012 08:36:18 -0700 (PDT) In-Reply-To: <500EBE6F.5030208@einfach.org> References: <1342126445-13408-1-git-send-email-br1@einfach.org> <500EBB99.5050209@einfach.org> <500EBE6F.5030208@einfach.org> From: Manuel Lauss Date: Tue, 24 Jul 2012 17:36:18 +0200 Message-ID: Subject: Re: [PATCH] mtx-1: add udelay to mtx1_pci_idsel To: Bruno Randolf Cc: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org, florian@openwrt.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33967 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3258 Lines: 90 On Tue, Jul 24, 2012 at 5:25 PM, Bruno Randolf wrote: > On 07/24/2012 04:20 PM, Manuel Lauss wrote: >> >> On Tue, Jul 24, 2012 at 5:13 PM, Bruno Randolf wrote: >>> >>> Hello? Any feedback? >>> >>> I know the description is not very good, but this patch is necessary for >>> PCI >>> to work on the Surfbox. >>> >>> Thanks, >>> bruno >>> >>> >>> On 07/12/2012 09:54 PM, Bruno Randolf wrote: >>>> >>>> >>>> Without this udelay(1) PCI idsel does not work correctly on the >>>> "singleboard" >>>> (T-Mobile Surfbox) for the MiniPCI device. The result is that PCI >>>> configuration >>>> fails and the MiniPCI card is not detected correctly. Instead of >>>> >>>> PCI host bridge to bus 0000:00 >>>> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >>>> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >>>> pci 0000:00:03.0: BAR 0: assigned [mem 0x40000000-0x4000ffff] >>>> pci 0000:00:00.0: BAR 0: assigned [mem 0x40010000-0x40010fff] >>>> pci 0000:00:00.1: BAR 0: assigned [mem 0x40011000-0x40011fff] >>>> >>>> We see only the CardBus device: >>>> >>>> PCI host bridge to bus 0000:00 >>>> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >>>> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >>>> pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x40000fff] >>>> pci 0000:00:00.1: BAR 0: assigned [mem 0x40001000-0x40001fff] >>>> >>>> Later the device driver shows this error: >>>> >>>> ath5k 0000:00:03.0: cannot remap PCI memory region >>>> ath5k: probe of 0000:00:03.0 failed with error -5 >>>> >>>> I assume that the logic chip which usually supresses the signal to the >>>> CardBus >>>> card has some settling time and without the delay it would still let the >>>> Cardbus interfere with the response from the MiniPCI card. >>>> >>>> What I cannot explain is why this behaviour shows up now and not in >>>> earlier >>>> kernel versions before. Maybe older PCI code was slower? >>>> >>>> Signed-off-by: Bruno Randolf >>>> --- >>>> arch/mips/alchemy/board-mtx1.c | 2 ++ >>>> 1 file changed, 2 insertions(+) >>>> >>>> diff --git a/arch/mips/alchemy/board-mtx1.c >>>> b/arch/mips/alchemy/board-mtx1.c >>>> index 295f1a9..e107a2f 100644 >>>> --- a/arch/mips/alchemy/board-mtx1.c >>>> +++ b/arch/mips/alchemy/board-mtx1.c >>>> @@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int >>>> assert) >>>> * adapter on the mtx-1 "singleboard" variant. It triggers a >>>> custom >>>> * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL >>>> signals. >>>> */ >>>> + udelay(1); >>>> + >>>> if (assert && devsel != 0) >>>> /* Suppress signal to Cardbus */ >>>> alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ >>>> >> >> Why don't you increase the delay value in the udelay() immediately >> following >> this part? > > > Yes that would be logical and was my first try. Unfortunately it does not > work. It's weird, but the delay needs to be before as well. I don't get it. I suppose the activation phase of the signal is too short, yes? Maybe a _much_ larger value (100/1000) would do the trick? Do you have an oscilloscope to check the duty cycle? Manuel From calculuspenguin@yahoo.com Tue Jul 24 19:29:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 21:22:00 +0200 (CEST) Received: from nm39-vm3.bullet.mail.ne1.yahoo.com ([98.138.229.163]:45971 "HELO nm39-vm3.bullet.mail.ne1.yahoo.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1903514Ab2GXR3B convert rfc822-to-8bit (ORCPT ); Tue, 24 Jul 2012 19:29:01 +0200 Received: from [98.138.90.53] by nm39.bullet.mail.ne1.yahoo.com with NNFMP; 24 Jul 2012 17:28:54 -0000 Received: from [98.138.87.3] by tm6.bullet.mail.ne1.yahoo.com with NNFMP; 24 Jul 2012 17:28:54 -0000 Received: from [127.0.0.1] by omp1003.mail.ne1.yahoo.com with NNFMP; 24 Jul 2012 17:28:54 -0000 X-Yahoo-Newman-Property: ymail-3 X-Yahoo-Newman-Id: 463954.41581.bm@omp1003.mail.ne1.yahoo.com Received: (qmail 42678 invoked by uid 60001); 24 Jul 2012 17:28:54 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yahoo.com; s=s1024; t=1343150934; bh=1IvZWmBPyQs/V5P1DmuftysmCCBIIlTxQ1d0fIuDhgE=; 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Tue, 24 Jul 2012 10:28:54 PDT X-Mailer: YahooMailWebService/0.8.120.356233 References: <1342922751.65328.YahooMailNeo@web120106.mail.ne1.yahoo.com> Message-ID: <1343150934.42443.YahooMailNeo@web120104.mail.ne1.yahoo.com> Date: Tue, 24 Jul 2012 10:28:54 -0700 (PDT) From: Victor Meyerson Reply-To: Victor Meyerson Subject: Re: Direct I/O bug in kernel To: Hillf Danton Cc: "linux-mips@linux-mips.org" , Ralf Baechle , LKML In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 33968 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: calculuspenguin@yahoo.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5185 Lines: 130 ----- Original Message ----- > From: Hillf Danton > To: Victor Meyerson > Cc: "linux-mips@linux-mips.org" ; Ralf Baechle ; LKML > Sent: Tuesday, July 24, 2012 6:04 AM > Subject: Re: Direct I/O bug in kernel > > On Sun, Jul 22, 2012 at 10:05 AM, Victor Meyerson > wrote: >> Hi, >> >> I recently found a bug related to direct io in post 3.3 linux kernels.  > Fortunately, my hardware (a Cobalt Qube2) is supported by the vanilla kernel so > I did not need additional patch sets to get the machine to boot.  I ran git > bisect on the main tree[1] and tested the various bisect results until git > reported the first bad commit.  After several bisects and many reboots, git > reported that [2] was the first bad commit. >> >> In testing this I came up with a repeatable process.  Unfortunately, I do > not have any other MIPS hardware to test this on and I believe that based on the > commit in question that it is MIPS related.  My procedure is as follows: >> >> 1) Create a random file to be used on the two kernels (one before the > commit, and one that includes the commit) >> $ dd if=/dev/urandom of=random-file bs=512 count=30720 >> 30720+0 records in >> 30720+0 records out >> 15728640 bytes (16 MB) copied, 60.7035 s, 259 kB/s >> $ chmod -w random-file >> >> 2) Reboot to the kernel before the commit and run dd with direct io.  > Repeat. >> $ uname -a >> Linux horadric 3.2.0-dirty #2 Fri Jul 13 06:20:22 PDT 2012 mips64 Nevada > V10.0 FPU V10.0 Cobalt Qube2 GNU/Linux >> $ dd if=random-file of=portion-of-random-3.2.0 bs=512 count=20480 > iflag=direct >> 20480+0 records in >> 20480+0 records out >> 10485760 bytes (10 MB) copied, 42.3636 s, 248 kB/s >> $ reboot >> $ dd if=random-file of=portion-of-random-3.2.0-2 bs=512 count=20480 > iflag=direct >> 20480+0 records in >> 20480+0 records out >> 10485760 bytes (10 MB) copied, 42.5252 s, 247 kB/s >> >> 3) Reboot to the kernel with the commit and run dd with direct io.  Repeat. >> $ uname -a >> Linux horadric 3.2.0-rc4-00003-gb1c10be-dirty #15 Fri Jul 20 15:05:13 PDT > 2012 mips64 Nevada V10.0 FPU V10.0 Cobalt Qube2 GNU/Linux >> $ dd if=random-file of=portion-of-random-3.2.0-rc4 bs=512 count=20480 > iflag=direct >> 20480+0 records in >> 20480+0 records out >> 10485760 bytes (10 MB) copied, 40.6226 s, 258 kB/s >> $ reboot >> $ dd if=random-file of=portion-of-random-3.2.0-rc4-2 bs=512 count=20480 > iflag=direct >> 20480+0 records in >> 20480+0 records out >> 10485760 bytes (10 MB) copied, 40.8856 s, 256 kB/s >> > Hi Victor, > > Create files with > >     dd if=random-file of=portion-of-random-3.2.0-rc4    bs=8k > count=1280 iflag=direct >     dd if=random-file of=portion-of-random-3.2.0-rc4-2 bs=8k > count=1280 iflag=direct > > without reboot(why reboot needed?), then see the changes in checksums. > > Thanks > Hillf > Hi Hillf, I rebooted in an attempt to make sure nothing was cached between runs.  In any case, here are the results without a reboot: $ dd if=random-file of=portion-of-random-3.2.0-rc4 bs=8k count=1280 iflag=direct 1280+0 records in 1280+0 records out 10485760 bytes (10 MB) copied, 6.00599 s, 1.7 MB/s $ dd if=random-file of=portion-of-random-3.2.0-rc4-2 bs=8k count=1280 iflag=direct 1280+0 records in 1280+0 records out 10485760 bytes (10 MB) copied, 5.25964 s, 2.0 MB/s $ sha256sum portion-of-random-3.2.0-rc4* 4c56820030ce22e6cc96127a53f6025d11a78f2fd3b0c1dec44f6d6746f70bbd  portion-of-random-3.2.0-rc4 05c41d626a67b9bcddb0e7b905533c63a0866092b819bf01cdb2a80f29c2b162  portion-of-random-3.2.0-rc4-2 Still different checksums and I used the same random-file from my first test. Victor >> 4) Compare checksums of the resulting files. >> $ sha256sum portion-of-random-3.2.0* >> c98a6e949b36448842a21f68e7c6a5daff1f161e1eb3e3529176cf56bf5af89e  > portion-of-random-3.2.0 >> c98a6e949b36448842a21f68e7c6a5daff1f161e1eb3e3529176cf56bf5af89e  > portion-of-random-3.2.0-2 >> dca27da87a78580b8a34bbff2790ae80d3aa880d5d00fc2126f109d6fff9e056  > portion-of-random-3.2.0-rc4 >> 703cf02d4fa90679d4a75900e7e5a3b8c3000a65bfc475610b10f17bb88bedbc  > portion-of-random-3.2.0-rc4-2 >> >> Notice how the last two files have different checksums between themselves > and even different from the first two files.  This lead me to believe that there > is a problem with direct io.  All the files are the same size and should include > the same portion of the random file created in step 1). >> >> My configuration is the Cobalt Qube2 with a 64-bit kernel and an n32 > userspace.  Hopefully someone with a much more deeper understanding of the > kernel can confirm and provide a fix for this (assuming one has not been created > yet). >> >> Thanks.  Let me know if there is any additional information that may help > with the investigation. >> >> Victor >> >> >> [1] http://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git >> [2] > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=b1c10bea620f79109b5cc9935267bea4f6f29ac6 > From manuel.lauss@gmail.com Tue Jul 24 21:35:48 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 21:35:53 +0200 (CEST) Received: from mail-gh0-f177.google.com ([209.85.160.177]:59671 "EHLO mail-gh0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903748Ab2GXTfs (ORCPT ); Tue, 24 Jul 2012 21:35:48 +0200 Received: by ghbf11 with SMTP id f11so7516453ghb.36 for ; Tue, 24 Jul 2012 12:35:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=J2b0GXca9azei93shWzdA3WCt9dtHltSGzQff+ybCyE=; b=zFEd/COu5j2zBVdX44R+9IJYgR/xWdD7wxjVkiB9VDo3KRPBPNUaicWY6uw8+iDahx cvjoFH2/cQ3ki7GZCbp5bxWiXc+MP39APT1oIA+RyQgkEcqKmP/OpVW1/QSrdVI4pqY3 cZYZ0lRCKUjN86Zt9zQJ65t+aoPnbNsidoQdYfAWCTDMeM67DZVmKDXceQjvaNYwQc/X ocAlyAkTcw+F7TijxdtqJ+HNDU/dFlbcw2/nWxAaLeQEK0jfXKv3BCFUN0SRgxmJCy+5 YoWuM7K8j2itLMIzeBFB2Dke4X1Ja9h6TphlHeo1hEt+vSpz44iv2guUYYey0cR4wZRd DHMw== Received: by 10.101.180.30 with SMTP id h30mr113235anp.52.1343156928566; Tue, 24 Jul 2012 12:08:48 -0700 (PDT) MIME-Version: 1.0 Received: by 10.236.92.208 with HTTP; Tue, 24 Jul 2012 12:08:08 -0700 (PDT) In-Reply-To: References: <1342126445-13408-1-git-send-email-br1@einfach.org> <500EBB99.5050209@einfach.org> <500EBE6F.5030208@einfach.org> From: Manuel Lauss Date: Tue, 24 Jul 2012 21:08:08 +0200 Message-ID: Subject: Re: [PATCH] mtx-1: add udelay to mtx1_pci_idsel To: Bruno Randolf Cc: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org, florian@openwrt.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33969 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3577 Lines: 96 On Tue, Jul 24, 2012 at 5:36 PM, Manuel Lauss wrote: > On Tue, Jul 24, 2012 at 5:25 PM, Bruno Randolf wrote: >> On 07/24/2012 04:20 PM, Manuel Lauss wrote: >>> >>> On Tue, Jul 24, 2012 at 5:13 PM, Bruno Randolf wrote: >>>> >>>> Hello? Any feedback? >>>> >>>> I know the description is not very good, but this patch is necessary for >>>> PCI >>>> to work on the Surfbox. >>>> >>>> Thanks, >>>> bruno >>>> >>>> >>>> On 07/12/2012 09:54 PM, Bruno Randolf wrote: >>>>> >>>>> >>>>> Without this udelay(1) PCI idsel does not work correctly on the >>>>> "singleboard" >>>>> (T-Mobile Surfbox) for the MiniPCI device. The result is that PCI >>>>> configuration >>>>> fails and the MiniPCI card is not detected correctly. Instead of >>>>> >>>>> PCI host bridge to bus 0000:00 >>>>> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >>>>> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >>>>> pci 0000:00:03.0: BAR 0: assigned [mem 0x40000000-0x4000ffff] >>>>> pci 0000:00:00.0: BAR 0: assigned [mem 0x40010000-0x40010fff] >>>>> pci 0000:00:00.1: BAR 0: assigned [mem 0x40011000-0x40011fff] >>>>> >>>>> We see only the CardBus device: >>>>> >>>>> PCI host bridge to bus 0000:00 >>>>> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >>>>> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >>>>> pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x40000fff] >>>>> pci 0000:00:00.1: BAR 0: assigned [mem 0x40001000-0x40001fff] >>>>> >>>>> Later the device driver shows this error: >>>>> >>>>> ath5k 0000:00:03.0: cannot remap PCI memory region >>>>> ath5k: probe of 0000:00:03.0 failed with error -5 >>>>> >>>>> I assume that the logic chip which usually supresses the signal to the >>>>> CardBus >>>>> card has some settling time and without the delay it would still let the >>>>> Cardbus interfere with the response from the MiniPCI card. >>>>> >>>>> What I cannot explain is why this behaviour shows up now and not in >>>>> earlier >>>>> kernel versions before. Maybe older PCI code was slower? >>>>> >>>>> Signed-off-by: Bruno Randolf >>>>> --- >>>>> arch/mips/alchemy/board-mtx1.c | 2 ++ >>>>> 1 file changed, 2 insertions(+) >>>>> >>>>> diff --git a/arch/mips/alchemy/board-mtx1.c >>>>> b/arch/mips/alchemy/board-mtx1.c >>>>> index 295f1a9..e107a2f 100644 >>>>> --- a/arch/mips/alchemy/board-mtx1.c >>>>> +++ b/arch/mips/alchemy/board-mtx1.c >>>>> @@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int >>>>> assert) >>>>> * adapter on the mtx-1 "singleboard" variant. It triggers a >>>>> custom >>>>> * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL >>>>> signals. >>>>> */ >>>>> + udelay(1); >>>>> + >>>>> if (assert && devsel != 0) >>>>> /* Suppress signal to Cardbus */ >>>>> alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ >>>>> >>> >>> Why don't you increase the delay value in the udelay() immediately >>> following >>> this part? >> >> >> Yes that would be logical and was my first try. Unfortunately it does not >> work. It's weird, but the delay needs to be before as well. > > I don't get it. I suppose the activation phase of the signal is too short, yes? > Maybe a _much_ larger value (100/1000) would do the trick? Do you have an > oscilloscope to check the duty cycle? Ignore that. After thinking more about it (and remembering VHDL/Verilog classes) I now understand what's going on and the original patch is okay. Manuel From br1@einfach.org Tue Jul 24 23:22:55 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:23:03 +0200 (CEST) Received: from postler.einfach.org ([86.59.21.13]:55474 "EHLO postler.einfach.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903509Ab2GXVWz (ORCPT ); Tue, 24 Jul 2012 23:22:55 +0200 Received: from [192.168.2.106] (79.Red-193-153-81.dynamicIP.rima-tde.net [193.153.81.79]) by postler.einfach.org (Postfix) with ESMTPSA id DDC9221421EB; Tue, 24 Jul 2012 23:22:48 +0200 (CEST) Message-ID: <500F1226.1070500@einfach.org> Date: Tue, 24 Jul 2012 22:22:46 +0100 From: Bruno Randolf User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Manuel Lauss CC: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org, florian@openwrt.org Subject: Re: [PATCH] mtx-1: add udelay to mtx1_pci_idsel References: <1342126445-13408-1-git-send-email-br1@einfach.org> <500EBB99.5050209@einfach.org> <500EBE6F.5030208@einfach.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 33970 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: br1@einfach.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3928 Lines: 101 On 07/24/2012 08:08 PM, Manuel Lauss wrote: > On Tue, Jul 24, 2012 at 5:36 PM, Manuel Lauss wrote: >> On Tue, Jul 24, 2012 at 5:25 PM, Bruno Randolf wrote: >>> On 07/24/2012 04:20 PM, Manuel Lauss wrote: >>>> >>>> On Tue, Jul 24, 2012 at 5:13 PM, Bruno Randolf wrote: >>>>> >>>>> Hello? Any feedback? >>>>> >>>>> I know the description is not very good, but this patch is necessary for >>>>> PCI >>>>> to work on the Surfbox. >>>>> >>>>> Thanks, >>>>> bruno >>>>> >>>>> >>>>> On 07/12/2012 09:54 PM, Bruno Randolf wrote: >>>>>> >>>>>> >>>>>> Without this udelay(1) PCI idsel does not work correctly on the >>>>>> "singleboard" >>>>>> (T-Mobile Surfbox) for the MiniPCI device. The result is that PCI >>>>>> configuration >>>>>> fails and the MiniPCI card is not detected correctly. Instead of >>>>>> >>>>>> PCI host bridge to bus 0000:00 >>>>>> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >>>>>> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >>>>>> pci 0000:00:03.0: BAR 0: assigned [mem 0x40000000-0x4000ffff] >>>>>> pci 0000:00:00.0: BAR 0: assigned [mem 0x40010000-0x40010fff] >>>>>> pci 0000:00:00.1: BAR 0: assigned [mem 0x40011000-0x40011fff] >>>>>> >>>>>> We see only the CardBus device: >>>>>> >>>>>> PCI host bridge to bus 0000:00 >>>>>> pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] >>>>>> pci_bus 0000:00: root bus resource [io 0x1000-0xffff] >>>>>> pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x40000fff] >>>>>> pci 0000:00:00.1: BAR 0: assigned [mem 0x40001000-0x40001fff] >>>>>> >>>>>> Later the device driver shows this error: >>>>>> >>>>>> ath5k 0000:00:03.0: cannot remap PCI memory region >>>>>> ath5k: probe of 0000:00:03.0 failed with error -5 >>>>>> >>>>>> I assume that the logic chip which usually supresses the signal to the >>>>>> CardBus >>>>>> card has some settling time and without the delay it would still let the >>>>>> Cardbus interfere with the response from the MiniPCI card. >>>>>> >>>>>> What I cannot explain is why this behaviour shows up now and not in >>>>>> earlier >>>>>> kernel versions before. Maybe older PCI code was slower? >>>>>> >>>>>> Signed-off-by: Bruno Randolf >>>>>> --- >>>>>> arch/mips/alchemy/board-mtx1.c | 2 ++ >>>>>> 1 file changed, 2 insertions(+) >>>>>> >>>>>> diff --git a/arch/mips/alchemy/board-mtx1.c >>>>>> b/arch/mips/alchemy/board-mtx1.c >>>>>> index 295f1a9..e107a2f 100644 >>>>>> --- a/arch/mips/alchemy/board-mtx1.c >>>>>> +++ b/arch/mips/alchemy/board-mtx1.c >>>>>> @@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int >>>>>> assert) >>>>>> * adapter on the mtx-1 "singleboard" variant. It triggers a >>>>>> custom >>>>>> * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL >>>>>> signals. >>>>>> */ >>>>>> + udelay(1); >>>>>> + >>>>>> if (assert && devsel != 0) >>>>>> /* Suppress signal to Cardbus */ >>>>>> alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ >>>>>> >>>> >>>> Why don't you increase the delay value in the udelay() immediately >>>> following >>>> this part? >>> >>> >>> Yes that would be logical and was my first try. Unfortunately it does not >>> work. It's weird, but the delay needs to be before as well. >> >> I don't get it. I suppose the activation phase of the signal is too short, yes? >> Maybe a _much_ larger value (100/1000) would do the trick? Do you have an >> oscilloscope to check the duty cycle? > > > Ignore that. After thinking more about it (and remembering > VHDL/Verilog classes) > I now understand what's going on and the original patch is okay. Thanks! Honestly I don't understand it, but I know it works only that way... ;) I tried a longer delay after (up to 100us for sure) and unfortunately I don't have an oscilloscope to see the signals. Bruno From sjhill@mips.com Tue Jul 24 23:39:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:40:01 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49861 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903509Ab2GXVjy (ORCPT ); Tue, 24 Jul 2012 23:39:54 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1StmpW-0003xh-KC; Tue, 24 Jul 2012 16:39:46 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v6,04/10] Add the MIPS32R2 'ins' and 'ext' instructions for use by the kernel's micro-assembler. Date: Tue, 24 Jul 2012 16:39:41 -0500 Message-Id: <1343165981-1570-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33971 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2595 Lines: 80 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/uasm.h | 4 ++-- arch/mips/mm/uasm.c | 15 +++++++++++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 53db9d7..7e0bf17 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -66,8 +66,6 @@ Ip_u3u1u2(_addu); Ip_u3u1u2(_and); Ip_u2u1u3(_andi); Ip_u1u2s3(_bbit0); -Ip_u1u2s3(_bbit0); -Ip_u1u2s3(_bbit1); Ip_u1u2s3(_bbit1); Ip_u1u2s3(_beq); Ip_u1u2s3(_beql); @@ -92,6 +90,8 @@ Ip_u2u1u3(_dsrl); Ip_u2u1u3(_dsrl32); Ip_u3u1u2(_dsubu); Ip_0(_eret); +Ip_u2u1msbu3(_ext); +Ip_u2u1msbu3(_ins); Ip_u1(_j); Ip_u1(_jal); Ip_u1(_jr); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 5fa1851..f6ba16e 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -63,8 +63,8 @@ enum opcode { insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, - insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, - insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, + insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ll, + insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, @@ -113,6 +113,8 @@ static struct insn insn_table[] __uasminitdata = { { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, @@ -343,6 +345,13 @@ Ip_u2u1msbu3(op) \ } \ UASM_EXPORT_SYMBOL(uasm_i##op); +#define I_u2u1msbdu3(op) \ +Ip_u2u1msbu3(op) \ +{ \ + build_insn(buf, insn##op, b, a, d-1, c); \ +} \ +UASM_EXPORT_SYMBOL(uasm_i##op); + #define I_u1u2(op) \ Ip_u1u2(op) \ { \ @@ -396,6 +405,8 @@ I_u2u1u3(_drotr) I_u2u1u3(_drotr32) I_u3u1u2(_dsubu) I_0(_eret) +I_u2u1msbdu3(_ext) +I_u2u1msbu3(_ins) I_u1(_j) I_u1(_jal) I_u1(_jr) -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:40:32 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49864 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903514Ab2GXVkB (ORCPT ); Tue, 24 Jul 2012 23:40:01 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Stmpd-0003xm-57; Tue, 24 Jul 2012 16:39:53 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, Douglas Leung , Chris Dearman Subject: [PATCH v5,01/10] MIPS: Add core files for MIPS SEAD-3 development platform. Date: Tue, 24 Jul 2012 16:39:48 -0500 Message-Id: <1343165988-1604-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33972 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 71984 Lines: 2747 From: "Steven J. Hill" More information about the SEAD-3 platform can be found at on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung Signed-off-by: Chris Dearman Signed-off-by: Steven J. Hill --- .../include/asm/mach-sead3/cpu-feature-overrides.h | 72 ++++ arch/mips/include/asm/mach-sead3/irq.h | 9 + .../include/asm/mach-sead3/kernel-entry-init.h | 52 +++ arch/mips/include/asm/mach-sead3/war.h | 25 ++ arch/mips/include/asm/mips-boards/sead3int.h | 67 ++++ arch/mips/mti-sead3/Makefile | 19 + arch/mips/mti-sead3/Platform | 7 + arch/mips/mti-sead3/leds-sead3.c | 128 ++++++ arch/mips/mti-sead3/sead3-cmdline.c | 46 +++ arch/mips/mti-sead3/sead3-console.c | 46 +++ arch/mips/mti-sead3/sead3-display.c | 78 ++++ arch/mips/mti-sead3/sead3-ehci.c | 47 +++ arch/mips/mti-sead3/sead3-i2c-dev.c | 33 ++ arch/mips/mti-sead3/sead3-i2c-drv.c | 405 +++++++++++++++++++ arch/mips/mti-sead3/sead3-i2c.c | 37 ++ arch/mips/mti-sead3/sead3-init.c | 169 ++++++++ arch/mips/mti-sead3/sead3-int.c | 86 ++++ arch/mips/mti-sead3/sead3-lcd.c | 43 ++ arch/mips/mti-sead3/sead3-leds.c | 83 ++++ arch/mips/mti-sead3/sead3-memory.c | 138 +++++++ arch/mips/mti-sead3/sead3-mtd.c | 54 +++ arch/mips/mti-sead3/sead3-net.c | 51 +++ arch/mips/mti-sead3/sead3-pic32-bus.c | 103 +++++ arch/mips/mti-sead3/sead3-pic32-i2c-drv.c | 435 +++++++++++++++++++++ arch/mips/mti-sead3/sead3-platform.c | 45 +++ arch/mips/mti-sead3/sead3-reset.c | 39 ++ arch/mips/mti-sead3/sead3-serial.c | 45 +++ arch/mips/mti-sead3/sead3-setup.c | 20 + arch/mips/mti-sead3/sead3-time.c | 117 ++++++ 29 files changed, 2499 insertions(+) create mode 100644 arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-sead3/irq.h create mode 100644 arch/mips/include/asm/mach-sead3/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-sead3/war.h create mode 100644 arch/mips/include/asm/mips-boards/sead3int.h create mode 100644 arch/mips/mti-sead3/Makefile create mode 100644 arch/mips/mti-sead3/Platform create mode 100644 arch/mips/mti-sead3/leds-sead3.c create mode 100644 arch/mips/mti-sead3/sead3-cmdline.c create mode 100644 arch/mips/mti-sead3/sead3-console.c create mode 100644 arch/mips/mti-sead3/sead3-display.c create mode 100644 arch/mips/mti-sead3/sead3-ehci.c create mode 100644 arch/mips/mti-sead3/sead3-i2c-dev.c create mode 100644 arch/mips/mti-sead3/sead3-i2c-drv.c create mode 100644 arch/mips/mti-sead3/sead3-i2c.c create mode 100644 arch/mips/mti-sead3/sead3-init.c create mode 100644 arch/mips/mti-sead3/sead3-int.c create mode 100644 arch/mips/mti-sead3/sead3-lcd.c create mode 100644 arch/mips/mti-sead3/sead3-leds.c create mode 100644 arch/mips/mti-sead3/sead3-memory.c create mode 100644 arch/mips/mti-sead3/sead3-mtd.c create mode 100644 arch/mips/mti-sead3/sead3-net.c create mode 100644 arch/mips/mti-sead3/sead3-pic32-bus.c create mode 100644 arch/mips/mti-sead3/sead3-pic32-i2c-drv.c create mode 100644 arch/mips/mti-sead3/sead3-platform.c create mode 100644 arch/mips/mti-sead3/sead3-reset.c create mode 100644 arch/mips/mti-sead3/sead3-serial.c create mode 100644 arch/mips/mti-sead3/sead3-setup.c create mode 100644 arch/mips/mti-sead3/sead3-time.c diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h new file mode 100644 index 0000000..7f3e3f9 --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h @@ -0,0 +1,72 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Chris Dearman + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H + + +/* + * CPU feature overrides for MIPS boards + */ +#ifdef CONFIG_CPU_MIPS32 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#ifdef CONFIG_CPU_HAS_LLSC +#define cpu_has_llsc 1 +#else +#define cpu_has_llsc 0 +#endif +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#ifdef CONFIG_CPU_MIPS64 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h new file mode 100644 index 0000000..652ea4c --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/irq.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_MIPS_IRQ_H +#define __ASM_MACH_MIPS_IRQ_H + +#define NR_IRQS 256 + + +#include_next + +#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h new file mode 100644 index 0000000..3dfbd8e --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Chris Dearman (chris@mips.com) + * Copyright (C) 2007 Mips Technologies, Inc. + */ +#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H + + .macro kernel_entry_setup +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 t0, CP0_CONFIG + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 3 + and t0, 1<<2 + bnez t0, 0f +9 : + /* Assume we came from YAMON... */ + PTR_LA v0, 0x9fc00534 /* YAMON print */ + lw v0, (v0) + move a0, zero + PTR_LA a1, nonmt_processor + jal v0 + + PTR_LA v0, 0x9fc00520 /* YAMON exit */ + lw v0, (v0) + li a0, 1 + jal v0 + +1 : b 1b + + __INITDATA +nonmt_processor : + .asciz "SMTC kernel requires the MT ASE to run\n" + __FINIT +0 : +#endif + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute C code. + */ + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h new file mode 100644 index 0000000..7c6931d --- /dev/null +++ b/arch/mips/include/asm/mach-sead3/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h new file mode 100644 index 0000000..2563b82 --- /dev/null +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -0,0 +1,67 @@ +/* + * Douglas Leung, douglas@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Defines for the SEAD3 interrupt controller. + * + */ +#ifndef _MIPS_SEAD3INT_H +#define _MIPS_SEAD3INT_H + +/* + * SEAD3 GIC's address space definitions + */ +#define GIC_BASE_ADDR 0x1b1c0000 +#define GIC_ADDRSPACE_SZ (128 * 1024) + +/* GIC's Nomenclature for Core Interrupt Pins on the SEAD3 */ +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ +#define GIC_CPU_INT1 1 /* . */ +#define GIC_CPU_INT2 2 /* . */ +#define GIC_CPU_INT3 3 /* . */ +#define GIC_CPU_INT4 4 /* . */ +#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ + +/* SEAD3 GIC local interrupts */ +#define GIC_INT_TMR (GIC_CPU_INT5) +#define GIC_INT_PERFCTR (GIC_CPU_INT5) + +/* SEAD3 GIC constants */ +/* Add 2 to convert non-eic hw int # to eic vector # */ +#define GIC_CPU_TO_VEC_OFFSET (2) + +/* GIC constants */ +/* If we map an intr to pin X, GIC will actually generate vector X+1 */ +#define GIC_PIN_TO_VEC_OFFSET (1) + +#define GIC_EXT_INTR(x) x + +/* Dummy data */ +#define X 0xdead + +/* External Interrupts used for IPI */ +/* Currently linux don't know about GIC => GIC base must be same as what Linux is using */ +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) + +#ifndef __ASSEMBLY__ +extern void sead3int_init(void); +#endif + +#endif /* !(_MIPS_SEAD3INT_H) */ diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile new file mode 100644 index 0000000..626afea --- /dev/null +++ b/arch/mips/mti-sead3/Makefile @@ -0,0 +1,19 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Copyright (C) 2008 Wind River Systems, Inc. +# written by Ralf Baechle +# +obj-y := sead3-lcd.o sead3-cmdline.o \ + sead3-display.o sead3-init.o sead3-int.o \ + sead3-mtd.o sead3-net.o \ + sead3-memory.o sead3-platform.o \ + sead3-reset.o sead3-setup.o sead3-time.o + +obj-y += sead3-i2c-dev.o sead3-i2c.o \ + sead3-pic32-i2c-drv.o sead3-pic32-bus.o \ + leds-sead3.o sead3-leds.o + +obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o +obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o diff --git a/arch/mips/mti-sead3/Platform b/arch/mips/mti-sead3/Platform new file mode 100644 index 0000000..3870924 --- /dev/null +++ b/arch/mips/mti-sead3/Platform @@ -0,0 +1,7 @@ +# +# MIPS SEAD-3 board +# +platform-$(CONFIG_MIPS_SEAD3) += mti-sead3/ +cflags-$(CONFIG_MIPS_SEAD3) += -I$(srctree)/arch/mips/include/asm/mach-sead3 +load-$(CONFIG_MIPS_SEAD3) += 0xffffffff80100000 +all-$(CONFIG_MIPS_SEAD3) := $(COMPRESSION_FNAME).srec diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c new file mode 100644 index 0000000..a95ac59 --- /dev/null +++ b/arch/mips/mti-sead3/leds-sead3.c @@ -0,0 +1,128 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "sead3-led" + +static struct platform_device *pdev; + +static void sead3_pled_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + pr_debug("sead3_pled_set\n"); + writel(value, (void __iomem *)0xBF000210); /* FIXME */ +} + +static void sead3_fled_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + pr_debug("sead3_fled_set\n"); + writel(value, (void __iomem *)0xBF000218); /* FIXME */ +} + +static struct led_classdev sead3_pled = { + .name = "sead3::pled", + .brightness_set = sead3_pled_set, +}; + +static struct led_classdev sead3_fled = { + .name = "sead3::fled", + .brightness_set = sead3_fled_set, +}; + +#ifdef CONFIG_PM +static int sead3_led_suspend(struct platform_device *dev, + pm_message_t state) +{ + led_classdev_suspend(&sead3_pled); + led_classdev_suspend(&sead3_fled); + return 0; +} + +static int sead3_led_resume(struct platform_device *dev) +{ + led_classdev_resume(&sead3_pled); + led_classdev_resume(&sead3_fled); + return 0; +} +#else +#define sead3_led_suspend NULL +#define sead3_led_resume NULL +#endif + +static int sead3_led_probe(struct platform_device *pdev) +{ + int ret; + + ret = led_classdev_register(&pdev->dev, &sead3_pled); + if (ret < 0) + return ret; + + ret = led_classdev_register(&pdev->dev, &sead3_fled); + if (ret < 0) + led_classdev_unregister(&sead3_pled); + + return ret; +} + +static int sead3_led_remove(struct platform_device *pdev) +{ + led_classdev_unregister(&sead3_pled); + led_classdev_unregister(&sead3_fled); + return 0; +} + +static struct platform_driver sead3_led_driver = { + .probe = sead3_led_probe, + .remove = sead3_led_remove, + .suspend = sead3_led_suspend, + .resume = sead3_led_resume, + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, +}; + +static int __init sead3_led_init(void) +{ + int ret; + + ret = platform_driver_register(&sead3_led_driver); + if (ret < 0) + goto out; + + pdev = platform_device_register_simple(DRVNAME, -1, NULL, 0); + if (IS_ERR(pdev)) { + ret = PTR_ERR(pdev); + platform_driver_unregister(&sead3_led_driver); + goto out; + } + +out: + return ret; +} + +static void __exit sead3_led_exit(void) +{ + platform_device_unregister(pdev); + platform_driver_unregister(&sead3_led_driver); +} + +module_init(sead3_led_init); +module_exit(sead3_led_exit); + +MODULE_AUTHOR("Kristian Kielhofner "); +MODULE_DESCRIPTION("SEAD3 LED driver"); +MODULE_LICENSE("GPL"); + diff --git a/arch/mips/mti-sead3/sead3-cmdline.c b/arch/mips/mti-sead3/sead3-cmdline.c new file mode 100644 index 0000000..a2e6cec --- /dev/null +++ b/arch/mips/mti-sead3/sead3-cmdline.c @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include + +#include + +extern int prom_argc; +extern int *_prom_argv; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while (actr < prom_argc) { + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) { + /* get rid of trailing space */ + --cp; + *cp = '\0'; + } +} diff --git a/arch/mips/mti-sead3/sead3-console.c b/arch/mips/mti-sead3/sead3-console.c new file mode 100644 index 0000000..b367391 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-console.c @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include + +#define SEAD_UART1_REGS_BASE 0xbf000800 /* ttyS1 = DB9 port */ +#define SEAD_UART0_REGS_BASE 0xbf000900 /* ttyS0 = USB port */ +#define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4)) + +static char console_port = 1; + +static inline unsigned int serial_in(int offset, unsigned int base_addr) +{ + return __raw_readl(PORT(base_addr, offset)) & 0xff; +} + +static inline void serial_out(int offset, int value, unsigned int base_addr) +{ + __raw_writel(value, PORT(base_addr, offset)); +} + +void __init prom_init_early_console(char port) +{ + console_port = port; +} + +int prom_putchar(char c) +{ + unsigned int base_addr; + + base_addr = console_port ? SEAD_UART1_REGS_BASE : SEAD_UART0_REGS_BASE; + + while ((serial_in(UART_LSR, base_addr) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c, base_addr); + + return 1; +} diff --git a/arch/mips/mti-sead3/sead3-display.c b/arch/mips/mti-sead3/sead3-display.c new file mode 100644 index 0000000..8308c7f --- /dev/null +++ b/arch/mips/mti-sead3/sead3-display.c @@ -0,0 +1,78 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include + +static unsigned int display_count; +static unsigned int max_display_count; + +#define LCD_DISPLAY_POS_BASE 0x1f000400 +#define DISPLAY_LCDINSTRUCTION (0*2) +#define DISPLAY_LCDDATA (1*2) +#define DISPLAY_CPLDSTATUS (2*2) +#define DISPLAY_CPLDDATA (3*2) +#define LCD_SETDDRAM 0x80 +#define LCD_IR_BF 0x80 + +const char display_string[] = " LINUX ON SEAD3 "; + +static void scroll_display_message(unsigned long data); +static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0); + +static void lcd_wait(unsigned int __iomem *display) +{ + /* Wait for CPLD state machine to become idle. */ + do { } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); + + do { + __raw_readl(display + DISPLAY_LCDINSTRUCTION); + + /* Wait for CPLD state machine to become idle. */ + do { } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); + } while (__raw_readl(display + DISPLAY_CPLDDATA) & LCD_IR_BF); +} + +void mips_display_message(const char *str) +{ + static unsigned int __iomem *display; + char ch; + int i; + + if (unlikely(display == NULL)) + display = ioremap_nocache(LCD_DISPLAY_POS_BASE, + (8 * sizeof(int))); + + for (i = 0; i < 16; i++) { + if (*str) + ch = *str++; + else + ch = ' '; + lcd_wait(display); + __raw_writel((LCD_SETDDRAM | i), + (display + DISPLAY_LCDINSTRUCTION)); + lcd_wait(display); + __raw_writel(ch, display + DISPLAY_LCDDATA); + } +} + +static void scroll_display_message(unsigned long data) +{ + mips_display_message(&display_string[display_count++]); + if (display_count == max_display_count) + display_count = 0; + mod_timer(&mips_scroll_timer, jiffies + HZ); +} + +void mips_scroll_message(void) +{ + del_timer_sync(&mips_scroll_timer); + max_display_count = strlen(display_string) + 1 - 16; + mod_timer(&mips_scroll_timer, jiffies + 1); +} diff --git a/arch/mips/mti-sead3/sead3-ehci.c b/arch/mips/mti-sead3/sead3-ehci.c new file mode 100644 index 0000000..772fc05 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-ehci.c @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include + +struct resource ehci_resources[] = { + { + .start = 0x1b200000, + .end = 0x1b200fff, + .flags = IORESOURCE_MEM + }, + { + .start = MIPS_CPU_IRQ_BASE + 2, + .flags = IORESOURCE_IRQ + } +}; + +u64 sead3_usbdev_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device ehci_device = { + .name = "sead3-ehci", + .id = 0, + .dev = { + .dma_mask = &sead3_usbdev_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32) + }, + .num_resources = ARRAY_SIZE(ehci_resources), + .resource = ehci_resources +}; + +static int __init ehci_init(void) +{ + return platform_device_register(&ehci_device); +} + +module_init(ehci_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("EHCI probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-i2c-dev.c b/arch/mips/mti-sead3/sead3-i2c-dev.c new file mode 100644 index 0000000..eca0b53 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c-dev.c @@ -0,0 +1,33 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include + +static struct i2c_board_info __initdata sead3_i2c_devices[] = { + { + I2C_BOARD_INFO("adt7476", 0x2c), + .irq = 0, + }, + { + I2C_BOARD_INFO("m41t80", 0x68), + .irq = 0, + }, +}; + +static int __init sead3_i2c_init(void) +{ + int err; + + err = i2c_register_board_info(0, sead3_i2c_devices, + ARRAY_SIZE(sead3_i2c_devices)); + if (err < 0) + pr_err("sead3-i2c-dev: cannot register board I2C devices\n"); + return err; +} + +arch_initcall(sead3_i2c_init); diff --git a/arch/mips/mti-sead3/sead3-i2c-drv.c b/arch/mips/mti-sead3/sead3-i2c-drv.c new file mode 100644 index 0000000..0375ee6 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c-drv.c @@ -0,0 +1,405 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include + +#define PIC32_I2CxCON 0x0000 +#define PIC32_I2CCON_ON (1<<15) +#define PIC32_I2CCON_ACKDT (1<<5) +#define PIC32_I2CCON_ACKEN (1<<4) +#define PIC32_I2CCON_RCEN (1<<3) +#define PIC32_I2CCON_PEN (1<<2) +#define PIC32_I2CCON_RSEN (1<<1) +#define PIC32_I2CCON_SEN (1<<0) +#define PIC32_I2CxCONCLR 0x0004 +#define PIC32_I2CxCONSET 0x0008 +#define PIC32_I2CxSTAT 0x0010 +#define PIC32_I2CxSTATCLR 0x0014 +#define PIC32_I2CSTAT_ACKSTAT (1<<15) +#define PIC32_I2CSTAT_TRSTAT (1<<14) +#define PIC32_I2CSTAT_BCL (1<<10) +#define PIC32_I2CSTAT_IWCOL (1<<7) +#define PIC32_I2CSTAT_I2COV (1<<6) +#define PIC32_I2CxBRG 0x0040 +#define PIC32_I2CxTRN 0x0050 +#define PIC32_I2CxRCV 0x0060 + +static DEFINE_SPINLOCK(pic32_bus_lock); + +static void __iomem *bus_xfer = (void __iomem *)0xbf000600; +static void __iomem *bus_status = (void __iomem *)0xbf000060; + +#define DELAY() udelay(100) + +static inline unsigned int ioready(void) +{ + return readl(bus_status) & 1; +} + +static inline void wait_ioready(void) +{ + do { } while (!ioready()); +} + +static inline void wait_ioclear(void) +{ + do { } while (ioready()); +} + +static inline void check_ioclear(void) +{ + if (ioready()) { + do { + (void) readl(bus_xfer); + DELAY(); + } while (ioready()); + } +} + +static u32 pic32_bus_readl(u32 reg) +{ + unsigned long flags; + u32 status, val; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + writel((0x01 << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + DELAY(); + val = readl(bus_xfer); + wait_ioclear(); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); + + return val; +} + +static void pic32_bus_writel(u32 val, u32 reg) +{ + unsigned long flags; + u32 status; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + writel((0x10 << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + writel(val, bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + wait_ioclear(); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); +} + +struct pic32_i2c_platform_data { + u32 base; + struct i2c_adapter adap; + u32 xfer_timeout; + u32 ack_timeout; + u32 ctl_timeout; +}; + +static inline void pic32_i2c_start(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_SEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void pic32_i2c_stop(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_PEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void pic32_i2c_ack(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR); + pic32_bus_writel(PIC32_I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void pic32_i2c_nack(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET); + pic32_bus_writel(PIC32_I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline int pic32_i2c_idle(struct pic32_i2c_platform_data *adap) +{ + int i; + + for (i = 0; i < adap->ctl_timeout; i++) { + if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) & + (PIC32_I2CCON_ACKEN | PIC32_I2CCON_RCEN | + PIC32_I2CCON_PEN | PIC32_I2CCON_RSEN | + PIC32_I2CCON_SEN)) == 0) && + ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + (PIC32_I2CSTAT_TRSTAT)) == 0)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static inline u32 pic32_i2c_master_write(struct pic32_i2c_platform_data *adap, + u32 byte) +{ + pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN); + return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + PIC32_I2CSTAT_IWCOL; +} + +static inline u32 pic32_i2c_master_read(struct pic32_i2c_platform_data *adap) +{ + pic32_bus_writel(PIC32_I2CCON_RCEN, adap->base + PIC32_I2CxCONSET); + while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & PIC32_I2CCON_RCEN) + ; + pic32_bus_writel(PIC32_I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR); + return pic32_bus_readl(adap->base + PIC32_I2CxRCV); +} + +static int pic32_i2c_address(struct pic32_i2c_platform_data *adap, + unsigned int addr, int rd) +{ + pic32_i2c_idle(adap); + pic32_i2c_start(adap); + pic32_i2c_idle(adap); + + addr <<= 1; + if (rd) + addr |= 1; + + if (pic32_i2c_master_write(adap, addr)) + return -EIO; + pic32_i2c_idle(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + PIC32_I2CSTAT_ACKSTAT) + return -EIO; + return 0; +} + +static int sead3_i2c_read(struct pic32_i2c_platform_data *adap, + unsigned char *buf, unsigned int len) +{ + u32 data; + int i; + + i = 0; + while (i < len) { + data = pic32_i2c_master_read(adap); + buf[i++] = data; + if (i < len) + pic32_i2c_ack(adap); + else + pic32_i2c_nack(adap); + } + + pic32_i2c_stop(adap); + pic32_i2c_idle(adap); + return 0; +} + +static int sead3_i2c_write(struct pic32_i2c_platform_data *adap, + unsigned char *buf, unsigned int len) +{ + int i; + u32 data; + + i = 0; + while (i < len) { + data = buf[i]; + if (pic32_i2c_master_write(adap, data)) + return -EIO; + pic32_i2c_idle(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + PIC32_I2CSTAT_ACKSTAT) + return -EIO; + i++; + } + + pic32_i2c_stop(adap); + pic32_i2c_idle(adap); + return 0; +} + +static int sead3_pic32_platform_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct pic32_i2c_platform_data *adap = i2c_adap->algo_data; + struct i2c_msg *p; + int i, err = 0; + + for (i = 0; i < num; i++) { +#define __BUFSIZE 80 + int ii; + static char buf[__BUFSIZE]; + char *b = buf; + + p = &msgs[i]; + b += sprintf(buf, " [%d bytes]", p->len); + if ((p->flags & I2C_M_RD) == 0) { + for (ii = 0; ii < p->len; ii++) { + if (b < &buf[__BUFSIZE-4]) { + b += sprintf(b, " %02x", p->buf[ii]); + } else { + strcat(b, "..."); + break; + } + } + } + } + + for (i = 0; !err && i < num; i++) { + p = &msgs[i]; + err = pic32_i2c_address(adap, p->addr, p->flags & I2C_M_RD); + if (err || !p->len) + continue; + if (p->flags & I2C_M_RD) + err = sead3_i2c_read(adap, p->buf, p->len); + else + err = sead3_i2c_write(adap, p->buf, p->len); + } + + /* Return the number of messages processed, or the error code. */ + if (err == 0) + err = num; + + return err; +} + +static u32 sead3_pic32_platform_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm sead3_platform_algo = { + .master_xfer = sead3_pic32_platform_xfer, + .functionality = sead3_pic32_platform_func, +}; + +static void sead3_i2c_platform_setup(struct pic32_i2c_platform_data *priv) +{ + pic32_bus_writel(500, priv->base + PIC32_I2CxBRG); + pic32_bus_writel(PIC32_I2CCON_ON, priv->base + PIC32_I2CxCONCLR); + pic32_bus_writel(PIC32_I2CCON_ON, priv->base + PIC32_I2CxCONSET); + pic32_bus_writel(PIC32_I2CSTAT_BCL | PIC32_I2CSTAT_IWCOL, + priv->base + PIC32_I2CxSTATCLR); +} + +static int __devinit sead3_i2c_platform_probe(struct platform_device *pdev) +{ + struct pic32_i2c_platform_data *priv; + struct resource *r; + int ret; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENODEV; + goto out; + } + + priv = kzalloc(sizeof(struct pic32_i2c_platform_data), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto out; + } + + priv->base = r->start; + if (!priv->base) { + ret = -EBUSY; + goto out_mem; + } + + priv->xfer_timeout = 200; + priv->ack_timeout = 200; + priv->ctl_timeout = 200; + + priv->adap.nr = pdev->id; + priv->adap.algo = &sead3_platform_algo; + priv->adap.algo_data = priv; + priv->adap.dev.parent = &pdev->dev; + strlcpy(priv->adap.name, "SEAD3 PIC32", sizeof(priv->adap.name)); + + sead3_i2c_platform_setup(priv); + + ret = i2c_add_numbered_adapter(&priv->adap); + if (ret == 0) { + platform_set_drvdata(pdev, priv); + return 0; + } + +out_mem: + kfree(priv); +out: + return ret; +} + +static int __devexit sead3_i2c_platform_remove(struct platform_device *pdev) +{ + struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + i2c_del_adapter(&priv->adap); + kfree(priv); + return 0; +} + +#ifdef CONFIG_PM +static int sead3_i2c_platform_suspend(struct platform_device *pdev, + pm_message_t state) +{ + dev_dbg(&pdev->dev, "i2c_platform_disable\n"); + return 0; +} + +static int sead3_i2c_platform_resume(struct platform_device *pdev) +{ + struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "sead3_i2c_platform_setup\n"); + sead3_i2c_platform_setup(priv); + + return 0; +} +#else +#define sead3_i2c_platform_suspend NULL +#define sead3_i2c_platform_resume NULL +#endif + +static struct platform_driver sead3_i2c_platform_driver = { + .driver = { + .name = "sead3-i2c", + .owner = THIS_MODULE, + }, + .probe = sead3_i2c_platform_probe, + .remove = __devexit_p(sead3_i2c_platform_remove), + .suspend = sead3_i2c_platform_suspend, + .resume = sead3_i2c_platform_resume, +}; + +static int __init sead3_i2c_platform_init(void) +{ + return platform_driver_register(&sead3_i2c_platform_driver); +} +module_init(sead3_i2c_platform_init); + +static void __exit sead3_i2c_platform_exit(void) +{ + platform_driver_unregister(&sead3_i2c_platform_driver); +} +module_exit(sead3_i2c_platform_exit); + +MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC."); +MODULE_DESCRIPTION("SEAD3 PIC32 I2C driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/mti-sead3/sead3-i2c.c b/arch/mips/mti-sead3/sead3-i2c.c new file mode 100644 index 0000000..f70d5fc --- /dev/null +++ b/arch/mips/mti-sead3/sead3-i2c.c @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include + +struct resource sead3_i2c_resources[] = { + { + .start = 0x805200, + .end = 0x8053ff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sead3_i2c_device = { + .name = "sead3-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(sead3_i2c_resources), + .resource = sead3_i2c_resources, +}; + +static int __init sead3_i2c_init(void) +{ + return platform_device_register(&sead3_i2c_device); +} + +module_init(sead3_i2c_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("I2C probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c new file mode 100644 index 0000000..215b710 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-init.c @@ -0,0 +1,169 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include + +#include +#include +#include +#include +#include + +extern void prom_init_early_console(char port); + +extern char except_vec_nmi; +extern char except_vec_ejtag_debug; + +int prom_argc; +int *_prom_argv, *_prom_envp; + +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index = 0; + + i = strlen(envname); + + while (prom_envp(index)) { + if (strncmp(envname, prom_envp(index), i) == 0) + return prom_envp(index+1); + index += 2; + } + + return NULL; +} + +static inline unsigned char str2hexnum(unsigned char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if ((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + pr_warn("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + + return 0; +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static void __init console_config(void) +{ + char console_string[40]; + int baud = 0; + char parity = '\0', bits = '\0', flow = '\0'; + char *s; + + if ((strstr(prom_getcmdline(), "console=")) == NULL) { + s = prom_getenv("modetty0"); + if (s) { + while (*s >= '0' && *s <= '9') + baud = baud*10 + *s++ - '0'; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; + } + if (baud == 0) + baud = 38400; + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + if (flow == '\0') + flow = 'r'; + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); + strcat(prom_getcmdline(), console_string); + } +} +#endif + +static void __init mips_nmi_setup(void) +{ + void *base; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); + memcpy(base, &except_vec_ejtag_debug, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + _prom_argv = (int *) fw_arg1; + _prom_envp = (int *) fw_arg2; + + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + prom_init_cmdline(); + prom_meminit(); +#ifdef CONFIG_EARLY_PRINTK + if ((strstr(prom_getcmdline(), "console=ttyS0")) != NULL) + prom_init_early_console(0); + else if ((strstr(prom_getcmdline(), "console=ttyS1")) != NULL) + prom_init_early_console(1); +#endif +#ifdef CONFIG_SERIAL_8250_CONSOLE + console_config(); +#endif +} diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c new file mode 100644 index 0000000..345cac6 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-int.c @@ -0,0 +1,86 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include + +#include +#include +#include +#include + +#define SEAD_CONFIG_GIC_PRESENT_SHF 1 +#define SEAD_CONFIG_GIC_PRESENT_MSK (1 << SEAD_CONFIG_GIC_PRESENT_SHF) +#define SEAD_CONFIG_BASE 0x1b100110 +#define SEAD_CONFIG_SIZE 4 + +int gic_present; +static unsigned long sead3_config_reg; + +/* + * This table defines the setup for each external GIC interrupt. It is + * indexed by interrupt number. + */ +#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, +}; + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = (fls(pending) - CAUSEB_IP - 1); + if (irq >= 0) + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + int i; + + if (!cpu_has_veic) { + mips_cpu_irq_init(); + + if (cpu_has_vint) { + /* install generic handler */ + for (i = 0; i < 8; i++) + set_vi_handler(i, plat_irq_dispatch); + } + } + + sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE, + SEAD_CONFIG_SIZE); + gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >> + SEAD_CONFIG_GIC_PRESENT_SHF; + pr_info("GIC: %spresent\n", (gic_present) ? "" : "not "); + pr_info("EIC: %s\n", + (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off"); + + if (gic_present) + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); +} diff --git a/arch/mips/mti-sead3/sead3-lcd.c b/arch/mips/mti-sead3/sead3-lcd.c new file mode 100644 index 0000000..10b10ed2 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-lcd.c @@ -0,0 +1,43 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include + +static struct resource __initdata sead3_lcd_resource = { + .start = 0x1f000400, + .end = 0x1f00041f, + .flags = IORESOURCE_MEM, +}; + +static __init int sead3_lcd_add(void) +{ + struct platform_device *pdev; + int retval; + + /* SEAD-3 and Cobalt platforms use same display type. */ + pdev = platform_device_alloc("cobalt-lcd", -1); + if (!pdev) + return -ENOMEM; + + retval = platform_device_add_resources(pdev, &sead3_lcd_resource, 1); + if (retval) + goto err_free_device; + + retval = platform_device_add(pdev); + if (retval) + goto err_free_device; + + return 0; + +err_free_device: + platform_device_put(pdev); + + return retval; +} + +device_initcall(sead3_lcd_add); diff --git a/arch/mips/mti-sead3/sead3-leds.c b/arch/mips/mti-sead3/sead3-leds.c new file mode 100644 index 0000000..20102a6 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-leds.c @@ -0,0 +1,83 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include + +#define LEDFLAGS(bits, shift) \ + ((bits << 8) | (shift << 8)) + +#define LEDBITS(id, shift, bits) \ + .name = id #shift, \ + .flags = LEDFLAGS(bits, shift) + +struct led_info led_data_info[] = { + { LEDBITS("bit", 0, 1) }, + { LEDBITS("bit", 1, 1) }, + { LEDBITS("bit", 2, 1) }, + { LEDBITS("bit", 3, 1) }, + { LEDBITS("bit", 4, 1) }, + { LEDBITS("bit", 5, 1) }, + { LEDBITS("bit", 6, 1) }, + { LEDBITS("bit", 7, 1) }, + { LEDBITS("all", 0, 8) }, +}; + +static struct led_platform_data led_data = { + .num_leds = ARRAY_SIZE(led_data_info), + .leds = led_data_info +}; + +static struct resource pled_resources[] = { + { + .start = 0x1f000210, + .end = 0x1f000217, + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device pled_device = { + .name = "sead3::pled", + .id = 0, + .dev = { + .platform_data = &led_data, + }, + .num_resources = ARRAY_SIZE(pled_resources), + .resource = pled_resources +}; + + +static struct resource fled_resources[] = { + { + .start = 0x1f000218, + .end = 0x1f00021f, + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device fled_device = { + .name = "sead3::fled", + .id = 0, + .dev = { + .platform_data = &led_data, + }, + .num_resources = ARRAY_SIZE(fled_resources), + .resource = fled_resources +}; + +static int __init led_init(void) +{ + platform_device_register(&pled_device); + return platform_device_register(&fled_device); +} + +module_init(led_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("LED probe driver for SEAD-3"); diff --git a/arch/mips/mti-sead3/sead3-memory.c b/arch/mips/mti-sead3/sead3-memory.c new file mode 100644 index 0000000..da92441 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-memory.c @@ -0,0 +1,138 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include + +#include +#include +#include + +enum yamon_memtypes { + yamon_dontuse, + yamon_prom, + yamon_free, +}; + +static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +/* determined physical memory size, not overridden by command line args */ +unsigned long physical_memsize = 0L; + +struct prom_pmemblock * __init prom_getmdesc(void) +{ + char *memsize_str, *ptr; + unsigned int memsize; + static char cmdline[COMMAND_LINE_SIZE] __initdata; + long val; + int tmp; + + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + pr_warn("memsize not set in boot prom, set to default 32Mb\n"); + physical_memsize = 0x02000000; + } else { + tmp = kstrtol(memsize_str, 0, &val); + physical_memsize = (unsigned long)val; + } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + word of physical memory */ + physical_memsize -= PAGE_SIZE; +#endif + + /* Check the command line for a memsize directive that overrides + the physical/default amount */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) + memsize = memparse(ptr + 8, &ptr); + else + memsize = physical_memsize; + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = yamon_dontuse; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = yamon_prom; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ef000; + + /* + * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the + * south bridge and PCI access always forwarded to the ISA Bus and + * BIOSCS# is always generated. + * This mean that this area can't be used as DMA memory for PCI + * devices. + */ + mdesc[2].type = yamon_dontuse; + mdesc[2].base = 0x000f0000; + mdesc[2].size = 0x00010000; + + mdesc[3].type = yamon_dontuse; + mdesc[3].base = 0x00100000; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - + mdesc[3].base; + + mdesc[4].type = yamon_free; + mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[4].size = memsize - mdesc[4].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case yamon_free: + return BOOT_MEM_RAM; + case yamon_prom: + return BOOT_MEM_ROM_DATA; + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/mti-sead3/sead3-mtd.c b/arch/mips/mti-sead3/sead3-mtd.c new file mode 100644 index 0000000..ffa35f5 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-mtd.c @@ -0,0 +1,54 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include + +static struct mtd_partition sead3_mtd_partitions[] = { + { + .name = "User FS", + .offset = 0x00000000, + .size = 0x01fc0000, + }, { + .name = "Board Config", + .offset = 0x01fc0000, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE + }, +}; + +static struct physmap_flash_data sead3_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(sead3_mtd_partitions), + .parts = sead3_mtd_partitions +}; + +static struct resource sead3_flash_resource = { + .start = 0x1c000000, + .end = 0x1dffffff, + .flags = IORESOURCE_MEM +}; + +static struct platform_device sead3_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &sead3_flash_data, + }, + .num_resources = 1, + .resource = &sead3_flash_resource, +}; + +static int __init sead3_mtd_init(void) +{ + platform_device_register(&sead3_flash); + + return 0; +} + +module_init(sead3_mtd_init) diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c new file mode 100644 index 0000000..04d704d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-net.c @@ -0,0 +1,51 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include + +static struct smsc911x_platform_config sead3_smsc911x_data = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +struct resource sead3_net_resourcess[] = { + { + .start = 0x1f010000, + .end = 0x1f01ffff, + .flags = IORESOURCE_MEM + }, + { + .start = MIPS_CPU_IRQ_BASE + 6, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device sead3_net_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &sead3_smsc911x_data, + }, + .num_resources = ARRAY_SIZE(sead3_net_resourcess), + .resource = sead3_net_resourcess +}; + +static int __init sead3_net_init(void) +{ + return platform_device_register(&sead3_net_device); +} + +module_init(sead3_net_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Network probe driver for SEAD-3"); diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c new file mode 100644 index 0000000..9f0d89b --- /dev/null +++ b/arch/mips/mti-sead3/sead3-pic32-bus.c @@ -0,0 +1,103 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include + +#define PIC32_NULL 0x00 +#define PIC32_RD 0x01 +#define PIC32_SYSRD 0x02 +#define PIC32_WR 0x10 +#define PIC32_SYSWR 0x20 +#define PIC32_IRQ_CLR 0x40 +#define PIC32_STATUS 0x80 + +#define DELAY() udelay(100) /* FIXME: needed? */ + +/* spinlock to ensure atomic access to PIC32 */ +static DEFINE_SPINLOCK(pic32_bus_lock); + +/* FIXME: io_remap these */ +static void __iomem *bus_xfer = (void __iomem *)0xbf000600; +static void __iomem *bus_status = (void __iomem *)0xbf000060; + +static inline unsigned int ioready(void) +{ + return readl(bus_status) & 1; +} + +static inline void wait_ioready(void) +{ + do { } while (!ioready()); +} + +static inline void wait_ioclear(void) +{ + do { } while (ioready()); +} + +static inline void check_ioclear(void) +{ + if (ioready()) { + pr_debug("ioclear: initially busy\n"); + do { + (void) readl(bus_xfer); + DELAY(); + } while (ioready()); + pr_debug("ioclear: cleared busy\n"); + } +} + +u32 pic32_bus_readl(u32 reg) +{ + unsigned long flags; + u32 status, val; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + + writel((PIC32_RD << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + DELAY(); + val = readl(bus_xfer); + wait_ioclear(); + + pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); + + return val; +} + +void pic32_bus_writel(u32 val, u32 reg) +{ + unsigned long flags; + u32 status; + + spin_lock_irqsave(&pic32_bus_lock, flags); + + check_ioclear(); + + writel((PIC32_WR << 24) | (reg & 0x00ffffff), bus_xfer); + DELAY(); + writel(val, bus_xfer); + DELAY(); + wait_ioready(); + status = readl(bus_xfer); + wait_ioclear(); + + pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status); + + spin_unlock_irqrestore(&pic32_bus_lock, flags); +} diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c new file mode 100644 index 0000000..46509b0 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c @@ -0,0 +1,435 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PIC32_I2CxCON 0x0000 +#define PIC32_I2CxCONCLR 0x0004 +#define PIC32_I2CxCONSET 0x0008 +#define PIC32_I2CxCONINV 0x000C +#define I2CCON_ON (1<<15) +#define I2CCON_FRZ (1<<14) +#define I2CCON_SIDL (1<<13) +#define I2CCON_SCLREL (1<<12) +#define I2CCON_STRICT (1<<11) +#define I2CCON_A10M (1<<10) +#define I2CCON_DISSLW (1<<9) +#define I2CCON_SMEN (1<<8) +#define I2CCON_GCEN (1<<7) +#define I2CCON_STREN (1<<6) +#define I2CCON_ACKDT (1<<5) +#define I2CCON_ACKEN (1<<4) +#define I2CCON_RCEN (1<<3) +#define I2CCON_PEN (1<<2) +#define I2CCON_RSEN (1<<1) +#define I2CCON_SEN (1<<0) + +#define PIC32_I2CxSTAT 0x0010 +#define PIC32_I2CxSTATCLR 0x0014 +#define PIC32_I2CxSTATSET 0x0018 +#define PIC32_I2CxSTATINV 0x001C +#define I2CSTAT_ACKSTAT (1<<15) +#define I2CSTAT_TRSTAT (1<<14) +#define I2CSTAT_BCL (1<<10) +#define I2CSTAT_GCSTAT (1<<9) +#define I2CSTAT_ADD10 (1<<8) +#define I2CSTAT_IWCOL (1<<7) +#define I2CSTAT_I2COV (1<<6) +#define I2CSTAT_DA (1<<5) +#define I2CSTAT_P (1<<4) +#define I2CSTAT_S (1<<3) +#define I2CSTAT_RW (1<<2) +#define I2CSTAT_RBF (1<<1) +#define I2CSTAT_TBF (1<<0) + +#define PIC32_I2CxADD 0x0020 +#define PIC32_I2CxADDCLR 0x0024 +#define PIC32_I2CxADDSET 0x0028 +#define PIC32_I2CxADDINV 0x002C +#define PIC32_I2CxMSK 0x0030 +#define PIC32_I2CxMSKCLR 0x0034 +#define PIC32_I2CxMSKSET 0x0038 +#define PIC32_I2CxMSKINV 0x003C +#define PIC32_I2CxBRG 0x0040 +#define PIC32_I2CxBRGCLR 0x0044 +#define PIC32_I2CxBRGSET 0x0048 +#define PIC32_I2CxBRGINV 0x004C +#define PIC32_I2CxTRN 0x0050 +#define PIC32_I2CxTRNCLR 0x0054 +#define PIC32_I2CxTRNSET 0x0058 +#define PIC32_I2CxTRNINV 0x005C +#define PIC32_I2CxRCV 0x0060 + +struct i2c_platform_data { + u32 base; + struct i2c_adapter adap; + u32 xfer_timeout; + u32 ack_timeout; + u32 ctl_timeout; +}; + +extern u32 pic32_bus_readl(u32 reg); +extern void pic32_bus_writel(u32 val, u32 reg); + +static inline void +StartI2C(struct i2c_platform_data *adap) +{ + pr_debug("StartI2C\n"); + pic32_bus_writel(I2CCON_SEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +StopI2C(struct i2c_platform_data *adap) +{ + pr_debug("StopI2C\n"); + pic32_bus_writel(I2CCON_PEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +AckI2C(struct i2c_platform_data *adap) +{ + pr_debug("AckI2C\n"); + pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR); + pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline void +NotAckI2C(struct i2c_platform_data *adap) +{ + pr_debug("NakI2C\n"); + pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET); + pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET); +} + +static inline int +IdleI2C(struct i2c_platform_data *adap) +{ + int i; + + pr_debug("IdleI2C\n"); + for (i = 0; i < adap->ctl_timeout; i++) { + if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) & + (I2CCON_ACKEN | I2CCON_RCEN | I2CCON_PEN | I2CCON_RSEN | + I2CCON_SEN)) == 0) && + ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + (I2CSTAT_TRSTAT)) == 0)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static inline u32 +MasterWriteI2C(struct i2c_platform_data *adap, u32 byte) +{ + pr_debug("MasterWriteI2C\n"); + + pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN); + + return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_IWCOL; +} + +static inline u32 +MasterReadI2C(struct i2c_platform_data *adap) +{ + pr_debug("MasterReadI2C\n"); + + pic32_bus_writel(I2CCON_RCEN, adap->base + PIC32_I2CxCONSET); + + while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & I2CCON_RCEN) + ; + + pic32_bus_writel(I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR); + + return pic32_bus_readl(adap->base + PIC32_I2CxRCV); +} + +static int +do_address(struct i2c_platform_data *adap, unsigned int addr, int rd) +{ + pr_debug("doaddress\n"); + + IdleI2C(adap); + StartI2C(adap); + IdleI2C(adap); + + addr <<= 1; + if (rd) + addr |= 1; + + if (MasterWriteI2C(adap, addr)) + return -EIO; + IdleI2C(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT) + return -EIO; + return 0; +} + +static int +i2c_read(struct i2c_platform_data *adap, unsigned char *buf, + unsigned int len) +{ + int i; + u32 data; + + pr_debug("i2c_read\n"); + + i = 0; + while (i < len) { + data = MasterReadI2C(adap); + buf[i++] = data; + if (i < len) + AckI2C(adap); + else + NotAckI2C(adap); + } + + StopI2C(adap); + IdleI2C(adap); + return 0; +} + +static int +i2c_write(struct i2c_platform_data *adap, unsigned char *buf, + unsigned int len) +{ + int i; + u32 data; + + pr_debug("i2c_write\n"); + + i = 0; + while (i < len) { + data = buf[i]; + if (MasterWriteI2C(adap, data)) + return -EIO; + IdleI2C(adap); + if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & + I2CSTAT_ACKSTAT) + return -EIO; + i++; + } + + StopI2C(adap); + IdleI2C(adap); + return 0; +} + +static int +platform_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) +{ + struct i2c_platform_data *adap = i2c_adap->algo_data; + struct i2c_msg *p; + int i, err = 0; + + pr_debug("platform_xfer\n"); + for (i = 0; i < num; i++) { +#define __BUFSIZE 80 + int ii; + static char buf[__BUFSIZE]; + char *b = buf; + + p = &msgs[i]; + b += sprintf(buf, " [%d bytes]", p->len); + if ((p->flags & I2C_M_RD) == 0) { + for (ii = 0; ii < p->len; ii++) { + if (b < &buf[__BUFSIZE-4]) { + b += sprintf(b, " %02x", p->buf[ii]); + } else { + strcat(b, "..."); + break; + } + } + } + pr_debug("xfer%d: DevAddr: %04x Op:%s Data:%s\n", i, p->addr, + (p->flags & I2C_M_RD) ? "Rd" : "Wr", buf); + } + + + for (i = 0; !err && i < num; i++) { + p = &msgs[i]; + err = do_address(adap, p->addr, p->flags & I2C_M_RD); + if (err || !p->len) + continue; + if (p->flags & I2C_M_RD) + err = i2c_read(adap, p->buf, p->len); + else + err = i2c_write(adap, p->buf, p->len); + } + + /* Return the number of messages processed, or the error code. */ + if (err == 0) + err = num; + + return err; +} + +static u32 +platform_func(struct i2c_adapter *adap) +{ + pr_debug("platform_algo\n"); + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm platform_algo = { + .master_xfer = platform_xfer, + .functionality = platform_func, +}; + +static void i2c_platform_setup(struct i2c_platform_data *priv) +{ + pr_debug("i2c_platform_setup\n"); + + pic32_bus_writel(500, priv->base + PIC32_I2CxBRG); + pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONCLR); + pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONSET); + pic32_bus_writel((I2CSTAT_BCL | I2CSTAT_IWCOL), + (priv->base + PIC32_I2CxSTATCLR)); +} + +static void i2c_platform_disable(struct i2c_platform_data *priv) +{ + pr_debug("i2c_platform_disable\n"); +} + +static int __devinit +i2c_platform_probe(struct platform_device *pdev) +{ + struct i2c_platform_data *priv; + struct resource *r; + int ret; + + pr_debug("i2c_platform_probe\n"); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENODEV; + goto out; + } + + priv = kzalloc(sizeof(struct i2c_platform_data), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto out; + } + + /* FIXME: need to allocate resource in PIC32 space */ +#if 0 + priv->base = bus_request_region(r->start, resource_size(r), + pdev->name); +#else + priv->base = r->start; +#endif + if (!priv->base) { + ret = -EBUSY; + goto out_mem; + } + + priv->xfer_timeout = 200; + priv->ack_timeout = 200; + priv->ctl_timeout = 200; + + priv->adap.nr = pdev->id; + priv->adap.algo = &platform_algo; + priv->adap.algo_data = priv; + priv->adap.dev.parent = &pdev->dev; + strlcpy(priv->adap.name, "PIC32 I2C", sizeof(priv->adap.name)); + + i2c_platform_setup(priv); + + ret = i2c_add_numbered_adapter(&priv->adap); + if (ret == 0) { + platform_set_drvdata(pdev, priv); + return 0; + } + + i2c_platform_disable(priv); + +out_mem: + kfree(priv); +out: + return ret; +} + +static int __devexit +i2c_platform_remove(struct platform_device *pdev) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + pr_debug("i2c_platform_remove\n"); + platform_set_drvdata(pdev, NULL); + i2c_del_adapter(&priv->adap); + i2c_platform_disable(priv); + kfree(priv); + return 0; +} + +#ifdef CONFIG_PM +static int +i2c_platform_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "i2c_platform_disable\n"); + i2c_platform_disable(priv); + + return 0; +} + +static int +i2c_platform_resume(struct platform_device *pdev) +{ + struct i2c_platform_data *priv = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "i2c_platform_setup\n"); + i2c_platform_setup(priv); + + return 0; +} +#else +#define i2c_platform_suspend NULL +#define i2c_platform_resume NULL +#endif + +static struct platform_driver i2c_platform_driver = { + .driver = { + .name = "i2c_pic32", + .owner = THIS_MODULE, + }, + .probe = i2c_platform_probe, + .remove = __devexit_p(i2c_platform_remove), + .suspend = i2c_platform_suspend, + .resume = i2c_platform_resume, +}; + +static int __init +i2c_platform_init(void) +{ + pr_debug("i2c_platform_init\n"); + return platform_driver_register(&i2c_platform_driver); +} + +static void __exit +i2c_platform_exit(void) +{ + pr_debug("i2c_platform_exit\n"); + platform_driver_unregister(&i2c_platform_driver); +} + +MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC."); +MODULE_DESCRIPTION("PIC32 I2C driver"); +MODULE_LICENSE("GPL"); + +module_init(i2c_platform_init); +module_exit(i2c_platform_exit); diff --git a/arch/mips/mti-sead3/sead3-platform.c b/arch/mips/mti-sead3/sead3-platform.c new file mode 100644 index 0000000..6c3b33d --- /dev/null +++ b/arch/mips/mti-sead3/sead3-platform.c @@ -0,0 +1,45 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include + +#define UART(base, int) \ +{ \ + .mapbase = base, \ + .irq = int, \ + .uartclk = 14745600, \ + .iotype = UPIO_MEM32, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, \ + .regshift = 2, \ +} + +static struct plat_serial8250_port uart8250_data[] = { + UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */ + UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */ + { }, +}; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for SEAD3"); diff --git a/arch/mips/mti-sead3/sead3-reset.c b/arch/mips/mti-sead3/sead3-reset.c new file mode 100644 index 0000000..20475c5 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-reset.c @@ -0,0 +1,39 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include + +#include +#include + +static void mips_machine_restart(char *command) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + +static void mips_machine_halt(void) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + +static int __init mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; + pm_power_off = mips_machine_halt; + + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/arch/mips/mti-sead3/sead3-serial.c b/arch/mips/mti-sead3/sead3-serial.c new file mode 100644 index 0000000..bc52705 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-serial.c @@ -0,0 +1,45 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include +#include + +#define UART(base, int) \ +{ \ + .mapbase = base, \ + .irq = int, \ + .uartclk = 14745600, \ + .iotype = UPIO_MEM32, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, \ + .regshift = 2, \ +} + +static struct plat_serial8250_port uart8250_data[] = { + UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */ + UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */ + { }, +}; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Chris Dearman "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for the SEAD-3 platform"); diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c new file mode 100644 index 0000000..8ad46ad --- /dev/null +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -0,0 +1,20 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include + +int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ +int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ + +const char *get_system_type(void) +{ + return "MIPS SEAD3"; +} + +void __init plat_mem_setup(void) +{ +} diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c new file mode 100644 index 0000000..048e781 --- /dev/null +++ b/arch/mips/mti-sead3/sead3-time.c @@ -0,0 +1,117 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ +#include + +#include +#include +#include +#include +#include + +unsigned long cpu_khz; + +static int mips_cpu_timer_irq; +static int mips_cpu_perf_irq; + +static void mips_timer_dispatch(void) +{ + do_IRQ(mips_cpu_timer_irq); +} + +static void mips_perf_dispatch(void) +{ + do_IRQ(mips_cpu_perf_irq); +} + +static void __iomem *status_reg = (void __iomem *)0xbf000410; + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect. + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int tick = 0; + unsigned int freq; + unsigned int orig; + unsigned long flags; + + local_irq_save(flags); + + orig = readl(status_reg) & 0x2; /* get original sample */ + /* wait for transition */ + while ((readl(status_reg) & 0x2) == orig) + ; + orig = orig ^ 0x2; /* flip the bit */ + + write_c0_count(0); + + /* wait 1 second (the sampling clock transitions every 10ms) */ + while (tick < 100) { + /* wait for transition */ + while ((readl(status_reg) & 0x2) == orig) + ; + orig = orig ^ 0x2; /* flip the bit */ + tick++; + } + + freq = read_c0_count(); + + local_irq_restore(flags); + + mips_hpt_frequency = freq; + + /* Adjust for processor */ + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + freq *= 2; + + freq += 5000; /* rounding */ + freq -= freq%10000; + + return freq ; +} + +void read_persistent_clock(struct timespec *ts) +{ + ts->tv_sec = 0; + ts->tv_nsec = 0; +} + +static void __init plat_perf_setup(void) +{ + if (cp0_perfcount_irq >= 0) { + if (cpu_has_vint) + set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); + mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; + } +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ + if (cpu_has_vint) + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; + return mips_cpu_timer_irq; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq; + + est_freq = estimate_cpu_frequency(); + + pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000), + (est_freq % 1000000) * 100 / 1000000); + + cpu_khz = est_freq / 1000; + + mips_scroll_message(); + + plat_perf_setup(); +} -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:40:54 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49866 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903752Ab2GXVkF (ORCPT ); Tue, 24 Jul 2012 23:40:05 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Stmpj-0003xr-Cj; Tue, 24 Jul 2012 16:39:59 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Add detection of DSP ASE Revision 2. Date: Tue, 24 Jul 2012 16:39:54 -0500 Message-Id: <1343165994-1648-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33973 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: X-Status: A Content-Length: 3630 Lines: 103 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/include/asm/mipsregs.h | 1 + arch/mips/kernel/cpu-probe.c | 6 ++++-- arch/mips/kernel/proc.c | 3 ++- 5 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 98bee29..bba9398 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -180,6 +180,10 @@ #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif +#ifndef cpu_has_dsp2 +#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) +#endif + #ifndef cpu_has_mipsmt #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 559bd12..5fb8aa4 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -331,6 +331,7 @@ enum cpu_type_enum { #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ +#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ #endif /* _ASM_CPU_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7695edb..cdb9c87 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -590,6 +590,7 @@ #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 4842870..8fd9f9f 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -142,7 +142,7 @@ int __cpuinitdata mips_dsp_disabled; static int __init dsp_disable(char *s) { - cpu_data[0].ases &= ~MIPS_ASE_DSP; + cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); mips_dsp_disabled = 1; return 1; @@ -735,6 +735,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->ases |= MIPS_ASE_SMARTMIPS; if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; + if (config3 & MIPS_CONF3_DSP2P) + c->ases |= MIPS_ASE_DSP2P; if (config3 & MIPS_CONF3_VINT) c->options |= MIPS_CPU_VINT; if (config3 & MIPS_CONF3_VEIC) @@ -1172,7 +1174,7 @@ __cpuinit void cpu_probe(void) c->options &= ~MIPS_CPU_FPU; if (mips_dsp_disabled) - c->ases &= ~MIPS_ASE_DSP; + c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index c5e97d4..bb5e6dd 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -64,12 +64,13 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_data[n].watch_reg_masks[i]); seq_printf(m, "]\n"); } - seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s%s\n", + seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s%s%s\n", cpu_has_mips16 ? " mips16" : "", cpu_has_mdmx ? " mdmx" : "", cpu_has_mips3d ? " mips3d" : "", cpu_has_smartmips ? " smartmips" : "", cpu_has_dsp ? " dsp" : "", + cpu_has_dsp2 ? " dsp2" : "", cpu_has_mipsmt ? " mt" : "", cpu_has_mmips ? " micromips" : "" ); -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:11 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:41:18 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49870 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903754Ab2GXVkL (ORCPT ); Tue, 24 Jul 2012 23:40:11 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Stmpp-0003y0-A4; Tue, 24 Jul 2012 16:40:05 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2,1/9] MIPS: Add microMIPS breakpoints and DSP support. Date: Tue, 24 Jul 2012 16:40:00 -0500 Message-Id: <1343166000-1682-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33974 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 12163 Lines: 464 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/break.h | 7 + arch/mips/include/asm/dsp.h | 4 + arch/mips/include/asm/mipsregs.h | 333 ++++++++++++++++----------------------- 3 files changed, 143 insertions(+), 201 deletions(-) diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 9161e68..63fe206 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -27,8 +27,15 @@ #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ + +#ifdef CONFIG_CPU_MICROMIPS +#define BRK_BUG 12 /* Used by BUG() */ +#define BRK_KDB 13 /* Used in KDB_ENTER() */ +#else #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ +#endif +#define MM_BRK_MEMU 14 /* Used by FPU emulator (microMIPS) */ #define BRK_MEMU 514 /* Used by FPU emulator */ #define BRK_KPROBE_BP 515 /* Kprobe break */ #define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */ diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h index e9bfc08..3149b30 100644 --- a/arch/mips/include/asm/dsp.h +++ b/arch/mips/include/asm/dsp.h @@ -16,7 +16,11 @@ #include #define DSP_DEFAULT 0x00000000 +#ifdef CONFIG_CPU_MICROMIPS +#define DSP_MASK 0x7f +#else #define DSP_MASK 0x3ff +#endif #define __enable_dsp_hazard() \ do { \ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index ba3d53d..1b8db8d 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1148,48 +1148,31 @@ do { \ /* * Macros to access the floating point coprocessor control registers */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) - -#define rddsp(mask) \ +#define read_32bit_cp1_register(source) \ ({ \ - unsigned int __res; \ + int __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ - : "i" (mask)); \ - __res; \ -}) - -#define wrdsp(val, mask) \ -do { \ - __asm__ __volatile__( \ " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " cfc1 %0,"STR(source)" \n" \ " .set pop \n" \ - : \ - : "r" (val), "i" (mask)); \ -} while (0) + : "=r" (__res)); \ + __res; \ +}) +/* + * Macros to access the DSP ASE registers + */ #if 0 /* Need DSP ASE capable assembler ... */ +#define rddsp(mask) \ +({ long dspctl; __asm__("rddsp %0, %x1" : "=r" (dspctl) : "i" (mask)); dspctl;}) + +#define wrdsp(val, mask) (__asm__("wrdsp %0, %x1" : "r" (val) : "i" (mask))) + #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) @@ -1212,230 +1195,178 @@ do { \ #else -#define mfhi0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo3() \ +#ifdef CONFIG_CPU_MICROMIPS +#define rddsp(mask) \ ({ \ - unsigned long __treg; \ + unsigned int __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mthi0(x) \ -do { \ - __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ + " # rddsp $1, %x1 \n" \ + " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) -#define mthi1(x) \ +#define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ + " # wrdsp $1, %x1 \n" \ + " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (mask)); \ } while (0) -#define mthi2(x) \ -do { \ +#define _umips_dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mthi3(x) \ +#define _umips_dsp_mtxxx(val, ins) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (ins)); \ } while (0) -#define mtlo0(x) \ -do { \ +#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) +#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) + +#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) +#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) + +#define mflo0() _umips_dsp_mflo(0) +#define mflo1() _umips_dsp_mflo(1) +#define mflo2() _umips_dsp_mflo(2) +#define mflo3() _umips_dsp_mflo(3) + +#define mfhi0() _umips_dsp_mfhi(0) +#define mfhi1() _umips_dsp_mfhi(1) +#define mfhi2() _umips_dsp_mfhi(2) +#define mfhi3() _umips_dsp_mfhi(3) + +#define mtlo0(x) _umips_dsp_mtlo(x, 0) +#define mtlo1(x) _umips_dsp_mtlo(x, 1) +#define mtlo2(x) _umips_dsp_mtlo(x, 2) +#define mtlo3(x) _umips_dsp_mtlo(x, 3) + +#define mthi0(x) _umips_dsp_mthi(x, 0) +#define mthi1(x) _umips_dsp_mthi(x, 1) +#define mthi2(x) _umips_dsp_mthi(x, 2) +#define mthi3(x) _umips_dsp_mthi(x, 3) + +#else /* !CONFIG_CPU_MICROMIPS */ + +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) -#define mtlo1(x) \ +#define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (mask)); \ } while (0) -#define mtlo2(x) \ -do { \ +#define _dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ + " .word (0x00000810 | %1) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mtlo3(x) \ +#define _dsp_mtxxx(val, ins) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ + " .word (0x00200011 | %1) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (ins)); \ } while (0) +#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) +#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) + +#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) +#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) + +#define mflo0() _dsp_mflo(0) +#define mflo1() _dsp_mflo(1) +#define mflo2() _dsp_mflo(2) +#define mflo3() _dsp_mflo(3) + +#define mfhi0() _dsp_mfhi(0) +#define mfhi1() _dsp_mfhi(1) +#define mfhi2() _dsp_mfhi(2) +#define mfhi3() _dsp_mfhi(3) + +#define mtlo0(x) _dsp_mtlo(x, 0) +#define mtlo1(x) _dsp_mtlo(x, 1) +#define mtlo2(x) _dsp_mtlo(x, 2) +#define mtlo3(x) _dsp_mtlo(x, 3) + +#define mthi0(x) _dsp_mthi(x, 0) +#define mthi1(x) _dsp_mthi(x, 1) +#define mthi2(x) _dsp_mthi(x, 2) +#define mthi3(x) _dsp_mthi(x, 3) + +#endif /* CONFIG_CPU_MICROMIPS */ #endif /* -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:17 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:41:44 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49873 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903755Ab2GXVkR (ORCPT ); Tue, 24 Jul 2012 23:40:17 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Stmpv-0003y5-3x; Tue, 24 Jul 2012 16:40:11 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2,9/9] MIPS: Add microMIPS configuration option. Date: Tue, 24 Jul 2012 16:40:06 -0500 Message-Id: <1343166006-1723-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33975 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5772 Lines: 204 From: "Steven J. Hill" This adds the option to build the Linux kernel using only the microMIPS ISA. The resulting kernel binary is, at a minimum, 20% smaller than using the MIPS32R2 ISA. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 10 +++ arch/mips/Makefile | 1 + arch/mips/configs/sead3micro_defconfig | 125 +++++++++++++++++++++++++++++++++ arch/mips/kernel/proc.c | 4 ++ 4 files changed, 140 insertions(+) create mode 100644 arch/mips/configs/sead3micro_defconfig diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index eb34851..a38d016 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2077,6 +2077,13 @@ config CPU_HAS_SMARTMIPS you don't know you probably don't have SmartMIPS and should say N here. +config CPU_MICROMIPS + depends on SYS_SUPPORTS_MICROMIPS + bool "Build kernel using microMIPS ISA" + help + When this option is enabled the kernel will be built using the + microMIPS ISA + config CPU_HAS_WB bool @@ -2140,6 +2147,9 @@ config SYS_SUPPORTS_HIGHMEM config SYS_SUPPORTS_SMARTMIPS bool +config SYS_SUPPORTS_MICROMIPS + bool + config ARCH_FLATMEM_ENABLE def_bool y depends on !NUMA && !CPU_LOONGSON2 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 764e37a..363d8c8 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -114,6 +114,7 @@ cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*e cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le)) cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips) +cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips -mno-jals) cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ -fno-omit-frame-pointer diff --git a/arch/mips/configs/sead3micro_defconfig b/arch/mips/configs/sead3micro_defconfig new file mode 100644 index 0000000..403332f --- /dev/null +++ b/arch/mips/configs/sead3micro_defconfig @@ -0,0 +1,125 @@ +CONFIG_MIPS_SEAD3=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MICROMIPS=y +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_ICPLUS_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_CONSOLE_TRANSLATIONS is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=32 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_SPI=y +CONFIG_SENSORS_ADT7475=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +# CONFIG_FTRACE is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 5569d09..c5e97d4 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -73,6 +73,10 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_has_mipsmt ? " mt" : "", cpu_has_mmips ? " micromips" : "" ); + if (cpu_has_mmips) { + seq_printf(m, "micromips kernel\t: %s\n", + (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); + } seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); seq_printf(m, "kscratch registers\t: %d\n", -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:22 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:42:09 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49874 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903509Ab2GXVkW (ORCPT ); Tue, 24 Jul 2012 23:40:22 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Stmq0-0003yA-Bi; Tue, 24 Jul 2012 16:40:16 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: Douglas Leung , ralf@linux-mips.org, "Steven J. Hill" Subject: [PATCH] MIPS: Add microMIPS vdso support. Date: Tue, 24 Jul 2012 16:40:12 -0500 Message-Id: <1343166012-1759-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33976 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 883 Lines: 35 From: Douglas Leung Signed-off-by: Steven J. Hill --- arch/mips/kernel/signal.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index f2c09cf..51d13c1 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "signal-common.h" @@ -518,7 +519,12 @@ static void handle_signal(unsigned long sig, siginfo_t *info, sigset_t *oldset = sigmask_to_save(); int ret; struct mips_abi *abi = current->thread.abi; +#ifdef CONFIG_CPU_MICROMIPS + void *vdso = (void *) + ((unsigned int)current->mm->context.vdso | MIPS_ISA_MODE); +#else void *vdso = current->mm->context.vdso; +#endif if (regs->regs[0]) { switch(regs->regs[2]) { -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:28 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:42:34 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49877 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903769Ab2GXVk2 (ORCPT ); Tue, 24 Jul 2012 23:40:28 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Stmq6-0003yF-0s; Tue, 24 Jul 2012 16:40:22 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2,3/9] MIPS: Add support for microMIPS exception handling. Date: Tue, 24 Jul 2012 16:40:17 -0500 Message-Id: <1343166017-1793-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33977 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 28585 Lines: 968 From: "Steven J. Hill" All exceptions must be taken in microMIPS mode, never in MIPS32R2 mode or the kernel falls apart. A few 'nop' instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsregs.h | 1 + arch/mips/include/asm/stackframe.h | 12 +- arch/mips/kernel/cpu-probe.c | 3 + arch/mips/kernel/genex.S | 78 +++++++--- arch/mips/kernel/scall32-o32.S | 18 ++- arch/mips/kernel/smtc-asm.S | 3 + arch/mips/kernel/traps.c | 300 ++++++++++++++++++++++++++----------- arch/mips/mm/tlbex.c | 21 +++ arch/mips/mti-sead3/sead3-init.c | 48 ++++++ 9 files changed, 370 insertions(+), 114 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 1b8db8d..7695edb 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -592,6 +592,7 @@ #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) +#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index cb41af5..335ce06 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -139,7 +139,7 @@ 1: move ra, k0 li k0, 3 mtc0 k0, $22 -#endif /* CONFIG_CPU_LOONGSON2F */ +#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */ #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -189,6 +189,7 @@ LONG_S $0, PT_R0(sp) mfc0 v1, CP0_STATUS LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) #ifdef CONFIG_MIPS_MT_SMTC /* * Ideally, these instructions would be shuffled in @@ -200,21 +201,20 @@ LONG_S k0, PT_TCSTATUS(sp) #endif /* CONFIG_MIPS_MT_SMTC */ LONG_S $4, PT_R4(sp) - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_STATUS(sp) mfc0 v1, CP0_CAUSE - LONG_S $6, PT_R6(sp) - LONG_S $7, PT_R7(sp) + LONG_S $5, PT_R5(sp) LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) #ifdef CONFIG_64BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif + LONG_S v1, PT_EPC(sp) LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) - LONG_S v1, PT_EPC(sp) ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f3f42d7..4842870 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -745,6 +745,9 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->options |= MIPS_CPU_ULRI; if (config3 & MIPS_CONF3_ISA) c->options |= MIPS_CPU_MICROMIPS; +#ifdef CONFIG_CPU_MICROMIPS + write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE); +#endif return config3 & MIPS_CONF_M; } diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 8882e57..3494d68 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -5,8 +5,8 @@ * * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. * Copyright (C) 2002, 2007 Maciej W. Rozycki + * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved. */ #include @@ -22,8 +22,10 @@ #include #include +#ifdef CONFIG_MIPS_MT_SMTC #define PANIC_PIC(msg) \ - .set push; \ + .set push; \ + .set nomicromips; \ .set reorder; \ PTR_LA a0,8f; \ .set noat; \ @@ -32,17 +34,10 @@ 9: b 9b; \ .set pop; \ TEXT(msg) +#endif __INIT -NESTED(except_vec0_generic, 0, sp) - PANIC_PIC("Exception vector 0 called") - END(except_vec0_generic) - -NESTED(except_vec1_generic, 0, sp) - PANIC_PIC("Exception vector 1 called") - END(except_vec1_generic) - /* * General exception vector for all other CPUs. * @@ -65,6 +60,7 @@ NESTED(except_vec3_generic, 0, sp) .set pop END(except_vec3_generic) +#if (cpu_has_vce != 0) /* * General exception handler for CPUs with virtual coherency exception. * @@ -124,6 +120,7 @@ handle_vcei: eret .set pop END(except_vec3_r4000) +#endif /* (cpu_has_vce == 0) */ __FINIT @@ -139,12 +136,19 @@ LEAF(r4k_wait) nop nop nop +#ifdef CONFIG_CPU_MICROMIPS + nop + nop + nop + nop +#endif .set mips3 wait /* end of rollback region (the region size must be power of two) */ - .set pop 1: jr ra + nop + .set pop END(r4k_wait) .macro BUILD_ROLLBACK_PROLOGUE handler @@ -202,7 +206,11 @@ NESTED(handle_int, PT_SIZE, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) PTR_LA ra, ret_from_irq - j plat_irq_dispatch + PTR_LA v0, plat_irq_dispatch + jr v0 +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(handle_int) __INIT @@ -223,11 +231,14 @@ NESTED(except_vec4, 0, sp) /* * EJTAG debug exception handler. * The EJTAG debug exception entry point is 0xbfc00480, which - * normally is in the boot PROM, so the boot PROM must do a + * normally is in the boot PROM, so the boot PROM must do an * unconditional jump to this vector. */ NESTED(except_vec_ejtag_debug, 0, sp) j ejtag_debug_handler +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(except_vec_ejtag_debug) __FINIT @@ -252,9 +263,10 @@ NESTED(except_vec_vi, 0, sp) FEXPORT(except_vec_vi_mori) ori a0, $0, 0 #endif /* CONFIG_MIPS_MT_SMTC */ + PTR_LA v1, except_vec_vi_handler FEXPORT(except_vec_vi_lui) lui v0, 0 /* Patched */ - j except_vec_vi_handler + jr v1 FEXPORT(except_vec_vi_ori) ori v0, 0 /* Patched */ .set pop @@ -355,6 +367,9 @@ EXPORT(ejtag_debug_buffer) */ NESTED(except_vec_nmi, 0, sp) j nmi_handler +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif END(except_vec_nmi) __FINIT @@ -363,7 +378,7 @@ NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat SAVE_ALL - move a0, sp + move a0, sp jal nmi_exception_handler RESTORE_ALL .set mips3 @@ -501,13 +516,36 @@ NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat .set noreorder - /* 0x7c03e83b: rdhwr v1,$29 */ + /* MIPS32: 0x7c03e83b: rdhwr v1,$29 */ + /* uMIPS: 0x007d6b3c: rdhwr v1,$29 -- in MIPS16e it is */ + /* ADDIUSP $16,0x7d; LI $3,0x3c and never RI. LY22 */ MFC0 k1, CP0_EPC - lui k0, 0x7c03 - lw k1, (k1) - ori k0, 0xe83b - .set reorder +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2) + and k0, k1, 1 + beqz k0, 1f + xor k1, k0 + lhu k0, (k1) + lhu k1, 2(k1) + ins k1, k0, 16, 16 + lui k0, 0x007d + b docheck + ori k0, 0x6b3c +1: + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b +#else + andi k0, k1, 1 + bnez k0, handle_ri + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b +#endif + .set reorder +docheck: bne k0, k1, handle_ri /* if not ours */ + +isrdhwr: /* The insn is rdhwr. No need to check CAUSE.BD here. */ get_saved_sp /* k1 := current_thread_info */ .set noreorder diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index a632bc1..bcb6982f 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -143,15 +143,25 @@ stackargs: jr t1 addiu t1, 6f - 5f -2: lw t8, 28(t0) # argument #8 from usp -3: lw t7, 24(t0) # argument #7 from usp -4: lw t6, 20(t0) # argument #6 from usp -5: jr t1 + lw t8, 28(t0) # argument #8 from usp + lw t7, 24(t0) # argument #7 from usp + lw t6, 20(t0) # argument #6 from usp + jr t1 sw t5, 16(sp) # argument #5 to ksp +#ifdef CONFIG_CPU_MICROMIPS + ## FIXME: + sw t8, 28(sp) # argument #8 to ksp + nop + sw t7, 24(sp) # argument #7 to ksp + nop + sw t6, 20(sp) # argument #6 to ksp + nop +#else sw t8, 28(sp) # argument #8 to ksp sw t7, 24(sp) # argument #7 to ksp sw t6, 20(sp) # argument #6 to ksp +#endif 6: j stack_done # go back nop .set pop diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index 20938a4..8e9ae50 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -49,6 +49,9 @@ CAN WE PROVE THAT WE WON'T DO THIS IF INTS DISABLED?? .text .align 5 FEXPORT(__smtc_ipi_vector) +#ifdef CONFIG_CPU_MICROMIPS + nop +#endif .set noat /* Disable thread scheduling to make Status update atomic */ DMT 27 # dmt k1 diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 8322ce9..3d76ece 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -8,8 +8,8 @@ * Copyright (C) 1998 Ulf Carlsson * Copyright (C) 1999 Silicon Graphics, Inc. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 01 MIPS Technologies, Inc. * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. */ #include #include @@ -82,10 +82,6 @@ extern asmlinkage void handle_dsp(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); -extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, - struct mips_fpu_struct *ctx, int has_fpu, - void *__user *fault_addr); - void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); void (*board_nmi_handler_setup)(void); @@ -491,6 +487,12 @@ asmlinkage void do_be(struct pt_regs *regs) #define SYNC 0x0000000f #define RDHWR 0x0000003b +/* microMIPS definitions */ +#define MM_POOL32A_FUNC 0xfc00ffff +#define MM_RDHWR 0x00006b3c +#define MM_RS 0x001f0000 +#define MM_RT 0x03e00000 + /* * The ll_bit is cleared by r*_switch.S */ @@ -605,42 +607,62 @@ static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) * Simulate trapping 'rdhwr' instructions to provide user accessible * registers not implemented in hardware. */ -static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) +static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) { struct thread_info *ti = task_thread_info(current); + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, regs, 0); + switch (rd) { + case 0: /* CPU number */ + regs->regs[rt] = smp_processor_id(); + return 0; + case 1: /* SYNCI length */ + regs->regs[rt] = min(current_cpu_data.dcache.linesz, + current_cpu_data.icache.linesz); + return 0; + case 2: /* Read count register */ + regs->regs[rt] = read_c0_count(); + return 0; + case 3: /* Count register resolution */ + switch (current_cpu_data.cputype) { + case CPU_20KC: + case CPU_25KF: + regs->regs[rt] = 1; + break; + default: + regs->regs[rt] = 2; + } + return 0; + case 29: + regs->regs[rt] = ti->tp_value; + return 0; + default: + return -1; + } +} + +static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) +{ if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { int rd = (opcode & RD) >> 11; int rt = (opcode & RT) >> 16; - perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, - 1, regs, 0); - switch (rd) { - case 0: /* CPU number */ - regs->regs[rt] = smp_processor_id(); - return 0; - case 1: /* SYNCI length */ - regs->regs[rt] = min(current_cpu_data.dcache.linesz, - current_cpu_data.icache.linesz); - return 0; - case 2: /* Read count register */ - regs->regs[rt] = read_c0_count(); - return 0; - case 3: /* Count register resolution */ - switch (current_cpu_data.cputype) { - case CPU_20KC: - case CPU_25KF: - regs->regs[rt] = 1; - break; - default: - regs->regs[rt] = 2; - } - return 0; - case 29: - regs->regs[rt] = ti->tp_value; - return 0; - default: - return -1; - } + + simulate_rdhwr(regs, rd, rt); + return 0; + } + + /* Not ours. */ + return -1; +} + +static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) +{ + if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { + int rd = (opcode & MM_RS) >> 16; + int rt = (opcode & MM_RT) >> 21; + simulate_rdhwr(regs, rd, rt); + return 0; } /* Not ours. */ @@ -671,7 +693,7 @@ asmlinkage void do_ov(struct pt_regs *regs) force_sig_info(SIGFPE, &info, current); } -static int process_fpemu_return(int sig, void __user *fault_addr) +int process_fpemu_return(int sig, void __user *fault_addr) { if (sig == SIGSEGV || sig == SIGBUS) { struct siginfo si = {0}; @@ -797,6 +819,7 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, die_if_kernel("Kernel bug detected", regs); force_sig(SIGTRAP, current); break; + case MM_BRK_MEMU: case BRK_MEMU: /* * Address errors may be deliberately induced by the FPU @@ -822,9 +845,29 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, asmlinkage void do_bp(struct pt_regs *regs) { unsigned int opcode, bcode; - - if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) - goto out_sigsegv; + unsigned long epc; + u16 instr[2]; + + if (regs->cp0_epc & MIPS_ISA_MODE) { + /* calc exception pc */ + epc = exception_epc(regs); + if (cpu_has_mmips) { + if ((__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) || + (__get_user(instr[1], (u16 __user *)((epc+2) & ~MIPS_ISA_MODE)))) + goto out_sigsegv; + opcode = (instr[0] << 16) | instr[1]; + } else { + /* MIPS16e mode */ + if (__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) + goto out_sigsegv; + bcode = (instr[0] >> 6) & 0x3f; + do_trap_or_bp(regs, bcode, "Break"); + return; + } + } else { + if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) + goto out_sigsegv; + } /* * There is the ancient bug in the MIPS assemblers that the break @@ -865,13 +908,22 @@ out_sigsegv: asmlinkage void do_tr(struct pt_regs *regs) { unsigned int opcode, tcode = 0; + u16 instr[2]; + unsigned long epc = exception_epc(regs); - if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) - goto out_sigsegv; + if ((__get_user(instr[0], (u16 __user *)(epc & ~MIPS_ISA_MODE))) || + (__get_user(instr[1], (u16 __user *)((epc+2) & ~MIPS_ISA_MODE)))) + goto out_sigsegv; + opcode = (instr[0] << 16) | instr[1]; /* Immediate versions don't provide a code. */ - if (!(opcode & OPCODE)) - tcode = ((opcode >> 6) & ((1 << 10) - 1)); + if (!(opcode & OPCODE)) { + if (is16mode(regs)) + /* microMIPS */ + tcode = (opcode >> 12) & 0x1f; + else + tcode = ((opcode >> 6) & ((1 << 10) - 1)); + } do_trap_or_bp(regs, tcode, "Trap"); return; @@ -884,6 +936,7 @@ asmlinkage void do_ri(struct pt_regs *regs) { unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); unsigned long old_epc = regs->cp0_epc; + unsigned long old31 = regs->regs[31]; unsigned int opcode = 0; int status = -1; @@ -896,23 +949,37 @@ asmlinkage void do_ri(struct pt_regs *regs) if (unlikely(compute_return_epc(regs) < 0)) return; - if (unlikely(get_user(opcode, epc) < 0)) - status = SIGSEGV; + if (is16mode(regs)) { + unsigned short mmop[2] = { 0 }; - if (!cpu_has_llsc && status < 0) - status = simulate_llsc(regs, opcode); + if (unlikely(get_user(mmop[0], epc) < 0)) + status = SIGSEGV; + if (unlikely(get_user(mmop[1], epc) < 0)) + status = SIGSEGV; + opcode = (mmop[0] << 16) | mmop[1]; - if (status < 0) - status = simulate_rdhwr(regs, opcode); + if (status < 0) + status = simulate_rdhwr_mm(regs, opcode); + } else { + if (unlikely(get_user(opcode, epc) < 0)) + status = SIGSEGV; - if (status < 0) - status = simulate_sync(regs, opcode); + if (!cpu_has_llsc && status < 0) + status = simulate_llsc(regs, opcode); + + if (status < 0) + status = simulate_rdhwr_normal(regs, opcode); + + if (status < 0) + status = simulate_sync(regs, opcode); + } if (status < 0) status = SIGILL; if (unlikely(status > 0)) { regs->cp0_epc = old_epc; /* Undo skip-over. */ + regs->regs[31] = old31; force_sig(status, current); } } @@ -982,7 +1049,7 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action, asmlinkage void do_cpu(struct pt_regs *regs) { unsigned int __user *epc; - unsigned long old_epc; + unsigned long old_epc, old31; unsigned int opcode; unsigned int cpid; int status; @@ -996,26 +1063,41 @@ asmlinkage void do_cpu(struct pt_regs *regs) case 0: epc = (unsigned int __user *)exception_epc(regs); old_epc = regs->cp0_epc; + old31 = regs->regs[31]; opcode = 0; status = -1; if (unlikely(compute_return_epc(regs) < 0)) return; - if (unlikely(get_user(opcode, epc) < 0)) - status = SIGSEGV; + if (is16mode(regs)) { + unsigned short mmop[2] = { 0 }; - if (!cpu_has_llsc && status < 0) - status = simulate_llsc(regs, opcode); + if (unlikely(get_user(mmop[0], epc) < 0)) + status = SIGSEGV; + if (unlikely(get_user(mmop[1], epc) < 0)) + status = SIGSEGV; + opcode = (mmop[0] << 16) | mmop[1]; - if (status < 0) - status = simulate_rdhwr(regs, opcode); + if (status < 0) + status = simulate_rdhwr_mm(regs, opcode); + } else { + if (unlikely(get_user(opcode, epc) < 0)) + status = SIGSEGV; + + if (!cpu_has_llsc && status < 0) + status = simulate_llsc(regs, opcode); + + if (status < 0) + status = simulate_rdhwr_normal(regs, opcode); + } if (status < 0) status = SIGILL; if (unlikely(status > 0)) { regs->cp0_epc = old_epc; /* Undo skip-over. */ + regs->regs[31] = old31; force_sig(status, current); } @@ -1328,7 +1410,7 @@ asmlinkage void cache_parity_error(void) void ejtag_exception_handler(struct pt_regs *regs) { const int field = 2 * sizeof(unsigned long); - unsigned long depc, old_epc; + unsigned long depc, old_epc, old_ra; unsigned int debug; printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); @@ -1343,10 +1425,12 @@ void ejtag_exception_handler(struct pt_regs *regs) * calculation. */ old_epc = regs->cp0_epc; + old_ra = regs->regs[31]; regs->cp0_epc = depc; - __compute_return_epc(regs); + compute_return_epc(regs); depc = regs->cp0_epc; regs->cp0_epc = old_epc; + regs->regs[31] = old_ra; } else depc += 4; write_c0_depc(depc); @@ -1387,9 +1471,24 @@ void __init *set_except_vector(int n, void *addr) unsigned long handler = (unsigned long) addr; unsigned long old_handler = exception_handlers[n]; +#ifdef CONFIG_CPU_MICROMIPS + /* + * Only the TLB handlers are cache aligned with an even + * address. All other handlers are on an odd address and + * require no modification. Otherwise, MIPS32 mode will + * be entered when handling any TLB exceptions. That + * would be bad...since we must stay in microMIPS mode. + */ + if (!(handler & 0x1)) + handler |= 1; +#endif exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { +#ifdef CONFIG_CPU_MICROMIPS + unsigned long jump_mask = ~((1 << 27) - 1); +#else unsigned long jump_mask = ~((1 << 28) - 1); +#endif u32 *buf = (u32 *)(ebase + 0x200); unsigned int k0 = 26; if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { @@ -1416,17 +1515,18 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) unsigned long handler; unsigned long old_handler = vi_handlers[n]; int srssets = current_cpu_data.srsets; - u32 *w; + u16 *h; unsigned char *b; BUG_ON(!cpu_has_veic && !cpu_has_vint); + BUG_ON((n < 0) && (n > 9)); if (addr == NULL) { handler = (unsigned long) do_default_vi; srs = 0; } else handler = (unsigned long) addr; - vi_handlers[n] = (unsigned long) addr; + vi_handlers[n] = handler; b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); @@ -1445,9 +1545,8 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) if (srs == 0) { /* * If no shadow set is selected then use the default handler - * that does normal register saving and a standard interrupt exit + * that does normal register saving and standard interrupt exit */ - extern char except_vec_vi, except_vec_vi_lui; extern char except_vec_vi_ori, except_vec_vi_end; extern char rollback_except_vec_vi; @@ -1460,11 +1559,20 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * Status.IM bit to be masked before going there. */ extern char except_vec_vi_mori; +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) + const int mori_offset = &except_vec_vi_mori - vec_start + 2; +#else const int mori_offset = &except_vec_vi_mori - vec_start; +#endif #endif /* CONFIG_MIPS_MT_SMTC */ - const int handler_len = &except_vec_vi_end - vec_start; +#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) + const int lui_offset = &except_vec_vi_lui - vec_start + 2; + const int ori_offset = &except_vec_vi_ori - vec_start + 2; +#else const int lui_offset = &except_vec_vi_lui - vec_start; const int ori_offset = &except_vec_vi_ori - vec_start; +#endif + const int handler_len = &except_vec_vi_end - vec_start; if (handler_len > VECTORSPACING) { /* @@ -1474,30 +1582,44 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) panic("VECTORSPACING too small"); } - memcpy(b, vec_start, handler_len); + set_handler(((unsigned long)b - ebase), vec_start, +#ifdef CONFIG_CPU_MICROMIPS + (handler_len - 1)); +#else + handler_len); +#endif #ifdef CONFIG_MIPS_MT_SMTC BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ - w = (u32 *)(b + mori_offset); - *w = (*w & 0xffff0000) | (0x100 << n); + h = (u16 *)(b + mori_offset); + *h = (0x100 << n); #endif /* CONFIG_MIPS_MT_SMTC */ - w = (u32 *)(b + lui_offset); - *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); - w = (u32 *)(b + ori_offset); - *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); + h = (u16 *)(b + lui_offset); + *h = (handler >> 16) & 0xffff; + h = (u16 *)(b + ori_offset); + *h = (handler & 0xffff); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } else { /* - * In other cases jump directly to the interrupt handler - * - * It is the handlers responsibility to save registers if required - * (eg hi/lo) and return from the exception using "eret" + * In other cases jump directly to the interrupt handler. It + * is the handler's responsibility to save registers if required + * (eg hi/lo) and return from the exception using "eret". */ - w = (u32 *)b; - *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ - *w = 0; + u32 insn; + + h = (u16 *)b; + /* j handler */ +#ifdef CONFIG_CPU_MICROMIPS + insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); +#else + insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); +#endif + h[0] = (insn >> 16) & 0xffff; + h[1] = insn & 0xffff; + h[2] = 0; + h[3] = 0; local_flush_icache_range((unsigned long)b, (unsigned long)(b+8)); } @@ -1656,7 +1778,11 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) /* Install CPU exception handler */ void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) { +#ifdef CONFIG_CPU_MICROMIPS + memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); +#else memcpy((void *)(ebase + offset), addr, size); +#endif local_flush_icache_range(ebase + offset, ebase + offset + size); } @@ -1690,8 +1816,11 @@ __setup("rdhwr_noopt", set_rdhwr_noopt); void __init trap_init(void) { - extern char except_vec3_generic, except_vec3_r4000; + extern char except_vec3_generic; extern char except_vec4; +#if (cpu_has_vce != 0) + extern char except_vec3_r4000; +#endif unsigned long i; int rollback; @@ -1822,13 +1951,16 @@ void __init trap_init(void) if (board_cache_error_setup) board_cache_error_setup(); +#if (cpu_has_vce != 0) if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); - else if (cpu_has_4kex) - memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); + set_handler(0x180, &except_vec3_r4000, 0x100); + else +#endif + if (cpu_has_4kex) + set_handler(0x180, &except_vec3_generic, 0x80); else - memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); + set_handler(0x080, &except_vec3_generic, 0x80); local_flush_icache_range(ebase, ebase + 0x400); flush_tlb_handlers(); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 1566297..202908e 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2012,6 +2012,13 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_l_nopage_tlbl(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_0 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); uasm_i_nop(&p); @@ -2059,6 +2066,13 @@ static void __cpuinit build_r4000_tlb_store_handler(void) uasm_l_nopage_tlbs(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_1 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); @@ -2107,6 +2121,13 @@ static void __cpuinit build_r4000_tlb_modify_handler(void) uasm_l_nopage_tlbm(&l, p); build_restore_work_registers(&p); +#ifdef CONFIG_CPU_MICROMIPS + if ((unsigned long)tlb_do_page_fault_1 & 1) { + uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); + uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); + uasm_i_jr(&p, K0); + } else +#endif uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c index 215b710..2d2f54b 100644 --- a/arch/mips/mti-sead3/sead3-init.c +++ b/arch/mips/mti-sead3/sead3-init.c @@ -131,7 +131,41 @@ static void __init mips_nmi_setup(void) base = cpu_has_veic ? (void *)(CAC_BASE + 0xa80) : (void *)(CAC_BASE + 0x380); +#ifdef CONFIG_CPU_MICROMIPS + /* + * Decrement the exception vector address by one for microMIPS. + */ + memcpy(base, (&except_vec_nmi - 1), 0x80); + + /* + * This is a hack. We do not know if the boot loader was built with + * microMIPS instructions or not. If it was not, the NMI exception + * code at 0x80000a80 will be taken in MIPS32 mode. The hand coded + * assembly below forces us into microMIPS mode if we are a pure + * microMIPS kernel. The assembly instructions are: + * + * 3C1A8000 lui k0,0x8000 + * 375A0381 ori k0,k0,0x381 + * 03400008 jr k0 + * 00000000 nop + * + * The mode switch occurs by jumping to the unaligned exception + * vector address at 0x80000381 which would have been 0x80000380 + * in MIPS32 mode. The jump to the unaligned address transitions + * us into microMIPS mode. + */ + if (!cpu_has_veic) { + void *base2 = (void *)(CAC_BASE + 0xa80); + *((unsigned int *)base2) = 0x3c1a8000; + *((unsigned int *)base2 + 1) = 0x375a0381; + *((unsigned int *)base2 + 2) = 0x03400008; + *((unsigned int *)base2 + 3) = 0x00000000; + flush_icache_range((unsigned long)base2, + (unsigned long)base2 + 0x10); + } +#else memcpy(base, &except_vec_nmi, 0x80); +#endif flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } @@ -142,7 +176,21 @@ static void __init mips_ejtag_setup(void) base = cpu_has_veic ? (void *)(CAC_BASE + 0xa00) : (void *)(CAC_BASE + 0x300); +#ifdef CONFIG_CPU_MICROMIPS + /* Deja vu... */ + memcpy(base, (&except_vec_ejtag_debug - 1), 0x80); + if (!cpu_has_veic) { + void *base2 = (void *)(CAC_BASE + 0xa00); + *((unsigned int *)base2) = 0x3c1a8000; + *((unsigned int *)base2 + 1) = 0x375a0301; + *((unsigned int *)base2 + 2) = 0x03400008; + *((unsigned int *)base2 + 3) = 0x00000000; + flush_icache_range((unsigned long)base2, + (unsigned long)base2 + 0x10); + } +#else memcpy(base, &except_vec_ejtag_debug, 0x80); +#endif flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:34 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:43:02 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49879 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903774Ab2GXVke (ORCPT ); Tue, 24 Jul 2012 23:40:34 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1StmqB-0003yN-Fq; Tue, 24 Jul 2012 16:40:27 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v2,2/9] MIPS: Add support for microMIPS instructions. Date: Tue, 24 Jul 2012 16:40:23 -0500 Message-Id: <1343166023-1827-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33978 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 42229 Lines: 1515 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/inst.h | 774 ++++++++++++++++++++++++++++++++++++++++++ arch/mips/mm/uasm-micromips.c | 194 +++++++++++ arch/mips/mm/uasm-mips.c | 178 ++++++++++ arch/mips/mm/uasm.c | 210 ++---------- 4 files changed, 1180 insertions(+), 176 deletions(-) create mode 100644 arch/mips/mm/uasm-micromips.c create mode 100644 arch/mips/mm/uasm-mips.c diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index ab84064..6212f58 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -7,6 +7,7 @@ * * Copyright (C) 1996, 2000 by Ralf Baechle * Copyright (C) 2006 by Thiemo Seufer + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #ifndef _ASM_INST_H #define _ASM_INST_H @@ -267,6 +268,225 @@ struct b_format { /* BREAK and SYSCALL */ unsigned int func:6; }; +struct fb_format { /* FPU branch format */ + unsigned int opcode:6; + unsigned int bc:5; + unsigned int cc:3; + unsigned int flag:2; + unsigned int simmediate:16; +}; + +struct fp0_format { /* FPU multipy and add format (MIPS32) */ + unsigned int opcode:6; + unsigned int fmt:5; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ + unsigned int opcode:6; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int fmt:3; + unsigned int op:2; + unsigned int func:6; +}; + +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ + unsigned int opcode:6; + unsigned int op:5; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fmt:2; + unsigned int op:8; + unsigned int func:6; +}; + +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ + unsigned int opcode:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int cc:3; + unsigned int zero:2; + unsigned int fmt:2; + unsigned int op:3; + unsigned int func:6; +}; + +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int fmt:3; + unsigned int op:7; + unsigned int func:6; +}; + +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int fs:5; + unsigned int cc:3; + unsigned int fmt:3; + unsigned int cond:4; + unsigned int func:6; +}; + +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ + unsigned int opcode:6; + unsigned int index:5; + unsigned int base:5; + unsigned int fd:5; + unsigned int op:5; + unsigned int func:6; +}; + +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ + unsigned int opcode:6; + unsigned int fr:5; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int func:6; +}; + +struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ + unsigned int opcode:6; + unsigned int ft:5; + unsigned int fs:5; + unsigned int fd:5; + unsigned int fr:5; + unsigned int func:6; +}; + +struct mm16b1_format { /* microMIPS 16-bit branch format */ + unsigned int opcode:6; + unsigned int rs:3; + signed int simmediate:7; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm16b0_format { /* microMIPS 16-bit branch format */ + unsigned int opcode:6; + signed int simmediate:10; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm_i_format { /* Immediate format (addi, lw, ...) */ + unsigned int opcode:6; + unsigned int rt:5; + unsigned int rs:5; + signed int simmediate:16; +}; + +/* MIPS16e */ + +struct rr { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int nd:1; + unsigned int l:1; + unsigned int ra:1; + unsigned int func:5; +}; + +struct jal { + unsigned int opcode:5; + unsigned int x:1; + unsigned int imm20_16:5; + signed int imm25_21:5; + /* unsigned int imm20_15:0; here is only first 16bits in first HW */ +}; + +struct i64 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int imm:8; +}; + +struct ri64 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int ry:3; + unsigned int imm:5; +}; + +struct ri { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int imm:8; +}; + +struct rri { + unsigned int opcode:5; + unsigned int rx:3; + unsigned int ry:3; + unsigned int imm:5; +}; + +struct i8 { + unsigned int opcode:5; + unsigned int func:3; + unsigned int imm:8; +}; + +struct mm_m_format { + unsigned int opcode:6; + unsigned int rd:5; + unsigned int base:5; + unsigned int func:4; + signed int simmediate:12; +}; + +struct mm_x_format { + unsigned int opcode:6; + unsigned int index:5; + unsigned int base:5; + unsigned int rd:5; + unsigned int func:11; +}; + +struct mm16_m_format { + unsigned int opcode:6; + unsigned int func:4; + unsigned int rlist:2; + unsigned int imm:4; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm16_rb_format { + unsigned int opcode:6; + unsigned int rt:3; + unsigned int base:3; + signed int simmediate:4; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm16_r5_format { + unsigned int opcode:6; + unsigned int rt:5; + signed int simmediate:5; + unsigned int duplicate:16; /* a copy of the instr */ +}; + +struct mm16_r3_format { + unsigned int opcode:6; + unsigned int rt:3; + signed int simmediate:7; + unsigned int duplicate:16; /* a copy of the instr */ +}; + #elif defined(__MIPSEL__) struct j_format { /* Jump format */ @@ -340,6 +560,225 @@ struct b_format { /* BREAK and SYSCALL */ unsigned int opcode:6; }; +struct fb_format { /* FPU branch format */ + unsigned int simmediate:16; + unsigned int flag:2; + unsigned int cc:3; + unsigned int bc:5; + unsigned int opcode:6; +}; + +struct fp0_format { /* FPU multipy and add format (MIPS32) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fmt:5; + unsigned int opcode:6; +}; + +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ + unsigned int func:6; + unsigned int op:2; + unsigned int fmt:3; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int opcode:6; +}; + +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int rt:5; + unsigned int op:5; + unsigned int opcode:6; +}; + +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ + unsigned int func:6; + unsigned int op:8; + unsigned int fmt:2; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ + unsigned int func:6; + unsigned int op:3; + unsigned int fmt:2; + unsigned int zero:2; + unsigned int cc:3; + unsigned int fs:5; + unsigned int fd:5; + unsigned int opcode:6; +}; + +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ + unsigned int func:6; + unsigned int op:7; + unsigned int fmt:3; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ + unsigned int func:6; + unsigned int cond:4; + unsigned int fmt:3; + unsigned int cc:3; + unsigned int fs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ + unsigned int func:6; + unsigned int op:5; + unsigned int fd:5; + unsigned int base:5; + unsigned int index:5; + unsigned int opcode:6; +}; + +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ + unsigned int func:6; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fr:5; + unsigned int opcode:6; +}; + +struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ + unsigned int func:6; + unsigned int fr:5; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int opcode:6; +}; + +struct mm16b1_format { /* microMIPS 16-bit branch format */ + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:7; + unsigned int rs:3; + unsigned int opcode:6; +}; + +struct mm16b0_format { /* microMIPS 16-bit branch format */ + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:10; + unsigned int opcode:6; +}; + +struct mm_i_format { /* Immediate format */ + signed int simmediate:16; + unsigned int rs:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +/* MIPS16e */ + +struct rr { + unsigned int func:5; + unsigned int ra:1; + unsigned int l:1; + unsigned int nd:1; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct jal { + /* unsigned int imm20_15:0; here is only first 16bits in first HW */ + signed int imm25_21:5; + unsigned int imm20_16:5; + unsigned int x:1; + unsigned int opcode:5; +}; + +struct i64 { + unsigned int imm:8; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct ri64 { + unsigned int imm:5; + unsigned int ry:3; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct ri { + unsigned int imm:8; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct rri { + unsigned int imm:5; + unsigned int ry:3; + unsigned int rx:3; + unsigned int opcode:5; +}; + +struct i8 { + unsigned int imm:8; + unsigned int func:3; + unsigned int opcode:5; +}; + +struct mm_m_format { + signed int simmediate:12; + unsigned int func:4; + unsigned int base:5; + unsigned int rd:5; + unsigned int opcode:6; +}; + +struct mm_x_format { + unsigned int func:11; + unsigned int rd:5; + unsigned int base:5; + unsigned int index:5; + unsigned int opcode:6; +}; + +struct mm16_m_format { + unsigned int duplicate:16; /* a copy of the instr */ + unsigned int imm:4; + unsigned int rlist:2; + unsigned int func:4; + unsigned int opcode:6; +}; + +struct mm16_rb_format { + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:4; + unsigned int base:3; + unsigned int rt:3; + unsigned int opcode:6; +}; + +struct mm16_r5_format { + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:5; + unsigned int rt:5; + unsigned int opcode:6; +}; + +struct mm16_r3_format { + unsigned int duplicate:16; /* a copy of the instr */ + signed int simmediate:7; + unsigned int rt:3; + unsigned int opcode:6; +}; + #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" #endif @@ -356,6 +795,26 @@ union mips_instruction { struct f_format f_format; struct ma_format ma_format; struct b_format b_format; + struct mm16b0_format mm16b0_format; + struct mm16b1_format mm16b1_format; + struct mm_i_format mm_i_format; + struct fb_format fb_format; + struct fp0_format fp0_format; + struct fp1_format fp1_format; + struct fp6_format fp6_format; + struct mm_fp0_format mm_fp0_format; + struct mm_fp1_format mm_fp1_format; + struct mm_fp2_format mm_fp2_format; + struct mm_fp3_format mm_fp3_format; + struct mm_fp4_format mm_fp4_format; + struct mm_fp5_format mm_fp5_format; + struct mm_fp6_format mm_fp6_format; + struct mm_m_format mm_m_format; + struct mm_x_format mm_x_format; + struct mm16_m_format mm16_m_format; + struct mm16_rb_format mm16_rb_format; + struct mm16_r3_format mm16_r3_format; + struct mm16_r5_format mm16_r5_format; }; /* HACHACHAHCAHC ... */ @@ -418,4 +877,319 @@ union mips_instruction { typedef unsigned int mips_instruction; +/* The following are for microMIPS mode */ +#define MM_16_OPCODE_SFT 10 +#define MM_NOP16 0x0c00 +#define MM_POOL32A_MINOR_MSK 0x3f +#define MM_POOL32A_MINOR_SFT 0x6 +#define MIPS32_COND_FC 0x30 + +/* + * Major opcodes; microMIPS mode. + */ +enum mm_major_op { + mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, + mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, + mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, + mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, + mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, + mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, + mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, + mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, + mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, + mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, + mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, + mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, + mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, + mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, + mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, + mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, +}; + +/* + * POOL32I minor opcodes. + */ +enum mm_32i_minor_op { + mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, + mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, + mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, + mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, + mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, + mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, + mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, + mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, + mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, +}; + +/* + * POOL32A minor opcodes. + */ +enum mm_32a_minor_op { + mm_sll32_op = 0x000, + mm_ins_op = 0x00c, + mm_ext_op = 0x02c, + mm_pool32axf_op = 0x03c, + mm_srl32_op = 0x040, + mm_sra_op = 0x080, + mm_rotr_op = 0x0c0, + mm_lwxs_op = 0x118, + mm_addu32_op = 0x150, + mm_subu32_op = 0x1d0, + mm_and_op = 0x250, + mm_or32_op = 0x290, + mm_xor32_op = 0x310, +}; + +/* + * POOL32B functions. + */ +enum mm_32b_func { + mm_lwc2_func = 0x0, + mm_lwp_func = 0x1, + mm_ldc2_func = 0x2, + mm_ldp_func = 0x4, + mm_lwm32_func = 0x5, + mm_cache_func = 0x6, + mm_ldm_func = 0x7, + mm_swc2_func = 0x8, + mm_swp_func = 0x9, + mm_sdc2_func = 0xa, + mm_sdp_func = 0xc, + mm_swm32_func = 0xd, + mm_sdm_func = 0xf, +}; + +/* + * POOL32C functions. + */ +enum mm_32c_func { + mm_pref_func = 0x2, + mm_ll_func = 0x3, + mm_swr_func = 0x9, + mm_sc_func = 0xb, + mm_lwu_func = 0xe, +}; + +/* + * POOL32AXF minor opcodes. + */ +enum mm_32axf_minor_op { + mm_mfc0_op = 0x003, + mm_mtc0_op = 0x00b, + mm_tlbp_op = 0x00d, + mm_jalr_op = 0x03c, + mm_tlbr_op = 0x04d, + mm_jalrhb_op = 0x07c, + mm_tlbwi_op = 0x08d, + mm_tlbwr_op = 0x0cd, + mm_jalrs_op = 0x13c, + mm_jalrshb_op = 0x17c, + mm_syscall_op = 0x22d, + mm_eret_op = 0x3cd, +}; + +/* + * POOL32F minor opcodes. + */ +enum mm_32f_minor_op { + mm_32f_00_op = 0x00, + mm_32f_01_op = 0x01, + mm_32f_02_op = 0x02, + mm_32f_10_op = 0x08, + mm_32f_11_op = 0x09, + mm_32f_12_op = 0x0a, + mm_32f_20_op = 0x10, + mm_32f_30_op = 0x18, + mm_32f_40_op = 0x20, + mm_32f_41_op = 0x21, + mm_32f_42_op = 0x22, + mm_32f_50_op = 0x28, + mm_32f_51_op = 0x29, + mm_32f_52_op = 0x2a, + mm_32f_60_op = 0x30, + mm_32f_70_op = 0x38, + mm_32f_73_op = 0x3b, + mm_32f_74_op = 0x3c, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_10_minor_op { + mm_lwxc1_op = 0x1, + mm_swxc1_op, + mm_ldxc1_op, + mm_sdxc1_op, + mm_luxc1_op, + mm_suxc1_op, +}; + +enum mm_32f_func { + mm_lwxc1_func = 0x048, + mm_swxc1_func = 0x088, + mm_ldxc1_func = 0x0c8, + mm_sdxc1_func = 0x108, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_40_minor_op { + mm_fmovf_op, + mm_fmovt_op, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_60_minor_op { + mm_fadd_op, + mm_fsub_op, + mm_fmul_op, + mm_fdiv_op, +}; + +/* + * POOL32F secondary minor opcodes. + */ +enum mm_32f_70_minor_op { + mm_fmovn_op, + mm_fmovz_op, +}; + +/* + * POOL32F secondary minor opcodes (POOL32FXF). + */ +enum mm_32f_73_minor_op { + mm_fmov0_op = 0x01, + mm_fcvtl_op = 0x04, + mm_movf0_op = 0x05, + mm_frsqrt_op = 0x08, + mm_ffloorl_op = 0x0c, + mm_fabs0_op = 0x0d, + mm_fcvtw_op = 0x24, + mm_movt0_op = 0x25, + mm_fsqrt_op = 0x28, + mm_ffloorw_op = 0x2c, + mm_fneg0_op = 0x2d, + mm_cfc1_op = 0x40, + mm_frecip_op = 0x48, + mm_fceill_op = 0x4c, + mm_fcvtd0_op = 0x4d, + mm_ctc1_op = 0x60, + mm_fceilw_op = 0x6c, + mm_fcvts0_op = 0x6d, + mm_mfc1_op = 0x80, + mm_fmov1_op = 0x81, + mm_movf1_op = 0x85, + mm_ftruncl_op = 0x8c, + mm_fabs1_op = 0x8d, + mm_mtc1_op = 0xa0, + mm_movt1_op = 0xa5, + mm_ftruncw_op = 0xac, + mm_fneg1_op = 0xad, + mm_froundl_op = 0xcc, + mm_fcvtd1_op = 0xcd, + mm_froundw_op = 0xec, + mm_fcvts1_op = 0xed, +}; + +/* + * POOL16C minor opcodes. + */ +enum mm_16c_minor_op { + mm_lwm16_op = 0x04, + mm_swm16_op = 0x05, + mm_jr16_op = 0x18, + mm_jrc_op = 0x1a, + mm_jalr16_op = 0x1c, + mm_jalrs16_op = 0x1e, +}; + +/* + * POOL16D minor opcodes. + */ +enum mm_16d_minor_op { + mm_addius5_func, + mm_addiusp_func, +}; + +struct decoded_instn { + mips_instruction insn; + mips_instruction next_insn; + int pc_inc; + int next_pc_inc; + int micro_mips_mode; +}; + +/* Recode table from MIPS16e register notation to GPR */ +extern int mips16e_reg2gpr[]; + +union mips16e_instruction { + unsigned int full:16; + struct rr rr; + struct jal jal; + struct i64 i64; + struct ri64 ri64; + struct ri ri; + struct rri rri; + struct i8 i8; +}; + +enum MIPS16e_ops { + MIPS16e_jal_op = 003, + MIPS16e_ld_op = 007, + MIPS16e_i8_op = 014, + MIPS16e_sd_op = 017, + MIPS16e_lb_op = 020, + MIPS16e_lh_op = 021, + MIPS16e_lwsp_op = 022, + MIPS16e_lw_op = 023, + MIPS16e_lbu_op = 024, + MIPS16e_lhu_op = 025, + MIPS16e_lwpc_op = 026, + MIPS16e_lwu_op = 027, + MIPS16e_sb_op = 030, + MIPS16e_sh_op = 031, + MIPS16e_swsp_op = 032, + MIPS16e_sw_op = 033, + MIPS16e_rr_op = 035, + MIPS16e_extend_op = 036, + MIPS16e_i64_op = 037, +}; + +enum MIPS16e_i64_func { + MIPS16e_ldsp_func, + MIPS16e_sdsp_func, + MIPS16e_sdrasp_func, + MIPS16e_dadjsp_func, + MIPS16e_ldpc_func, +}; + +enum MIPS16e_rr_func { + MIPS16e_jr_func, +}; + +enum MIPS6e_i8_func { + MIPS16e_swrasp_func = 02, +}; + +/* + * This functions returns 1 if the microMIPS instr is a 16 bit instr. + * Otherwise return 0. + */ +#define MIPS_ISA_MODE 01 +#define is16mode(regs) (regs->cp0_epc & MIPS_ISA_MODE) + +static inline int mm_is16bit(u16 instr) +{ + /* take LS 3 bits */ + u16 opcode_low = (instr >> MM_16_OPCODE_SFT) & 0x7; + + if (opcode_low >= 1 && opcode_low <= 3) + return 1; + else + return 0; +} + #endif /* _ASM_INST_H */ diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c new file mode 100644 index 0000000..f2b834a --- /dev/null +++ b/arch/mips/mm/uasm-micromips.c @@ -0,0 +1,194 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ + +#define RS_MASK 0x1f +#define RS_SH 16 +#define RT_MASK 0x1f +#define RT_SH 21 +#define SCIMM_MASK 0x3ff +#define SCIMM_SH 16 + +/* This macro sets the non-variable bits of an instruction. */ +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RT_SH \ + | (c) << RS_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) + +static struct insn insn_table[] __uasminitdata = { + { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, + { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, + { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beql, 0, 0 }, + { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM }, + { insn_bgezl, 0, 0 }, + { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM }, + { insn_bltzl, 0, 0 }, + { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, + { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, + { insn_daddu, 0, 0 }, + { insn_daddiu, 0, 0 }, + { insn_dmfc0, 0, 0 }, + { insn_dmtc0, 0, 0 }, + { insn_dsll, 0, 0 }, + { insn_dsll32, 0, 0 }, + { insn_dsra, 0, 0 }, + { insn_dsrl, 0, 0 }, + { insn_dsrl32, 0, 0 }, + { insn_drotr, 0, 0 }, + { insn_drotr32, 0, 0 }, + { insn_dsubu, 0, 0 }, + { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 }, + { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE }, + { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE }, + { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS }, + { insn_ld, 0, 0 }, + { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM }, + { insn_lld, 0, 0 }, + { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, + { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, + { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM }, + { insn_rfe, 0, 0 }, + { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM }, + { insn_scd, 0, 0 }, + { insn_sd, 0, 0 }, + { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD }, + { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD }, + { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD }, + { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, + { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, + { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, + { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, + { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, + { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 }, + { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD }, + { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_dins, 0, 0 }, + { insn_dinsm, 0, 0 }, + { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM}, + { insn_bbit0, 0, 0 }, + { insn_bbit1, 0, 0 }, + { insn_lwx, 0, 0 }, + { insn_ldx, 0, 0 }, + { insn_invalid, 0, 0 } +}; + +#undef M + +static inline __uasminit u32 build_bimm(s32 arg) +{ + if(arg > 0xffff || arg < -0x10000) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + if(arg & 0x3) + printk(KERN_WARNING "Invalid micro-assembler branch target\n"); + + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff); +} + +static inline __uasminit u32 build_jimm(u32 arg) +{ + if ((arg & ~(JIMM_MASK << 1)) - 1) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + return (arg >> 1) & JIMM_MASK; +} + +/* + * The order of opcode arguments is implicitly left to right, + * starting with RS and ending with FUNC or IMM. + */ +static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) +{ + struct insn *ip = NULL; + unsigned int i; + va_list ap; + u32 op; + + for (i = 0; insn_table[i].opcode != insn_invalid; i++) + if (insn_table[i].opcode == opc) { + ip = &insn_table[i]; + break; + } + + if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) + panic("Unsupported Micro-assembler instruction %d", opc); + + op = ip->match; + va_start(ap, opc); + if (ip->fields & RS) { + if (opc == insn_mfc0 || opc == insn_mtc0) + op |= build_rt(va_arg(ap, u32)); + else + op |= build_rs(va_arg(ap, u32)); + } + if (ip->fields & RT) { + if (opc == insn_mfc0 || opc == insn_mtc0) + op |= build_rs(va_arg(ap, u32)); + else + op |= build_rt(va_arg(ap, u32)); + } + if (ip->fields & RD) + op |= build_rd(va_arg(ap, u32)); + if (ip->fields & RE) + op |= build_re(va_arg(ap, u32)); + if (ip->fields & SIMM) + op |= build_simm(va_arg(ap, s32)); + if (ip->fields & UIMM) + op |= build_uimm(va_arg(ap, u32)); + if (ip->fields & BIMM) + op |= build_bimm(va_arg(ap, s32)); + if (ip->fields & JIMM) + op |= build_jimm(va_arg(ap, u32)); + if (ip->fields & FUNC) + op |= build_func(va_arg(ap, u32)); + if (ip->fields & SET) + op |= build_set(va_arg(ap, u32)); + if (ip->fields & SCIMM) + op |= build_scimm(va_arg(ap, u32)); + va_end(ap); + +#ifdef CONFIG_CPU_LITTLE_ENDIAN + **buf = ((op & 0xffff) << 16) | (op >> 16); +#else + **buf = op; +#endif + (*buf)++; +} + +static inline void __uasminit +__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) +{ + long laddr = (long)lab->addr; + long raddr = (long)rel->addr; + + switch (rel->type) { + case R_MIPS_PC16: +#ifdef CONFIG_CPU_LITTLE_ENDIAN + *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16); +#else + *rel->addr |= build_bimm(laddr - (raddr + 4)); +#endif + break; + + default: + panic("Unsupported Micro-assembler relocation %d", + rel->type); + } +} diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c new file mode 100644 index 0000000..e86334b --- /dev/null +++ b/arch/mips/mm/uasm-mips.c @@ -0,0 +1,178 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + */ + +#define RS_MASK 0x1f +#define RS_SH 21 +#define RT_MASK 0x1f +#define RT_SH 16 +#define SCIMM_MASK 0xfffff +#define SCIMM_SH 6 + +/* This macro sets the non-variable bits of an instruction. */ +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RS_SH \ + | (c) << RT_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) + +static struct insn insn_table[] __uasminitdata = { + { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, + { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, + { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, + { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, + { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, + { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, + { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, + { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, + { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, + { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, + { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, + { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, + { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, + { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, + { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, + { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, + { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, + { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, + { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, + { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, + { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, + { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, + { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, + { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, + { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, + { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, + { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, + { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, + { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, + { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, + { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, + { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, + { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, + { insn_invalid, 0, 0 } +}; + +#undef M + +static inline __uasminit u32 build_bimm(s32 arg) +{ + if(arg > 0x1ffff || arg < -0x20000) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + if(arg & 0x3) + printk(KERN_WARNING "Invalid micro-assembler branch target\n"); + + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); +} + +static inline __uasminit u32 build_jimm(u32 arg) +{ + if(arg & ~(JIMM_MASK << 2)) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + return (arg >> 2) & JIMM_MASK; +} + +/* + * The order of opcode arguments is implicitly left to right, + * starting with RS and ending with FUNC or IMM. + */ +static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) +{ + struct insn *ip = NULL; + unsigned int i; + va_list ap; + u32 op; + + for (i = 0; insn_table[i].opcode != insn_invalid; i++) + if (insn_table[i].opcode == opc) { + ip = &insn_table[i]; + break; + } + + if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) + panic("Unsupported Micro-assembler instruction %d", opc); + + op = ip->match; + va_start(ap, opc); + if (ip->fields & RS) + op |= build_rs(va_arg(ap, u32)); + if (ip->fields & RT) + op |= build_rt(va_arg(ap, u32)); + if (ip->fields & RD) + op |= build_rd(va_arg(ap, u32)); + if (ip->fields & RE) + op |= build_re(va_arg(ap, u32)); + if (ip->fields & SIMM) + op |= build_simm(va_arg(ap, s32)); + if (ip->fields & UIMM) + op |= build_uimm(va_arg(ap, u32)); + if (ip->fields & BIMM) + op |= build_bimm(va_arg(ap, s32)); + if (ip->fields & JIMM) + op |= build_jimm(va_arg(ap, u32)); + if (ip->fields & FUNC) + op |= build_func(va_arg(ap, u32)); + if (ip->fields & SET) + op |= build_set(va_arg(ap, u32)); + if (ip->fields & SCIMM) + op |= build_scimm(va_arg(ap, u32)); + va_end(ap); + + **buf = op; + (*buf)++; +} + +static inline void __uasminit +__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) +{ + long laddr = (long)lab->addr; + long raddr = (long)rel->addr; + + switch (rel->type) { + case R_MIPS_PC16: + *rel->addr |= build_bimm(laddr - (raddr + 4)); + break; + + default: + panic("Unsupported Micro-assembler relocation %d", + rel->type); + } +} diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index f6ba16e..51728b7 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -10,6 +10,7 @@ * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer * Copyright (C) 2005, 2007 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include @@ -38,9 +39,18 @@ enum fields { #define OP_MASK 0x3f #define OP_SH 26 #define RS_MASK 0x1f -#define RS_SH 21 #define RT_MASK 0x1f +#ifdef CONFIG_CPU_MICROMIPS +#define RS_SH 16 +#define RT_SH 21 +#define SCIMM_MASK 0x3ff +#define SCIMM_SH 16 +#else +#define RS_SH 21 #define RT_SH 16 +#define SCIMM_MASK 0xfffff +#define SCIMM_SH 6 +#endif #define RD_MASK 0x1f #define RD_SH 11 #define RE_MASK 0x1f @@ -53,8 +63,6 @@ enum fields { #define FUNC_SH 0 #define SET_MASK 0x7 #define SET_SH 0 -#define SCIMM_MASK 0xfffff -#define SCIMM_SH 6 enum opcode { insn_invalid, @@ -78,216 +86,83 @@ struct insn { enum fields fields; }; -/* This macro sets the non-variable bits of an instruction. */ -#define M(a, b, c, d, e, f) \ - ((a) << OP_SH \ - | (b) << RS_SH \ - | (c) << RT_SH \ - | (d) << RD_SH \ - | (e) << RE_SH \ - | (f) << FUNC_SH) - -static struct insn insn_table[] __uasminitdata = { - { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, - { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, - { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, - { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, - { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, - { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, - { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, - { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, - { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, - { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, - { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, - { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, - { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, - { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, - { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, - { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, - { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, - { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, - { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, - { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, - { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, - { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, - { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, - { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, - { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, - { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, - { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, - { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, - { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, - { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, - { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, - { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, - { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, - { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, - { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, - { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, - { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, - { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, - { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, - { insn_invalid, 0, 0 } -}; - -#undef M - static inline __uasminit u32 build_rs(u32 arg) { - WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RS_MASK) + printk(KERN_WARNING "Micro-assembler RS field overflow\n"); return (arg & RS_MASK) << RS_SH; } static inline __uasminit u32 build_rt(u32 arg) { - WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RT_MASK) + printk(KERN_WARNING "Micro-assembler RT field overflow\n"); return (arg & RT_MASK) << RT_SH; } static inline __uasminit u32 build_rd(u32 arg) { - WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RD_MASK) + printk(KERN_WARNING "Micro-assembler RD field overflow\n"); return (arg & RD_MASK) << RD_SH; } static inline __uasminit u32 build_re(u32 arg) { - WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~RE_MASK) + printk(KERN_WARNING "Micro-assembler RE field overflow\n"); return (arg & RE_MASK) << RE_SH; } static inline __uasminit u32 build_simm(s32 arg) { - WARN(arg > 0x7fff || arg < -0x8000, - KERN_WARNING "Micro-assembler field overflow\n"); + if (arg > 0x7fff || arg < -0x8000) + printk(KERN_WARNING "Micro-assembler SIMM field overflow\n"); return arg & 0xffff; } static inline __uasminit u32 build_uimm(u32 arg) { - WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~IMM_MASK) + printk(KERN_WARNING "Micro-assembler UIMM field overflow\n"); return arg & IMM_MASK; } -static inline __uasminit u32 build_bimm(s32 arg) -{ - WARN(arg > 0x1ffff || arg < -0x20000, - KERN_WARNING "Micro-assembler field overflow\n"); - - WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); - - return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); -} - -static inline __uasminit u32 build_jimm(u32 arg) -{ - WARN(arg & ~(JIMM_MASK << 2), - KERN_WARNING "Micro-assembler field overflow\n"); - - return (arg >> 2) & JIMM_MASK; -} - static inline __uasminit u32 build_scimm(u32 arg) { - WARN(arg & ~SCIMM_MASK, - KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~SCIMM_MASK) + printk(KERN_WARNING "Micro-assembler SCIMM field overflow\n"); return (arg & SCIMM_MASK) << SCIMM_SH; } static inline __uasminit u32 build_func(u32 arg) { - WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~FUNC_MASK) + printk(KERN_WARNING "Micro-assembler FUNC field overflow\n"); return arg & FUNC_MASK; } static inline __uasminit u32 build_set(u32 arg) { - WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); + if (arg & ~SET_MASK) + printk(KERN_WARNING "Micro-assembler SET field overflow\n"); return arg & SET_MASK; } -/* - * The order of opcode arguments is implicitly left to right, - * starting with RS and ending with FUNC or IMM. - */ -static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) -{ - struct insn *ip = NULL; - unsigned int i; - va_list ap; - u32 op; - - for (i = 0; insn_table[i].opcode != insn_invalid; i++) - if (insn_table[i].opcode == opc) { - ip = &insn_table[i]; - break; - } - - if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) - panic("Unsupported Micro-assembler instruction %d", opc); - - op = ip->match; - va_start(ap, opc); - if (ip->fields & RS) - op |= build_rs(va_arg(ap, u32)); - if (ip->fields & RT) - op |= build_rt(va_arg(ap, u32)); - if (ip->fields & RD) - op |= build_rd(va_arg(ap, u32)); - if (ip->fields & RE) - op |= build_re(va_arg(ap, u32)); - if (ip->fields & SIMM) - op |= build_simm(va_arg(ap, s32)); - if (ip->fields & UIMM) - op |= build_uimm(va_arg(ap, u32)); - if (ip->fields & BIMM) - op |= build_bimm(va_arg(ap, s32)); - if (ip->fields & JIMM) - op |= build_jimm(va_arg(ap, u32)); - if (ip->fields & FUNC) - op |= build_func(va_arg(ap, u32)); - if (ip->fields & SET) - op |= build_set(va_arg(ap, u32)); - if (ip->fields & SCIMM) - op |= build_scimm(va_arg(ap, u32)); - va_end(ap); - - **buf = op; - (*buf)++; -} +#ifdef CONFIG_CPU_MICROMIPS +#include "uasm-micromips.c" +#else +#include "uasm-mips.c" +#endif #define I_u1u2u3(op) \ Ip_u1u2u3(op) \ @@ -552,23 +427,6 @@ uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) } UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); -static inline void __uasminit -__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) -{ - long laddr = (long)lab->addr; - long raddr = (long)rel->addr; - - switch (rel->type) { - case R_MIPS_PC16: - *rel->addr |= build_bimm(laddr - (raddr + 4)); - break; - - default: - panic("Unsupported Micro-assembler relocation %d", - rel->type); - } -} - void __uasminit uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) { -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:38 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:43:26 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49880 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903778Ab2GXVki (ORCPT ); Tue, 24 Jul 2012 23:40:38 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1StmqG-0003yS-Sd; Tue, 24 Jul 2012 16:40:32 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v3] MIPS: Add support for the M14KEc core. Date: Tue, 24 Jul 2012 16:40:28 -0500 Message-Id: <1343166028-1861-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33979 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5138 Lines: 155 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/cpu-features.h | 3 +++ arch/mips/include/asm/cpu.h | 4 +++- arch/mips/include/asm/mipsregs.h | 1 + arch/mips/kernel/cpu-probe.c | 7 +++++++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_model_mipsxx.c | 4 ++++ 8 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 2daf1c5..98bee29 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -98,6 +98,9 @@ #ifndef kernel_uses_smartmips_rixi #define kernel_uses_smartmips_rixi 0 #endif +#ifndef cpu_has_mmips +#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) +#endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index ad3caba..559bd12 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -96,6 +96,7 @@ #define PRID_IMP_1004K 0x9900 #define PRID_IMP_1074K 0x9a00 #define PRID_IMP_M14KC 0x9c00 +#define PRID_IMP_M14KEC 0x9e00 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -262,7 +263,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, - CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC, + CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC, CPU_M14KEC, /* * MIPS64 class processors @@ -319,6 +320,7 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ +#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index ac36bb9..ba3d53d 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -591,6 +591,7 @@ #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) +#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 78644e8..f3f42d7 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -200,6 +200,7 @@ void __init check_wait(void) break; case CPU_M14KC: + case CPU_M14KEC: case CPU_24K: case CPU_34K: case CPU_1004K: @@ -742,6 +743,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->ases |= MIPS_ASE_MIPSMT; if (config3 & MIPS_CONF3_ULRI) c->options |= MIPS_CPU_ULRI; + if (config3 & MIPS_CONF3_ISA) + c->options |= MIPS_CPU_MICROMIPS; return config3 & MIPS_CONF_M; } @@ -839,6 +842,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_M14KC; __cpu_name[cpu] = "MIPS M14Kc"; break; + case PRID_IMP_M14KEC: + c->cputype = CPU_M14KEC; + __cpu_name[cpu] = "MIPS M14KEc"; + break; case PRID_IMP_1004K: c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 71a4935..cb7d242 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1082,6 +1082,7 @@ static void __cpuinit probe_pcache(void) } /* fall through */ case CPU_M14KC: + case CPU_M14KEC: case CPU_24K: case CPU_34K: case CPU_1004K: diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 196641a..1566297 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -510,6 +510,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_4KC: case CPU_4KEC: case CPU_M14KC: + case CPU_M14KEC: case CPU_SB1: case CPU_SB1A: case CPU_4KSC: diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index b6e3782..ccf629a 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -79,6 +79,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) switch (current_cpu_type()) { case CPU_5KC: case CPU_M14KC: + case CPU_M14KEC: case CPU_20KC: case CPU_24K: case CPU_25KF: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 52da646..a86cc41 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -326,6 +326,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/M14Kc"; break; + case CPU_M14KEC: + op_model_mipsxx_ops.cpu_type = "mips/M14KEc"; + break; + case CPU_20KC: op_model_mipsxx_ops.cpu_type = "mips/20K"; break; -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:45 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:43:52 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49883 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903782Ab2GXVkp (ORCPT ); Tue, 24 Jul 2012 23:40:45 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1StmqN-0003yX-7v; Tue, 24 Jul 2012 16:40:39 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v3,02/10] MIPS: Changes to configuration files for SEAD-3 platform. Date: Tue, 24 Jul 2012 16:40:34 -0500 Message-Id: <1343166034-1895-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33980 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5818 Lines: 223 From: "Steven J. Hill" Change MIPS configuration files to add the SEAD-3. Also add new default configuration file for a SEAD-3 kernel. Signed-off-by: Steven J. Hill --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 33 +++++++++- arch/mips/configs/sead3_defconfig | 124 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 155 insertions(+), 3 deletions(-) create mode 100644 arch/mips/configs/sead3_defconfig diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 5ce8029..84a3a81 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -16,6 +16,7 @@ platforms += lasat platforms += loongson platforms += mipssim platforms += mti-malta +platforms += mti-sead3 platforms += netlogic platforms += pmc-sierra platforms += pnx833x diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 437b2cb..78fdba4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -304,6 +304,35 @@ config MIPS_MALTA This enables support for the MIPS Technologies Malta evaluation board. +config MIPS_SEAD3 + bool "MIPS SEAD3 board" + select BOOT_ELF32 + select BOOT_RAW + select CEVT_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select IRQ_GIC + select MIPS_BOARDS_GEN + select MIPS_CPU_SCACHE + select MIPS_MSC + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R1 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_SMARTMIPS + select SYS_SUPPORTS_MICROMIPS + select USB_ARCH_HAS_EHCI + select USB_EHCI_BIG_ENDIAN_DESC + select USB_EHCI_BIG_ENDIAN_MMIO + help + This enables support for the MIPS Technologies SEAD3 evaluation + board. + config MIPS_SIM bool 'MIPS simulator (MIPSsim)' select CEVT_R4K @@ -1711,7 +1740,6 @@ config HARDWARE_WATCHPOINTS menu "Kernel type" choice - prompt "Kernel code model" help You should only select this option if you have a workload that @@ -1855,7 +1883,7 @@ config MIPS_MT_DISABLED config MIPS_MT_SMP bool "Use 1 TC on each available VPE for SMP" - depends on SYS_SUPPORTS_MULTITHREADING + depends on SYS_SUPPORTS_MULTITHREADING && !MIPS_SEAD3 select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT @@ -1919,7 +1947,6 @@ config SCHED_SMT config SYS_SUPPORTS_SCHED_SMT bool - config SYS_SUPPORTS_MULTITHREADING bool diff --git a/arch/mips/configs/sead3_defconfig b/arch/mips/configs/sead3_defconfig new file mode 100644 index 0000000..e3eec68 --- /dev/null +++ b/arch/mips/configs/sead3_defconfig @@ -0,0 +1,124 @@ +CONFIG_MIPS_SEAD3=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_ICPLUS_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_CONSOLE_TRANSLATIONS is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=32 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_SPI=y +CONFIG_SENSORS_ADT7475=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +# CONFIG_FTRACE is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:44:16 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49884 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903654Ab2GXVkv (ORCPT ); Tue, 24 Jul 2012 23:40:51 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1StmqS-0003yc-GG; Tue, 24 Jul 2012 16:40:44 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Update MALTA config files. Date: Tue, 24 Jul 2012 16:40:40 -0500 Message-Id: <1343166040-1936-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33981 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 27302 Lines: 1043 From: "Steven J. Hill" Update all the MIPS Technologies MALTA configuration files. This patch will pick up all the new configuratin options added from the previous patches. Signed-off-by: Steven J. Hill --- arch/mips/configs/malta_defconfig | 55 +++------ arch/mips/configs/maltaaprp_defconfig | 200 +++++++++++++++++++++++++++++++++ arch/mips/configs/maltasmtc_defconfig | 202 +++++++++++++++++++++++++++++++++ arch/mips/configs/maltasmvp_defconfig | 205 ++++++++++++++++++++++++++++++++++ arch/mips/configs/maltaup_defconfig | 198 ++++++++++++++++++++++++++++++++ 5 files changed, 818 insertions(+), 42 deletions(-) create mode 100644 arch/mips/configs/maltaaprp_defconfig create mode 100644 arch/mips/configs/maltasmtc_defconfig create mode 100644 arch/mips/configs/maltasmvp_defconfig create mode 100644 arch/mips/configs/maltaup_defconfig diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 5527abb..e3dfe9e 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -2,30 +2,22 @@ CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y CONFIG_MIPS_MT_SMP=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_HZ_100=y CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=15 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_IPC_NS=y -CONFIG_PID_NS=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_RELAY=y CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_PCI=y -CONFIG_PM=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_XFRM_USER=m @@ -41,8 +33,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y @@ -65,7 +55,6 @@ CONFIG_IPV6_MROUTE=y CONFIG_IPV6_PIMSM_V2=y CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y @@ -141,19 +130,16 @@ CONFIG_IP_VS_FTP=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m @@ -163,7 +149,6 @@ CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -174,7 +159,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m @@ -244,16 +228,15 @@ CONFIG_NET_ACT_SIMP=m CONFIG_NET_ACT_SKBEDIT=m CONFIG_NET_CLS_IND=y CONFIG_CFG80211=m +CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_MAC80211=m CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_DEFAULT_PID=y CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CONNECTOR=m CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_OOPS=m @@ -272,7 +255,6 @@ CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m CONFIG_ATA_OVER_ETH=m -# CONFIG_MISC_DEVICES is not set CONFIG_IDE=y CONFIG_BLK_DEV_IDECD=y CONFIG_IDE_GENERIC=y @@ -318,13 +300,19 @@ CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_NETDEVICES=y -CONFIG_IFB=m -CONFIG_DUMMY=m CONFIG_BONDING=m -CONFIG_MACVLAN=m +CONFIG_DUMMY=m CONFIG_EQUALIZER=m +CONFIG_IFB=m +CONFIG_MACVLAN=m CONFIG_TUN=m CONFIG_VETH=m +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_PCNET32=y +CONFIG_CHELSIO_T3=m +CONFIG_AX88796=m +CONFIG_NETXEN_NIC=m +CONFIG_TC35815=m CONFIG_MARVELL_PHY=m CONFIG_DAVICOM_PHY=m CONFIG_QSEMI_PHY=m @@ -335,14 +323,6 @@ CONFIG_SMSC_PHY=m CONFIG_BROADCOM_PHY=m CONFIG_ICPLUS_PHY=m CONFIG_REALTEK_PHY=m -CONFIG_MDIO_BITBANG=m -CONFIG_NET_ETHERNET=y -CONFIG_AX88796=m -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -CONFIG_TC35815=m -CONFIG_CHELSIO_T3=m -CONFIG_NETXEN_NIC=m CONFIG_ATMEL=m CONFIG_PCI_ATMEL=m CONFIG_PRISM54=m @@ -374,12 +354,6 @@ CONFIG_FB_CIRRUS=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_HID=m -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_IDE_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_CMOS=y CONFIG_UIO=m @@ -399,7 +373,6 @@ CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_QUOTA=y CONFIG_QFMT_V2=y -CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_ISO9660_FS=m CONFIG_JOLIET=y @@ -426,7 +399,6 @@ CONFIG_ROMFS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NFSD=y CONFIG_NFSD_V3=y @@ -467,7 +439,6 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_LRW=m diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig new file mode 100644 index 0000000..ee37c4d --- /dev/null +++ b/arch/mips/configs/maltaaprp_defconfig @@ -0,0 +1,200 @@ +CONFIG_MIPS_MALTA=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_APSP_API=y +# CONFIG_MIPS_APSP_KSPD is not set +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="aprp" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_LRO is not set +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_CLS_IND=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_IDE=y +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_PIIX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_WLAN is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_G=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/configs/maltasmtc_defconfig b/arch/mips/configs/maltasmtc_defconfig new file mode 100644 index 0000000..f7fa921 --- /dev/null +++ b/arch/mips/configs/maltasmtc_defconfig @@ -0,0 +1,202 @@ +CONFIG_MIPS_MALTA=y +CONFIG_CSRC_R4K=y +CONFIG_CSRC_GIC=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_MIPS_MT_SMTC=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_NR_CPUS=9 +CONFIG_HZ_48=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="smtc" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_LRO is not set +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_CLS_IND=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_IDE=y +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_PIIX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_WLAN is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_G=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig new file mode 100644 index 0000000..2c56134 --- /dev/null +++ b/arch/mips/configs/maltasmvp_defconfig @@ -0,0 +1,205 @@ +CONFIG_MIPS_MALTA=y +CONFIG_CSRC_R4K=y +CONFIG_CSRC_GIC=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_MIPS_MT_SMP=y +CONFIG_SCHED_SMT=y +CONFIG_MIPS_CMP=y +CONFIG_NR_CPUS=8 +CONFIG_HZ_48=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="cmp" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_LRO is not set +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_CLS_IND=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_IDE=y +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_PIIX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_G=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/configs/maltaup_defconfig b/arch/mips/configs/maltaup_defconfig new file mode 100644 index 0000000..ab3d8f4 --- /dev/null +++ b/arch/mips/configs/maltaup_defconfig @@ -0,0 +1,198 @@ +CONFIG_MIPS_MALTA=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HZ_100=y +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="up" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=m +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +# CONFIG_INET_LRO is not set +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_CLS_IND=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_IDE=y +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_GENERIC=y +CONFIG_BLK_DEV_PIIX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_PCNET32=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_WLAN is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_G=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set -- 1.7.11.1 From sjhill@mips.com Tue Jul 24 23:40:56 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Jul 2012 23:44:42 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:49887 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903786Ab2GXVk4 (ORCPT ); Tue, 24 Jul 2012 23:40:56 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1StmqX-0003yh-F3; Tue, 24 Jul 2012 16:40:49 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Whitespace and various formatting clean-ups for microMIPS. Date: Tue, 24 Jul 2012 16:40:45 -0500 Message-Id: <1343166045-1974-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.11.1 X-archive-position: 33982 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 12337 Lines: 393 From: "Steven J. Hill" Signed-off-by: Steven J. Hill --- arch/mips/include/asm/inst.h | 134 +++++++++++++++++++++---------------------- arch/mips/kernel/proc.c | 5 +- arch/mips/kernel/traps.c | 4 +- 3 files changed, 72 insertions(+), 71 deletions(-) diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 6212f58..39f943c 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -262,7 +262,7 @@ struct ma_format { /* FPU multiply and add format (MIPS IV) */ unsigned int fmt : 2; }; -struct b_format { /* BREAK and SYSCALL */ +struct b_format { /* BREAK and SYSCALL */ unsigned int opcode:6; unsigned int code:20; unsigned int func:6; @@ -276,7 +276,7 @@ struct fb_format { /* FPU branch format */ unsigned int simmediate:16; }; -struct fp0_format { /* FPU multipy and add format (MIPS32) */ +struct fp0_format { /* FPU multipy and add format (MIPS32) */ unsigned int opcode:6; unsigned int fmt:5; unsigned int ft:5; @@ -285,7 +285,7 @@ struct fp0_format { /* FPU multipy and add format (MIPS32) */ unsigned int func:6; }; -struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ unsigned int opcode:6; unsigned int ft:5; unsigned int fs:5; @@ -295,7 +295,7 @@ struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ unsigned int func:6; }; -struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ unsigned int opcode:6; unsigned int op:5; unsigned int rt:5; @@ -304,7 +304,7 @@ struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ unsigned int func:6; }; -struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ unsigned int opcode:6; unsigned int rt:5; unsigned int fs:5; @@ -313,7 +313,7 @@ struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ unsigned int func:6; }; -struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ unsigned int opcode:6; unsigned int fd:5; unsigned int fs:5; @@ -324,7 +324,7 @@ struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ unsigned int func:6; }; -struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ unsigned int opcode:6; unsigned int rt:5; unsigned int fs:5; @@ -333,7 +333,7 @@ struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ unsigned int func:6; }; -struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ unsigned int opcode:6; unsigned int rt:5; unsigned int fs:5; @@ -343,7 +343,7 @@ struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ unsigned int func:6; }; -struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ unsigned int opcode:6; unsigned int index:5; unsigned int base:5; @@ -370,20 +370,20 @@ struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ unsigned int func:6; }; -struct mm16b1_format { /* microMIPS 16-bit branch format */ +struct mm16b1_format { /* microMIPS 16-bit branch format */ unsigned int opcode:6; unsigned int rs:3; signed int simmediate:7; unsigned int duplicate:16; /* a copy of the instr */ }; -struct mm16b0_format { /* microMIPS 16-bit branch format */ +struct mm16b0_format { /* microMIPS 16-bit branch format */ unsigned int opcode:6; signed int simmediate:10; unsigned int duplicate:16; /* a copy of the instr */ }; -struct mm_i_format { /* Immediate format (addi, lw, ...) */ +struct mm_i_format { /* Immediate format (addi, lw, ...) */ unsigned int opcode:6; unsigned int rt:5; unsigned int rs:5; @@ -495,72 +495,72 @@ struct j_format { /* Jump format */ }; struct i_format { /* Immediate format */ - signed int simmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + signed int simmediate:16; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct u_format { /* Unsigned immediate format */ - unsigned int uimmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int uimmediate:16; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct c_format { /* Cache (>= R6000) format */ - unsigned int simmediate : 16; - unsigned int cache : 2; - unsigned int c_op : 3; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int simmediate:16; + unsigned int cache:2; + unsigned int c_op:3; + unsigned int rs:5; + unsigned int opcode:6; }; struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int rs:5; + unsigned int opcode:6; }; struct f_format { /* FPU register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int fmt : 4; - unsigned int : 1; - unsigned int opcode : 6; + unsigned int func:6; + unsigned int re:5; + unsigned int rd:5; + unsigned int rt:5; + unsigned int fmt:4; + unsigned int:1; + unsigned int opcode:6; }; -struct ma_format { /* FPU multiply and add format (MIPS IV) */ - unsigned int fmt : 2; - unsigned int func : 4; - unsigned int fd : 5; - unsigned int fs : 5; - unsigned int ft : 5; - unsigned int fr : 5; - unsigned int opcode : 6; +struct ma_format { /* FPU multipy and add format (MIPS IV) */ + unsigned int fmt:2; + unsigned int func:4; + unsigned int fd:5; + unsigned int fs:5; + unsigned int ft:5; + unsigned int fr:5; + unsigned int opcode:6; }; -struct b_format { /* BREAK and SYSCALL */ +struct b_format { /* BREAK and SYSCALL */ unsigned int func:6; unsigned int code:20; unsigned int opcode:6; }; -struct fb_format { /* FPU branch format */ +struct fb_format { /* FPU branch format */ unsigned int simmediate:16; unsigned int flag:2; unsigned int cc:3; @@ -568,7 +568,7 @@ struct fb_format { /* FPU branch format */ unsigned int opcode:6; }; -struct fp0_format { /* FPU multipy and add format (MIPS32) */ +struct fp0_format { /* FPU multipy and add format (MIPS32) */ unsigned int func:6; unsigned int fd:5; unsigned int fs:5; @@ -577,7 +577,7 @@ struct fp0_format { /* FPU multipy and add format (MIPS32) */ unsigned int opcode:6; }; -struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ unsigned int func:6; unsigned int op:2; unsigned int fmt:3; @@ -587,7 +587,7 @@ struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ unsigned int opcode:6; }; -struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ unsigned int func:6; unsigned int fd:5; unsigned int fs:5; @@ -596,7 +596,7 @@ struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ unsigned int opcode:6; }; -struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ unsigned int func:6; unsigned int op:8; unsigned int fmt:2; @@ -605,7 +605,7 @@ struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ unsigned int opcode:6; }; -struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ unsigned int func:6; unsigned int op:3; unsigned int fmt:2; @@ -616,7 +616,7 @@ struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ unsigned int opcode:6; }; -struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ unsigned int func:6; unsigned int op:7; unsigned int fmt:3; @@ -625,7 +625,7 @@ struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ unsigned int opcode:6; }; -struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ unsigned int func:6; unsigned int cond:4; unsigned int fmt:3; @@ -635,7 +635,7 @@ struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ unsigned int opcode:6; }; -struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ unsigned int func:6; unsigned int op:5; unsigned int fd:5; @@ -644,7 +644,7 @@ struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ unsigned int opcode:6; }; -struct fp6_format { /* FPU madd and msub format (MIPS IV) */ +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ unsigned int func:6; unsigned int fd:5; unsigned int fs:5; @@ -653,7 +653,7 @@ struct fp6_format { /* FPU madd and msub format (MIPS IV) */ unsigned int opcode:6; }; -struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ +struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ unsigned int func:6; unsigned int fr:5; unsigned int fd:5; @@ -662,20 +662,20 @@ struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ unsigned int opcode:6; }; -struct mm16b1_format { /* microMIPS 16-bit branch format */ +struct mm16b1_format { /* microMIPS 16-bit branch format */ unsigned int duplicate:16; /* a copy of the instr */ signed int simmediate:7; unsigned int rs:3; unsigned int opcode:6; }; -struct mm16b0_format { /* microMIPS 16-bit branch format */ +struct mm16b0_format { /* microMIPS 16-bit branch format */ unsigned int duplicate:16; /* a copy of the instr */ signed int simmediate:10; unsigned int opcode:6; }; -struct mm_i_format { /* Immediate format */ +struct mm_i_format { /* Immediate format */ signed int simmediate:16; unsigned int rs:5; unsigned int rt:5; diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 5542817..5569d09 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -64,13 +64,14 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_data[n].watch_reg_masks[i]); seq_printf(m, "]\n"); } - seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", + seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s%s\n", cpu_has_mips16 ? " mips16" : "", cpu_has_mdmx ? " mdmx" : "", cpu_has_mips3d ? " mips3d" : "", cpu_has_smartmips ? " smartmips" : "", cpu_has_dsp ? " dsp" : "", - cpu_has_mipsmt ? " mt" : "" + cpu_has_mipsmt ? " mt" : "", + cpu_has_mmips ? " micromips" : "" ); seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 516668c..8322ce9 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -514,7 +514,7 @@ static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); if ((unsigned long)vaddr & 3) return SIGBUS; @@ -554,7 +554,7 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) offset >>= 16; vaddr = (unsigned long __user *) - ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); reg = (opcode & RT) >> 16; if ((unsigned long)vaddr & 3) -- 1.7.11.1 From keguang.zhang@gmail.com Wed Jul 25 08:06:57 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 25 Jul 2012 08:07:06 +0200 (CEST) Received: from mail-gg0-f177.google.com ([209.85.161.177]:60713 "EHLO mail-gg0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1901173Ab2GYGG5 (ORCPT ); Wed, 25 Jul 2012 08:06:57 +0200 Received: by ggcs5 with SMTP id s5so356961ggc.36 for ; Tue, 24 Jul 2012 23:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=3ju8WvNY7xi2GYeY5hi8LsLpK3ktSZrCS5nbhLjRKCY=; b=dNtl9E5WKnJ4fWvWKGPAWLYGftyCMOfwUpXiTMzmGeXh93JIL05lkiZfdB3RfnDfOA 0qNDqDkosaZyp3cXK4wXUrYUHtvz4zruwvMq+CqWleXhXyafaWkc6lyUeODXO+PDj5UR rrNVR55t1UZM9qHBb47EByNhnDXoVPWMtRdlzR85U0vS3DhTERbCd8Hy57cSfZvbR6JQ wGPQ9rpHBnCxtWDY0rR4aVzWGkjGASx1fos8bt4o3Nw3uvGcqvYNQ8XMO570BoU3bSic Vgn0vfwhmJgBn6yEiS0Qb3k5odOi99sV5TCl4jlWY1zHsub+uNiiGUPr319qUD69DZ29 /vlQ== Received: by 10.68.217.73 with SMTP id ow9mr51492639pbc.75.1343196410164; Tue, 24 Jul 2012 23:06:50 -0700 (PDT) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id pj10sm13694271pbb.46.2012.07.24.23.06.45 (version=SSLv3 cipher=OTHER); Tue, 24 Jul 2012 23:06:49 -0700 (PDT) From: Kelvin Cheung To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ralf@linux-mips.org Cc: wuzhangjin@gmail.com, zhzhl555@gmail.com, Kelvin Cheung Subject: [PATCH V7 2/4] (Updated) MIPS: Add board support for Loongson1B Date: Wed, 25 Jul 2012 14:06:39 +0800 Message-Id: <1343196401-6435-1-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 X-archive-position: 33983 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 27746 Lines: 1011 This patch adds basic platform devices for Loongson1B, including serial port, ethernet, usb, rtc and interrupt handler. Loongson1B UART is compatible with NS16550A. Loongson1B GMAC is built around Synopsys IP Core. Use normal descriptor instead of enhanced descriptor. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung --- V7(updated): 1.Remove 'ifdef' of platform devices. (Asked by Ralf) 2.Modify plat_stmmacenet_data accordingly due to the change of upstream. --- arch/mips/include/asm/mach-loongson1/irq.h | 73 ++++++++++ arch/mips/include/asm/mach-loongson1/loongson1.h | 44 ++++++ arch/mips/include/asm/mach-loongson1/platform.h | 23 +++ arch/mips/include/asm/mach-loongson1/prom.h | 24 +++ arch/mips/include/asm/mach-loongson1/regs-clk.h | 33 +++++ arch/mips/include/asm/mach-loongson1/regs-wdt.h | 22 +++ arch/mips/include/asm/mach-loongson1/war.h | 25 ++++ arch/mips/loongson1/common/clock.c | 165 ++++++++++++++++++++++ arch/mips/loongson1/common/irq.c | 147 +++++++++++++++++++ arch/mips/loongson1/common/platform.c | 124 ++++++++++++++++ arch/mips/loongson1/common/prom.c | 87 ++++++++++++ arch/mips/loongson1/common/reset.c | 45 ++++++ arch/mips/loongson1/common/setup.c | 29 ++++ arch/mips/loongson1/ls1b/board.c | 33 +++++ 14 files changed, 874 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h create mode 100644 arch/mips/include/asm/mach-loongson1/war.h create mode 100644 arch/mips/loongson1/common/clock.c create mode 100644 arch/mips/loongson1/common/irq.c create mode 100644 arch/mips/loongson1/common/platform.c create mode 100644 arch/mips/loongson1/common/prom.c create mode 100644 arch/mips/loongson1/common/reset.c create mode 100644 arch/mips/loongson1/common/setup.c create mode 100644 arch/mips/loongson1/ls1b/board.c diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h new file mode 100644 index 0000000..ccc42cc --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/irq.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * IRQ mappings for Loongson1. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_IRQ_H +#define __ASM_MACH_LOONGSON1_IRQ_H + +/* + * CPU core Interrupt Numbers + */ +#define MIPS_CPU_IRQ_BASE 0 +#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) + +#define SOFTINT0_IRQ MIPS_CPU_IRQ(0) +#define SOFTINT1_IRQ MIPS_CPU_IRQ(1) +#define INT0_IRQ MIPS_CPU_IRQ(2) +#define INT1_IRQ MIPS_CPU_IRQ(3) +#define INT2_IRQ MIPS_CPU_IRQ(4) +#define INT3_IRQ MIPS_CPU_IRQ(5) +#define INT4_IRQ MIPS_CPU_IRQ(6) +#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ + +#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) + +/* + * INT0~3 Interrupt Numbers + */ +#define LS1X_IRQ_BASE MIPS_CPU_IRQS +#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) + +#define LS1X_UART0_IRQ LS1X_IRQ(0, 2) +#define LS1X_UART1_IRQ LS1X_IRQ(0, 3) +#define LS1X_UART2_IRQ LS1X_IRQ(0, 4) +#define LS1X_UART3_IRQ LS1X_IRQ(0, 5) +#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) +#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) +#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) +#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) +#define LS1X_AC97_IRQ LS1X_IRQ(0, 10) +#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) +#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) +#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) +#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) +#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) +#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) +#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) +#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) +#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) +#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) +#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) +#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) +#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) +#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) +#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) + +#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) +#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) +#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) +#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) + +#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE) + +#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) + +#endif /* __ASM_MACH_LOONGSON1_IRQ_H */ diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h new file mode 100644 index 0000000..0440627 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/loongson1.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Register mappings for Loongson1. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H +#define __ASM_MACH_LOONGSON1_LOONGSON1_H + +#define DEFAULT_MEMSIZE 256 /* If no memsize provided */ + +/* Loongson1 Register Bases */ +#define LS1X_INTC_BASE 0x1fd01040 +#define LS1X_EHCI_BASE 0x1fe00000 +#define LS1X_OHCI_BASE 0x1fe08000 +#define LS1X_GMAC0_BASE 0x1fe10000 +#define LS1X_GMAC1_BASE 0x1fe20000 + +#define LS1X_UART0_BASE 0x1fe40000 +#define LS1X_UART1_BASE 0x1fe44000 +#define LS1X_UART2_BASE 0x1fe48000 +#define LS1X_UART3_BASE 0x1fe4c000 +#define LS1X_CAN0_BASE 0x1fe50000 +#define LS1X_CAN1_BASE 0x1fe54000 +#define LS1X_I2C0_BASE 0x1fe58000 +#define LS1X_I2C1_BASE 0x1fe68000 +#define LS1X_I2C2_BASE 0x1fe70000 +#define LS1X_PWM_BASE 0x1fe5c000 +#define LS1X_WDT_BASE 0x1fe5c060 +#define LS1X_RTC_BASE 0x1fe64000 +#define LS1X_AC97_BASE 0x1fe74000 +#define LS1X_NAND_BASE 0x1fe78000 +#define LS1X_CLK_BASE 0x1fe78030 + +#include +#include + +#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */ diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h new file mode 100644 index 0000000..2f17161 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/platform.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H +#define __ASM_MACH_LOONGSON1_PLATFORM_H + +#include + +extern struct platform_device ls1x_uart_device; +extern struct platform_device ls1x_eth0_device; +extern struct platform_device ls1x_ehci_device; +extern struct platform_device ls1x_rtc_device; + +void ls1x_serial_setup(void); + +#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h new file mode 100644 index 0000000..b871dc4 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/prom.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_PROM_H +#define __ASM_MACH_LOONGSON1_PROM_H + +#include +#include +#include + +/* environment arguments from bootloader */ +extern unsigned long memsize, highmemsize; + +/* loongson-specific command line, env and memory initialization */ +extern char *prom_getenv(char *name); +extern void __init prom_init_cmdline(void); + +#endif /* __ASM_MACH_LOONGSON1_PROM_H */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h new file mode 100644 index 0000000..5b9635a --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Loongson1 Clock Register Definitions. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H +#define __ASM_MACH_LOONGSON1_REGS_CLK_H + +#define LS1X_CLK_REG(x) \ + ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x))) + +#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) +#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) + +/* Clock PLL Divisor Register Bits */ +#define DIV_DC_EN (0x1 << 31) +#define DIV_DC (0x1f << 26) +#define DIV_CPU_EN (0x1 << 25) +#define DIV_CPU (0x1f << 20) +#define DIV_DDR_EN (0x1 << 19) +#define DIV_DDR (0x1f << 14) + +#define DIV_DC_SHIFT 26 +#define DIV_CPU_SHIFT 20 +#define DIV_DDR_SHIFT 14 + +#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h new file mode 100644 index 0000000..d339fe7 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Loongson1 Watchdog register definitions. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H +#define __ASM_MACH_LOONGSON1_REGS_WDT_H + +#define LS1X_WDT_REG(x) \ + ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x))) + +#define LS1X_WDT_EN LS1X_WDT_REG(0x0) +#define LS1X_WDT_SET LS1X_WDT_REG(0x4) +#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8) + +#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */ diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h new file mode 100644 index 0000000..e3680a8 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson1/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_LOONGSON1_WAR_H +#define __ASM_MACH_LOONGSON1_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_LOONGSON1_WAR_H */ diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c new file mode 100644 index 0000000..2d98fb0 --- /dev/null +++ b/arch/mips/loongson1/common/clock.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +struct clk *clk_get(struct device *dev, const char *name) +{ + struct clk *c; + struct clk *ret = NULL; + + mutex_lock(&clocks_mutex); + list_for_each_entry(c, &clocks, node) { + if (!strcmp(c->name, name)) { + ret = c; + break; + } + } + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL(clk_get); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +static void pll_clk_init(struct clk *clk) +{ + u32 pll; + + pll = __raw_readl(LS1X_CLK_PLL_FREQ); + clk->rate = (12 + (pll & 0x3f)) * 33 / 2 + + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2; + clk->rate *= 1000000; +} + +static void cpu_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU; + clk->rate = pll / (ctrl >> DIV_CPU_SHIFT); +} + +static void ddr_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR; + clk->rate = pll / (ctrl >> DIV_DDR_SHIFT); +} + +static void dc_clk_init(struct clk *clk) +{ + u32 pll, ctrl; + + pll = clk_get_rate(clk->parent); + ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC; + clk->rate = pll / (ctrl >> DIV_DC_SHIFT); +} + +static struct clk_ops pll_clk_ops = { + .init = pll_clk_init, +}; + +static struct clk_ops cpu_clk_ops = { + .init = cpu_clk_init, +}; + +static struct clk_ops ddr_clk_ops = { + .init = ddr_clk_init, +}; + +static struct clk_ops dc_clk_ops = { + .init = dc_clk_init, +}; + +static struct clk pll_clk = { + .name = "pll", + .ops = &pll_clk_ops, +}; + +static struct clk cpu_clk = { + .name = "cpu", + .parent = &pll_clk, + .ops = &cpu_clk_ops, +}; + +static struct clk ddr_clk = { + .name = "ddr", + .parent = &pll_clk, + .ops = &ddr_clk_ops, +}; + +static struct clk dc_clk = { + .name = "dc", + .parent = &pll_clk, + .ops = &dc_clk_ops, +}; + +int clk_register(struct clk *clk) +{ + mutex_lock(&clocks_mutex); + list_add(&clk->node, &clocks); + if (clk->ops->init) + clk->ops->init(clk); + mutex_unlock(&clocks_mutex); + + return 0; +} +EXPORT_SYMBOL(clk_register); + +static struct clk *ls1x_clks[] = { + &pll_clk, + &cpu_clk, + &ddr_clk, + &dc_clk, +}; + +int __init ls1x_clock_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++) + clk_register(ls1x_clks[i]); + + return 0; +} + +void __init plat_time_init(void) +{ + struct clk *clk; + + /* Initialize LS1X clocks */ + ls1x_clock_init(); + + /* setup mips r4k timer */ + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get dc clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; +} diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/irq.c new file mode 100644 index 0000000..41bc8ff --- /dev/null +++ b/arch/mips/loongson1/common/irq.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include +#include + +#define LS1X_INTC_REG(n, x) \ + ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x))) + +#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0) +#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4) +#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8) +#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc) +#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10) +#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14) + +static void ls1x_irq_ack(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) + | (1 << bit), LS1X_INTC_INTCLR(n)); +} + +static void ls1x_irq_mask(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + & ~(1 << bit), LS1X_INTC_INTIEN(n)); +} + +static void ls1x_irq_mask_ack(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + & ~(1 << bit), LS1X_INTC_INTIEN(n)); + __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) + | (1 << bit), LS1X_INTC_INTCLR(n)); +} + +static void ls1x_irq_unmask(struct irq_data *d) +{ + unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; + unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; + + __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) + | (1 << bit), LS1X_INTC_INTIEN(n)); +} + +static struct irq_chip ls1x_irq_chip = { + .name = "LS1X-INTC", + .irq_ack = ls1x_irq_ack, + .irq_mask = ls1x_irq_mask, + .irq_mask_ack = ls1x_irq_mask_ack, + .irq_unmask = ls1x_irq_unmask, +}; + +static void ls1x_irq_dispatch(int n) +{ + u32 int_status, irq; + + /* Get pending sources, masked by current enables */ + int_status = __raw_readl(LS1X_INTC_INTISR(n)) & + __raw_readl(LS1X_INTC_INTIEN(n)); + + if (int_status) { + irq = LS1X_IRQ(n, __ffs(int_status)); + do_IRQ(irq); + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending; + + pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) + do_IRQ(TIMER_IRQ); + else if (pending & CAUSEF_IP2) + ls1x_irq_dispatch(0); /* INT0 */ + else if (pending & CAUSEF_IP3) + ls1x_irq_dispatch(1); /* INT1 */ + else if (pending & CAUSEF_IP4) + ls1x_irq_dispatch(2); /* INT2 */ + else if (pending & CAUSEF_IP5) + ls1x_irq_dispatch(3); /* INT3 */ + else if (pending & CAUSEF_IP6) + ls1x_irq_dispatch(4); /* INT4 */ + else + spurious_interrupt(); + +} + +struct irqaction cascade_irqaction = { + .handler = no_action, + .name = "cascade", + .flags = IRQF_NO_THREAD, +}; + +static void __init ls1x_irq_init(int base) +{ + int n; + + /* Disable interrupts and clear pending, + * setup all IRQs as high level triggered + */ + for (n = 0; n < 4; n++) { + __raw_writel(0x0, LS1X_INTC_INTIEN(n)); + __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n)); + __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n)); + /* set DMA0, DMA1 and DMA2 to edge trigger */ + __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n)); + } + + + for (n = base; n < LS1X_IRQS; n++) { + irq_set_chip_and_handler(n, &ls1x_irq_chip, + handle_level_irq); + } + + setup_irq(INT0_IRQ, &cascade_irqaction); + setup_irq(INT1_IRQ, &cascade_irqaction); + setup_irq(INT2_IRQ, &cascade_irqaction); + setup_irq(INT3_IRQ, &cascade_irqaction); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + ls1x_irq_init(LS1X_IRQ_BASE); +} diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/common/platform.c new file mode 100644 index 0000000..e92d59c --- /dev/null +++ b/arch/mips/loongson1/common/platform.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LS1X_UART(_id) \ + { \ + .mapbase = LS1X_UART ## _id ## _BASE, \ + .irq = LS1X_UART ## _id ## _IRQ, \ + .iotype = UPIO_MEM, \ + .flags = UPF_IOREMAP | UPF_FIXED_TYPE, \ + .type = PORT_16550A, \ + } + +static struct plat_serial8250_port ls1x_serial8250_port[] = { + LS1X_UART(0), + LS1X_UART(1), + LS1X_UART(2), + LS1X_UART(3), + {}, +}; + +struct platform_device ls1x_uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = ls1x_serial8250_port, + }, +}; + +void __init ls1x_serial_setup(void) +{ + struct clk *clk; + struct plat_serial8250_port *p; + + clk = clk_get(NULL, "dc"); + if (IS_ERR(clk)) + panic("unable to get dc clock, err=%ld", PTR_ERR(clk)); + + for (p = ls1x_serial8250_port; p->flags != 0; ++p) + p->uartclk = clk_get_rate(clk); +} + +/* Synopsys Ethernet GMAC */ +static struct resource ls1x_eth0_resources[] = { + [0] = { + .start = LS1X_GMAC0_BASE, + .end = LS1X_GMAC0_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "macirq", + .start = LS1X_GMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = { + .bus_id = 0, + .phy_mask = 0, +}; + +static struct plat_stmmacenet_data ls1x_eth_data = { + .bus_id = 0, + .phy_addr = -1, + .mdio_bus_data = &ls1x_mdio_bus_data, + .has_gmac = 1, + .tx_coe = 1, +}; + +struct platform_device ls1x_eth0_device = { + .name = "stmmaceth", + .id = 0, + .num_resources = ARRAY_SIZE(ls1x_eth0_resources), + .resource = ls1x_eth0_resources, + .dev = { + .platform_data = &ls1x_eth_data, + }, +}; + +/* USB EHCI */ +static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32); + +static struct resource ls1x_ehci_resources[] = { + [0] = { + .start = LS1X_EHCI_BASE, + .end = LS1X_EHCI_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = LS1X_EHCI_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ls1x_ehci_device = { + .name = "ls1x-ehci", + .id = -1, + .num_resources = ARRAY_SIZE(ls1x_ehci_resources), + .resource = ls1x_ehci_resources, + .dev = { + .dma_mask = &ls1x_ehci_dmamask, + }, +}; + +/* Real Time Clock */ +struct platform_device ls1x_rtc_device = { + .name = "ls1x-rtc", + .id = -1, +}; diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c new file mode 100644 index 0000000..1f8e49f --- /dev/null +++ b/arch/mips/loongson1/common/prom.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Modified from arch/mips/pnx833x/common/prom.c. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +unsigned long memsize, highmemsize; + +char *prom_getenv(char *envname) +{ + char **env = prom_envp; + int i; + + i = strlen(envname); + + while (*env) { + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') + return *env + i + 1; + env++; + } + + return 0; +} + +static inline unsigned long env_or_default(char *env, unsigned long dfl) +{ + char *str = prom_getenv(env); + return str ? simple_strtol(str, 0, 0) : dfl; +} + +void __init prom_init_cmdline(void) +{ + char *c = &(arcs_cmdline[0]); + int i; + + for (i = 1; i < prom_argc; i++) { + strcpy(c, prom_argv[i]); + c += strlen(prom_argv[i]); + if (i < prom_argc-1) + *c++ = ' '; + } + *c = 0; +} + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize = env_or_default("memsize", DEFAULT_MEMSIZE); + highmemsize = env_or_default("highmemsize", 0x0); +} + +void __init prom_free_prom_memory(void) +{ +} + +#define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset)) + +void __init prom_putchar(char c) +{ + int timeout; + + timeout = 1024; + + while (((readb(PORT(UART_LSR)) & UART_LSR_THRE) == 0) + && (timeout-- > 0)) + ; + + writeb(c, PORT(UART_TX)); +} diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c new file mode 100644 index 0000000..fb979a7 --- /dev/null +++ b/arch/mips/loongson1/common/reset.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include + +static void ls1x_restart(char *command) +{ + __raw_writel(0x1, LS1X_WDT_EN); + __raw_writel(0x5000000, LS1X_WDT_TIMER); + __raw_writel(0x1, LS1X_WDT_SET); +} + +static void ls1x_halt(void) +{ + while (1) { + if (cpu_wait) + cpu_wait(); + } +} + +static void ls1x_power_off(void) +{ + ls1x_halt(); +} + +static int __init ls1x_reboot_setup(void) +{ + _machine_restart = ls1x_restart; + _machine_halt = ls1x_halt; + pm_power_off = ls1x_power_off; + + return 0; +} + +arch_initcall(ls1x_reboot_setup); diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/common/setup.c new file mode 100644 index 0000000..62128cc --- /dev/null +++ b/arch/mips/loongson1/common/setup.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +void __init plat_mem_setup(void) +{ + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +} + +const char *get_system_type(void) +{ + unsigned int processor_id = (¤t_cpu_data)->processor_id; + + switch (processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON1B: + return "LOONGSON LS1B"; + default: + return "LOONGSON (unknown)"; + } +} diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c new file mode 100644 index 0000000..295b1be --- /dev/null +++ b/arch/mips/loongson1/ls1b/board.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +static struct platform_device *ls1b_platform_devices[] __initdata = { + &ls1x_uart_device, + &ls1x_eth0_device, + &ls1x_ehci_device, + &ls1x_rtc_device, +}; + +static int __init ls1b_platform_init(void) +{ + int err; + + ls1x_serial_setup(); + + err = platform_add_devices(ls1b_platform_devices, + ARRAY_SIZE(ls1b_platform_devices)); + return err; +} + +arch_initcall(ls1b_platform_init); -- 1.7.1 From keguang.zhang@gmail.com Wed Jul 25 08:07:00 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 25 Jul 2012 08:07:51 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:41249 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903468Ab2GYGHA (ORCPT ); Wed, 25 Jul 2012 08:07:00 +0200 Received: by pbbrq13 with SMTP id rq13so940607pbb.36 for ; Tue, 24 Jul 2012 23:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=80p4AWDn8gStwztO1Y57NIC1eU+Sr9lhkR8jhE+KrPc=; b=kjLOqH2xFEdMyB+gfR3c6+4ySyz5jjfNce3EspRurP2lqPDtMjVTHcGCDpyi51zRdJ 16TqdP1+vA9sGE77Xg/+qVlvFYFfk9jgGPru7RDuDNR2nXgtEzYSmCjlrMyF5EpUgZqA FYyfuQb5Zjc98HJlz8oAseyCF2blJX05w7w2qb1VTmCumE62Gv9hyamQlILN+ri38mBF JDYS2Nq1MxKe35hVAJPLH51ef5nCEgmZwuaU0hGDAKCGOwJ/tF34BNYLTNhqqafQd6ma a3CWnr3ACJEQisZNxtslLOYwWhuJUDEP3F6tvjkgMctihwHZNF3vqLwvhbQD5APOUylu UWTg== Received: by 10.68.136.229 with SMTP id qd5mr50802210pbb.2.1343196413706; Tue, 24 Jul 2012 23:06:53 -0700 (PDT) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id pj10sm13694271pbb.46.2012.07.24.23.06.50 (version=SSLv3 cipher=OTHER); Tue, 24 Jul 2012 23:06:53 -0700 (PDT) From: Kelvin Cheung To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ralf@linux-mips.org Cc: wuzhangjin@gmail.com, zhzhl555@gmail.com, Kelvin Cheung Subject: [PATCH V7 3/4] (Updated) MIPS: Add Makefile and Kconfig for Loongson1B Date: Wed, 25 Jul 2012 14:06:40 +0800 Message-Id: <1343196401-6435-2-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1343196401-6435-1-git-send-email-keguang.zhang@gmail.com> References: <1343196401-6435-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 33984 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5266 Lines: 186 This patch adds Makefile and Kconfig related to Loongson1B. Signed-off-by: Kelvin Cheung --- V7(updated): Change the load address of kernel to 0xffffffff80100000. --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 31 +++++++++++++++++++++++++++++++ arch/mips/loongson1/Kconfig | 21 +++++++++++++++++++++ arch/mips/loongson1/Makefile | 11 +++++++++++ arch/mips/loongson1/Platform | 7 +++++++ arch/mips/loongson1/common/Makefile | 5 +++++ arch/mips/loongson1/ls1b/Makefile | 5 +++++ 7 files changed, 81 insertions(+), 0 deletions(-) create mode 100644 arch/mips/loongson1/Kconfig create mode 100644 arch/mips/loongson1/Makefile create mode 100644 arch/mips/loongson1/Platform create mode 100644 arch/mips/loongson1/common/Makefile create mode 100644 arch/mips/loongson1/ls1b/Makefile diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 5ce8029..d64786d 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -14,6 +14,7 @@ platforms += jz4740 platforms += lantiq platforms += lasat platforms += loongson +platforms += loongson1 platforms += mipssim platforms += mti-malta platforms += netlogic diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 08dfc79..61e1459 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -265,6 +265,17 @@ config MACH_LOONGSON Chinese Academy of Sciences (CAS) in the People's Republic of China. The chief architect is Professor Weiwu Hu. +config MACH_LOONGSON1 + bool "Loongson1 family of machines" + select SYS_SUPPORTS_ZBOOT + help + This enables the support of Loongson1 family of machines. + + Loongson1 is a family of 32-bit MIPS-compatible SoCs. + developed at Institute of Computing Technology (ICT), + Chinese Academy of Sciences (CAS) in the People's Republic + of China. + config MIPS_MALTA bool "MIPS Malta board" select ARCH_MAY_HAVE_PC_FDC @@ -838,6 +849,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/loongson1/Kconfig" source "arch/mips/netlogic/Kconfig" endmenu @@ -1219,6 +1231,14 @@ config CPU_LOONGSON2F have a similar programming interface with FPGA northbridge used in Loongson2E. +config CPU_LOONGSON1B + bool "Loongson 1B" + depends on SYS_HAS_CPU_LOONGSON1B + select CPU_LOONGSON1 + help + The Loongson 1B is a 32-bit SoC, which implements the MIPS32 + release 2 instruction set. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1548,6 +1568,14 @@ config CPU_LOONGSON2 select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM +config CPU_LOONGSON1 + bool + select CPU_MIPS32 + select CPU_MIPSR2 + select CPU_HAS_PREFETCH + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + config CPU_BMIPS bool select CPU_MIPS32 @@ -1566,6 +1594,9 @@ config SYS_HAS_CPU_LOONGSON2F select CPU_SUPPORTS_ADDRWINCFG if 64BIT select CPU_SUPPORTS_UNCACHED_ACCELERATED +config SYS_HAS_CPU_LOONGSON1B + bool + config SYS_HAS_CPU_MIPS32_R1 bool diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig new file mode 100644 index 0000000..237fa21 --- /dev/null +++ b/arch/mips/loongson1/Kconfig @@ -0,0 +1,21 @@ +if MACH_LOONGSON1 + +choice + prompt "Machine Type" + +config LOONGSON1_LS1B + bool "Loongson LS1B board" + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON1B + select DMA_NONCOHERENT + select BOOT_ELF32 + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + +endchoice + +endif # MACH_LOONGSON1 diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile new file mode 100644 index 0000000..e9123c2 --- /dev/null +++ b/arch/mips/loongson1/Makefile @@ -0,0 +1,11 @@ +# +# Common code for all Loongson1 based systems +# + +obj-$(CONFIG_MACH_LOONGSON1) += common/ + +# +# Loongson LS1B board +# + +obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/ diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform new file mode 100644 index 0000000..99bdefe --- /dev/null +++ b/arch/mips/loongson1/Platform @@ -0,0 +1,7 @@ +cflags-$(CONFIG_CPU_LOONGSON1) += \ + $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ + -Wa,-mips32r2 -Wa,--trap + +platform-$(CONFIG_MACH_LOONGSON1) += loongson1/ +cflags-$(CONFIG_MACH_LOONGSON1) += -I$(srctree)/arch/mips/include/asm/mach-loongson1 +load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000 diff --git a/arch/mips/loongson1/common/Makefile b/arch/mips/loongson1/common/Makefile new file mode 100644 index 0000000..b279770 --- /dev/null +++ b/arch/mips/loongson1/common/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for common code of loongson1 based machines. +# + +obj-y += clock.o irq.o platform.o prom.o reset.o setup.o diff --git a/arch/mips/loongson1/ls1b/Makefile b/arch/mips/loongson1/ls1b/Makefile new file mode 100644 index 0000000..891eac4 --- /dev/null +++ b/arch/mips/loongson1/ls1b/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for loongson1B based machines. +# + +obj-y += board.o -- 1.7.1 From keguang.zhang@gmail.com Wed Jul 25 08:07:04 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 25 Jul 2012 08:09:26 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:42524 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1902235Ab2GYGHE (ORCPT ); Wed, 25 Jul 2012 08:07:04 +0200 Received: by pbbrq13 with SMTP id rq13so940719pbb.36 for ; Tue, 24 Jul 2012 23:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=E/+6Npb6c1lMdENGLTk3c2o9fCzoE8HiXHGWv6gfPsY=; b=wYy7hZFtVwSUPbDpkukOl2bR77uBYuhUTlFTI0FkrYi1UM2Kr8lwZBcGpBNH4IRMfg 8dVjZUbNbH/f29Xng6TXqosfSdBGuKQK8TLscP5CF5Cr3iXrWnXH3JyHTI/P9FCH8ut5 o6oiGNupGsrS0yLSHYqO7QrRCvYWk7weZdG2iLxWo6GpPaIjur3e2rKbsXEGNsm/yiWt cQ5Nnnb5KbsltKBVhYXtox7/SDcngShSiQHqydyifVrLl8zld5n7b7AE9Gax8cVHulHp bYZbz37Vfrh4Uz3fMebRG7z2vywCh4aecoxOC+DtCtykZQ4xc0z64URzv2Iw64MbYvUe fqoA== Received: by 10.68.193.196 with SMTP id hq4mr9346572pbc.76.1343196418040; Tue, 24 Jul 2012 23:06:58 -0700 (PDT) Received: from kelvin-Work.chd.intersil.com ([182.148.112.76]) by mx.google.com with ESMTPS id pj10sm13694271pbb.46.2012.07.24.23.06.54 (version=SSLv3 cipher=OTHER); Tue, 24 Jul 2012 23:06:57 -0700 (PDT) From: Kelvin Cheung To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ralf@linux-mips.org Cc: wuzhangjin@gmail.com, zhzhl555@gmail.com, Kelvin Cheung Subject: [PATCH V7 4/4] (Updated) MIPS: Add defconfig for Loongson1B Date: Wed, 25 Jul 2012 14:06:41 +0800 Message-Id: <1343196401-6435-3-git-send-email-keguang.zhang@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1343196401-6435-1-git-send-email-keguang.zhang@gmail.com> References: <1343196401-6435-1-git-send-email-keguang.zhang@gmail.com> X-archive-position: 33985 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keguang.zhang@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3560 Lines: 131 This patch adds defconfig for Loongson1B. Signed-off-by: Kelvin Cheung --- V7(updated): Add CONFIG_USB_ANNOUNCE_NEW_DEVICES in default configuration. --- arch/mips/configs/ls1b_defconfig | 109 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 109 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/ls1b_defconfig diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig new file mode 100644 index 0000000..80cff8b --- /dev/null +++ b/arch/mips/configs/ls1b_defconfig @@ -0,0 +1,109 @@ +CONFIG_MACH_LOONGSON1=y +CONFIG_PREEMPT=y +# CONFIG_SECCOMP is not set +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_SCSI=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=m +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_DA=y +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=8 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB_HID=m +CONFIG_HID_GENERIC=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_STORAGE=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_LOONGSON1=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +# CONFIG_EARLY_PRINTK is not set -- 1.7.1 From ralf@linux-mips.org Thu Jul 26 18:41:30 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Jul 2012 18:41:36 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:52363 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903819Ab2GZQla (ORCPT ); Thu, 26 Jul 2012 18:41:30 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6QGfSYn006593; Thu, 26 Jul 2012 18:41:28 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6QGfRkb006592; Thu, 26 Jul 2012 18:41:27 +0200 Date: Thu, 26 Jul 2012 18:41:27 +0200 From: Ralf Baechle To: Kelvin Cheung Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, zhzhl555@gmail.com Subject: Re: [PATCH V7 2/4] (Updated) MIPS: Add board support for Loongson1B Message-ID: <20120726164127.GB18035@linux-mips.org> References: <1343196401-6435-1-git-send-email-keguang.zhang@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1343196401-6435-1-git-send-email-keguang.zhang@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33986 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 71 Lines: 5 I replaced your old patch with the newly posted ones. Thanks, Ralf From ralf@linux-mips.org Thu Jul 26 21:42:24 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Jul 2012 21:42:28 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:48236 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1901173Ab2GZTmY (ORCPT ); Thu, 26 Jul 2012 21:42:24 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6QJgOKf015190; Thu, 26 Jul 2012 21:42:24 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6QJgNm2015189; Thu, 26 Jul 2012 21:42:23 +0200 Date: Thu, 26 Jul 2012 21:42:23 +0200 From: Ralf Baechle To: kr kr Cc: "linux-mips@linux-mips.org" Subject: Re: [mips32r1 cpu] Advice needed: "Machine Check exception - caused by multiple matching entries in the TLB" Message-ID: <20120726194222.GA23351@linux-mips.org> References: <194011342123405@web6e.yandex.ru> <20120720091602.GA15546@linux-mips.org> <189641343064148@web3g.yandex.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <189641343064148@web3g.yandex.ru> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33987 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 368 Lines: 10 On Mon, Jul 23, 2012 at 09:22:28PM +0400, kr kr wrote: > But, in case of, say, Malta, we don't need to turn on (or turn off) some > special CONFIG_* options in order to make it run MIPS-I binaries (which > Debian provides), whereas MIPS32 binaries are native for the board? No, there's nothing to be configured. That why it's called backward compatibility. Ralf From gregkh@linuxfoundation.org Thu Jul 26 23:21:40 2012 eddie.linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903819Ab2GZVWE (ORCPT ); Thu, 26 Jul 2012 23:22:04 +0200 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Jul 2012 23:21:47 +0200 (CEST) Received: from mail-gh0-f177.google.com ([209.85.160.177]:37374 "EHLO mail-gh0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903827Ab2GZVVk (ORCPT ); Thu, 26 Jul 2012 23:21:40 +0200 Received: by ghbf11 with SMTP id f11so2625512ghb.36 for ; Thu, 26 Jul 2012 14:21:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :user-agent:x-gm-message-state; bh=o59BJ0tPhRhgsWemssR4Hx3W0wzRvmy60QntA9tFC6k=; b=IQY7xt7eVoyuuV4TxwA+GcjpLPUCW69ramh4rD+S4clr2cUzcfINwecrSGG7vMMlDM WN69eRi8lKHpHMgYQExgiQkX4TxUkhRdqYhQAQ7Q5mJ6Co37XvAxMeJx0G7m2t0ikN1m q8dLqY9tZq9S4FAytFdtp+jLxNaoGy68qaa/OD+eplPvhTRp/cnGGZ1ce2wqf//EI8BM PaLoVQ0vYR/yHdgtWs4wIih5NwgSy24oA/dsIWijScF02Oobym204BdgfycUsuQF/WkL Sa+Zm8rpRo4Asmr4F0jowTotL+4GCYfsI7Y7twK4yW0OdgJ4yGtPY5QHBSwRrVSaFJiR yjRA== Received: by 10.66.74.36 with SMTP id q4mr550178pav.13.1343337689757; Thu, 26 Jul 2012 14:21:29 -0700 (PDT) Received: from localhost (c-67-168-183-230.hsd1.wa.comcast.net. [67.168.183.230]) by mx.google.com with ESMTPS id rz10sm422016pbc.32.2012.07.26.14.21.27 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 26 Jul 2012 14:21:28 -0700 (PDT) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg KH , torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@lxorguk.ukuu.org.uk, David Daney , Ralf Baechle , linux-mips@linux-mips.org Subject: [ 14/23] MIPS: Properly align the .data..init_task section. Date: Thu, 26 Jul 2012 14:19:53 -0700 Message-Id: <20120726211407.157467961@linuxfoundation.org> X-Mailer: git-send-email 1.7.10.1.362.g242cab3 In-Reply-To: <20120726211405.959857593@linuxfoundation.org> References: <20120726211420.GA7678@kroah.com> <20120726211405.959857593@linuxfoundation.org> User-Agent: quilt/0.60-20.4 X-Gm-Message-State: ALoCoQmLF9owZAHUvGJ9pWExFSQQUCNts6J2RJZ+6Y9PJGdsvGtDrtDIqtK6gjefvVcXqkwF4xHM X-archive-position: 33988 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2076 Lines: 66 From: Greg KH 3.0-stable review patch. If anyone has any objections, please let me know. ------------------ From: David Daney commit 7b1c0d26a8e272787f0f9fcc5f3e8531df3b3409 upstream. Improper alignment can lead to unbootable systems and/or random crashes. [ralf@linux-mips.org: This is a lond standing bug since 6eb10bc9e2deab06630261cd05c4cb1e9a60e980 (kernel.org) rsp. c422a10917f75fd19fa7fe070aaaa23e384dae6f (lmo) [MIPS: Clean up linker script using new linker script macros.] so dates back to 2.6.32.] Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3881/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/include/asm/thread_info.h | 4 ++-- arch/mips/kernel/vmlinux.lds.S | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -60,6 +60,8 @@ struct thread_info { register struct thread_info *__current_thread_info __asm__("$28"); #define current_thread_info() __current_thread_info +#endif /* !__ASSEMBLY__ */ + /* thread information allocation */ #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) #define THREAD_SIZE_ORDER (1) @@ -97,8 +99,6 @@ register struct thread_info *__current_t #define free_thread_info(info) kfree(info) -#endif /* !__ASSEMBLY__ */ - #define PREEMPT_ACTIVE 0x10000000 /* --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -1,5 +1,6 @@ #include #include +#include #include #undef mips @@ -73,7 +74,7 @@ SECTIONS .data : { /* Data */ . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ - INIT_TASK_DATA(PAGE_SIZE) + INIT_TASK_DATA(THREAD_SIZE) NOSAVE_DATA CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) >From patchwork Thu Jul 26 21:19:53 2012 Received: from localhost.localdomain ([127.0.0.1]:49942 "EHLO eddie.linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903787Ab2GZVal (ORCPT ); Thu, 26 Jul 2012 23:30:41 +0200 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Jul 2012 23:30:24 +0200 (CEST) Received: from mail-gg0-f177.google.com ([209.85.161.177]:38446 "EHLO mail-gg0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903782Ab2GZVaT (ORCPT ); Thu, 26 Jul 2012 23:30:19 +0200 Received: by ggcs5 with SMTP id s5so2630301ggc.36 for ; Thu, 26 Jul 2012 14:30:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :user-agent:x-gm-message-state; bh=MiDzq5Kk0iwo/c1nHYZO3Ozr7JXCWxeXk7Z2OZl37pw=; b=AUabfj3IfkIGfqF42OdAI8ssH0FY6AzKkDHil+FI6MZZ8j/C0qOwaQNEwrELQ5doKo UFOr//IMnWkQsX7XJCKp8BKS4MOpc6wfcKNyKzni5rl+SKNv293KlmoPPY3SF9tFSARI CSDulxkEtmGvHGKWpgaVnzi2qa+3qi1GUozjRLWKV/G7UZT+VvD2CULAFO8cuchiJHsZ HvoAxNqMUNclangSGcajUP6yraf7mMNJUcEY9M02IGr8ngBJ2Sk2MI+Z/QLK7ZziZbgw oJxioAD82LprZdQAnPb43jCwFClJ60Jq1ePjuRXHzvWTJNh47c0CQu6Ef0xXXhALkhhK 5Ikw== Received: by 10.66.87.2 with SMTP id t2mr560252paz.22.1343338212476; Thu, 26 Jul 2012 14:30:12 -0700 (PDT) Received: from localhost (c-67-168-183-230.hsd1.wa.comcast.net. [67.168.183.230]) by mx.google.com with ESMTPS id wi6sm433224pbc.35.2012.07.26.14.30.10 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 26 Jul 2012 14:30:11 -0700 (PDT) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg KH , torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@lxorguk.ukuu.org.uk, David Daney , Ralf Baechle , linux-mips@linux-mips.org Subject: [ 04/40] MIPS: Properly align the .data..init_task section. Date: Thu, 26 Jul 2012 14:29:22 -0700 Message-Id: <20120726211411.443368067@linuxfoundation.org> X-Mailer: git-send-email 1.7.10.1.362.g242cab3 In-Reply-To: <20120726211411.164006056@linuxfoundation.org> References: <20120726211424.GA7709@kroah.com> <20120726211411.164006056@linuxfoundation.org> User-Agent: quilt/0.60-20.4 X-Gm-Message-State: ALoCoQlyrynR6POXahUUboagsvOGcv8ctEaTKn6doJyP7M5vVFpgr2dd7NMsA4SRca6CLT3gzroR X-archive-position: 33989 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2076 Lines: 66 From: Greg KH 3.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: David Daney commit 7b1c0d26a8e272787f0f9fcc5f3e8531df3b3409 upstream. Improper alignment can lead to unbootable systems and/or random crashes. [ralf@linux-mips.org: This is a lond standing bug since 6eb10bc9e2deab06630261cd05c4cb1e9a60e980 (kernel.org) rsp. c422a10917f75fd19fa7fe070aaaa23e384dae6f (lmo) [MIPS: Clean up linker script using new linker script macros.] so dates back to 2.6.32.] Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3881/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/include/asm/thread_info.h | 4 ++-- arch/mips/kernel/vmlinux.lds.S | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -60,6 +60,8 @@ struct thread_info { register struct thread_info *__current_thread_info __asm__("$28"); #define current_thread_info() __current_thread_info +#endif /* !__ASSEMBLY__ */ + /* thread information allocation */ #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) #define THREAD_SIZE_ORDER (1) @@ -97,8 +99,6 @@ register struct thread_info *__current_t #define free_thread_info(info) kfree(info) -#endif /* !__ASSEMBLY__ */ - #define PREEMPT_ACTIVE 0x10000000 /* --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -1,5 +1,6 @@ #include #include +#include #include #undef mips @@ -72,7 +73,7 @@ SECTIONS .data : { /* Data */ . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ - INIT_TASK_DATA(PAGE_SIZE) + INIT_TASK_DATA(THREAD_SIZE) NOSAVE_DATA CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) >From linux-mips-bounce@linux-mips.org Fri Jul 27 11:38:48 2012 X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on eddie.linux-mips.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM,RDNS_NONE,T_TO_NO_BRKTS_FREEMAIL autolearn=no version=3.3.2 Received: from localhost.localdomain ([127.0.0.1]:47262 "EHLO eddie.linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903523Ab2G0Jir (ORCPT ); Fri, 27 Jul 2012 11:38:47 +0200 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Jul 2012 11:38:31 +0200 (CEST) Received: from sam.nabble.com ([216.139.236.26]:55450 "EHLO sam.nabble.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903480Ab2G0Ji0 (ORCPT ); Fri, 27 Jul 2012 11:38:26 +0200 Received: from telerig.nabble.com ([192.168.236.162]) by sam.nabble.com with esmtp (Exim 4.72) (envelope-from ) id 1Suh04-0007sg-9f for linux-mips@linux-mips.org; Fri, 27 Jul 2012 02:38:24 -0700 Message-ID: <34219711.post@talk.nabble.com> Date: Fri, 27 Jul 2012 02:38:24 -0700 (PDT) From: JoeJ To: linux-mips@linux-mips.org Subject: SMVP Support on MIPS34KC (linux-2.6.35) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Nabble-From: tttechmail@gmail.com X-archive-position: 33990 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tttechmail@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1040 Lines: 24 Hi, we are using mips34Kc processor & are facing some issues while enabling SMVP (2 VPEs with 1 TC attached to each VPE) support on the same. We are using linux-2.6.35 kernel downloaded from malta repository. The issue is seen during system boot-up with the control looping in the function stop_machine_cpu_stop. The CPU freezes after the message "Switching to clocksource" . On further debugging, we observed that the function stop_machine_cpu_stop (defined in kernel/stop_machine.c) loops continuously in the 'do while' loop with the condition 'if (smdata->state != curstate)' never matching. The value of curstate is '1' even after we try to re-initialize to 0. What could be going wrong here? We use External timer interrupt as clocksource. One timer interrupt routed on to vpe0 & another timer interrupt routed on to vpe1. Regards, Joe -- View this message in context: http://old.nabble.com/SMVP-Support-on-MIPS34KC-%28linux-2.6.35%29-tp34219711p34219711.html Sent from the linux-mips main mailing list archive at Nabble.com. From dhillf@gmail.com Fri Jul 27 16:47:19 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Jul 2012 16:47:25 +0200 (CEST) Received: from mail-vc0-f177.google.com ([209.85.220.177]:38522 "EHLO mail-vc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903556Ab2G0OrT (ORCPT ); Fri, 27 Jul 2012 16:47:19 +0200 Received: by vcbfl13 with SMTP id fl13so2821549vcb.36 for ; Fri, 27 Jul 2012 07:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=kmwH53DQ7bhX4LK+XTWQ1oxcB5/83zEFEYWbaLgLAcQ=; b=j+lYMDWw1Z4ie527MfVqnEMSgSzVq0jnDzvpjSqRvWROgisRe/zaz+eYqmdj5acY1p +x83Kvbd+PEpstFJtHFPRKz/HJPg6u+0L4Hesb/Ho6p/cGhK0JqkdBd5oaoQvQ63wIhH BHln8JzAHiz1PY++6axyI8ce4dPKePKzslEUqJI47cWc5uR6XWk+TqF2dHpvXIXbMZTz xchpy/lZuh15/OyPm/qD4Pv7JRVETLOoHDPUPmdj7ie7TipBsySgroM9SX+0wnXT983E bA5W699fbcnp5BntjX/VMge2ldAbiLX5i376lLHUL9iRFAnv/ncenh6/OlfGXrNLb1uZ 1lkA== MIME-Version: 1.0 Received: by 10.52.90.144 with SMTP id bw16mr2269104vdb.129.1343400433293; Fri, 27 Jul 2012 07:47:13 -0700 (PDT) Received: by 10.220.1.210 with HTTP; Fri, 27 Jul 2012 07:47:13 -0700 (PDT) In-Reply-To: <1343150934.42443.YahooMailNeo@web120104.mail.ne1.yahoo.com> References: <1342922751.65328.YahooMailNeo@web120106.mail.ne1.yahoo.com> <1343150934.42443.YahooMailNeo@web120104.mail.ne1.yahoo.com> Date: Fri, 27 Jul 2012 22:47:13 +0800 Message-ID: Subject: Re: Direct I/O bug in kernel From: Hillf Danton To: Victor Meyerson Cc: "linux-mips@linux-mips.org" , Ralf Baechle , LKML Content-Type: text/plain; charset=UTF-8 X-archive-position: 33991 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 256 Lines: 10 On Wed, Jul 25, 2012 at 1:28 AM, Victor Meyerson wrote: > > Still different checksums and I used the same random-file from my first test. > Then try the fix at https://lkml.org/lkml/2012/7/27/54 Good Weekend Hillf From sjhill@realitydiluted.com Fri Jul 27 19:19:49 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Jul 2012 19:19:55 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:34446 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903480Ab2G0RTt (ORCPT ); Fri, 27 Jul 2012 19:19:49 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SuoCS-0001FF-4p; Fri, 27 Jul 2012 12:19:40 -0500 Message-ID: <5012CDA4.5000008@realitydiluted.com> Date: Fri, 27 Jul 2012 12:19:32 -0500 From: "Steven J. Hill" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: JoeJ CC: linux-mips@linux-mips.org, sjhill@mips.com Subject: Re: SMVP Support on MIPS34KC (linux-2.6.35) References: <34219711.post@talk.nabble.com> In-Reply-To: <34219711.post@talk.nabble.com> X-Enigmail-Version: 1.4.3 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33992 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@realitydiluted.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 785 Lines: 26 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello Joe. The 2.6.35.9 is obsolete with regards to SMVP support. You should grab the latest 3.4.2 kernel that has complete and working SMVP. To access it, do the following: git clone git://git.linux-mips.org/pub/scm/linux-mti git checkout -b linux-mti-3.4.2 origin/linux-mti-3.4.2 Use the 'arch/mips/configs/maltasmvp_defconfig' as your base configuration file. If you have any issues, please let me know. - -Steve P.S. You can also reach me at -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAlASzaQACgkQgyK5H2Ic36cjbACfcgtny/+QYPBNhiDqC0I9QIfV 4ZQAn2TlJWe+t2Jsriji2KAAtk8fwnu3 =0aZ6 -----END PGP SIGNATURE----- From roy.qing.li@gmail.com Sat Jul 28 11:09:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 28 Jul 2012 11:09:09 +0200 (CEST) Received: from mail-ob0-f177.google.com ([209.85.214.177]:38128 "EHLO mail-ob0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903487Ab2G1JJF (ORCPT ); Sat, 28 Jul 2012 11:09:05 +0200 Received: by obbta17 with SMTP id ta17so5945551obb.36 for ; Sat, 28 Jul 2012 02:08:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=z7SkNGRZ70BVnzB7iFrNqvOiYYMEflKFV9Uo5+7Cbjw=; b=Y45NFkQzlrHGdERa87NXE7vIvEFpSPx6r6wciu/jOV+YRTCSC5j+fn1+yFAVI+5tBt 0k7VOnsgjwwT0DfddlDMmFaTsXlaDewSJReQUNv9LE0T9cv0sopIj5ecRyScWCsFdIqG 73eBi4nZ56iSsO7nZouufmeScHgCKuaEePBhkClUthns6HLg8++JxiXpAjjsPdIdU2if JOmLTY+53ehCcBgsi4uujh31YGmLe0PVCQvO+ko9JSz5KqC0xin1pOQHXMqmXp2gyLbM qTol0g84cgM3yJc9Zxrt4nLvAPQM9G4ZJm0A136qjZWsAZnnJ8QW2eO323YVYi7jG4Tn Rzyw== MIME-Version: 1.0 Received: by 10.60.19.232 with SMTP id i8mr7390477oee.35.1343466539424; Sat, 28 Jul 2012 02:08:59 -0700 (PDT) Received: by 10.60.61.193 with HTTP; Sat, 28 Jul 2012 02:08:59 -0700 (PDT) In-Reply-To: <1341203670-17544-1-git-send-email-roy.qing.li@gmail.com> References: <1341203670-17544-1-git-send-email-roy.qing.li@gmail.com> Date: Sat, 28 Jul 2012 17:08:59 +0800 Message-ID: Subject: Re: [PATCH] MIPS: fix tc_id calculation From: RongQing Li To: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 33993 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: roy.qing.li@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1004 Lines: 33 Any advice 2012/7/2 : > From: RongQing.Li > > Now the tc_id is: > (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC; > After substitute macro: > (read_c0_tcbind() >> 21) & ((0xff) << 21) > It should be: > (read_c0_tcbind() & ((0xff)<< 21)) >>21 > > Signed-off-by: RongQing.Li > --- > arch/mips/kernel/smp-cmp.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c > index e7e03ec..afc379c 100644 > --- a/arch/mips/kernel/smp-cmp.c > +++ b/arch/mips/kernel/smp-cmp.c > @@ -102,7 +102,7 @@ static void cmp_init_secondary(void) > c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; > #endif > #ifdef CONFIG_MIPS_MT_SMTC > - c->tc_id = (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC; > + c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT; > #endif > } > > -- > 1.7.1 > From dhillf@gmail.com Sun Jul 29 03:19:29 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 29 Jul 2012 03:19:36 +0200 (CEST) Received: from mail-vb0-f49.google.com ([209.85.212.49]:60530 "EHLO mail-vb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903611Ab2G2BT3 (ORCPT ); Sun, 29 Jul 2012 03:19:29 +0200 Received: by vbbfo1 with SMTP id fo1so3839878vbb.36 for ; Sat, 28 Jul 2012 18:19:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=w/fxVMJTjCrLL5JlIZYI4UrXwkzQUAUCVxpwEUgC4ro=; b=STzRT6Rez3VYdQqyUBe/Sr96OpWUbVnI12xO8bcR6TXRcKvmpJnG2IXRPzhcTM2IR2 fszftlZUYOyD3YuaTNqCLTMDqHjniv+hsXV3L5lUCHxxOd2VtvPciq55U5BiVWLy9OF+ QZrbqV4E6FSeB/fIS8xv2ZDGQ4UXjNKau204sz+XMolVBsIik+j4T67swp7/ageP6T1G UG775vOHWGeP/w9nCruE3Ij5LbQwwcADvBbdTCtbIkSeOb5/+LZMPeIArRUuOsK8acnA e94u8CvoNG0hgSk1BCAbZLFVTkEywfGD1me47w/kXOobI0flfSZn7If4FD32HgEH83UH 1LSQ== MIME-Version: 1.0 Received: by 10.220.247.148 with SMTP id mc20mr4249946vcb.50.1343524763343; Sat, 28 Jul 2012 18:19:23 -0700 (PDT) Received: by 10.220.1.210 with HTTP; Sat, 28 Jul 2012 18:19:23 -0700 (PDT) In-Reply-To: References: <1341203670-17544-1-git-send-email-roy.qing.li@gmail.com> Date: Sun, 29 Jul 2012 09:19:23 +0800 Message-ID: Subject: Re: [PATCH] MIPS: fix tc_id calculation From: Hillf Danton To: RongQing Li Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Content-Type: text/plain; charset=UTF-8 X-archive-position: 33994 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhillf@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1421 Lines: 48 On Sat, Jul 28, 2012 at 5:08 PM, RongQing Li wrote: > Any advice > > 2012/7/2 : >> From: RongQing.Li >> >> Now the tc_id is: >> (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC; >> After substitute macro: >> (read_c0_tcbind() >> 21) & ((0xff) << 21) >> It should be: >> (read_c0_tcbind() & ((0xff)<< 21)) >>21 >> >> Signed-off-by: RongQing.Li >> --- Good catch ;) Thanks, Hillf >> arch/mips/kernel/smp-cmp.c | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c >> index e7e03ec..afc379c 100644 >> --- a/arch/mips/kernel/smp-cmp.c >> +++ b/arch/mips/kernel/smp-cmp.c >> @@ -102,7 +102,7 @@ static void cmp_init_secondary(void) >> c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; >> #endif >> #ifdef CONFIG_MIPS_MT_SMTC >> - c->tc_id = (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC; >> + c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT; >> #endif >> } >> >> -- >> 1.7.1 >> > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ > > From tsbogend@alpha.franken.de Mon Jul 30 12:54:51 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jul 2012 12:55:01 +0200 (CEST) Received: from elvis.franken.de ([193.175.24.41]:32786 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903453Ab2G3Kyv (ORCPT ); Mon, 30 Jul 2012 12:54:51 +0200 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1Svncg-0007cs-00; Mon, 30 Jul 2012 12:54:50 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id DBB961D1CF; Mon, 30 Jul 2012 12:54:16 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] Fix newport con crashes To: linux-mips@linux-mips.org, linux-fbdev@vger.kernel.org cc: ralf@linux-mips.org, FlorianSchandinat@gmx.de Message-Id: <20120730105416.DBB961D1CF@solo.franken.de> Date: Mon, 30 Jul 2012 12:54:16 +0200 (CEST) X-archive-position: 33995 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1052 Lines: 34 Because of commit e84de0c61905030a0fe66b7210b6f1bb7c3e1eab [MIPS: GIO bus support for SGI IP22/28] newport con is now taking over console from dummy con, therefore it's necessary to resize the VC to the correct size to avoid crashes and garbage on console Signed-off-by: Thomas Bogendoerfer --- drivers/video/console/newport_con.c | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c index 6d15966..b05afd0 100644 --- a/drivers/video/console/newport_con.c +++ b/drivers/video/console/newport_con.c @@ -327,9 +327,16 @@ out_unmap: static void newport_init(struct vc_data *vc, int init) { - vc->vc_cols = newport_xsize / 8; - vc->vc_rows = newport_ysize / 16; + int cols, rows; + + cols = newport_xsize / 8; + rows = newport_ysize / 16; vc->vc_can_do_color = 1; + if (init) { + vc->vc_cols = cols; + vc->vc_rows = rows; + } else + vc_resize(vc, cols, rows); } static void newport_deinit(struct vc_data *c) From tttechmail@gmail.com Mon Jul 30 15:21:01 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jul 2012 15:21:09 +0200 (CEST) Received: from sam.nabble.com ([216.139.236.26]:55676 "EHLO sam.nabble.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903611Ab2G3NVB (ORCPT ); Mon, 30 Jul 2012 15:21:01 +0200 Received: from telerig.nabble.com ([192.168.236.162]) by sam.nabble.com with esmtp (Exim 4.72) (envelope-from ) id 1Svpu7-0002zs-Mb for linux-mips@linux-mips.org; Mon, 30 Jul 2012 06:20:59 -0700 Message-ID: <34230427.post@talk.nabble.com> Date: Mon, 30 Jul 2012 06:20:59 -0700 (PDT) From: JoeJ To: linux-mips@linux-mips.org Subject: Re: SMVP Support on MIPS34KC (linux-2.6.35) In-Reply-To: <5012CDA4.5000008@realitydiluted.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Nabble-From: tttechmail@gmail.com References: <34219711.post@talk.nabble.com> <5012CDA4.5000008@realitydiluted.com> X-archive-position: 33996 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tttechmail@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1958 Lines: 67 Hi Steve, Thanks for the suggestion. We moved to 3.4.2 kernel and observed the same issue, ie System hangs while booting. In 3.4.2 port, we are using mips timers (count & compare - csrc-r4k.c & cevt-r4k.c) as clocksource. The last few prints on the console are : Synchronize counters across 2 CPUs: done. NET: Registered protocol family 16 bio: create slab at 0 Switching to clocksource MIPS As mentioned in my previous post, even with 3.4.2 kernel, the control loops in stop_machine_cpu_stop function. Do you suspect anything here? btw, if we set "clocksource=jiffies" in the bootargs, the system boot goes fine. The issue is observed only during switching from default clocksource to MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS clocksource. Please suggest on the possible debug approach for this issue. Thanks for your support. Regards, Joe sjhill-3 wrote: > > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hello Joe. > > The 2.6.35.9 is obsolete with regards to SMVP support. You should grab the > latest 3.4.2 kernel that has complete and working SMVP. To access it, do > the > following: > > git clone git://git.linux-mips.org/pub/scm/linux-mti > git checkout -b linux-mti-3.4.2 origin/linux-mti-3.4.2 > > Use the 'arch/mips/configs/maltasmvp_defconfig' as your base configuration > file. If you have any issues, please let me know. > > - -Steve > > P.S. You can also reach me at > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.11 (GNU/Linux) > Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ > > iEYEARECAAYFAlASzaQACgkQgyK5H2Ic36cjbACfcgtny/+QYPBNhiDqC0I9QIfV > 4ZQAn2TlJWe+t2Jsriji2KAAtk8fwnu3 > =0aZ6 > -----END PGP SIGNATURE----- > > > -- View this message in context: http://old.nabble.com/SMVP-Support-on-MIPS34KC-%28linux-2.6.35%29-tp34219711p34230427.html Sent from the linux-mips main mailing list archive at Nabble.com. From ralf@linux-mips.org Mon Jul 30 15:34:52 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jul 2012 15:34:55 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:59727 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903637Ab2G3New (ORCPT ); Mon, 30 Jul 2012 15:34:52 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6UDYnui032036; Mon, 30 Jul 2012 15:34:49 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6UDYlM2032035; Mon, 30 Jul 2012 15:34:47 +0200 Date: Mon, 30 Jul 2012 15:34:47 +0200 From: Ralf Baechle To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org, linux-fbdev@vger.kernel.org, FlorianSchandinat@gmx.de Subject: Re: [PATCH] Fix newport con crashes Message-ID: <20120730133447.GA29993@linux-mips.org> References: <20120730105416.DBB961D1CF@solo.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120730105416.DBB961D1CF@solo.franken.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 33997 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 655 Lines: 18 On Mon, Jul 30, 2012 at 12:54:16PM +0200, Thomas Bogendoerfer wrote: > Because of commit e84de0c61905030a0fe66b7210b6f1bb7c3e1eab > [MIPS: GIO bus support for SGI IP22/28] newport con is now taking over > console from dummy con, therefore it's necessary to resize the VC to > the correct size to avoid crashes and garbage on console > > Signed-off-by: Thomas Bogendoerfer I've applied your patch to master and the affected -stable branches of the lmo git tree. Florian, since this is a driver specific to certain MIPS platforms I'd like to merge it through the MIPS tree with your ack, if that's ok? Thanks folks, Ralf From sjhill@realitydiluted.com Mon Jul 30 16:52:39 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jul 2012 16:52:43 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:47595 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903645Ab2G3Owj (ORCPT ); Mon, 30 Jul 2012 16:52:39 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1SvrKh-0006vk-7t; Mon, 30 Jul 2012 09:52:31 -0500 Message-ID: <50169FA7.8010603@realitydiluted.com> Date: Mon, 30 Jul 2012 09:52:23 -0500 From: "Steven J. Hill" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: JoeJ CC: linux-mips@linux-mips.org Subject: Re: SMVP Support on MIPS34KC (linux-2.6.35) References: <34219711.post@talk.nabble.com> <5012CDA4.5000008@realitydiluted.com> <34230427.post@talk.nabble.com> In-Reply-To: <34230427.post@talk.nabble.com> X-Enigmail-Version: 1.4.3 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 33998 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@realitydiluted.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1164 Lines: 30 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 07/30/2012 08:20 AM, JoeJ wrote: > > Synchronize counters across 2 CPUs: done. NET: Registered protocol family > 16 bio: create slab at 0 Switching to clocksource MIPS > > > As mentioned in my previous post, even with 3.4.2 kernel, the control > loops in stop_machine_cpu_stop function. Do you suspect anything here? btw, > if we set "clocksource=jiffies" in the bootargs, the system boot goes fine. > The issue is observed only during switching from default clocksource to > MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS > clocksource. > Make user that you select both CONFIG_CSRC_R4K ad CONFIG_CSRC_GIC for your clock sources. The GIC counter will be used from synchronization across the CPUs. Secondly, the hang is not actually a hard hang. Wait 50 seconds and I bet you will see the boot complete. - -Steve -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAlAWn6cACgkQgyK5H2Ic36f47wCbBM7J8Bl0iEyELwxx2sYHBRxZ SukAniQlkEwYyNdolwPhi1vOJgxNrba+ =NW6E -----END PGP SIGNATURE----- From jeffinmammen@gmail.com Mon Jul 30 17:28:50 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jul 2012 17:28:54 +0200 (CEST) Received: from mail-qc0-f177.google.com ([209.85.216.177]:41055 "EHLO mail-qc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903463Ab2G3P2u (ORCPT ); Mon, 30 Jul 2012 17:28:50 +0200 Received: by qcsu28 with SMTP id u28so2954986qcs.36 for ; Mon, 30 Jul 2012 08:28:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=GbUDvh5aLbwIDZ0bhuOyK8WXMUuX+NyjrTTgAYgyXFw=; b=ZCqhF3UA4RQ3CsDRccrgZuc1DihldYWSrPEG84lxxfUe0i4i1ER6HPiGVcMIhJmWes 5pnxidXZ1+5YN+Ex1GvQ82O72jNWk8FZWS8yMa+jzTM4sr3jMZ8NgOLiieQ7im5phc49 MNpccU0RCynw8Qzs1kTw+yH0fY+4O14ky20AtIJPICQgbN5hyS2V22c2nzoXinhW2yJi qvT6zcY6/yxNLHEOM4bCqYEGhAAvCDnS4aTrLBnC0QA5YjPwHu2jMnuqlH4kXbvE/j7C EgDkk4oWWG/6dc5dIJuVAuxBOIEDRThf4hhmzVsbnlk1GsppISPY6yW82tpmE8Kj7h/P G2Gg== Received: by 10.50.89.130 with SMTP id bo2mr8693578igb.19.1343662124173; Mon, 30 Jul 2012 08:28:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.17.197 with HTTP; Mon, 30 Jul 2012 08:28:23 -0700 (PDT) In-Reply-To: <50169FA7.8010603@realitydiluted.com> References: <34219711.post@talk.nabble.com> <5012CDA4.5000008@realitydiluted.com> <34230427.post@talk.nabble.com> <50169FA7.8010603@realitydiluted.com> From: Jeffin Date: Mon, 30 Jul 2012 20:58:23 +0530 Message-ID: Subject: Re: SMVP Support on MIPS34KC (linux-2.6.35) To: "Steven J. Hill" Cc: JoeJ , linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=e89a8f2351ab9c080b04c60db72e X-archive-position: 33999 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jeffinmammen@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5062 Lines: 130 --e89a8f2351ab9c080b04c60db72e Content-Type: text/plain; charset=ISO-8859-1 Hi Steve, CONFIG_CSRC_R4K is defined . However, I have not enabled CONFIG_CSRC_GIC and gic_present is initialized to 'zero' . I am a bit confused about CONFIG_SRC_GIC macros. I am not sure if GIC is an external timer outside the mips 34Kc core (specific to malta reference board)? In that case, we might have to replace to GIC source code with our own General purpose timer code. Can you please confirm if i am missing something here? It will be verfy helpful if you can explain a bit about the significance of CSRC_R4K & CSRC_GIC macros definitions in SMVP model. We have been stuck with this issue for quiet sometime and looking for ways to resolve this at the best possible way. Your suggestions are really helpful in this regard. Regards, Jeffin On Mon, Jul 30, 2012 at 8:22 PM, Steven J. Hill wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On 07/30/2012 08:20 AM, JoeJ wrote: > > > > Synchronize counters across 2 CPUs: done. NET: Registered protocol family > > 16 bio: create slab at 0 Switching to clocksource MIPS > > > > > > As mentioned in my previous post, even with 3.4.2 kernel, the control > > loops in stop_machine_cpu_stop function. Do you suspect anything here? > btw, > > if we set "clocksource=jiffies" in the bootargs, the system boot goes > fine. > > The issue is observed only during switching from default clocksource to > > MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS > > clocksource. > > > Make user that you select both CONFIG_CSRC_R4K ad CONFIG_CSRC_GIC for your > clock sources. The GIC counter will be used from synchronization across the > CPUs. Secondly, the hang is not actually a hard hang. Wait 50 seconds and I > bet you will see the boot complete. > > - -Steve > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.11 (GNU/Linux) > Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ > > iEYEARECAAYFAlAWn6cACgkQgyK5H2Ic36f47wCbBM7J8Bl0iEyELwxx2sYHBRxZ > SukAniQlkEwYyNdolwPhi1vOJgxNrba+ > =NW6E > -----END PGP SIGNATURE----- > --e89a8f2351ab9c080b04c60db72e Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Hi Steve,

=A0 =A0 CONFIG_CSRC_R4K=A0is defined . However,=A0=A0I have not enabled=A0CONFIG_CS= RC_GIC and gic_present is initialized to 'zero'=A0. I am a bit conf= used about CONFIG_SRC_GIC macros. I am not sure if GIC is an external timer= outside the mips 34Kc core (specific to malta reference board)? In that ca= se, we might have to replace to GIC source code with our own General purpos= e timer code. Can you please confirm if i am missing something here? It wil= l be verfy helpful if you can explain a bit about the significance of CSRC_= R4K & CSRC_GIC macros definitions in SMVP model.

=A0We have been stuck with this issue for quiet sometim= e and looking for ways to resolve this at the best possible way. Your sugge= stions are really helpful in this regard.=A0

Regar= ds,
Jeffin



On = Mon, Jul 30, 2012 at 8:22 PM, Steven J. Hill <sjhill@realitydilut= ed.com> wrote:
-----BEGIN PGP SIGNED MESS= AGE-----
Hash: SHA1

On 07/30/2012 08:20 AM, JoeJ wrote:
>
> Synchronize counters across 2 CPUs: done. NET: Registered protocol fam= ily
> 16 bio: create slab <bio-0> at 0 Switching to clocksource MIPS >
>
> As mentioned in my previous post, even with 3.4.2 kernel, the control<= br> > loops in stop_machine_cpu_stop function. Do you suspect anything here?= btw,
> if we set "clocksource=3Djiffies" in the bootargs, the syste= m boot goes fine.
> The issue is observed only during switching from default clocksource t= o
> MIPS clocksource. Also, the boot works fine with 'nosmp=3D1' o= ption & MIPS
> clocksource.
>
Make user that you select both CONFIG_CSRC_R4K ad CONFIG_CSRC_GIC for your<= br> clock sources. The GIC counter will be used from synchronization across the=
CPUs. Secondly, the hang is not actually a hard hang. Wait 50 seconds and I=
bet you will see the boot complete.

- -Steve
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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iEYEARECAAYFAlAWn6cACgkQgyK5H2Ic36f47wCbBM7J8Bl0iEyELwxx2sYHBRxZ
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=3DNW6E
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--e89a8f2351ab9c080b04c60db72e-- From gregkh@linuxfoundation.org Mon Jul 30 19:32:27 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jul 2012 19:32:34 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:33933 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903637Ab2G3Rc1 (ORCPT ); Mon, 30 Jul 2012 19:32:27 +0200 Received: by pbbrq13 with SMTP id rq13so11008378pbb.36 for ; Mon, 30 Jul 2012 10:32:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :user-agent:x-gm-message-state; bh=MiDzq5Kk0iwo/c1nHYZO3Ozr7JXCWxeXk7Z2OZl37pw=; b=ijg7Q+Y4pzXZQS/hFqm2NrMLh0RVIIAwf16jyqr+HkIjCNUHLZVD2Wm3AQZbxRsHL6 LNU8jEKIz+/dQwxnLrnW21APahxc4/hNpXFlrJXTx8FZCFBDrVxAQyXt7BXS4amlhbMs zike4HfOM5QVRDrXqQwdS/otH4d6iqrz9pO/hs0u9hpBvZKioPA7m5HhR9MM3IMctOiK kd8FZ8XAZI27Xfrrvg+6RjZTe+jSwOuE5qaDHQW2p3Hm1Sn9UkTIYwQ4454kh1tvM43Y TRv6EXk1By+CaaB1VMeIrZuE/ziPzjb8/Kc0I9YRjqBeqvlqVedx+GkrwfXQDeOXCXnz pPAQ== Received: by 10.68.217.202 with SMTP id pa10mr7905967pbc.15.1343669540107; Mon, 30 Jul 2012 10:32:20 -0700 (PDT) Received: from localhost (c-67-168-183-230.hsd1.wa.comcast.net. [67.168.183.230]) by mx.google.com with ESMTPS id qp6sm8290255pbc.55.2012.07.30.10.32.18 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Jul 2012 10:32:19 -0700 (PDT) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg KH , torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@lxorguk.ukuu.org.uk, David Daney , Ralf Baechle , linux-mips@linux-mips.org Subject: [ 04/41] MIPS: Properly align the .data..init_task section. Date: Mon, 30 Jul 2012 10:31:03 -0700 Message-Id: <20120730172901.652451653@linuxfoundation.org> X-Mailer: git-send-email 1.7.10.1.362.g242cab3 In-Reply-To: <20120730172901.306897424@linuxfoundation.org> References: <20120730172901.306897424@linuxfoundation.org> User-Agent: quilt/0.60-20.4 X-Gm-Message-State: ALoCoQmIpyCRp4g4kd0R3XLAPyCWxd8OX3bmkZ6GTMH/ua6pxcaFqeGRtWINQuk11PITyMUSF3pB X-archive-position: 34000 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2080 Lines: 69 From: Greg KH 3.0-stable review patch. If anyone has any objections, please let me know. ------------------ From: David Daney commit 7b1c0d26a8e272787f0f9fcc5f3e8531df3b3409 upstream. Improper alignment can lead to unbootable systems and/or random crashes. [ralf@linux-mips.org: This is a lond standing bug since 6eb10bc9e2deab06630261cd05c4cb1e9a60e980 (kernel.org) rsp. c422a10917f75fd19fa7fe070aaaa23e384dae6f (lmo) [MIPS: Clean up linker script using new linker script macros.] so dates back to 2.6.32.] Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3881/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/include/asm/thread_info.h | 4 ++-- arch/mips/kernel/vmlinux.lds.S | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -60,6 +60,8 @@ struct thread_info { register struct thread_info *__current_thread_info __asm__("$28"); #define current_thread_info() __current_thread_info +#endif /* !__ASSEMBLY__ */ + /* thread information allocation */ #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) #define THREAD_SIZE_ORDER (1) @@ -97,8 +99,6 @@ register struct thread_info *__current_t #define free_thread_info(info) kfree(info) -#endif /* !__ASSEMBLY__ */ - #define PREEMPT_ACTIVE 0x10000000 /* --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -1,5 +1,6 @@ #include #include +#include #include #undef mips @@ -73,7 +74,7 @@ SECTIONS .data : { /* Data */ . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ - INIT_TASK_DATA(PAGE_SIZE) + INIT_TASK_DATA(THREAD_SIZE) NOSAVE_DATA CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) From viric@viric.name Mon Jul 30 21:48:05 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jul 2012 21:48:12 +0200 (CEST) Received: from mho-01-ewr.mailhop.org ([204.13.248.71]:21588 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903458Ab2G3TsF convert rfc822-to-8bit (ORCPT ); Mon, 30 Jul 2012 21:48:05 +0200 Received: from [188.77.107.114] (helo=mail.viric.name) by mho-01-ewr.mailhop.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1Svvwd-000HQE-1a; Mon, 30 Jul 2012 19:47:59 +0000 Received: by mail.viric.name (Postfix, from userid 1000) id 8F8491E47; Mon, 30 Jul 2012 21:47:54 +0200 (CEST) X-Mail-Handler: Dyn Standard SMTP by Dyn X-Originating-IP: 188.77.107.114 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/sendlabs/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX18XKJE4AnmnqaOOB8hSjhbA Date: Mon, 30 Jul 2012 21:47:54 +0200 From: =?iso-8859-1?Q?Llu=EDs?= Batlle i Rossell To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org, tsbogend@alpha.franken.de Subject: Re: [PATCH] MIPS: Add emulation for fpureg-mem unaligned access Message-ID: <20120730194754.GA25996@vicerveza.homeunix.net> References: <20120615234641.6938B58FE7C@mail.viric.name> <20120616121513.GP2039@vicerveza.homeunix.net> <20120616124001.GQ2039@vicerveza.homeunix.net> <20120620190545.GV2039@vicerveza.homeunix.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: X-Accept-Language: ca, es, eo, ru, en, jbo, tokipona User-Agent: Mutt/1.5.20 (2009-06-14) Content-Transfer-Encoding: 8BIT X-archive-position: 34001 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: viric@viric.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1800 Lines: 40 Hello Maciej, On Wed, Jul 11, 2012 at 01:05:04AM +0100, Maciej W. Rozycki wrote: > On Wed, 20 Jun 2012, Lluís Batlle i Rossell wrote: > > > > > Well, I think I take my words back. Handling the ldc1/sdc1 cases in MIPS32 is > > > > tricker than I thought first, because I can't use ldl/ldr or sdl/sdr there. > > > > Given my ability with mips assembly, I leave the patch as is. > I suggest that for 32-bit kernels you simply reuse the existing snippets > from that function and handle ldc1/sdc1 with a pair of lwl/ldr or swl/swr > pairs ordered as appropriate for the endianness selected -- that should be > fairly easy. Hm I still don't understand well enough how to do that. Would I need to get some aligned memory (a stack automatic variable for example), copy the double word there with proper endianness, and then call again ldc1? (similar for sdc1) > Also regardless of that, please make sure that your code handles the two > possible settings of CP0 Status register's bit FR correctly, as the 32-bit > halves of floating-point data are distributed differently across > floating-point registers based on this bit's setting (check if an o32 and > an n64 or n32 program gets these values right). Hm I'm failing to find in the mips-iv.pdf how to check that FR bit, although I see it mentioned there. Sorry. > > As Jonas reported, I think that maybe I should rework the patch for it to emit > > sigbus instead of sigill on ldc1,ldc1 for mips32. Do I understand it right? > > Have you checked your code against a non-FPU processor (or with the > "nofpu" kernel option) too? No. Would in that case the processor have the fpu disabled? I understand that the code path is called only in a particular case of 'unaligned access' exception. Thank you for your comments. Regards, Lluís. From sjhill@realitydiluted.com Mon Jul 30 23:02:42 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 30 Jul 2012 23:02:46 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:48822 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903645Ab2G3VCm (ORCPT ); Mon, 30 Jul 2012 23:02:42 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Svx6o-0007Sf-FA; Mon, 30 Jul 2012 16:02:34 -0500 Message-ID: <5016F660.5020502@realitydiluted.com> Date: Mon, 30 Jul 2012 16:02:24 -0500 From: "Steven J. Hill" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Jeffin CC: JoeJ , linux-mips@linux-mips.org Subject: Re: SMVP Support on MIPS34KC (linux-2.6.35) References: <34219711.post@talk.nabble.com> <5012CDA4.5000008@realitydiluted.com> <34230427.post@talk.nabble.com> <50169FA7.8010603@realitydiluted.com> In-Reply-To: X-Enigmail-Version: 1.4.3 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 34002 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@realitydiluted.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 471 Lines: 17 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Jeffin, You will need to file an official support request with MIPS to proceed further. Additional time spent on this will need to be tracked. Thanks. - -Steve -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAlAW9mAACgkQgyK5H2Ic36eS0QCfW8Z1mH1qvLnarlr7HRAr1Lbc tloAni+7cilKyEy5eJD6ONUa+oZFctMp =Iz5d -----END PGP SIGNATURE----- From macro@linux-mips.org Tue Jul 31 01:56:54 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jul 2012 01:56:57 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:37626 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903671Ab2G3X4y (ORCPT ); Tue, 31 Jul 2012 01:56:54 +0200 Date: Tue, 31 Jul 2012 00:56:54 +0100 (BST) From: "Maciej W. Rozycki" To: =?ISO-8859-15?Q?Llu=EDs_Batlle_i_Rossell?= cc: linux-mips@linux-mips.org, tsbogend@alpha.franken.de Subject: Re: [PATCH] MIPS: Add emulation for fpureg-mem unaligned access In-Reply-To: <20120730194754.GA25996@vicerveza.homeunix.net> Message-ID: References: <20120615234641.6938B58FE7C@mail.viric.name> <20120616121513.GP2039@vicerveza.homeunix.net> <20120616124001.GQ2039@vicerveza.homeunix.net> <20120620190545.GV2039@vicerveza.homeunix.net> <20120730194754.GA25996@vicerveza.homeunix.net> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT X-archive-position: 34003 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2583 Lines: 52 Hi Lluís > > I suggest that for 32-bit kernels you simply reuse the existing snippets > > from that function and handle ldc1/sdc1 with a pair of lwl/ldr or swl/swr > > pairs ordered as appropriate for the endianness selected -- that should be > > fairly easy. > > Hm I still don't understand well enough how to do that. Would I need to get some > aligned memory (a stack automatic variable for example), copy the double word > there with proper endianness, and then call again ldc1? (similar for sdc1) No need to copy anything to scratch space, you'd just handle the thing piecewise in 32-bit chunks, transferring one FPR first, followed with the other one -- this is exactly what LDC1/SDC1 logically do in the 32-bit mode anyway. Of course FPR indices are swapped between endiannesses (or data in memory is swapped -- depending on how you look at it). > > Also regardless of that, please make sure that your code handles the two > > possible settings of CP0 Status register's bit FR correctly, as the 32-bit > > halves of floating-point data are distributed differently across > > floating-point registers based on this bit's setting (check if an o32 and > > an n64 or n32 program gets these values right). > > Hm I'm failing to find in the mips-iv.pdf how to check that FR bit, although I > see it mentioned there. Sorry. That'll be set in Linux's task status structure somewhere as the floating-point model is implied by the ABI (FR is clear for o32 and set for n32/n64) -- no need to poke at hardware. Have a look at FP context switching code -- it has to take similar measures. There may be some code that checks that in the FPU emulator as well. > > > As Jonas reported, I think that maybe I should rework the patch for it to emit > > > sigbus instead of sigill on ldc1,ldc1 for mips32. Do I understand it right? > > > > Have you checked your code against a non-FPU processor (or with the > > "nofpu" kernel option) too? > > No. Would in that case the processor have the fpu disabled? I understand that > the code path is called only in a particular case of 'unaligned access' > exception. It may well possibly be, I'm not sure offhand, but unaligned access emulation just has to work the same for floating-point transfers regardless of whether the FPU has been enabled or is fully emulated. This just have to be verified. The MIPS/Linux user ABI specifies the presence of an FPU unconditionally and a missing or disabled unit is automatically emulated in software transparently (except for the performance loss of course). Maciej From ralf@linux-mips.org Tue Jul 31 15:40:07 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jul 2012 15:40:11 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:41588 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903610Ab2GaNkH (ORCPT ); Tue, 31 Jul 2012 15:40:07 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6VDe5Gh015982; Tue, 31 Jul 2012 15:40:05 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6VDe1Lc015963; Tue, 31 Jul 2012 15:40:01 +0200 Date: Tue, 31 Jul 2012 15:40:01 +0200 From: Ralf Baechle To: Lluis Batlle i Rossell Cc: linux-mips@linux-mips.org, loongson-dev@googlegroups.com Subject: Re: [PATCH] MIPS: Add emulation for fpureg-mem unaligned access Message-ID: <20120731134001.GA14151@linux-mips.org> References: <20120615234641.6938B58FE7C@mail.viric.name> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120615234641.6938B58FE7C@mail.viric.name> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34004 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 702 Lines: 17 On Sat, Jun 16, 2012 at 12:22:53AM +0200, Lluis Batlle i Rossell wrote: > Reusing most of the code from lw,ld,sw,sd emulation, > I add the emulation for lwc1,ldc1,swc1,sdc1. > > This avoids the direct SIGBUS sent to userspace processes that have > misaligned memory accesses. > > I've tested the change in Loongson2F, with an own test program, and > WebKit 1.4.0, as both were killed by sigbus without this patch. A misaligned FPU access is a strong indication for broken, non-portable software. which means you're likely trying to fix the wrong issue. It's quite intentional that there is no unaligned handling for the FPU in the kernel - and afaics there isn't for any other MIPS UNIX. Ralf From viric@viric.name Tue Jul 31 16:07:33 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jul 2012 16:07:40 +0200 (CEST) Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:25745 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1903610Ab2GaOHd convert rfc822-to-8bit (ORCPT ); Tue, 31 Jul 2012 16:07:33 +0200 Received: from 114.107.77.188.dynamic.jazztel.es ([188.77.107.114] helo=mail.viric.name) by mho-02-ewr.mailhop.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1SwD6d-000IDg-Sf; Tue, 31 Jul 2012 14:07:28 +0000 Received: by mail.viric.name (Postfix, from userid 1000) id BCBCC2446; Tue, 31 Jul 2012 16:07:23 +0200 (CEST) X-Mail-Handler: Dyn Standard SMTP by Dyn X-Originating-IP: 188.77.107.114 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/sendlabs/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX18fsuIpaQBQwB9FMRSDIWw6 Date: Tue, 31 Jul 2012 16:07:23 +0200 From: =?iso-8859-1?Q?Llu=EDs?= Batlle i Rossell To: Ralf Baechle Cc: linux-mips@linux-mips.org, loongson-dev@googlegroups.com Subject: Re: [PATCH] MIPS: Add emulation for fpureg-mem unaligned access Message-ID: <20120731140723.GB25996@vicerveza.homeunix.net> Mail-Followup-To: Ralf Baechle , linux-mips@linux-mips.org, loongson-dev@googlegroups.com References: <20120615234641.6938B58FE7C@mail.viric.name> <20120731134001.GA14151@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <20120731134001.GA14151@linux-mips.org> X-Accept-Language: ca, es, eo, ru, en, jbo, tokipona User-Agent: Mutt/1.5.20 (2009-06-14) Content-Transfer-Encoding: 8BIT X-archive-position: 34005 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: viric@viric.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1001 Lines: 24 On Tue, Jul 31, 2012 at 03:40:01PM +0200, Ralf Baechle wrote: > On Sat, Jun 16, 2012 at 12:22:53AM +0200, Lluis Batlle i Rossell wrote: > > > Reusing most of the code from lw,ld,sw,sd emulation, > > I add the emulation for lwc1,ldc1,swc1,sdc1. > > > > This avoids the direct SIGBUS sent to userspace processes that have > > misaligned memory accesses. > > > > I've tested the change in Loongson2F, with an own test program, and > > WebKit 1.4.0, as both were killed by sigbus without this patch. > > A misaligned FPU access is a strong indication for broken, non-portable > software. which means you're likely trying to fix the wrong issue. It's > quite intentional that there is no unaligned handling for the FPU in the > kernel - and afaics there isn't for any other MIPS UNIX. Ah, I had no idea it was intentional. Maybe there could be a cleaner declaration of that intention, though. The only code there was "I herewith declare: this does not happen. So send SIGBUS." Thank you, Lluís. From ralf@linux-mips.org Tue Jul 31 17:10:08 2012 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 31 Jul 2012 17:10:12 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:51996 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1903690Ab2GaPKI (ORCPT ); Tue, 31 Jul 2012 17:10:08 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id q6VFA6G2020406; Tue, 31 Jul 2012 17:10:06 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id q6VFA5fL020405; Tue, 31 Jul 2012 17:10:05 +0200 Date: Tue, 31 Jul 2012 17:10:05 +0200 From: Ralf Baechle To: linux-mips@linux-mips.org, loongson-dev@googlegroups.com Subject: Re: [PATCH] MIPS: Add emulation for fpureg-mem unaligned access Message-ID: <20120731151005.GB14151@linux-mips.org> References: <20120615234641.6938B58FE7C@mail.viric.name> <20120731134001.GA14151@linux-mips.org> <20120731140723.GB25996@vicerveza.homeunix.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20120731140723.GB25996@vicerveza.homeunix.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34006 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1071 Lines: 22 On Tue, Jul 31, 2012 at 04:07:23PM +0200, Lluís Batlle i Rossell wrote: > Maybe there could be a cleaner declaration of that intention, though. The only > code there was "I herewith declare: this does not happen. So send SIGBUS." To give you an idea, the emulation is on the order of a 1000 times slower than the processing a properly aligned load in hardware. And even where hardware does unaligned handling such as on x86 there still is a performance penalty though that would far less severe. So given that proper alignment is always the right thing. There are very few cases were handling misalignment in software is justified, for example the IP stack. Even the checks if a packet is misaligned would cause a performance penalty and it's (assuming sane networking hardware) a very rare event. lwl/lwr in the IP stack would be a bad tradeoff. It's faster than the unaligned exception handler but would slow down processing of every correctly aligned packet. So lwl/lwr are only a good choice where a high fraction of misaligned packets is expected. Ralf