From florian@openwrt.org Fri Feb 1 12:43:30 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Feb 2013 12:43:31 +0100 (CET) Received: from mail-ee0-f51.google.com ([74.125.83.51]:57287 "EHLO mail-ee0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823006Ab3BALnaRF5qA (ORCPT ); Fri, 1 Feb 2013 12:43:30 +0100 Received: by mail-ee0-f51.google.com with SMTP id d17so1953433eek.38 for ; Fri, 01 Feb 2013 03:43:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=uL9nf2wGosgLxRR+90O3khs/nH0F3kP8OJKLggGUJyM=; b=NIAd1Z6eUEhGt3PHmK9G9jHHChVWrJFhfBD2n2XsexEiWYplX9NYfPGeALWPl2HYTA YP66ekSZiqgzPhTdqkUZQPQrIi3/QTwdaIUZtbGWhZC8ppTjaGejjZ4vakiRfMpP77fx njroihDQeKAWkr1GbXTSbyiKFl5bAjt0H44vTkoIT1N2opQNXL6WwA/vfUdZt7bgcclO WlMMYfGpBv9Dahlf6zcLV2HOc+EDNj1gbbF+o6sy6D/J+YbV8Kr/d85RNzVyuu6w0ocA geQT+nb9NGgx9iRA3YqGcqxyoL6A5Is88Xw6DgPrjNSgEgedI0PwbrL7x4wkJHNzHX/6 PlnA== X-Received: by 10.14.1.195 with SMTP id 43mr38441280eed.31.1359719004135; Fri, 01 Feb 2013 03:43:24 -0800 (PST) Received: from [192.168.108.37] (freebox.vlq16.iliad.fr. [213.36.7.13]) by mx.google.com with ESMTPS id q42sm2875303eem.14.2013.02.01.03.43.22 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 01 Feb 2013 03:43:23 -0800 (PST) Message-ID: <510BA9AF.9030905@openwrt.org> Date: Fri, 01 Feb 2013 12:40:31 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH V3 00/10] MIPS: ralink: adds support for ralink platform References: <1359633561-4980-1-git-send-email-blogic@openwrt.org> In-Reply-To: <1359633561-4980-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35675 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 323 Lines: 11 Hey John, On 01/31/2013 12:59 PM, John Crispin wrote: > This series adds support for the ralink SoC family. Currently RT305X type > SoC is supported. RT2880/3883 are in my local queue already but require > further testing. One last thing, I think Ralf wants a defconfig for this new platform as well. Thanks! -- Florian From blogic@openwrt.org Fri Feb 1 12:50:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Feb 2013 12:50:17 +0100 (CET) Received: from nbd.name ([46.4.11.11]:45424 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823006Ab3BALuQPQyhV (ORCPT ); Fri, 1 Feb 2013 12:50:16 +0100 Message-ID: <510BAB57.4030708@openwrt.org> Date: Fri, 01 Feb 2013 12:47:35 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: Florian Fainelli CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH V3 00/10] MIPS: ralink: adds support for ralink platform References: <1359633561-4980-1-git-send-email-blogic@openwrt.org> <510BA9AF.9030905@openwrt.org> In-Reply-To: <510BA9AF.9030905@openwrt.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35676 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 453 Lines: 21 On 01/02/13 12:40, Florian Fainelli wrote: > Hey John, > > On 01/31/2013 12:59 PM, John Crispin wrote: >> This series adds support for the ralink SoC family. Currently RT305X >> type >> SoC is supported. RT2880/3883 are in my local queue already but require >> further testing. > > One last thing, I think Ralf wants a defconfig for this new platform > as well. Thanks! > -- > Florian > Hi, well noticed, i will add it to the pull tree John From ddaney.cavm@gmail.com Fri Feb 1 20:21:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Feb 2013 20:21:44 +0100 (CET) Received: from mail-da0-f41.google.com ([209.85.210.41]:41019 "EHLO mail-da0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825898Ab3BATVnYbwdN (ORCPT ); Fri, 1 Feb 2013 20:21:43 +0100 Received: by mail-da0-f41.google.com with SMTP id e20so1848892dak.0 for ; Fri, 01 Feb 2013 11:21:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=bGn/qD+qLnzakEI+QTY6ilHV3tpN+rYIpG1n8sL6jo0=; b=MqxHxq5OGAHGX1fg93OcvC07e/M7S0RDa1dLynMXgR0rNnceXxuuCZjpWnG7SG/dvd IZQo7+whxZObhLaE5E/MN1bh++28JdMHGIENgpt8XyqRwYro4Juu+JPRCZoizop4f96Y ds3QcBpkEGwduT3NlQsvC2EbgM973rDd5L2JdCo0KoSdhcA7HdnTs2NNqV4y5nvNiq95 5gRdSPXC/M2Q3XH3j/lg35Sr1EdvAdoB9GLHci4ooc/9GjOyKnR2TbVHszxteQxRixod 7l6EkcpDqqFdD9M7YTptNN+Ubf/PBAbpFnRsSISdbMz5n8WIA8bFdJjwqBqj7IgRzPvj Webg== X-Received: by 10.68.213.233 with SMTP id nv9mr35071708pbc.155.1359746496378; Fri, 01 Feb 2013 11:21:36 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id x6sm10002052paw.0.2013.02.01.11.21.35 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 01 Feb 2013 11:21:35 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r11JLY14017939; Fri, 1 Feb 2013 11:21:34 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r11JLXsm017938; Fri, 1 Feb 2013 11:21:33 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Don't export kernel internal details in uapi/asm/break.h Date: Fri, 1 Feb 2013 11:21:32 -0800 Message-Id: <1359746492-17905-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-archive-position: 35677 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 996 Lines: 31 From: David Daney Only the codes used by userspace should be exported. Signed-off-by: David Daney --- arch/mips/include/uapi/asm/break.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/include/uapi/asm/break.h b/arch/mips/include/uapi/asm/break.h index 6f61d08..652431f 100644 --- a/arch/mips/include/uapi/asm/break.h +++ b/arch/mips/include/uapi/asm/break.h @@ -20,10 +20,14 @@ #define BRK_OVERFLOW 6 /* Overflow check */ #define BRK_DIVZERO 7 /* Divide by zero check */ #define BRK_RANGE 8 /* Range error check */ + +#ifdef __KERNEL__ +/* Break codes used internally to the kernel. */ #define BRK_BUG 12 /* Used by BUG() */ #define BRK_MEMU 514 /* Used by FPU emulator */ #define BRK_KPROBE_BP 515 /* Kprobe break */ #define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */ #define BRK_MULOVF 1023 /* Multiply overflow */ +#endif /* __KERNEL__ */ #endif /* __ASM_BREAK_H */ -- 1.7.11.7 From ddaney.cavm@gmail.com Fri Feb 1 20:39:47 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Feb 2013 20:39:50 +0100 (CET) Received: from mail-pb0-f47.google.com ([209.85.160.47]:56056 "EHLO mail-pb0-f47.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823006Ab3BATjrdeZ4n (ORCPT ); Fri, 1 Feb 2013 20:39:47 +0100 Received: by mail-pb0-f47.google.com with SMTP id rp8so2277710pbb.20 for ; Fri, 01 Feb 2013 11:39:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=7Vzhll3N3LqeAxl7wqTpLxlP7khdAYPQml7veZQ7h+Q=; b=zGiwXFd1Mtt7jCCMy3ivSuVBoONYMcAQkEhnLdhW257EtGCpNAH6gXXKF6UCg/SALr tbdgDTQxMPV56yEhCYgX/czWz2QAT+g7hQGsl8BLFFdoRsxBRZvOTC15RU4jOC4Dy3nP Xq1BnjogUx8xuqjVK73Wu2Wjj3v0GwrUerQHTnMcQ8cma44m45tRzHsG07qMXT5ud+6A +gsusXzhLmXQsBnKO20jFwkStxC9QB9BeTJWKRIb3uyl+xDClnIpulzTvOQP4p4eszE8 bS3hnWQuRBGpXFyYKTxqx0j8NpMexXKPE3zaVmogd7wDYu/oJQYcfwVhR2fy3+q6l2cQ gkBA== X-Received: by 10.68.217.104 with SMTP id ox8mr34927888pbc.105.1359747579799; Fri, 01 Feb 2013 11:39:39 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id vn2sm9282842pbc.31.2013.02.01.11.39.38 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 01 Feb 2013 11:39:39 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r11JdbkD029059; Fri, 1 Feb 2013 11:39:37 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r11Jdb8V029058; Fri, 1 Feb 2013 11:39:37 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Probe for and report hardware virtualization support. Date: Fri, 1 Feb 2013 11:39:36 -0800 Message-Id: <1359747576-29025-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-archive-position: 35678 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2898 Lines: 80 From: David Daney The presence of the MIPS Virtualization Application-Specific Extension is indicated by CP0_Config3[23]. Probe for this and report it in /proc/cpuinfo. Signed-off-by: David Daney --- arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 2 +- arch/mips/include/asm/mipsregs.h | 1 + arch/mips/kernel/cpu-probe.c | 2 ++ arch/mips/kernel/proc.c | 1 + 5 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1e83b24..e4bce0b 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -273,4 +273,8 @@ #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) #endif +#ifndef cpu_has_vz +#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ) +#endif + #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 9904697..cd9c223 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -333,6 +333,6 @@ enum cpu_type_enum { #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ - +#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ #endif /* _ASM_CPU_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 2145162..b9ca9a1 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -595,6 +595,7 @@ #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) +#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 2656c89..da2222e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -467,6 +467,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->ases |= MIPS_ASE_MIPSMT; if (config3 & MIPS_CONF3_ULRI) c->options |= MIPS_CPU_ULRI; + if (config3 & MIPS_CONF3_VZ) + c->ases |= MIPS_ASE_VZ; return config3 & MIPS_CONF_M; } diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 79d4b8e..4673fa3 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -95,6 +95,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); + if (cpu_has_vz) seq_printf(m, "%s", " vz"); seq_printf(m, "\n"); seq_printf(m, "shadow register sets\t: %d\n", -- 1.7.11.7 From zajec5@gmail.com Fri Feb 1 23:44:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Feb 2013 23:44:15 +0100 (CET) Received: from mail-ob0-f169.google.com ([209.85.214.169]:64794 "EHLO mail-ob0-f169.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823006Ab3BAWoOqhwMb convert rfc822-to-8bit (ORCPT ); Fri, 1 Feb 2013 23:44:14 +0100 Received: by mail-ob0-f169.google.com with SMTP id ta14so4666835obb.14 for ; Fri, 01 Feb 2013 14:44:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:date:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=dCNw1WBN6CHA2gU8BCYoksczFuUaBU25m2G/GICzwQI=; b=fbpV/BpJT8J4UYdUWZxNPA5/325nBk+oO9/R1/ii/qI/z3rsz0GdXJG1Uxgq1QQZOX ELwOOt+zRXAkfM3f+8RIeBttKpXg1S9pDP1ccsRwUo1Tbps8Zud4r9bKt04BUU00OkDd HNzNFp6IQ9ANtJmsUYALScGL0xp780DUyrvAhgRErhNPERiJzMvUYs6i+CiZjX48QZse 4pujIfEX4vG8+VDcv4IJ5IJkFiuIzgWa1GC6uyoHcrRFfRBKI1+NgtKbYZ08pm8dUZEU aT+o+ErYLyZVu+POQ0aB5lhPg2WIuGTnP6rchJFhLGqflCAKbCj8bPshMBfDxU4/xIsA NLlg== MIME-Version: 1.0 X-Received: by 10.60.32.33 with SMTP id f1mr11457037oei.122.1359758648348; Fri, 01 Feb 2013 14:44:08 -0800 (PST) Received: by 10.76.109.197 with HTTP; Fri, 1 Feb 2013 14:44:08 -0800 (PST) Date: Fri, 1 Feb 2013 23:44:08 +0100 Message-ID: Subject: CPU hang on cpu_wait in CPU_74K From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: linux-mips@linux-mips.org Cc: Hauke Mehrtens Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 35679 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 853 Lines: 28 Hello again ;) I'm hacking a BCM4706 based board which uses a 74K CPU. The problem is that wait_cpu (see cpu-probe.c) hangs my machine (is happens as soon as the first [um]sleep is called). The hang is related to the cpu-probe.c and: > cpu_wait = r4k_wait; > if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) > cpu_wait = r4k_wait_irqoff; If I remove that lines completely [um]sleep doesn't hang machine anymore. I'm not sure if removing that code is a proper solution. I'm not sure what is the > c->processor_id & 0xff on my machine, but I've tried forcing both: > cpu_wait = r4k_wait; and > cpu_wait = r4k_wait_irqoff; and both are causing hangs. If I recall correctly, Hauke was checking Broadcom's code and they're using the same solution: removing that lines completely. Do you have any idea how this could be solved? -- RafaÅ‚ From juhosg@openwrt.org Sat Feb 2 13:41:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 13:41:20 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:45752 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816511Ab3BBMlSoSUbN (ORCPT ); Sat, 2 Feb 2013 13:41:18 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 0FD9225D27A; Sat, 2 Feb 2013 13:41:13 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Zj6n4NGWraOw; Sat, 2 Feb 2013 13:41:12 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id B919B25D03A; Sat, 2 Feb 2013 13:41:07 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 1/5] MIPS: pci-ar724x: convert into a platform driver Date: Sat, 2 Feb 2013 13:40:42 +0100 Message-Id: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35680 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2610 Lines: 105 The patch converts the pci-ar724x driver into a platform driver. This makes it possible to register the PCI controller as a plain platform device. Signed-off-by: Gabor Juhos --- Note: In order to make the patch simple, the registration of the corresponding platform device, and the removal of the ar724x_pcibios_init function is implemented in subsequent patches. --- arch/mips/pci/pci-ar724x.c | 57 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index c11c75b..e7aca88b 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -11,6 +11,8 @@ #include #include +#include +#include #include #include #include @@ -262,7 +264,7 @@ static struct irq_chip ar724x_pci_irq_chip = { .irq_mask_ack = ar724x_pci_irq_mask, }; -static void __init ar724x_pci_irq_init(int irq) +static void ar724x_pci_irq_init(int irq) { void __iomem *base; int i; @@ -282,7 +284,7 @@ static void __init ar724x_pci_irq_init(int irq) irq_set_chained_handler(irq, ar724x_pci_irq_handler); } -int __init ar724x_pcibios_init(int irq) +int ar724x_pcibios_init(int irq) { int ret; @@ -312,3 +314,54 @@ err_unmap_devcfg: err: return ret; } + +static int ar724x_pci_probe(struct platform_device *pdev) +{ + struct resource *res; + int irq; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); + if (!res) + return -EINVAL; + + ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res); + if (ar724x_pci_ctrl_base == NULL) + return -EBUSY; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); + if (!res) + return -EINVAL; + + ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res); + if (!ar724x_pci_devcfg_base) + return -EBUSY; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return -EINVAL; + + ar724x_pci_link_up = ar724x_pci_check_link(); + if (!ar724x_pci_link_up) + dev_warn(&pdev->dev, "PCIe link is down\n"); + + ar724x_pci_irq_init(irq); + + register_pci_controller(&ar724x_pci_controller); + + return 0; +} + +static struct platform_driver ar724x_pci_driver = { + .probe = ar724x_pci_probe, + .driver = { + .name = "ar724x-pci", + .owner = THIS_MODULE, + }, +}; + +static int __init ar724x_pci_init(void) +{ + return platform_driver_register(&ar724x_pci_driver); +} + +postcore_initcall(ar724x_pci_init); -- 1.7.10 From juhosg@openwrt.org Sat Feb 2 13:41:28 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 13:41:37 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:45756 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827471Ab3BBMl2cbTAb (ORCPT ); Sat, 2 Feb 2013 13:41:28 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 6A4FD25D27A; Sat, 2 Feb 2013 13:41:23 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MuFi7mqAVhSe; Sat, 2 Feb 2013 13:41:23 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 6B8C025D03A; Sat, 2 Feb 2013 13:41:13 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 2/5] MIPS: pci-ar71xx: convert into a platform driver Date: Sat, 2 Feb 2013 13:40:43 +0100 Message-Id: <1359808846-23083-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> References: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35681 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2947 Lines: 115 The patch converts the pci-ar71xx driver into a platform driver. This makes it possible to register the PCI controller as a plain platform device. Signed-off-by: Gabor Juhos --- Note: In order to make the patch simple, the registration of the corresponding platform device, and the removal of the ar71xx_pcibios_init function is implemented in subsequent patches. --- arch/mips/pci/pci-ar71xx.c | 60 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index 6eaa4f2..0d8412f 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include #include @@ -309,7 +311,7 @@ static struct irq_chip ar71xx_pci_irq_chip = { .irq_mask_ack = ar71xx_pci_irq_mask, }; -static __init void ar71xx_pci_irq_init(void) +static void ar71xx_pci_irq_init(int irq) { void __iomem *base = ath79_reset_base; int i; @@ -324,10 +326,10 @@ static __init void ar71xx_pci_irq_init(void) irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, handle_level_irq); - irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler); + irq_set_chained_handler(irq, ar71xx_pci_irq_handler); } -static __init void ar71xx_pci_reset(void) +static void ar71xx_pci_reset(void) { void __iomem *ddr_base = ath79_ddr_base; @@ -367,9 +369,59 @@ __init int ar71xx_pcibios_init(void) /* clear bus errors */ ar71xx_pci_check_error(1); - ar71xx_pci_irq_init(); + ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2); register_pci_controller(&ar71xx_pci_controller); return 0; } + +static int ar71xx_pci_probe(struct platform_device *pdev) +{ + struct resource *res; + int irq; + u32 t; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); + if (!res) + return -EINVAL; + + ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res); + if (!ar71xx_pcicfg_base) + return -ENOMEM; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return -EINVAL; + + ar71xx_pci_reset(); + + /* setup COMMAND register */ + t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE + | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; + ar71xx_pci_local_write(PCI_COMMAND, 4, t); + + /* clear bus errors */ + ar71xx_pci_check_error(1); + + ar71xx_pci_irq_init(irq); + + register_pci_controller(&ar71xx_pci_controller); + + return 0; +} + +static struct platform_driver ar71xx_pci_driver = { + .probe = ar71xx_pci_probe, + .driver = { + .name = "ar71xx-pci", + .owner = THIS_MODULE, + }, +}; + +static int __init ar71xx_pci_init(void) +{ + return platform_driver_register(&ar71xx_pci_driver); +} + +postcore_initcall(ar71xx_pci_init); -- 1.7.10 From juhosg@openwrt.org Sat Feb 2 13:44:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 13:44:57 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:45814 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827470Ab3BBMo4Y5SK6 (ORCPT ); Sat, 2 Feb 2013 13:44:56 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 3DACC25D27C; Sat, 2 Feb 2013 13:44:51 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uBbie7X6EeGo; Sat, 2 Feb 2013 13:44:51 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 5ACA425D27A; Sat, 2 Feb 2013 13:44:50 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 3/5] MIPS: ath79: move global PCI defines into a common header Date: Sat, 2 Feb 2013 13:44:23 +0100 Message-Id: <1359809064-23253-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> References: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35682 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3331 Lines: 98 The constants will be used by a subsequent patch. Signed-off-by: Gabor Juhos --- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 24 ++++++++++++++++++++++++ arch/mips/pci/pci-ar71xx.c | 16 ---------------- arch/mips/pci/pci-ar724x.c | 8 -------- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 7d44b5d..7c87bfe 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -41,11 +41,35 @@ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) #define AR71XX_RESET_SIZE 0x100 +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) #define AR7240_USB_CTRL_SIZE 0x100 #define AR7240_OHCI_BASE 0x1b000000 #define AR7240_OHCI_SIZE 0x1000 +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + #define AR724X_EHCI_BASE 0x1b000000 #define AR724X_EHCI_SIZE 0x1000 diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index 0d8412f..35ee234 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -25,22 +25,6 @@ #include #include -#define AR71XX_PCI_MEM_BASE 0x10000000 -#define AR71XX_PCI_MEM_SIZE 0x07000000 - -#define AR71XX_PCI_WIN0_OFFS 0x10000000 -#define AR71XX_PCI_WIN1_OFFS 0x11000000 -#define AR71XX_PCI_WIN2_OFFS 0x12000000 -#define AR71XX_PCI_WIN3_OFFS 0x13000000 -#define AR71XX_PCI_WIN4_OFFS 0x14000000 -#define AR71XX_PCI_WIN5_OFFS 0x15000000 -#define AR71XX_PCI_WIN6_OFFS 0x16000000 -#define AR71XX_PCI_WIN7_OFFS 0x07000000 - -#define AR71XX_PCI_CFG_BASE \ - (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) -#define AR71XX_PCI_CFG_SIZE 0x100 - #define AR71XX_PCI_REG_CRP_AD_CBE 0x00 #define AR71XX_PCI_REG_CRP_WRDATA 0x04 #define AR71XX_PCI_REG_CRP_RDDATA 0x08 diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index e7aca88b..b3f9d09 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -17,14 +17,6 @@ #include #include -#define AR724X_PCI_CFG_BASE 0x14000000 -#define AR724X_PCI_CFG_SIZE 0x1000 -#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) -#define AR724X_PCI_CTRL_SIZE 0x100 - -#define AR724X_PCI_MEM_BASE 0x10000000 -#define AR724X_PCI_MEM_SIZE 0x04000000 - #define AR724X_PCI_REG_RESET 0x18 #define AR724X_PCI_REG_INT_STATUS 0x4c #define AR724X_PCI_REG_INT_MASK 0x50 -- 1.7.10 From juhosg@openwrt.org Sat Feb 2 13:44:57 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 13:45:16 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:45817 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827471Ab3BBMo5Rre8Q (ORCPT ); Sat, 2 Feb 2013 13:44:57 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 2554325D27E; Sat, 2 Feb 2013 13:44:52 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rulRCVM7WJyn; Sat, 2 Feb 2013 13:44:52 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 6483425D27A; Sat, 2 Feb 2013 13:44:51 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 4/5] MIPS: ath79: register platform devices for the PCI controllers Date: Sat, 2 Feb 2013 13:44:24 +0100 Message-Id: <1359809064-23253-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1359809064-23253-1-git-send-email-juhosg@openwrt.org> References: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> <1359809064-23253-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35683 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3310 Lines: 124 The pci-ar71xx and pci-ar724x drivers were converted into platform drivers. Register the corresponding platform devices for the PCI controllers instead of using the ar7{1x,24}x_pcibios_init functions. Signed-off-by: Gabor Juhos --- arch/mips/ath79/pci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 78 insertions(+), 9 deletions(-) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index ca83abd..81ef579 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -14,6 +14,8 @@ #include #include +#include +#include #include #include #include @@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) ath79_pci_plat_dev_init = func; } -int __init ath79_register_pci(void) +static struct platform_device * +ath79_register_pci_ar71xx(void) +{ + struct platform_device *pdev; + struct resource res[2]; + + memset(res, 0, sizeof(res)); + + res[0].name = "cfg_base"; + res[0].flags = IORESOURCE_MEM; + res[0].start = AR71XX_PCI_CFG_BASE; + res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; + + res[1].flags = IORESOURCE_IRQ; + res[1].start = ATH79_CPU_IRQ_IP2; + res[1].end = ATH79_CPU_IRQ_IP2; + + pdev = platform_device_register_simple("ar71xx-pci", -1, + res, ARRAY_SIZE(res)); + return pdev; +} + +static struct platform_device * +ath79_register_pci_ar724x(int id, + unsigned long cfg_base, + unsigned long ctrl_base, + int irq) { - if (soc_is_ar71xx()) - return ar71xx_pcibios_init(); + struct platform_device *pdev; + struct resource res[3]; - if (soc_is_ar724x()) - return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + memset(res, 0, sizeof(res)); - if (soc_is_ar9342() || soc_is_ar9344()) { + res[0].name = "cfg_base"; + res[0].flags = IORESOURCE_MEM; + res[0].start = cfg_base; + res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1; + + res[1].name = "ctrl_base"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ctrl_base; + res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1; + + res[2].flags = IORESOURCE_IRQ; + res[2].start = irq; + res[2].end = irq; + + pdev = platform_device_register_simple("ar724x-pci", id, + res, ARRAY_SIZE(res)); + return pdev; +} + +int __init ath79_register_pci(void) +{ + struct platform_device *pdev = NULL; + + if (soc_is_ar71xx()) { + pdev = ath79_register_pci_ar71xx(); + } else if (soc_is_ar724x()) { + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, + AR724X_PCI_CTRL_BASE, + ATH79_CPU_IRQ_IP2); + } else if (soc_is_ar9342() || + soc_is_ar9344()) { u32 bootstrap; bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); - if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) - return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); + if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0) + return -ENODEV; + + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, + AR724X_PCI_CTRL_BASE, + ATH79_IP2_IRQ(0)); + } else { + /* No PCI support */ + return -ENODEV; } - return -ENODEV; + if (!pdev) + pr_err("unable to register PCI controller device\n"); + + return pdev ? 0 : -ENODEV; } -- 1.7.10 From juhosg@openwrt.org Sat Feb 2 13:46:08 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 13:46:09 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:45836 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827475Ab3BBMqI260bt (ORCPT ); Sat, 2 Feb 2013 13:46:08 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 558FA25D27C; Sat, 2 Feb 2013 13:46:03 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fOikWnNzS1bT; Sat, 2 Feb 2013 13:46:03 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id AE10B25D03A; Sat, 2 Feb 2013 13:46:02 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: =?UTF-8?q?=5BPATCH=205/5=5D=20MIPS=3A=20ath79=3A=20remove=20unused=20ar7=7B1x=2C24=7Dx=5Fpcibios=5Finit=20functions?= Date: Sat, 2 Feb 2013 13:45:57 +0100 Message-Id: <1359809157-23430-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> References: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 35684 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4349 Lines: 154 The functions are unused now, so remove them. Signed-off-by: Gabor Juhos --- arch/mips/ath79/pci.c | 1 - arch/mips/include/asm/mach-ath79/pci.h | 28 ---------------------------- arch/mips/pci/pci-ar71xx.c | 26 -------------------------- arch/mips/pci/pci-ar724x.c | 32 -------------------------------- 4 files changed, 87 deletions(-) delete mode 100644 arch/mips/include/asm/mach-ath79/pci.h diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 81ef579..c94bcec 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "pci.h" static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h deleted file mode 100644 index 7868f7f..0000000 --- a/arch/mips/include/asm/mach-ath79/pci.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Atheros AR71XX/AR724X PCI support - * - * Copyright (C) 2011 René Bolldorf - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef __ASM_MACH_ATH79_PCI_H -#define __ASM_MACH_ATH79_PCI_H - -#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX) -int ar71xx_pcibios_init(void); -#else -static inline int ar71xx_pcibios_init(void) { return 0; } -#endif - -#if defined(CONFIG_PCI_AR724X) -int ar724x_pcibios_init(int irq); -#else -static inline int ar724x_pcibios_init(int irq) { return 0; } -#endif - -#endif /* __ASM_MACH_ATH79_PCI_H */ diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index 35ee234..69e0bb4 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -23,7 +23,6 @@ #include #include -#include #define AR71XX_PCI_REG_CRP_AD_CBE 0x00 #define AR71XX_PCI_REG_CRP_WRDATA 0x04 @@ -335,31 +334,6 @@ static void ar71xx_pci_reset(void) mdelay(100); } -__init int ar71xx_pcibios_init(void) -{ - u32 t; - - ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); - if (ar71xx_pcicfg_base == NULL) - return -ENOMEM; - - ar71xx_pci_reset(); - - /* setup COMMAND register */ - t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE - | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; - ar71xx_pci_local_write(PCI_COMMAND, 4, t); - - /* clear bus errors */ - ar71xx_pci_check_error(1); - - ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2); - - register_pci_controller(&ar71xx_pci_controller); - - return 0; -} - static int ar71xx_pci_probe(struct platform_device *pdev) { struct resource *res; diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index b3f9d09..8f008d9 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -15,7 +15,6 @@ #include #include #include -#include #define AR724X_PCI_REG_RESET 0x18 #define AR724X_PCI_REG_INT_STATUS 0x4c @@ -276,37 +275,6 @@ static void ar724x_pci_irq_init(int irq) irq_set_chained_handler(irq, ar724x_pci_irq_handler); } -int ar724x_pcibios_init(int irq) -{ - int ret; - - ret = -ENOMEM; - - ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, - AR724X_PCI_CFG_SIZE); - if (ar724x_pci_devcfg_base == NULL) - goto err; - - ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE, - AR724X_PCI_CTRL_SIZE); - if (ar724x_pci_ctrl_base == NULL) - goto err_unmap_devcfg; - - ar724x_pci_link_up = ar724x_pci_check_link(); - if (!ar724x_pci_link_up) - pr_warn("ar724x: PCIe link is down\n"); - - ar724x_pci_irq_init(irq); - register_pci_controller(&ar724x_pci_controller); - - return PCIBIOS_SUCCESSFUL; - -err_unmap_devcfg: - iounmap(ar724x_pci_devcfg_base); -err: - return ret; -} - static int ar724x_pci_probe(struct platform_device *pdev) { struct resource *res; -- 1.7.10 From juhosg@openwrt.org Sat Feb 2 15:19:17 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 15:19:18 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:47448 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827465Ab3BBOTR3H1SJ (ORCPT ); Sat, 2 Feb 2013 15:19:17 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 3923B25D29B; Sat, 2 Feb 2013 15:19:11 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UQwEDOQuwp7F; Sat, 2 Feb 2013 15:19:11 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 164D525D296; Sat, 2 Feb 2013 15:19:09 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH] MIPS: avoid possible resource conflict in register_pci_controller Date: Sat, 2 Feb 2013 15:18:54 +0100 Message-Id: <1359814734-13963-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35685 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1333 Lines: 47 The IO and memory resources of a PCI controller might already have a parent resource set when they are passed to 'register_pci_controller'. If the parent resource is set, the request_resource call will fail due to resource conflict and the current code will not be able to register the PCI controller. Use the parent resource if it is available in the request_resource call to avoid the isssue. Signed-off-by: Gabor Juhos --- arch/mips/pci/pci.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index a184344..eb65399 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -175,9 +175,20 @@ static DEFINE_MUTEX(pci_scan_mutex); void register_pci_controller(struct pci_controller *hose) { - if (request_resource(&iomem_resource, hose->mem_resource) < 0) + struct resource *parent; + + parent = hose->mem_resource->parent; + if (!parent) + parent = &iomem_resource; + + if (request_resource(parent, hose->mem_resource) < 0) goto out; - if (request_resource(&ioport_resource, hose->io_resource) < 0) { + + parent = hose->io_resource->parent; + if (!parent) + parent = &ioport_resource; + + if (request_resource(parent, hose->io_resource) < 0) { release_resource(hose->mem_resource); goto out; } -- 1.7.10 From john@phrozen.org Sat Feb 2 15:20:33 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 15:20:34 +0100 (CET) Received: from nbd.name ([46.4.11.11]:60005 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823088Ab3BBOUdtxVfF (ORCPT ); Sat, 2 Feb 2013 15:20:33 +0100 Message-ID: <510D2012.8070408@phrozen.org> Date: Sat, 02 Feb 2013 15:17:54 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH 1/5] MIPS: pci-ar724x: convert into a platform driver References: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> In-Reply-To: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35686 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 654 Lines: 25 On 02/02/13 13:40, Gabor Juhos wrote: > +static int ar724x_pci_probe(struct platform_device *pdev) > +{ > + struct resource *res; > + int irq; > + > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); > + if (!res) > + return -EINVAL; > + > + ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res); > + if (ar724x_pci_ctrl_base == NULL) > + return -EBUSY; > + > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); > + if (!res) > + return -EINVAL; Hi, maybe better use platform_get_resource(pdev, IORESOURCE_MEM, 0/1) ... you will otherwise have to patch this again when you convert to OF John From juhosg@openwrt.org Sat Feb 2 15:27:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 15:27:41 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:57438 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823088Ab3BBO1kiKgy4 (ORCPT ); Sat, 2 Feb 2013 15:27:40 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9OgJzdZ_xO9b; Sat, 2 Feb 2013 15:27:38 +0100 (CET) Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 0E67A284B53; Sat, 2 Feb 2013 15:27:36 +0100 (CET) Message-ID: <510D2256.4000703@openwrt.org> Date: Sat, 02 Feb 2013 15:27:34 +0100 From: Gabor Juhos MIME-Version: 1.0 To: John Crispin CC: linux-mips@linux-mips.org Subject: Re: [PATCH 1/5] MIPS: pci-ar724x: convert into a platform driver References: <1359808846-23083-1-git-send-email-juhosg@openwrt.org> <510D2012.8070408@phrozen.org> In-Reply-To: <510D2012.8070408@phrozen.org> X-Enigmail-Version: 1.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 35687 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1651 Lines: 55 2013.02.02. 15:17 keltezéssel, John Crispin írta: > On 02/02/13 13:40, Gabor Juhos wrote: >> +static int ar724x_pci_probe(struct platform_device *pdev) >> +{ >> + struct resource *res; >> + int irq; >> + >> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); >> + if (!res) >> + return -EINVAL; >> + >> + ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res); >> + if (ar724x_pci_ctrl_base == NULL) >> + return -EBUSY; >> + >> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); >> + if (!res) >> + return -EINVAL; > > > Hi, > > maybe better use platform_get_resource(pdev, IORESOURCE_MEM, 0/1) ... you will > otherwise have to patch this again when you convert to OF I will not have to convert that. The node can have a reg-names property like this: > pci0: pcie@180f0000 { > #address-cells = <3>; > #size-cells = <2>; > #interrupt-cells = <1>; > device_type = "pci"; > interrupt-controller; > compatible = "qca,qca9558-pcie", "qca,ar7240-pcie"; > bus-range = <0 255>; > ranges = <0x02000000 0 0x00000000 0x10000000 0 0x02000000 /* pci memory */ > 0x01000000 0 0x00000000 0x00000000 0 0x00000001>; /* io space */ > reg = <0x180f0000 0x0100 /* controller base */ > 0x14000000 0x1000 /* config space */ > 0x180c0000 0x1000>; /* CRP base */ > reg-names = "ctrl_base", "cfg_base", "crp_base"; > > interrupt-map-mask = <0xf800 0 0 7>; > interrupt-map = <0 0 0 1 &pci0 0 > 0 0 0 2 &pci0 0 > 0 0 0 3 &pci0 0 > 0 0 0 4 &pci0 0>; > > interrupt-parent = <&EINTC>; > interrupts = <0>; > }; -Gabor From juhosg@openwrt.org Sat Feb 2 15:37:00 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Feb 2013 15:37:01 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:47761 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823088Ab3BBOhAFN44u (ORCPT ); Sat, 2 Feb 2013 15:37:00 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id E4A9425D296; Sat, 2 Feb 2013 15:36:54 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mMZ78i9sXDLO; Sat, 2 Feb 2013 15:36:54 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 9AF9325C036; Sat, 2 Feb 2013 15:36:53 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH] MIPS: add dummy pci_load_of_ranges Date: Sat, 2 Feb 2013 15:36:48 +0100 Message-Id: <1359815808-7829-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35688 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 992 Lines: 32 The pci_load_of_ranges function is only available if CONFIG_OF is selected. If the function is used without CONFIG_OF being enabled it will cause a build error. Add a dummy inline function to avoid this. Signed-off-by: Gabor Juhos --- arch/mips/include/asm/pci.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index d69ea74..630645e 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -144,8 +144,13 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern char * (*pcibios_plat_setup)(char *str); +#ifdef CONFIG_OF /* this function parses memory ranges from a device node */ extern void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node); +#else +static inline void pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node) {} +#endif #endif /* _ASM_PCI_H */ -- 1.7.10 From juhosg@openwrt.org Sun Feb 3 11:58:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Feb 2013 11:58:53 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37410 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819546Ab3BCK6wJJVIy (ORCPT ); Sun, 3 Feb 2013 11:58:52 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id CB2EE25D404; Sun, 3 Feb 2013 11:58:46 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pmSN2DpSBIQ5; Sun, 3 Feb 2013 11:58:46 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id DEECA25D3E0; Sun, 3 Feb 2013 11:58:45 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 2/4] MIPS: pci-ar724x: use dynamically allocated PCI controller structure Date: Sun, 3 Feb 2013 11:58:38 +0100 Message-Id: <1359889120-15699-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> References: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35689 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8866 Lines: 315 The current code uses static variables to store the PCI controller specific data. This works if the system contains one PCI controller only, however it becomes impractical when multiple PCI controllers are present. Move the variables into a dynamically allocated controller specific structure, and use that instead of the static variables. Signed-off-by: Gabor Juhos --- arch/mips/pci/pci-ar724x.c | 129 ++++++++++++++++++++++++++++---------------- 1 file changed, 82 insertions(+), 47 deletions(-) diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 8f008d9..93ab877 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -9,6 +9,7 @@ * by the Free Software Foundation. */ +#include #include #include #include @@ -28,38 +29,56 @@ #define AR7240_BAR0_WAR_VALUE 0xffff -static DEFINE_SPINLOCK(ar724x_pci_lock); -static void __iomem *ar724x_pci_devcfg_base; -static void __iomem *ar724x_pci_ctrl_base; +struct ar724x_pci_controller { + void __iomem *devcfg_base; + void __iomem *ctrl_base; -static u32 ar724x_pci_bar0_value; -static bool ar724x_pci_bar0_is_cached; -static bool ar724x_pci_link_up; + int irq; + + bool link_up; + bool bar0_is_cached; + u32 bar0_value; + + spinlock_t lock; + + struct pci_controller pci_controller; +}; -static inline bool ar724x_pci_check_link(void) +static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc) { u32 reset; - reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET); + reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); return reset & AR724X_PCI_RESET_LINK_UP; } +static inline struct ar724x_pci_controller * +pci_bus_to_ar724x_controller(struct pci_bus *bus) +{ + struct pci_controller *hose; + + hose = (struct pci_controller *) bus->sysdata; + return container_of(hose, struct ar724x_pci_controller, pci_controller); +} + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) { + struct ar724x_pci_controller *apc; unsigned long flags; void __iomem *base; u32 data; - if (!ar724x_pci_link_up) + apc = pci_bus_to_ar724x_controller(bus); + if (!apc->link_up) return PCIBIOS_DEVICE_NOT_FOUND; if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; - base = ar724x_pci_devcfg_base; + base = apc->devcfg_base; - spin_lock_irqsave(&ar724x_pci_lock, flags); + spin_lock_irqsave(&apc->lock, flags); data = __raw_readl(base + (where & ~3)); switch (size) { @@ -78,17 +97,17 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, case 4: break; default: - spin_unlock_irqrestore(&ar724x_pci_lock, flags); + spin_unlock_irqrestore(&apc->lock, flags); return PCIBIOS_BAD_REGISTER_NUMBER; } - spin_unlock_irqrestore(&ar724x_pci_lock, flags); + spin_unlock_irqrestore(&apc->lock, flags); if (where == PCI_BASE_ADDRESS_0 && size == 4 && - ar724x_pci_bar0_is_cached) { + apc->bar0_is_cached) { /* use the cached value */ - *value = ar724x_pci_bar0_value; + *value = apc->bar0_value; } else { *value = data; } @@ -99,12 +118,14 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t value) { + struct ar724x_pci_controller *apc; unsigned long flags; void __iomem *base; u32 data; int s; - if (!ar724x_pci_link_up) + apc = pci_bus_to_ar724x_controller(bus); + if (!apc->link_up) return PCIBIOS_DEVICE_NOT_FOUND; if (devfn) @@ -122,18 +143,18 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, * BAR0 register in order to make the device memory * accessible. */ - ar724x_pci_bar0_is_cached = true; - ar724x_pci_bar0_value = value; + apc->bar0_is_cached = true; + apc->bar0_value = value; value = AR7240_BAR0_WAR_VALUE; } else { - ar724x_pci_bar0_is_cached = false; + apc->bar0_is_cached = false; } } - base = ar724x_pci_devcfg_base; + base = apc->devcfg_base; - spin_lock_irqsave(&ar724x_pci_lock, flags); + spin_lock_irqsave(&apc->lock, flags); data = __raw_readl(base + (where & ~3)); switch (size) { @@ -151,7 +172,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, data = value; break; default: - spin_unlock_irqrestore(&ar724x_pci_lock, flags); + spin_unlock_irqrestore(&apc->lock, flags); return PCIBIOS_BAD_REGISTER_NUMBER; } @@ -159,7 +180,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, __raw_writel(data, base + (where & ~3)); /* flush write */ __raw_readl(base + (where & ~3)); - spin_unlock_irqrestore(&ar724x_pci_lock, flags); + spin_unlock_irqrestore(&apc->lock, flags); return PCIBIOS_SUCCESSFUL; } @@ -183,18 +204,14 @@ static struct resource ar724x_mem_resource = { .flags = IORESOURCE_MEM, }; -static struct pci_controller ar724x_pci_controller = { - .pci_ops = &ar724x_pci_ops, - .io_resource = &ar724x_io_resource, - .mem_resource = &ar724x_mem_resource, -}; - static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) { + struct ar724x_pci_controller *apc; void __iomem *base; u32 pending; - base = ar724x_pci_ctrl_base; + apc = irq_get_handler_data(irq); + base = apc->ctrl_base; pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & __raw_readl(base + AR724X_PCI_REG_INT_MASK); @@ -208,10 +225,12 @@ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) static void ar724x_pci_irq_unmask(struct irq_data *d) { + struct ar724x_pci_controller *apc; void __iomem *base; u32 t; - base = ar724x_pci_ctrl_base; + apc = irq_data_get_irq_chip_data(d); + base = apc->ctrl_base; switch (d->irq) { case ATH79_PCI_IRQ(0): @@ -225,10 +244,12 @@ static void ar724x_pci_irq_unmask(struct irq_data *d) static void ar724x_pci_irq_mask(struct irq_data *d) { + struct ar724x_pci_controller *apc; void __iomem *base; u32 t; - base = ar724x_pci_ctrl_base; + apc = irq_data_get_irq_chip_data(d); + base = apc->ctrl_base; switch (d->irq) { case ATH79_PCI_IRQ(0): @@ -255,12 +276,12 @@ static struct irq_chip ar724x_pci_irq_chip = { .irq_mask_ack = ar724x_pci_irq_mask, }; -static void ar724x_pci_irq_init(int irq) +static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc) { void __iomem *base; int i; - base = ar724x_pci_ctrl_base; + base = apc->ctrl_base; __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); @@ -268,45 +289,59 @@ static void ar724x_pci_irq_init(int irq) BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); for (i = ATH79_PCI_IRQ_BASE; - i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) + i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) { irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, handle_level_irq); + irq_set_chip_data(i, apc); + } - irq_set_chained_handler(irq, ar724x_pci_irq_handler); + irq_set_handler_data(apc->irq, apc); + irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler); } static int ar724x_pci_probe(struct platform_device *pdev) { + struct ar724x_pci_controller *apc; struct resource *res; - int irq; + + apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller), + GFP_KERNEL); + if (!apc) + return -ENOMEM; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); if (!res) return -EINVAL; - ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res); - if (ar724x_pci_ctrl_base == NULL) + apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res); + if (apc->ctrl_base == NULL) return -EBUSY; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); if (!res) return -EINVAL; - ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res); - if (!ar724x_pci_devcfg_base) + apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res); + if (!apc->devcfg_base) return -EBUSY; - irq = platform_get_irq(pdev, 0); - if (irq < 0) + apc->irq = platform_get_irq(pdev, 0); + if (apc->irq < 0) return -EINVAL; - ar724x_pci_link_up = ar724x_pci_check_link(); - if (!ar724x_pci_link_up) + spin_lock_init(&apc->lock); + + apc->pci_controller.pci_ops = &ar724x_pci_ops; + apc->pci_controller.io_resource = &ar724x_io_resource; + apc->pci_controller.mem_resource = &ar724x_mem_resource; + + apc->link_up = ar724x_pci_check_link(apc); + if (!apc->link_up) dev_warn(&pdev->dev, "PCIe link is down\n"); - ar724x_pci_irq_init(irq); + ar724x_pci_irq_init(apc); - register_pci_controller(&ar724x_pci_controller); + register_pci_controller(&apc->pci_controller); return 0; } -- 1.7.10 From juhosg@openwrt.org Sun Feb 3 11:58:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Feb 2013 11:59:10 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37407 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816288Ab3BCK6wJNJR0 (ORCPT ); Sun, 3 Feb 2013 11:58:52 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id CA82225D403; Sun, 3 Feb 2013 11:58:45 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QxI4b2OINsIN; Sun, 3 Feb 2013 11:58:45 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id E08F725D3E0; Sun, 3 Feb 2013 11:58:44 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 1/4] MIPS: ath79: allow to specify bus number in PCI IRQ maps Date: Sun, 3 Feb 2013 11:58:37 +0100 Message-Id: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35690 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 987 Lines: 38 This is needed for multiple PCI bus support. Signed-off-by: Gabor Juhos --- arch/mips/ath79/pci.c | 4 +++- arch/mips/ath79/pci.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index c94bcec..d90e071 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -75,7 +75,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) const struct ath79_pci_irq *entry; entry = &ath79_pci_irq_map[i]; - if (entry->slot == slot && entry->pin == pin) { + if (entry->bus == dev->bus->number && + entry->slot == slot && + entry->pin == pin) { irq = entry->irq; break; } diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h index 51c6625..1d00a38 100644 --- a/arch/mips/ath79/pci.h +++ b/arch/mips/ath79/pci.h @@ -14,6 +14,7 @@ #define _ATH79_PCI_H struct ath79_pci_irq { + int bus; u8 slot; u8 pin; int irq; -- 1.7.10 From juhosg@openwrt.org Sun Feb 3 11:59:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Feb 2013 11:59:57 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37445 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816288Ab3BCK74YQYH2 (ORCPT ); Sun, 3 Feb 2013 11:59:56 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 2082625D3E0; Sun, 3 Feb 2013 11:59:51 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id avSQjbKzCxy1; Sun, 3 Feb 2013 11:59:51 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 41C7425C680; Sun, 3 Feb 2013 11:59:50 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 3/4] MIPS: pci-ar724x: remove static PCI IO/MEM resources Date: Sun, 3 Feb 2013 11:59:45 +0100 Message-Id: <1359889185-15779-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> References: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35691 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4011 Lines: 137 Static resources become impractical when multiple PCI controllers are present. Move the resources into the platform device registration code and change the probe routine to get those from there platform device's resources. Signed-off-by: Gabor Juhos --- arch/mips/ath79/pci.c | 21 ++++++++++++++++++++- arch/mips/pci/pci-ar724x.c | 40 ++++++++++++++++++++++++---------------- 2 files changed, 44 insertions(+), 17 deletions(-) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index d90e071..45d1112 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -139,10 +139,13 @@ static struct platform_device * ath79_register_pci_ar724x(int id, unsigned long cfg_base, unsigned long ctrl_base, + unsigned long mem_base, + unsigned long mem_size, + unsigned long io_base, int irq) { struct platform_device *pdev; - struct resource res[3]; + struct resource res[5]; memset(res, 0, sizeof(res)); @@ -160,6 +163,16 @@ ath79_register_pci_ar724x(int id, res[2].start = irq; res[2].end = irq; + res[3].name = "mem_base"; + res[3].flags = IORESOURCE_MEM; + res[3].start = mem_base; + res[3].end = mem_base + mem_size - 1; + + res[4].name = "io_base"; + res[4].flags = IORESOURCE_IO; + res[4].start = io_base; + res[4].end = io_base; + pdev = platform_device_register_simple("ar724x-pci", id, res, ARRAY_SIZE(res)); return pdev; @@ -175,6 +188,9 @@ int __init ath79_register_pci(void) pdev = ath79_register_pci_ar724x(-1, AR724X_PCI_CFG_BASE, AR724X_PCI_CTRL_BASE, + AR724X_PCI_MEM_BASE, + AR724X_PCI_MEM_SIZE, + 0, ATH79_CPU_IRQ_IP2); } else if (soc_is_ar9342() || soc_is_ar9344()) { @@ -187,6 +203,9 @@ int __init ath79_register_pci(void) pdev = ath79_register_pci_ar724x(-1, AR724X_PCI_CFG_BASE, AR724X_PCI_CTRL_BASE, + AR724X_PCI_MEM_BASE, + AR724X_PCI_MEM_SIZE, + 0, ATH79_IP2_IRQ(0)); } else { /* No PCI support */ diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 93ab877..d0d707d 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -42,6 +42,8 @@ struct ar724x_pci_controller { spinlock_t lock; struct pci_controller pci_controller; + struct resource io_res; + struct resource mem_res; }; static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc) @@ -190,20 +192,6 @@ static struct pci_ops ar724x_pci_ops = { .write = ar724x_pci_write, }; -static struct resource ar724x_io_resource = { - .name = "PCI IO space", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO, -}; - -static struct resource ar724x_mem_resource = { - .name = "PCI memory space", - .start = AR724X_PCI_MEM_BASE, - .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) { struct ar724x_pci_controller *apc; @@ -331,9 +319,29 @@ static int ar724x_pci_probe(struct platform_device *pdev) spin_lock_init(&apc->lock); + res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base"); + if (!res) + return -EINVAL; + + apc->io_res.parent = res; + apc->io_res.name = "PCI IO space"; + apc->io_res.start = res->start; + apc->io_res.end = res->end; + apc->io_res.flags = IORESOURCE_IO; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base"); + if (!res) + return -EINVAL; + + apc->mem_res.parent = res; + apc->mem_res.name = "PCI memory space"; + apc->mem_res.start = res->start; + apc->mem_res.end = res->end; + apc->mem_res.flags = IORESOURCE_MEM; + apc->pci_controller.pci_ops = &ar724x_pci_ops; - apc->pci_controller.io_resource = &ar724x_io_resource; - apc->pci_controller.mem_resource = &ar724x_mem_resource; + apc->pci_controller.io_resource = &apc->io_res; + apc->pci_controller.mem_resource = &apc->mem_res; apc->link_up = ar724x_pci_check_link(apc); if (!apc->link_up) -- 1.7.10 From juhosg@openwrt.org Sun Feb 3 12:00:24 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Feb 2013 12:00:24 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37450 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816288Ab3BCLAYF6R9o (ORCPT ); Sun, 3 Feb 2013 12:00:24 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id E7B0725D404; Sun, 3 Feb 2013 12:00:18 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id I1AFiIdHCOql; Sun, 3 Feb 2013 12:00:18 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 94CEF25D403; Sun, 3 Feb 2013 12:00:18 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 4/4] MIPS: pci-ar724x: use per-controller IRQ base Date: Sun, 3 Feb 2013 12:00:16 +0100 Message-Id: <1359889216-15851-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> References: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35692 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3305 Lines: 113 Change to the code to use per-controller IRQ base. This is needed for multiple PCI controller support. Signed-off-by: Gabor Juhos --- arch/mips/pci/pci-ar724x.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index d0d707d..0440d88 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -34,6 +34,7 @@ struct ar724x_pci_controller { void __iomem *ctrl_base; int irq; + int irq_base; bool link_up; bool bar0_is_cached; @@ -205,7 +206,7 @@ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) __raw_readl(base + AR724X_PCI_REG_INT_MASK); if (pending & AR724X_PCI_INT_DEV0) - generic_handle_irq(ATH79_PCI_IRQ(0)); + generic_handle_irq(apc->irq_base + 0); else spurious_interrupt(); @@ -215,13 +216,15 @@ static void ar724x_pci_irq_unmask(struct irq_data *d) { struct ar724x_pci_controller *apc; void __iomem *base; + int offset; u32 t; apc = irq_data_get_irq_chip_data(d); base = apc->ctrl_base; + offset = apc->irq_base - d->irq; - switch (d->irq) { - case ATH79_PCI_IRQ(0): + switch (offset) { + case 0: t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_writel(t | AR724X_PCI_INT_DEV0, base + AR724X_PCI_REG_INT_MASK); @@ -234,13 +237,15 @@ static void ar724x_pci_irq_mask(struct irq_data *d) { struct ar724x_pci_controller *apc; void __iomem *base; + int offset; u32 t; apc = irq_data_get_irq_chip_data(d); base = apc->ctrl_base; + offset = apc->irq_base - d->irq; - switch (d->irq) { - case ATH79_PCI_IRQ(0): + switch (offset) { + case 0: t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_writel(t & ~AR724X_PCI_INT_DEV0, base + AR724X_PCI_REG_INT_MASK); @@ -264,7 +269,8 @@ static struct irq_chip ar724x_pci_irq_chip = { .irq_mask_ack = ar724x_pci_irq_mask, }; -static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc) +static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc, + int id) { void __iomem *base; int i; @@ -274,10 +280,10 @@ static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc) __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); - BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); + apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT); - for (i = ATH79_PCI_IRQ_BASE; - i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) { + for (i = apc->irq_base; + i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) { irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, handle_level_irq); irq_set_chip_data(i, apc); @@ -291,6 +297,11 @@ static int ar724x_pci_probe(struct platform_device *pdev) { struct ar724x_pci_controller *apc; struct resource *res; + int id; + + id = pdev->id; + if (id == -1) + id = 0; apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller), GFP_KERNEL); @@ -347,7 +358,7 @@ static int ar724x_pci_probe(struct platform_device *pdev) if (!apc->link_up) dev_warn(&pdev->dev, "PCIe link is down\n"); - ar724x_pci_irq_init(apc); + ar724x_pci_irq_init(apc, id); register_pci_controller(&apc->pci_controller); -- 1.7.10 From sshtylyov@mvista.com Sun Feb 3 12:19:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Feb 2013 12:19:29 +0100 (CET) Received: from mail-lb0-f179.google.com ([209.85.217.179]:50948 "EHLO mail-lb0-f179.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819546Ab3BCLTTr-Nsu (ORCPT ); Sun, 3 Feb 2013 12:19:19 +0100 Received: by mail-lb0-f179.google.com with SMTP id j14so5916257lbo.38 for ; Sun, 03 Feb 2013 03:19:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=45HgMP6NCBRX07s9NU85Ec/MMx0uK8i1Ot34WU1eXpU=; b=On+kySxPqrUK66DlhP1uYzog/8C/vNQeMRTiWwq5D4J60UaYDYOa+L/w4ZHN+xZlsI u6b0nne/WAn+bKIJZVk2T1iiDh/gOjth114OmWAt54GmZ0aUbTx9+U3PaPqdgmgv31sZ Sug0zfHShoLTHG4TJkOQyF1kenciDTtDNxwyr9xrdpUg8AjDNQ5qW+K4ee6Pg9PScYkM B+IAttJEzpQABC2q9xBpNsTK/6VG2UqufPOGO7VgleZP20xi/jYEHwBmlpps/iJVT/mI zIWAu13xkPOmBK8bdsE9q4U4RUrItt7q5Pdi2rlJTwv+hlXtQKPWohhPehInO7E6UU8C qCZg== X-Received: by 10.152.121.212 with SMTP id lm20mr15980493lab.42.1359890354023; Sun, 03 Feb 2013 03:19:14 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-88-113.pppoe.mtu-net.ru. [91.79.88.113]) by mx.google.com with ESMTPS id fh4sm4319173lbb.7.2013.02.03.03.19.12 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 03 Feb 2013 03:19:13 -0800 (PST) Message-ID: <510E479C.4020305@mvista.com> Date: Sun, 03 Feb 2013 15:18:52 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips , John Crispin Subject: Re: [PATCH 3/4] MIPS: pci-ar724x: remove static PCI IO/MEM resources References: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> <1359889185-15779-1-git-send-email-juhosg@openwrt.org> In-Reply-To: <1359889185-15779-1-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkeXMoTvkCPjp3LRNb1S6Hv3GtDCZGLGE7ytZbN3suuRxtRAh9th5A8lDcx+/q7r/+CCKZd X-archive-position: 35693 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1518 Lines: 53 Hello. On 03-02-2013 14:59, Gabor Juhos wrote: > Static resources become impractical when multiple > PCI controllers are present. Move the resources > into the platform device registration code and > change the probe routine to get those from there > platform device's resources. > Signed-off-by: Gabor Juhos > --- > arch/mips/ath79/pci.c | 21 ++++++++++++++++++++- > arch/mips/pci/pci-ar724x.c | 40 ++++++++++++++++++++++++---------------- > 2 files changed, 44 insertions(+), 17 deletions(-) > diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c > index d90e071..45d1112 100644 > --- a/arch/mips/ath79/pci.c > +++ b/arch/mips/ath79/pci.c > @@ -139,10 +139,13 @@ static struct platform_device * > ath79_register_pci_ar724x(int id, > unsigned long cfg_base, > unsigned long ctrl_base, > + unsigned long mem_base, > + unsigned long mem_size, > + unsigned long io_base, > int irq) > { > struct platform_device *pdev; > - struct resource res[3]; > + struct resource res[5]; > > memset(res, 0, sizeof(res)); > > @@ -160,6 +163,16 @@ ath79_register_pci_ar724x(int id, > res[2].start = irq; > res[2].end = irq; > > + res[3].name = "mem_base"; > + res[3].flags = IORESOURCE_MEM; > + res[3].start = mem_base; > + res[3].end = mem_base + mem_size - 1; > + > + res[4].name = "io_base"; > + res[4].flags = IORESOURCE_IO; > + res[4].start = io_base; > + res[4].end = io_base; One I/O port, hm? What is it good for? WBR, Sergei From hauke@hauke-m.de Sun Feb 3 12:35:28 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Feb 2013 12:35:29 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:45558 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817128Ab3BCLf2Zm5Ws (ORCPT ); Sun, 3 Feb 2013 12:35:28 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id A7B068F62; Sun, 3 Feb 2013 12:35:27 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eT0uZ6Y7ojg0; Sun, 3 Feb 2013 12:35:22 +0100 (CET) Received: from [IPv6:2001:470:1f0b:447:b54f:3623:690c:6cea] (unknown [IPv6:2001:470:1f0b:447:b54f:3623:690c:6cea]) by hauke-m.de (Postfix) with ESMTPSA id 933358F60; Sun, 3 Feb 2013 12:35:22 +0100 (CET) Message-ID: <510E4B79.3040903@hauke-m.de> Date: Sun, 03 Feb 2013 12:35:21 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= CC: linux-mips@linux-mips.org Subject: Re: CPU hang on cpu_wait in CPU_74K References: In-Reply-To: X-Enigmail-Version: 1.4.6 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 35694 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1395 Lines: 38 On 02/01/2013 11:44 PM, RafaÅ‚ MiÅ‚ecki wrote: > Hello again ;) > > I'm hacking a BCM4706 based board which uses a 74K CPU. The problem is > that wait_cpu (see cpu-probe.c) hangs my machine (is happens as soon > as the first [um]sleep is called). > > The hang is related to the cpu-probe.c and: >> cpu_wait = r4k_wait; >> if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) >> cpu_wait = r4k_wait_irqoff; > > If I remove that lines completely [um]sleep doesn't hang machine > anymore. I'm not sure if removing that code is a proper solution. I'm > not sure what is the >> c->processor_id & 0xff > on my machine, but I've tried forcing both: >> cpu_wait = r4k_wait; > and >> cpu_wait = r4k_wait_irqoff; > and both are causing hangs. > > If I recall correctly, Hauke was checking Broadcom's code and they're > using the same solution: removing that lines completely. > > Do you have any idea how this could be solved? > Hello RafaÅ‚, In the Linux kernel form the Broadcom SDK the lines you mentioned are removed, but we can not do this in the mainline kernel as this would also affect some other non broken Broadcom MIPS CPUs. I talked about this with Ralf some days ago and he said we should add cpu_wait = NULL; somewhere in the platform specific code. This problem seams to just affect the 74K CPU used on the BCM4706 and not on the other Broadcom SoC using a 74K CPU. Hauke From juhosg@openwrt.org Sun Feb 3 13:31:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Feb 2013 13:31:52 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:33590 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816288Ab3BCMbuv-HtJ (ORCPT ); Sun, 3 Feb 2013 13:31:50 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qGX-44jZrYlq; Sun, 3 Feb 2013 13:31:47 +0100 (CET) Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id E89682802BA; Sun, 3 Feb 2013 13:31:46 +0100 (CET) Message-ID: <510E58B5.9060107@openwrt.org> Date: Sun, 03 Feb 2013 13:31:49 +0100 From: Gabor Juhos MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , linux-mips , John Crispin Subject: Re: [PATCH 3/4] MIPS: pci-ar724x: remove static PCI IO/MEM resources References: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> <1359889185-15779-1-git-send-email-juhosg@openwrt.org> <510E479C.4020305@mvista.com> In-Reply-To: <510E479C.4020305@mvista.com> X-Enigmail-Version: 1.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 35695 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1013 Lines: 37 2013.02.03. 12:18 keltezéssel, Sergei Shtylyov írta: >> @@ -160,6 +163,16 @@ ath79_register_pci_ar724x(int id, >> res[2].start = irq; >> res[2].end = irq; >> >> + res[3].name = "mem_base"; >> + res[3].flags = IORESOURCE_MEM; >> + res[3].start = mem_base; >> + res[3].end = mem_base + mem_size - 1; >> + >> + res[4].name = "io_base"; >> + res[4].flags = IORESOURCE_IO; >> + res[4].start = io_base; >> + res[4].end = io_base; > > One I/O port, hm? What is it good for? Strictly speaking it is not good for anything. This is a PCIe controller and it does not support IO requests at all. However the whole PCI code assumes that each PCI controller have an IO resource and uses the hose->io_resource pointer unconditionally. Additionally, this matches with the removed static resource: > -static struct resource ar724x_io_resource = { > - .name = "PCI IO space", > - .start = 0, > - .end = 0, > - .flags = IORESOURCE_IO, > -}; > - Thank you for the review. -Gabor From juhosg@openwrt.org Sun Feb 3 16:52:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Feb 2013 16:52:56 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:42373 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816288Ab3BCPwwr5Blh (ORCPT ); Sun, 3 Feb 2013 16:52:52 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 6606E25D424; Sun, 3 Feb 2013 16:52:46 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5UfKkb4ZncJx; Sun, 3 Feb 2013 16:52:46 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 33AE025C76B; Sun, 3 Feb 2013 16:52:46 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips , John Crispin , Gabor Juhos Subject: [PATCH 5/4] MIPS: pci-ar724x: setup command register of the PCI controller Date: Sun, 3 Feb 2013 16:52:47 +0100 Message-Id: <1359906767-20512-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> References: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35696 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5056 Lines: 183 The command register of the PCI controller is not initialized correctly by the bootloader on some boards and this leads to non working PCI bus. Add code to initialize the command register from the Linux code to avoid this. Signed-off-by: Gabor Juhos --- Sorry for the confusing patch number. This belongs to the previous 'pci-ar724x' series but I forgot to add it there. Gabor arch/mips/ath79/pci.c | 10 +++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 + arch/mips/pci/pci-ar724x.c | 63 ++++++++++++++++++++++++ 3 files changed, 74 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 45d1112..942e3f9 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -139,13 +139,14 @@ static struct platform_device * ath79_register_pci_ar724x(int id, unsigned long cfg_base, unsigned long ctrl_base, + unsigned long crp_base, unsigned long mem_base, unsigned long mem_size, unsigned long io_base, int irq) { struct platform_device *pdev; - struct resource res[5]; + struct resource res[6]; memset(res, 0, sizeof(res)); @@ -173,6 +174,11 @@ ath79_register_pci_ar724x(int id, res[4].start = io_base; res[4].end = io_base; + res[5].name = "crp_base"; + res[5].flags = IORESOURCE_MEM; + res[5].start = crp_base; + res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1; + pdev = platform_device_register_simple("ar724x-pci", id, res, ARRAY_SIZE(res)); return pdev; @@ -188,6 +194,7 @@ int __init ath79_register_pci(void) pdev = ath79_register_pci_ar724x(-1, AR724X_PCI_CFG_BASE, AR724X_PCI_CTRL_BASE, + AR724X_PCI_CRP_BASE, AR724X_PCI_MEM_BASE, AR724X_PCI_MEM_SIZE, 0, @@ -203,6 +210,7 @@ int __init ath79_register_pci(void) pdev = ath79_register_pci_ar724x(-1, AR724X_PCI_CFG_BASE, AR724X_PCI_CTRL_BASE, + AR724X_PCI_CRP_BASE, AR724X_PCI_MEM_BASE, AR724X_PCI_MEM_SIZE, 0, diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 7c87bfe..a77f6ee 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -67,6 +67,8 @@ #define AR724X_PCI_CFG_BASE 0x14000000 #define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) #define AR724X_PCI_CTRL_SIZE 0x100 diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 0440d88..8a0700d 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -29,9 +29,17 @@ #define AR7240_BAR0_WAR_VALUE 0xffff +#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \ + PCI_COMMAND_MASTER | \ + PCI_COMMAND_INVALIDATE | \ + PCI_COMMAND_PARITY | \ + PCI_COMMAND_SERR | \ + PCI_COMMAND_FAST_BACK) + struct ar724x_pci_controller { void __iomem *devcfg_base; void __iomem *ctrl_base; + void __iomem *crp_base; int irq; int irq_base; @@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_bus *bus) return container_of(hose, struct ar724x_pci_controller, pci_controller); } +static int ar724x_pci_local_write(struct ar724x_pci_controller *apc, + int where, int size, u32 value) +{ + unsigned long flags; + void __iomem *base; + u32 data; + int s; + + WARN_ON(where & (size - 1)); + + if (!apc->link_up) + return PCIBIOS_DEVICE_NOT_FOUND; + + base = apc->crp_base; + + spin_lock_irqsave(&apc->lock, flags); + data = __raw_readl(base + (where & ~3)); + + switch (size) { + case 1: + s = ((where & 3) * 8); + data &= ~(0xff << s); + data |= ((value & 0xff) << s); + break; + case 2: + s = ((where & 2) * 8); + data &= ~(0xffff << s); + data |= ((value & 0xffff) << s); + break; + case 4: + data = value; + break; + default: + spin_unlock_irqrestore(&apc->lock, flags); + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + __raw_writel(data, base + (where & ~3)); + /* flush write */ + __raw_readl(base + (where & ~3)); + spin_unlock_irqrestore(&apc->lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) { @@ -324,6 +377,14 @@ static int ar724x_pci_probe(struct platform_device *pdev) if (!apc->devcfg_base) return -EBUSY; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base"); + if (!res) + return -EINVAL; + + apc->crp_base = devm_request_and_ioremap(&pdev->dev, res); + if (apc->crp_base == NULL) + return -EBUSY; + apc->irq = platform_get_irq(pdev, 0); if (apc->irq < 0) return -EINVAL; @@ -360,6 +421,8 @@ static int ar724x_pci_probe(struct platform_device *pdev) ar724x_pci_irq_init(apc, id); + ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT); + register_pci_controller(&apc->pci_controller); return 0; -- 1.7.10 From james.hogan@imgtec.com Mon Feb 4 11:10:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Feb 2013 11:10:15 +0100 (CET) Received: from multi.imgtec.com ([194.200.65.239]:57570 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816671Ab3BDKKKJYOYg (ORCPT ); Mon, 4 Feb 2013 11:10:10 +0100 From: James Hogan To: CC: , , , , , , , , James Hogan , "Thomas Gleixner" , Mike Frysinger , Fenghua Yu , Ralf Baechle , "James E.J. Bottomley" , Helge Deller , "Benjamin Herrenschmidt" , Paul Mackerras , Paul Mundt Subject: [PATCH RESEND 1/1] arch Kconfig: remove references to IRQ_PER_CPU Date: Mon, 4 Feb 2013 10:09:43 +0000 Message-ID: <1359972583-17134-1-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 1.7.7.6 MIME-Version: 1.0 Content-Type: text/plain X-SEF-Processed: 7_3_0_01181__2013_02_04_10_10_00 X-archive-position: 35697 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: james.hogan@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3727 Lines: 124 The IRQ_PER_CPU Kconfig symbol was removed in the following commit: Commit 6a58fb3bad099076f36f0f30f44507bc3275cdb6 ("genirq: Remove CONFIG_IRQ_PER_CPU") merged in v2.6.39-rc1. But IRQ_PER_CPU wasn't removed from any of the architecture Kconfig files where it was defined or selected. It's completely unused so remove the remaining references. Signed-off-by: James Hogan Cc: Thomas Gleixner Cc: Mike Frysinger Cc: Fenghua Yu Cc: Ralf Baechle Cc: "James E.J. Bottomley" Cc: Helge Deller Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Paul Mundt Acked-by: Tony Luck Acked-by: Richard Kuo --- Does anybody want to pick this patch up? arch/blackfin/Kconfig | 1 - arch/hexagon/Kconfig | 1 - arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 1 - arch/parisc/Kconfig | 1 - arch/powerpc/Kconfig | 1 - arch/sh/Kconfig | 3 --- 7 files changed, 0 insertions(+), 9 deletions(-) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index b6f3ad5..c709715 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -38,7 +38,6 @@ config BLACKFIN select HAVE_GENERIC_HARDIRQS select GENERIC_ATOMIC64 select GENERIC_IRQ_PROBE - select IRQ_PER_CPU if SMP select USE_GENERIC_SMP_HELPERS if SMP select HAVE_NMI_WATCHDOG if NMI_WATCHDOG select GENERIC_SMP_IDLE_THREAD diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig index 0744f7d..800dd9c 100644 --- a/arch/hexagon/Kconfig +++ b/arch/hexagon/Kconfig @@ -12,7 +12,6 @@ config HEXAGON # select ARCH_WANT_OPTIONAL_GPIOLIB # select ARCH_REQUIRE_GPIOLIB # select HAVE_CLK - # select IRQ_PER_CPU # select GENERIC_PENDING_IRQ if SMP select HAVE_IRQ_WORK select GENERIC_ATOMIC64 diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 3279646..00c2e88 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -29,7 +29,6 @@ config IA64 select ARCH_DISCARD_MEMBLOCK select GENERIC_IRQ_PROBE select GENERIC_PENDING_IRQ if SMP - select IRQ_PER_CPU select GENERIC_IRQ_SHOW select ARCH_WANT_OPTIONAL_GPIOLIB select ARCH_HAVE_NMI_SAFE_CMPXCHG diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2ac626a..451c2e7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2161,7 +2161,6 @@ source "mm/Kconfig" config SMP bool "Multi-Processing support" depends on SYS_SUPPORTS_SMP - select IRQ_PER_CPU select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index b77feff..8525be4 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -16,7 +16,6 @@ config PARISC select BROKEN_RODATA select GENERIC_IRQ_PROBE select GENERIC_PCI_IOMAP - select IRQ_PER_CPU select ARCH_HAVE_NMI_SAFE_CMPXCHG select GENERIC_SMP_IDLE_THREAD select GENERIC_STRNCPY_FROM_USER diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 17903f1..f3d7090a 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -125,7 +125,6 @@ config PPC select HAVE_GENERIC_HARDIRQS select ARCH_WANT_IPC_PARSE_VERSION select SPARSE_IRQ - select IRQ_PER_CPU select IRQ_DOMAIN select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index babc2b8..6f799ec 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -91,9 +91,6 @@ config GENERIC_CSUM config GENERIC_HWEIGHT def_bool y -config IRQ_PER_CPU - def_bool y - config GENERIC_GPIO def_bool n -- 1.7.7.6 From lethal@linux-sh.org Mon Feb 4 12:31:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Feb 2013 12:31:33 +0100 (CET) Received: from linux-sh.org ([111.68.239.195]:46106 "EHLO linux-sh.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822999Ab3BDLb34vNCy (ORCPT ); Mon, 4 Feb 2013 12:31:29 +0100 Received: from linux-sh.org (localhost.localdomain [127.0.0.1]) by linux-sh.org (8.14.5/8.14.4) with ESMTP id r14BUj4s021736; Mon, 4 Feb 2013 20:30:45 +0900 Received: (from pmundt@localhost) by linux-sh.org (8.14.5/8.14.4/Submit) id r14BUiuQ021716; Mon, 4 Feb 2013 20:30:44 +0900 X-Authentication-Warning: linux-sh.org: pmundt set sender to lethal@linux-sh.org using -f Date: Mon, 4 Feb 2013 20:30:44 +0900 From: Paul Mundt To: James Hogan Cc: , , , , , , , , , "Thomas Gleixner" , Mike Frysinger , Fenghua Yu , Ralf Baechle , "James E.J. Bottomley" , Helge Deller , "Benjamin Herrenschmidt" , Paul Mackerras Subject: Re: [PATCH RESEND 1/1] arch Kconfig: remove references to IRQ_PER_CPU Message-ID: <20130204113043.GB12216@linux-sh.org> References: <1359972583-17134-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1359972583-17134-1-git-send-email-james.hogan@imgtec.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35698 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lethal@linux-sh.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1002 Lines: 24 On Mon, Feb 04, 2013 at 10:09:43AM +0000, James Hogan wrote: > The IRQ_PER_CPU Kconfig symbol was removed in the following commit: > > Commit 6a58fb3bad099076f36f0f30f44507bc3275cdb6 ("genirq: Remove > CONFIG_IRQ_PER_CPU") merged in v2.6.39-rc1. > > But IRQ_PER_CPU wasn't removed from any of the architecture Kconfig > files where it was defined or selected. It's completely unused so remove > the remaining references. > > Signed-off-by: James Hogan > Cc: Thomas Gleixner > Cc: Mike Frysinger > Cc: Fenghua Yu > Cc: Ralf Baechle > Cc: "James E.J. Bottomley" > Cc: Helge Deller > Cc: Benjamin Herrenschmidt > Cc: Paul Mackerras > Cc: Paul Mundt > Acked-by: Tony Luck > Acked-by: Richard Kuo Acked-by: Paul Mundt From sshtylyov@mvista.com Mon Feb 4 13:13:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Feb 2013 13:13:53 +0100 (CET) Received: from mail-lb0-f171.google.com ([209.85.217.171]:53252 "EHLO mail-lb0-f171.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823081Ab3BDMNvm51p1 (ORCPT ); Mon, 4 Feb 2013 13:13:51 +0100 Received: by mail-lb0-f171.google.com with SMTP id gg13so6600776lbb.16 for ; Mon, 04 Feb 2013 04:13:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=dCwU74k/Bzwk8s3uknqA9eT7r9C+KnQ0Z2jk8mCCtCo=; b=k/L9hOOFLELBGqmxsS40Taol1RhiIRobbLtUR+15wUKtTyp2zjrRIatHezEodYqnp+ nUWtRylJfVD3/NFluoY1yPJ+y5KlMFMGRh3WB1ZMji4fT9HFLkKoJDyBXn/5M/qj1201 +fiVr+632brfyQR/a8xiBvqbEqG5zL33K8KbRYNn72TdI6uvnsa1TaVTrClA7javr/PF 91N3NPZ840BuZPkAk/tSX+3wxmJHe2zn3OV7TONiPN1NyVmwTCRjQ6+DwNt4InkpTZOh NvDQztgRQMVVLDKwt6H6AzM1wIj2fC85TV6XvutzjEv4yffWUx4Ck04/pPyzzXsKuQKJ koCQ== X-Received: by 10.152.133.133 with SMTP id pc5mr19008933lab.32.1359980025949; Mon, 04 Feb 2013 04:13:45 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-75-188.pppoe.mtu-net.ru. [91.79.75.188]) by mx.google.com with ESMTPS id b13sm2079412lbd.10.2013.02.04.04.13.43 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 04 Feb 2013 04:13:44 -0800 (PST) Message-ID: <510FA5E3.4010403@mvista.com> Date: Mon, 04 Feb 2013 16:13:23 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips , John Crispin Subject: Re: [PATCH 3/4] MIPS: pci-ar724x: remove static PCI IO/MEM resources References: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> <1359889185-15779-1-git-send-email-juhosg@openwrt.org> <510E479C.4020305@mvista.com> <510E58B5.9060107@openwrt.org> In-Reply-To: <510E58B5.9060107@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlOoo/YIeto7338c0PqfsITOuPEduLMllVM2/L9q0KgtNXIAgwZKu/Bj6k4ZaN+1zJ/Yo4b X-archive-position: 35699 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1215 Lines: 46 Hello. On 03-02-2013 16:31, Gabor Juhos wrote: >>> @@ -160,6 +163,16 @@ ath79_register_pci_ar724x(int id, >>> res[2].start = irq; >>> res[2].end = irq; >>> >>> + res[3].name = "mem_base"; >>> + res[3].flags = IORESOURCE_MEM; >>> + res[3].start = mem_base; >>> + res[3].end = mem_base + mem_size - 1; >>> + >>> + res[4].name = "io_base"; >>> + res[4].flags = IORESOURCE_IO; >>> + res[4].start = io_base; >>> + res[4].end = io_base; >> >> One I/O port, hm? What is it good for? > Strictly speaking it is not good for anything. This is a PCIe controller and it > does not support IO requests at all. Is this the case with every PCIe controller or only this particular one? > However the whole PCI code assumes that > each PCI controller have an IO resource and uses the hose->io_resource pointer > unconditionally. > Additionally, this matches with the removed static resource: >> -static struct resource ar724x_io_resource = { >> - .name = "PCI IO space", >> - .start = 0, >> - .end = 0, >> - .flags = IORESOURCE_IO, >> -}; >> - Since you seems to always pass 0, maybe you don't need 'io_base' parameter to the function above? > -Gabor WBR, Sergei From juhosg@openwrt.org Mon Feb 4 14:14:49 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Feb 2013 14:14:51 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:56526 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817032Ab3BDNOtvFFQ0 (ORCPT ); Mon, 4 Feb 2013 14:14:49 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tZt8X6F7sFPU; Mon, 4 Feb 2013 14:14:46 +0100 (CET) Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id CD32C2840E6; Mon, 4 Feb 2013 14:14:45 +0100 (CET) Message-ID: <510FB449.2040806@openwrt.org> Date: Mon, 04 Feb 2013 14:14:49 +0100 From: Gabor Juhos MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , linux-mips , John Crispin Subject: Re: [PATCH 3/4] MIPS: pci-ar724x: remove static PCI IO/MEM resources References: <1359889120-15699-1-git-send-email-juhosg@openwrt.org> <1359889185-15779-1-git-send-email-juhosg@openwrt.org> <510E479C.4020305@mvista.com> <510E58B5.9060107@openwrt.org> <510FA5E3.4010403@mvista.com> In-Reply-To: <510FA5E3.4010403@mvista.com> X-Enigmail-Version: 1.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 35700 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1647 Lines: 52 2013.02.04. 13:13 keltezéssel, Sergei Shtylyov írta: > Hello. > > On 03-02-2013 16:31, Gabor Juhos wrote: > >>>> @@ -160,6 +163,16 @@ ath79_register_pci_ar724x(int id, >>>> res[2].start = irq; >>>> res[2].end = irq; >>>> >>>> + res[3].name = "mem_base"; >>>> + res[3].flags = IORESOURCE_MEM; >>>> + res[3].start = mem_base; >>>> + res[3].end = mem_base + mem_size - 1; >>>> + >>>> + res[4].name = "io_base"; >>>> + res[4].flags = IORESOURCE_IO; >>>> + res[4].start = io_base; >>>> + res[4].end = io_base; >>> >>> One I/O port, hm? What is it good for? > >> Strictly speaking it is not good for anything. This is a PCIe controller and it >> does not support IO requests at all. > > Is this the case with every PCIe controller or only this particular one? It is a limitation of this controller. > >> However the whole PCI code assumes that >> each PCI controller have an IO resource and uses the hose->io_resource pointer >> unconditionally. > >> Additionally, this matches with the removed static resource: > >>> -static struct resource ar724x_io_resource = { >>> - .name = "PCI IO space", >>> - .start = 0, >>> - .end = 0, >>> - .flags = IORESOURCE_IO, >>> -}; >>> - > > Since you seems to always pass 0, maybe you don't need 'io_base' parameter to > the function above? The AR724x SoCs SoCs have one PCIe controller only. However newer chips have more than one PCIe controllers, and each of those controllers needs a different io_base value to avoid resource conflicts. I'm preparing patches for newer SoCs and if everything goes well I will send those today. -GAbor From sjhill@mips.com Mon Feb 4 17:06:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Feb 2013 17:06:57 +0100 (CET) Received: from dns1.mips.com ([12.201.5.69]:52341 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823901Ab3BDQGzmuUQw convert rfc822-to-8bit (ORCPT ); Mon, 4 Feb 2013 17:06:55 +0100 Received: from mailgate1.mips.com (mailgate1.mips.com [12.201.5.111]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id r14G6mRY001243; Mon, 4 Feb 2013 08:06:48 -0800 X-WSS-ID: 0MHPE39-01-0U0-02 X-M-MSG: Received: from exchdb01.mips.com (unknown [192.168.36.67]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate1.mips.com (Postfix) with ESMTP id 2E65F364664; Mon, 4 Feb 2013 08:06:44 -0800 (PST) Received: from EXCHDB03.MIPS.com ([fe80::6df1:ae84:797e:9076]) by exchdb01.mips.com ([::1]) with mapi id 14.02.0247.003; Mon, 4 Feb 2013 08:06:40 -0800 From: "Hill, Steven" To: David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "cernekee@gmail.com" Subject: RE: [PATCH][RFC] MIPS: microMIPS: Add support to micro-assembler. Thread-Topic: [PATCH][RFC] MIPS: microMIPS: Add support to micro-assembler. Thread-Index: AQHN/pSXpmmHN005Y0SyRQVcOld1K5hisX+AgAcyAHs= Date: Mon, 4 Feb 2013 16:06:39 +0000 Message-ID: <31E06A9FC96CEC488B43B19E2957C1B801146CA6BA@exchdb03.mips.com> References: <1359514228-2161-1-git-send-email-sjhill@mips.com>,<510960B9.1060800@gmail.com> In-Reply-To: <510960B9.1060800@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.36.79] x-ems-proccessed: 6LP3oGfGVdcdb8o1aBnt6w== x-ems-stamp: OLtTF1Ph702SdH+XV5a0hQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 35701 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 923 Lines: 18 > I wonder if we could get rid of most of these #ifdefs by taking the > approach used in scripts/recordmcount.{c,h} or scripts/sortextable.{c,h} > I do not see how these are at all applicable. I am not going to modify any compiled ELF binary. > That is, move all the code that varies between microMIPS and MIPS to an > included file. At the top of that file have a single > #if...#else...#endif block that defines the constants for each variety. > > Then include this file as many times as needed (once or twice) to > produce the definitions required. > > This would allow both a MIPS and microMIPS uasm to exist in the same kernel. > I did this already did this once before in the patch. The only modification of the patch would be to get rid of CONFIG_CPU_MICROMIPS controlling the inclusion of the 'uasm-micromips' and to include it unconditionally. Comments? -Steve From james.hogan@imgtec.com Mon Feb 4 19:09:25 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Feb 2013 19:09:28 +0100 (CET) Received: from terminus.zytor.com ([198.137.202.10]:47997 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6826484Ab3BDSJZOdTVP (ORCPT ); Mon, 4 Feb 2013 19:09:25 +0100 Received: from terminus.zytor.com (localhost [127.0.0.1]) by terminus.zytor.com (8.14.5/8.14.5) with ESMTP id r14I8GCr026632 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 4 Feb 2013 10:08:21 -0800 Received: (from tipbot@localhost) by terminus.zytor.com (8.14.5/8.14.5/Submit) id r14I8Dtq026629; Mon, 4 Feb 2013 10:08:13 -0800 Date: Mon, 4 Feb 2013 10:08:13 -0800 X-Authentication-Warning: terminus.zytor.com: tipbot set sender to tipbot@zytor.com using -f From: tip-bot for James Hogan Message-ID: Cc: mingo@kernel.org, linuxppc-dev@lists.ozlabs.org, tony.luck@intel.com, linux-mips@linux-mips.org, ralf@linux-mips.org, vapier@gentoo.org, tglx@linutronix.de, deller@gmx.de, linux-kernel@vger.kernel.org, hpa@zytor.com, paulus@samba.org, james.hogan@imgtec.com, lethal@linux-sh.org, benh@kernel.crashing.org, fenghua.yu@intel.com, jejb@parisc-linux.org, uclinux-dist-devel@blackfin.uclinux.org, rkuo@codeaurora.org Reply-To: mingo@kernel.org, linuxppc-dev@lists.ozlabs.org, tony.luck@intel.com, linux-mips@linux-mips.org, ralf@linux-mips.org, vapier@gentoo.org, tglx@linutronix.de, deller@gmx.de, linux-kernel@vger.kernel.org, hpa@zytor.com, paulus@samba.org, james.hogan@imgtec.com, lethal@linux-sh.org, benh@kernel.crashing.org, fenghua.yu@intel.com, jejb@parisc-linux.org, uclinux-dist-devel@blackfin.uclinux.org, rkuo@codeaurora.org In-Reply-To: <1359972583-17134-1-git-send-email-james.hogan@imgtec.com> References: <1359972583-17134-1-git-send-email-james.hogan@imgtec.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:irq/core] arch Kconfig: Remove references to IRQ_PER_CPU Git-Commit-ID: f7c819c020db9796ae3a662b82a310617f92b15b X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Precedence: bulk X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.2.7 (terminus.zytor.com [127.0.0.1]); Mon, 04 Feb 2013 10:08:22 -0800 (PST) X-archive-position: 35702 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: james.hogan@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4222 Lines: 130 Commit-ID: f7c819c020db9796ae3a662b82a310617f92b15b Gitweb: http://git.kernel.org/tip/f7c819c020db9796ae3a662b82a310617f92b15b Author: James Hogan AuthorDate: Mon, 4 Feb 2013 10:09:43 +0000 Committer: Thomas Gleixner CommitDate: Mon, 4 Feb 2013 18:53:20 +0100 arch Kconfig: Remove references to IRQ_PER_CPU The IRQ_PER_CPU Kconfig symbol was removed in the following commit: Commit 6a58fb3bad099076f36f0f30f44507bc3275cdb6 ("genirq: Remove CONFIG_IRQ_PER_CPU") merged in v2.6.39-rc1. But IRQ_PER_CPU wasn't removed from any of the architecture Kconfig files where it was defined or selected. It's completely unused so remove the remaining references. Signed-off-by: James Hogan Cc: Cc: Cc: Cc: Mike Frysinger Cc: Fenghua Yu Acked-by: Ralf Baechle Cc: James E.J. Bottomley Cc: Helge Deller Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Acked-by: Paul Mundt Acked-by: Tony Luck Acked-by: Richard Kuo Link: http://lkml.kernel.org/r/1359972583-17134-1-git-send-email-james.hogan@imgtec.com Signed-off-by: Thomas Gleixner --- arch/blackfin/Kconfig | 1 - arch/hexagon/Kconfig | 1 - arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 1 - arch/parisc/Kconfig | 1 - arch/powerpc/Kconfig | 1 - arch/sh/Kconfig | 3 --- 7 files changed, 9 deletions(-) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 86f891f..67e4aaa 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -37,7 +37,6 @@ config BLACKFIN select HAVE_GENERIC_HARDIRQS select GENERIC_ATOMIC64 select GENERIC_IRQ_PROBE - select IRQ_PER_CPU if SMP select USE_GENERIC_SMP_HELPERS if SMP select HAVE_NMI_WATCHDOG if NMI_WATCHDOG select GENERIC_SMP_IDLE_THREAD diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig index 40a3185..e4decc6 100644 --- a/arch/hexagon/Kconfig +++ b/arch/hexagon/Kconfig @@ -12,7 +12,6 @@ config HEXAGON # select ARCH_WANT_OPTIONAL_GPIOLIB # select ARCH_REQUIRE_GPIOLIB # select HAVE_CLK - # select IRQ_PER_CPU # select GENERIC_PENDING_IRQ if SMP select GENERIC_ATOMIC64 select HAVE_PERF_EVENTS diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 3279646..00c2e88 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -29,7 +29,6 @@ config IA64 select ARCH_DISCARD_MEMBLOCK select GENERIC_IRQ_PROBE select GENERIC_PENDING_IRQ if SMP - select IRQ_PER_CPU select GENERIC_IRQ_SHOW select ARCH_WANT_OPTIONAL_GPIOLIB select ARCH_HAVE_NMI_SAFE_CMPXCHG diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 121ed51..9becc44 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2160,7 +2160,6 @@ source "mm/Kconfig" config SMP bool "Multi-Processing support" depends on SYS_SUPPORTS_SMP - select IRQ_PER_CPU select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 9dd5c18..a32e34e 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -15,7 +15,6 @@ config PARISC select BROKEN_RODATA select GENERIC_IRQ_PROBE select GENERIC_PCI_IOMAP - select IRQ_PER_CPU select ARCH_HAVE_NMI_SAFE_CMPXCHG select GENERIC_SMP_IDLE_THREAD select GENERIC_STRNCPY_FROM_USER diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index d45edca..561ccca 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -124,7 +124,6 @@ config PPC select HAVE_GENERIC_HARDIRQS select ARCH_WANT_IPC_PARSE_VERSION select SPARSE_IRQ - select IRQ_PER_CPU select IRQ_DOMAIN select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 996e008..9c833c5 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -90,9 +90,6 @@ config GENERIC_CSUM config GENERIC_HWEIGHT def_bool y -config IRQ_PER_CPU - def_bool y - config GENERIC_GPIO def_bool n From James.Bottomley@HansenPartnership.com Mon Feb 4 19:30:28 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Feb 2013 19:30:31 +0100 (CET) Received: from bedivere.hansenpartnership.com ([66.63.167.143]:56408 "EHLO bedivere.hansenpartnership.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827479Ab3BDSa2X3blS (ORCPT ); Mon, 4 Feb 2013 19:30:28 +0100 Received: from localhost (localhost [127.0.0.1]) by bedivere.hansenpartnership.com (Postfix) with ESMTP id DFCF68EE0E2; Mon, 4 Feb 2013 10:30:19 -0800 (PST) Received: from bedivere.hansenpartnership.com ([127.0.0.1]) by localhost (bedivere.hansenpartnership.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CncHN6wDpoxw; Mon, 4 Feb 2013 10:30:19 -0800 (PST) Received: from [172.25.2.120] (66-59-47-3.static-ip.telepacific.net [66.59.47.3]) by bedivere.hansenpartnership.com (Postfix) with ESMTPSA id 4F0CE8EE0E0; Mon, 4 Feb 2013 10:30:18 -0800 (PST) Message-ID: <1360002617.2465.33.camel@dabdike> Subject: Re: [PATCH RESEND 1/1] arch Kconfig: remove references to IRQ_PER_CPU From: James Bottomley To: James Hogan Cc: linux-kernel@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org, Thomas Gleixner , Mike Frysinger , Fenghua Yu , Ralf Baechle , "James E.J. Bottomley" , Helge Deller , Benjamin Herrenschmidt , Paul Mackerras , Paul Mundt Date: Mon, 04 Feb 2013 10:30:17 -0800 In-Reply-To: <1359972583-17134-1-git-send-email-james.hogan@imgtec.com> References: <1359972583-17134-1-git-send-email-james.hogan@imgtec.com> Content-Type: text/plain; charset="ISO-8859-15" X-Mailer: Evolution 3.6.2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-archive-position: 35703 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: James.Bottomley@HansenPartnership.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1221 Lines: 35 On Mon, 2013-02-04 at 10:09 +0000, James Hogan wrote: > The IRQ_PER_CPU Kconfig symbol was removed in the following commit: > > Commit 6a58fb3bad099076f36f0f30f44507bc3275cdb6 ("genirq: Remove > CONFIG_IRQ_PER_CPU") merged in v2.6.39-rc1. > > But IRQ_PER_CPU wasn't removed from any of the architecture Kconfig > files where it was defined or selected. It's completely unused so remove > the remaining references. > > Signed-off-by: James Hogan > Cc: Thomas Gleixner > Cc: Mike Frysinger > Cc: Fenghua Yu > Cc: Ralf Baechle > Cc: "James E.J. Bottomley" > Cc: Helge Deller > Cc: Benjamin Herrenschmidt > Cc: Paul Mackerras > Cc: Paul Mundt > Acked-by: Tony Luck > Acked-by: Richard Kuo For what it's worth ACK, but I don't really think you need it since the patch is trivial and obviously correct. > > Does anybody want to pick this patch up? I see Thomas already has. Thanks, by the way, for not doing this as one patch per architecture ... James From ganesanr@broadcom.com Tue Feb 5 12:29:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 12:29:21 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:3746 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823099Ab3BEL3S6gAUx (ORCPT ); Tue, 5 Feb 2013 12:29:18 +0100 Received: from [10.9.208.53] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 05 Feb 2013 03:26:56 -0800 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) by IRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 5 Feb 2013 03:29:02 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) with Microsoft SMTP Server id 14.1.355.2; Tue, 5 Feb 2013 03:29:02 -0800 Received: from lc-blr-152.ban.broadcom.com (lc-blr-152.ban.broadcom.com [10.132.129.187]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2773C40FEA; Tue, 5 Feb 2013 03:29:02 -0800 (PST) Received: by lc-blr-152.ban.broadcom.com (Postfix, from userid 28730) id 003B92056BE; Tue, 5 Feb 2013 16:59:00 +0530 (IST) Date: Tue, 5 Feb 2013 16:59:00 +0530 From: "Ganesan Ramalignam" To: "Ben Hutchings" cc: linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 1/2] NET: ethernet/netlogic: Netlogic XLR/XLS GMAC driver Message-ID: <20130205112859.GA17465@ganesanr.netlogicmircro.com> References: <1359450699-26141-1-git-send-email-ganesanr@broadcom.com> <1359508293.4144.29.camel@bwh-desktop.uk.solarflarecom.com> MIME-Version: 1.0 In-Reply-To: <1359508293.4144.29.camel@bwh-desktop.uk.solarflarecom.com> User-Agent: Mutt/1.4.2.2i X-WSS-ID: 7D0E330A1YS828586-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit X-archive-position: 35704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ganesanr@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4587 Lines: 149 Ben, Thank you for your comments, will submit the driver with fixes. Reply inline. On Wed, Jan 30, 2013 at 01:11:33AM +0000, Ben Hutchings wrote: > On Tue, 2013-01-29 at 14:41 +0530, ganesanr@broadcom.com wrote: > > From: Ganesan Ramalingam > > > > Add support for the Network Accelerator Engine on Netlogic XLR/XLS > > MIPS SoCs. The XLR/XLS NAE blocks can be configured as one 10G > > interface or four 1G interfaces. This driver supports blocks > > with 1G ports. > > > > Signed-off-by: Ganesan Ramalingam > > --- > > This patch has to be merged through netdev tree. > > Please review and let me know if there are any comments or suggestions. > > > > drivers/net/ethernet/Kconfig | 1 + > > drivers/net/ethernet/Makefile | 1 + > > drivers/net/ethernet/netlogic/Kconfig | 8 + > > drivers/net/ethernet/netlogic/Makefile | 1 + > > drivers/net/ethernet/netlogic/xlr_net.c | 1132 +++++++++++++++++++++++++++++++ > > drivers/net/ethernet/netlogic/xlr_net.h | 1098 ++++++++++++++++++++++++++++++ > > 6 files changed, 2241 insertions(+), 0 deletions(-) > > create mode 100644 drivers/net/ethernet/netlogic/Kconfig > > create mode 100644 drivers/net/ethernet/netlogic/Makefile > > create mode 100644 drivers/net/ethernet/netlogic/xlr_net.c > > create mode 100644 drivers/net/ethernet/netlogic/xlr_net.h > > Why add a netlogic directory when the company is now a part of Broadcom? > > [...] All our submissions are still following the Netlogic convention, look at arch/mips/netlogic/, this will be changed in future with BRCM wrapper. > > --- /dev/null > > +++ b/drivers/net/ethernet/netlogic/xlr_net.c > [...] > > +/* Ethtool operation */ > > +static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) > > +{ > > + return 0; > > +} > > + > > +static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) > > +{ > > + return 0; > > +} > > + > > +static void xlr_get_drvinfo(struct net_device *ndev, > > + struct ethtool_drvinfo *drvinfo) > > +{ > > + return; > > +} > > + > > +static u32 xlr_get_link(struct net_device *ndev) > > +{ > > + return 0; > > +} > > + > > +static struct ethtool_ops xlr_ethtool_ops = { > > + .get_settings = xlr_get_settings, > > + .set_settings = xlr_set_settings, > > + .get_drvinfo = xlr_get_drvinfo, > > + .get_link = xlr_get_link, > > +}; > > Either implement them or don't. I'm guessing that phylib can handle > get_settings and set_settings for you. > > [...] Fixed > > +static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb, > > + struct net_device *ndev) > > +{ > > + struct nlm_fmn_msg msg; > > + struct xlr_net_priv *priv = netdev_priv(ndev); > > + int ret; > > + u16 qmap; > > + u32 flags; > > + > > + qmap = skb->queue_mapping; > > + xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb); > > + flags = nlm_cop2_enable(); > > + ret = nlm_fmn_send(2, 0, priv->nd->tx_stnid, &msg); > > + nlm_cop2_restore(flags); > > + return NETDEV_TX_OK; > > +} > > If nlm_fmn_send() fails then you need to free the skbuff. > > [...] Fixed > > +static void xlr_stats(struct net_device *ndev, struct net_device_stats *stats) > > +{ > > + struct xlr_net_priv *priv = netdev_priv(ndev); > > + > > + stats->rx_packets = nlm_read_reg(priv->base_addr, RX_PACKET_COUNTER); > > + stats->tx_packets = nlm_read_reg(priv->base_addr, TX_PACKET_COUNTER); > > + stats->rx_bytes = nlm_read_reg(priv->base_addr, RX_BYTE_COUNTER); > > + stats->tx_bytes = nlm_read_reg(priv->base_addr, TX_BYTE_COUNTER); > > 32-bit byte counters for a 1G/10G device? Seriously? > > [...] Yes, all are 32-bit byte counters > > +struct net_device_stats *xlr_get_stats(struct net_device *ndev) > > +{ > > + struct net_device_stats *stats = &ndev->stats; > > + > > + xlr_stats(ndev, stats); > > + return stats; > > +} > > You should probably be implementing ndo_get_stats64 to provide 64-bit > stats even on a 32-bit kernel. > Fixed > > +static int xlr_net_probe(struct platform_device *pdev) > > +{ > [...] > > + ndev->watchdog_timeo = 1000 * HZ; > [...] > Fixed > A watchdog timeout of 1000 seconds is ridiculous. I guess someone just > kept seeing the watchdog fire and increasing the timeout, and never > thought about *why* this was happening. > > Ben. > > -- > Ben Hutchings, Staff Engineer, Solarflare > Not speaking for my employer; that's the marketing department's job. > They asked us to note that Solarflare product names are trademarked. > > From ganesanr@broadcom.com Tue Feb 5 12:30:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 12:31:08 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:2331 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823008Ab3BELa4C4Fx5 (ORCPT ); Tue, 5 Feb 2013 12:30:56 +0100 Received: from [10.9.208.57] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 05 Feb 2013 03:27:27 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 5 Feb 2013 03:30:42 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.1.355.2; Tue, 5 Feb 2013 03:30:42 -0800 Received: from lc-blr-152.ban.broadcom.com (lc-blr-152.ban.broadcom.com [10.132.129.187]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 29EFE41007; Tue, 5 Feb 2013 03:30:24 -0800 (PST) From: ganesanr@broadcom.com To: linux-mips@linux-mips.org, netdev@vger.kernel.org cc: "Ganesan Ramalingam" Subject: [PATCH v2 1/2] NET: ethernet/netlogic: Netlogic XLR/XLS GMAC driver Date: Tue, 5 Feb 2013 17:00:19 +0530 Message-ID: <1360063819-17555-1-git-send-email-ganesanr@broadcom.com> X-Mailer: git-send-email 1.7.6 MIME-Version: 1.0 X-WSS-ID: 7D0E33153SK790817-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35705 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ganesanr@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 104409 Lines: 2294 From: Ganesan Ramalingam Add support for the Network Accelerator Engine on Netlogic XLR/XLS MIPS SoCs. The XLR/XLS NAE blocks can be configured as one 10G interface or four 1G interfaces. This driver supports blocks with 1G ports. Signed-off-by: Ganesan Ramalingam --- This patch has to be merged through netdev tree. Changes since v1: * Implementing ethtool using phylib * Free skb buf incase of nlm_fmn_send() fail * Use of ndo_get_stats64 instead of ndo_get_stats * Watchdog timeo fix drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile | 1 + drivers/net/ethernet/netlogic/Kconfig | 8 + drivers/net/ethernet/netlogic/Makefile | 1 + drivers/net/ethernet/netlogic/xlr_net.c | 1109 +++++++++++++++++++++++++++++++ drivers/net/ethernet/netlogic/xlr_net.h | 1099 ++++++++++++++++++++++++++++++ 6 files changed, 2219 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ethernet/netlogic/Kconfig create mode 100644 drivers/net/ethernet/netlogic/Makefile create mode 100644 drivers/net/ethernet/netlogic/xlr_net.c create mode 100644 drivers/net/ethernet/netlogic/xlr_net.h diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index e4ff389..5a8c9dc 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -168,5 +168,6 @@ source "drivers/net/ethernet/via/Kconfig" source "drivers/net/ethernet/wiznet/Kconfig" source "drivers/net/ethernet/xilinx/Kconfig" source "drivers/net/ethernet/xircom/Kconfig" +source "drivers/net/ethernet/netlogic/Kconfig" endif # ETHERNET diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index d447307..cef1593 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -75,3 +75,4 @@ obj-$(CONFIG_NET_VENDOR_VIA) += via/ obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/ obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/ obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/ +obj-$(CONFIG_NETLOGIC_XLR_NET) += netlogic/ diff --git a/drivers/net/ethernet/netlogic/Kconfig b/drivers/net/ethernet/netlogic/Kconfig new file mode 100644 index 0000000..a6c8a2f --- /dev/null +++ b/drivers/net/ethernet/netlogic/Kconfig @@ -0,0 +1,8 @@ +config NETLOGIC_XLR_NET + tristate "Netlogic XLR/XLS network device" + default y + select PHYLIB + depends on CPU_XLR + ---help--- + This driver support Netlogic XLR/XLS on chip gigabit + Ethernet. diff --git a/drivers/net/ethernet/netlogic/Makefile b/drivers/net/ethernet/netlogic/Makefile new file mode 100644 index 0000000..7fc927a --- /dev/null +++ b/drivers/net/ethernet/netlogic/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_NETLOGIC_XLR_NET) += xlr_net.o diff --git a/drivers/net/ethernet/netlogic/xlr_net.c b/drivers/net/ethernet/netlogic/xlr_net.c new file mode 100644 index 0000000..08ea04a --- /dev/null +++ b/drivers/net/ethernet/netlogic/xlr_net.c @@ -0,0 +1,1109 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "xlr_net.h" + +/* + * The readl/writel implementation byteswaps on XLR/XLS, so + * we need to use __raw_ IO to read the NAE registers + * because they are in the big-endian MMIO area on the SoC. + */ +static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val) +{ + __raw_writel(val, base + reg); +} + +static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg) +{ + return __raw_readl(base + reg); +} + +static inline void xlr_reg_update(u32 *base_addr, + u32 off, u32 val, u32 mask) +{ + u32 tmp; + + tmp = xlr_nae_rdreg(base_addr, off); + xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask)); +} + +/* + * Table of net_device pointers indexed by port, this will be used to + * lookup the net_device corresponding to a port by the message ring handler. + * + * Maximum ports in XLR/XLS is 8(8 GMAC on XLS, 4 GMAC + 2 XGMAC on XLR) + */ +static struct net_device *mac_to_ndev[8]; + +static inline struct sk_buff *mac_get_skb_back_ptr(void *addr) +{ + struct sk_buff **back_ptr; + + /* this function should be used only for newly allocated packets. + * It assumes the first cacheline is for the back pointer related + * book keeping info. + */ + back_ptr = (struct sk_buff **)(addr - MAC_SKB_BACK_PTR_SIZE); + return *back_ptr; +} + +static inline void mac_put_skb_back_ptr(struct sk_buff *skb) +{ + struct sk_buff **back_ptr = (struct sk_buff **)skb->data; + + /* this function should be used only for newly allocated packets. + * It assumes the first cacheline is for the back pointer related + * book keeping info. + */ + skb_reserve(skb, MAC_SKB_BACK_PTR_SIZE); + *back_ptr = skb; +} + +static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr) +{ + struct nlm_fmn_msg msg; + int ret = 0, num_try = 0, stnid; + unsigned long paddr, mflags; + + paddr = virt_to_bus(addr); + msg.msg0 = (u64)paddr & 0xffffffffe0ULL; + msg.msg1 = 0; + msg.msg2 = 0; + msg.msg3 = 0; + stnid = priv->nd->rfr_station; + do { + mflags = nlm_cop2_enable(); + ret = nlm_fmn_send(1, 0, stnid, &msg); + nlm_cop2_restore(mflags); + if (ret == 0) + return 0; + } while (++num_try < 10000); + + pr_err("Send to RFR failed in RX path\n"); + return ret; +} + +static inline struct sk_buff *xlr_alloc_skb(void) +{ + struct sk_buff *skb; + + /* skb->data is cache aligned */ + skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC); + if (!skb) { + pr_err("SKB allocation failed\n"); + return NULL; + } + mac_put_skb_back_ptr(skb); + return skb; +} + +static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, + int code, struct nlm_fmn_msg *msg, void *arg) +{ + struct sk_buff *skb, *skb_new = NULL; + struct net_device *ndev; + struct xlr_net_priv *priv; + u64 length, port; + void *addr; + + length = (msg->msg0 >> 40) & 0x3fff; + if (length == 0) { + addr = bus_to_virt(msg->msg0 & 0xffffffffffULL); + dev_kfree_skb_any(addr); + } else if (length) { + addr = bus_to_virt(msg->msg0 & 0xffffffffe0ULL); + length = length - BYTE_OFFSET - MAC_CRC_LEN; + port = msg->msg0 & 0x0f; + if (src_stnid == FMN_STNID_GMAC1) + port = port + 4; + skb = mac_get_skb_back_ptr(addr); + skb->dev = mac_to_ndev[port]; + ndev = skb->dev; + priv = netdev_priv(ndev); + + /* 16 byte IP header align */ + skb_reserve(skb, BYTE_OFFSET); + skb_put(skb, length); + skb->protocol = eth_type_trans(skb, skb->dev); + skb->dev->last_rx = jiffies; + netif_rx(skb); + /* Fill rx ring */ + skb_new = xlr_alloc_skb(); + if (skb_new) + send_to_rfr_fifo(priv, skb_new->data); + } + return; +} + +/* Ethtool operation */ +static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) +{ + struct xlr_net_priv *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; + + if (!phydev) + return -ENODEV; + return phy_ethtool_gset(phydev, ecmd); +} + +static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) +{ + struct xlr_net_priv *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; + + if (!phydev) + return -ENODEV; + return phy_ethtool_sset(phydev, ecmd); +} + +static struct ethtool_ops xlr_ethtool_ops = { + .get_settings = xlr_get_settings, + .set_settings = xlr_set_settings, +}; + +/* Net operations */ +static int xlr_net_fill_rx_ring(struct net_device *ndev) +{ + struct sk_buff *skb; + struct xlr_net_priv *priv = netdev_priv(ndev); + int i; + + for (i = 0; i < MAX_FRIN_SPILL/2; i++) { + skb = xlr_alloc_skb(); + if (!skb) + return -ENOMEM; + send_to_rfr_fifo(priv, skb->data); + } + pr_info("Rx ring setup done\n"); + return 0; +} + +static int xlr_net_open(struct net_device *ndev) +{ + u32 err; + struct xlr_net_priv *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; + + /* schedule a link state check */ + phy_start(phydev); + + err = phy_start_aneg(phydev); + if (err) { + pr_err("Autoneg failed\n"); + return err; + } + + /* Setup the speed from PHY to internal reg*/ + xlr_set_gmac_speed(priv); + netif_tx_start_all_queues(ndev); + return 0; +} + +static int xlr_net_stop(struct net_device *ndev) +{ + struct xlr_net_priv *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; + + phy_stop(phydev); + netif_tx_stop_all_queues(ndev); + return 0; +} + +static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr, + struct sk_buff *skb) +{ + unsigned long physkb = virt_to_phys(skb); + int cpu_core = nlm_core_id(); + int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */ + msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */ + ((u64)127 << 54) | /* No Free back */ + (u64)skb->len << 40 | /* Length of data */ + ((u64)addr)); + msg->msg1 = (((u64)1 << 63) | + ((u64)fr_stn_id << 54) | /* Free back id */ + (u64)0 << 40 | /* Set len to 0 */ + ((u64)physkb & 0xffffffff)); /* 32bit address */ + msg->msg2 = msg->msg3 = 0; +} + +static void __maybe_unused xlr_wakeup_queue(unsigned long dev) +{ + struct net_device *ndev = (struct net_device *) dev; + struct xlr_net_priv *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; + + if (phydev->link) + netif_tx_wake_queue(netdev_get_tx_queue(ndev, priv->wakeup_q)); +} + +static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb, + struct net_device *ndev) +{ + struct nlm_fmn_msg msg; + struct xlr_net_priv *priv = netdev_priv(ndev); + int ret; + u16 qmap; + u32 flags; + + qmap = skb->queue_mapping; + xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb); + flags = nlm_cop2_enable(); + ret = nlm_fmn_send(2, 0, priv->nd->tx_stnid, &msg); + nlm_cop2_restore(flags); + if (ret) + dev_kfree_skb_any(skb); + return NETDEV_TX_OK; +} + +static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb) +{ + return (u16)smp_processor_id(); +} + +static void xlr_hw_set_mac_addr(struct net_device *ndev) +{ + struct xlr_net_priv *priv = netdev_priv(ndev); + + /* set mac station address */ + xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0, + ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) | + (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2]))); + xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1, + ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16))); + + xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff); + xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff); + xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff); + xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff); + + xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, + (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) | + (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) | + (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID)); + + if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII || + priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII) + xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f); +} + +static int xlr_net_set_mac_addr(struct net_device *ndev, void *data) +{ + int err; + + err = eth_mac_addr(ndev, data); + if (err) + return err; + xlr_hw_set_mac_addr(ndev); + return 0; +} + +static void xlr_set_rx_mode(struct net_device *ndev) +{ + struct xlr_net_priv *priv = netdev_priv(ndev); + u32 regval; + + regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG); + + if (ndev->flags & IFF_PROMISC) { + regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) | + (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) | + (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) | + (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN); + } else { + regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) | + (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN)); + } + + xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval); +} + +static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats) +{ + struct xlr_net_priv *priv = netdev_priv(ndev); + + stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER); + stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER); + stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER); + stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER); + stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER); + stats->rx_dropped = xlr_nae_rdreg(priv->base_addr, + RX_DROP_PACKET_COUNTER); + stats->tx_dropped = xlr_nae_rdreg(priv->base_addr, + TX_DROP_FRAME_COUNTER); + + stats->multicast = xlr_nae_rdreg(priv->base_addr, + RX_MULTICAST_PACKET_COUNTER); + stats->collisions = xlr_nae_rdreg(priv->base_addr, + TX_TOTAL_COLLISION_COUNTER); + + stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr, + RX_FRAME_LENGTH_ERROR_COUNTER); + stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr, + RX_DROP_PACKET_COUNTER); + stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr, + RX_FCS_ERROR_COUNTER); + stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr, + RX_ALIGNMENT_ERROR_COUNTER); + + stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr, + RX_DROP_PACKET_COUNTER); + stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr, + RX_CARRIER_SENSE_ERROR_COUNTER); + + stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors + + stats->rx_frame_errors + stats->rx_fifo_errors + + stats->rx_missed_errors); + + stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr, + TX_EXCESSIVE_COLLISION_PACKET_COUNTER); + stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr, + TX_DROP_FRAME_COUNTER); + stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr, + TX_DROP_FRAME_COUNTER); +} + +static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev, + struct rtnl_link_stats64 *stats) +{ + xlr_stats(ndev, stats); + return stats; +} + +static struct net_device_ops xlr_netdev_ops = { + .ndo_open = xlr_net_open, + .ndo_stop = xlr_net_stop, + .ndo_start_xmit = xlr_net_start_xmit, + .ndo_select_queue = xlr_net_select_queue, + .ndo_set_mac_address = xlr_net_set_mac_addr, + .ndo_set_rx_mode = xlr_set_rx_mode, + .ndo_get_stats64 = xlr_get_stats64, +}; + +/* Gmac init */ +static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0, + int reg_start_1, int reg_size, int size) +{ + void *spill; + u32 *base; + unsigned long phys_addr; + u32 spill_size; + + base = priv->base_addr; + spill_size = size; + spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC); + if (!spill) + pr_err("Unable to allocate memory for spill area!\n"); + + spill = PTR_ALIGN(spill, SMP_CACHE_BYTES); + phys_addr = virt_to_phys(spill); + dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n", + size, phys_addr); + xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff); + xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07); + xlr_nae_wreg(base, reg_size, spill_size); + + return spill; +} + +/* + * Configure the 6 FIFO's that are used by the network accelarator to + * communicate with the rest of the XLx device. 4 of the FIFO's are for + * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding + * the NA with free descriptors. + */ +static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv) +{ + priv->frin_spill = xlr_config_spill(priv, + R_REG_FRIN_SPILL_MEM_START_0, + R_REG_FRIN_SPILL_MEM_START_1, + R_REG_FRIN_SPILL_MEM_SIZE, + MAX_FRIN_SPILL * + sizeof(u64)); + priv->frout_spill = xlr_config_spill(priv, + R_FROUT_SPILL_MEM_START_0, + R_FROUT_SPILL_MEM_START_1, + R_FROUT_SPILL_MEM_SIZE, + MAX_FROUT_SPILL * + sizeof(u64)); + priv->class_0_spill = xlr_config_spill(priv, + R_CLASS0_SPILL_MEM_START_0, + R_CLASS0_SPILL_MEM_START_1, + R_CLASS0_SPILL_MEM_SIZE, + MAX_CLASS_0_SPILL * + sizeof(u64)); + priv->class_1_spill = xlr_config_spill(priv, + R_CLASS1_SPILL_MEM_START_0, + R_CLASS1_SPILL_MEM_START_1, + R_CLASS1_SPILL_MEM_SIZE, + MAX_CLASS_1_SPILL * + sizeof(u64)); + priv->class_2_spill = xlr_config_spill(priv, + R_CLASS2_SPILL_MEM_START_0, + R_CLASS2_SPILL_MEM_START_1, + R_CLASS2_SPILL_MEM_SIZE, + MAX_CLASS_2_SPILL * + sizeof(u64)); + priv->class_3_spill = xlr_config_spill(priv, + R_CLASS3_SPILL_MEM_START_0, + R_CLASS3_SPILL_MEM_START_1, + R_CLASS3_SPILL_MEM_SIZE, + MAX_CLASS_3_SPILL * + sizeof(u64)); +} + +/* Configure PDE to Round-Robin distribution of packets to the + * available cpu */ +static void xlr_config_pde(struct xlr_net_priv *priv) +{ + int i = 0; + u64 bkt_map = 0; + + /* Each core has 8 buckets(station) */ + for (i = 0; i < hweight32(priv->nd->cpu_mask); i++) + bkt_map |= (0xff << (i * 8)); + + xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff)); + xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1, + ((bkt_map >> 32) & 0xffffffff)); + + xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff)); + xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1, + ((bkt_map >> 32) & 0xffffffff)); + + xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff)); + xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1, + ((bkt_map >> 32) & 0xffffffff)); + + xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff)); + xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1, + ((bkt_map >> 32) & 0xffffffff)); +} + +/* Setup the Message ring credits, bucket size and other + * common configuration */ +static void xlr_config_common(struct xlr_net_priv *priv) +{ + struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info; + int start_stn_id = gmac->start_stn_id; + int end_stn_id = gmac->end_stn_id; + int *bucket_size = priv->nd->bucket_size; + int i, j; + + /* Setting non-core MsgBktSize(0x321 - 0x325) */ + for (i = start_stn_id; i <= end_stn_id; i++) { + xlr_nae_wreg(priv->base_addr, + R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id, + bucket_size[i]); + } + + /* Setting non-core Credit counter register + * Distributing Gmac's credit to CPU's*/ + for (i = 0; i < 8; i++) { + for (j = 0; j < 8; j++) + xlr_nae_wreg(priv->base_addr, + (R_CC_CPU0_0 + (i * 8)) + j, + gmac->credit_config[(i * 8) + j]); + } + + xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3); + xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff); + xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff); + xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff); + xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff); + xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0); + + xlr_net_fill_rx_ring(priv->ndev); + nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler, + NULL); +} + +static void xlr_config_translate_table(struct xlr_net_priv *priv) +{ + u32 cpu_mask; + u32 val; + int bkts[32]; /* one bucket is assumed for each cpu */ + int b1, b2, c1, c2, i, j, k; + int use_bkt; + + use_bkt = 0; + cpu_mask = priv->nd->cpu_mask; + + pr_info("Using %s-based distribution\n", + (use_bkt) ? "bucket" : "class"); + j = 0; + for (i = 0; i < 32; i++) { + if ((1 << i) & cpu_mask) { + /* for each cpu, mark the 4+threadid bucket */ + bkts[j] = ((i / 4) * 8) + (i % 4); + j++; + } + } + + /*configure the 128 * 9 Translation table to send to available buckets*/ + k = 0; + c1 = 3; + c2 = 0; + for (i = 0; i < 64; i++) { + /* On use_bkt set the b0, b1 are used, else + * the 4 classes are used, here implemented + * a logic to distribute the packets to the + * buckets equally or based on the class + */ + c1 = (c1 + 1) & 3; + c2 = (c1 + 1) & 3; + b1 = bkts[k]; + k = (k + 1) % j; + b2 = bkts[k]; + k = (k + 1) % j; + val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) | + (c2 << 7) | (b2 << 1) | (use_bkt << 0)); + + val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) | + (c2 << 7) | (b2 << 1) | (use_bkt << 0)); + dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n", + i, b1, b2, c1, c2); + xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val); + c1 = c2; + } +} + +static void xlr_config_parser(struct xlr_net_priv *priv) +{ + u32 val; + + /* Mark it as ETHERNET type */ + xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01); + + /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/ + xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG, + ((0x7f << 8) | (1 << 1))); + + /* configure the parser : L2 Type is configured in the bootloader */ + /* extract IP: src, dest protocol */ + xlr_nae_wreg(priv->base_addr, R_L3CTABLE, + (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) | + (0x0800 << 0)); + xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1, + (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) | + (16 << 4) | 4); + + /* Configure to extract SRC port and Dest port for TCP and UDP pkts */ + xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6); + xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17); + val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7)); + xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val); + xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val); + + xlr_config_translate_table(priv); +} + +static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val) +{ + unsigned long timeout, stoptime, checktime; + int timedout; + + /* 100ms timeout*/ + timeout = msecs_to_jiffies(100); + stoptime = jiffies + timeout; + timedout = 0; + + xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum); + + /* Write the data which starts the write cycle */ + xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32) val); + + /* poll for the read cycle to complete */ + while (!timedout) { + checktime = jiffies; + if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0) + break; + timedout = time_after(checktime, stoptime); + } + if (timedout) { + pr_info("Phy device write err: device busy"); + return -EBUSY; + } + + return 0; +} + +static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum) +{ + unsigned long timeout, stoptime, checktime; + int timedout; + + /* 100ms timeout*/ + timeout = msecs_to_jiffies(100); + stoptime = jiffies + timeout; + timedout = 0; + + /* setup the phy reg to be used */ + xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, + (phy_addr << 8) | (regnum << 0)); + + /* Issue the read command */ + xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, + (1 << O_MII_MGMT_COMMAND__rstat)); + + + /* poll for the read cycle to complete */ + while (!timedout) { + checktime = jiffies; + if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0) + break; + timedout = time_after(checktime, stoptime); + } + if (timedout) { + pr_info("Phy device read err: device busy"); + return -EBUSY; + } + + /* clear the read cycle */ + xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0); + + /* Read the data */ + return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS); +} + +static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val) +{ + struct xlr_net_priv *priv = bus->priv; + int ret; + + ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val); + dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n", + phy_addr, regnum, val, ret); + return ret; +} + +static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum) +{ + struct xlr_net_priv *priv = bus->priv; + int ret; + + ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum); + dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n", + phy_addr, regnum, ret); + return ret; +} + +/* XLR ports are RGMII. XLS ports are SGMII mostly except the port0, + * which can be configured either SGMII or RGMII, considered SGMII + * by default, if board setup to RGMII the port_type need to set + * accordingly.Serdes and PCS layer need to configured for SGMII + */ +static void xlr_sgmii_init(struct xlr_net_priv *priv) +{ + int phy; + + xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0); + xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF); + xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0); + xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF); + xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000); + xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000); + xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005); + xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001); + xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000); + xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000); + xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000); + + /* program GPIO values for serdes init parameters */ + xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802); + xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104); + + xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802); + xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104); + + /* enable autoneg - more magic */ + phy = priv->port_id % 4 + 27; + xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000); + xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200); +} + +void xlr_set_gmac_speed(struct xlr_net_priv *priv) +{ + struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; + int speed; + + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) + xlr_sgmii_init(priv); + + if (phydev->speed != priv->phy_speed) { + pr_info("change %d to %d\n", priv->phy_speed, phydev->speed); + speed = phydev->speed; + if (speed == SPEED_1000) { + /* Set interface to Byte mode */ + xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217); + priv->phy_speed = speed; + } else if (speed == SPEED_100 || speed == SPEED_10) { + /* Set interface to Nibble mode */ + xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117); + priv->phy_speed = speed; + } + /* Set SGMII speed in Interface controll reg */ + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + if (speed == SPEED_10) + xlr_nae_wreg(priv->base_addr, + R_INTERFACE_CONTROL, SGMII_SPEED_10); + if (speed == SPEED_100) + xlr_nae_wreg(priv->base_addr, + R_INTERFACE_CONTROL, SGMII_SPEED_100); + if (speed == SPEED_1000) + xlr_nae_wreg(priv->base_addr, + R_INTERFACE_CONTROL, SGMII_SPEED_1000); + } + if (speed == SPEED_10) + xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2); + if (speed == SPEED_100) + xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1); + if (speed == SPEED_1000) + xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0); + } + pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed); +} + +static void xlr_gmac_link_adjust(struct net_device *ndev) +{ + struct xlr_net_priv *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; + u32 intreg; + + intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG); + if (phydev->link) { + if (phydev->speed != priv->phy_speed) { + pr_info("gmac%d : Link up\n", priv->port_id); + xlr_set_gmac_speed(priv); + } + } else { + pr_info("gmac%d : Link down\n", priv->port_id); + xlr_set_gmac_speed(priv); + } +} + +static int xlr_mii_probe(struct xlr_net_priv *priv) +{ + struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; + + if (!phydev) { + pr_err("no PHY found on phy_addr %d\n", priv->phy_addr); + return -ENODEV; + } + + /* Attach MAC to PHY */ + phydev = phy_connect(priv->ndev, dev_name(&phydev->dev), + &xlr_gmac_link_adjust, 0, priv->nd->phy_interface); + + if (IS_ERR(phydev)) { + pr_err("could not attach PHY\n"); + return PTR_ERR(phydev); + } + phydev->supported &= (ADVERTISED_10baseT_Full + | ADVERTISED_10baseT_Half + | ADVERTISED_100baseT_Full + | ADVERTISED_100baseT_Half + | ADVERTISED_1000baseT_Full + | ADVERTISED_Autoneg + | ADVERTISED_MII); + + phydev->advertising = phydev->supported; + pr_info("attached PHY driver [%s] (mii_bus:phy_addr=%s\n", + phydev->drv->name, dev_name(&phydev->dev)); + return 0; +} + +static int xlr_setup_mdio(struct xlr_net_priv *priv, + struct platform_device *pdev) +{ + int err; + + priv->phy_addr = priv->nd->phy_addr; + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { + pr_err("mdiobus alloc failed\n"); + return -ENOMEM; + } + + priv->mii_bus->priv = priv; + priv->mii_bus->name = "xlr-mdio"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", + priv->mii_bus->name, priv->port_id); + priv->mii_bus->read = xlr_mii_read; + priv->mii_bus->write = xlr_mii_write; + priv->mii_bus->parent = &pdev->dev; + priv->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); + priv->mii_bus->irq[priv->phy_addr] = priv->ndev->irq; + + /* Scan only the enabled address */ + priv->mii_bus->phy_mask = ~(1 << priv->phy_addr); + + /* setting clock divisor to 54 */ + xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7); + + err = mdiobus_register(priv->mii_bus); + if (err) { + mdiobus_free(priv->mii_bus); + pr_err("mdio bus registration failed\n"); + return err; + } + + pr_info("Registerd mdio bus id : %s\n", priv->mii_bus->id); + err = xlr_mii_probe(priv); + if (err) { + mdiobus_free(priv->mii_bus); + return err; + } + return 0; +} + +static void xlr_port_enable(struct xlr_net_priv *priv) +{ + /* Setup MAC_CONFIG reg */ + if (nlm_chip_is_xls() && + priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII) + xlr_reg_update(priv->base_addr, R_RX_CONTROL, + (1 << O_RX_CONTROL__RGMII), (1 << O_RX_CONTROL__RGMII)); + + /* Rx Tx enable */ + xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1, + ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) | + (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)), + ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) | + (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc))); + + /* Setup tx control reg */ + xlr_reg_update(priv->base_addr, R_TX_CONTROL, + ((1 << O_TX_CONTROL__TxEnable) | + (512 << O_TX_CONTROL__TxThreshold)), 0x3fff); + + /* Setup rx control reg */ + xlr_reg_update(priv->base_addr, R_RX_CONTROL, + 1 << O_RX_CONTROL__RxEnable, 1 << O_RX_CONTROL__RxEnable); +} + +static void xlr_port_disable(struct xlr_net_priv *priv) +{ + /* Setup MAC_CONFIG reg */ + /* Rx Tx disable*/ + xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1, + ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) | + (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)), + 0x0); + + /* Setup tx control reg */ + xlr_reg_update(priv->base_addr, R_TX_CONTROL, + ((1 << O_TX_CONTROL__TxEnable) | + (512 << O_TX_CONTROL__TxThreshold)), 0); + + /* Setup rx control reg */ + xlr_reg_update(priv->base_addr, R_RX_CONTROL, + 1 << O_RX_CONTROL__RxEnable, 0); +} + +/* Initialization of gmac */ +static int xlr_gmac_init(struct xlr_net_priv *priv, + struct platform_device *pdev) +{ + int ret; + + pr_info("Initializing the gmac%d\n", priv->port_id); + + xlr_port_disable(priv); + xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL, + (1 << O_DESC_PACK_CTRL__MaxEntry) + | (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset) + | (1600 << O_DESC_PACK_CTRL__RegularSize)); + + ret = xlr_setup_mdio(priv, pdev); + if (ret) + return ret; + xlr_port_enable(priv); + + /* Enable Full-duplex/1000Mbps/CRC */ + xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217); + /* speed 2.5Mhz */ + xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02); + /* Setup Interrupt mask reg */ + xlr_nae_wreg(priv->base_addr, R_INTMASK, + (1 << O_INTMASK__TxIllegal) | + (1 << O_INTMASK__MDInt) | + (1 << O_INTMASK__TxFetchError) | + (1 << O_INTMASK__P2PSpillEcc) | + (1 << O_INTMASK__TagFull) | + (1 << O_INTMASK__Underrun) | + (1 << O_INTMASK__Abort) + ); + + /* Clear all stats */ + xlr_reg_update(priv->base_addr, R_STATCTRL, + 0, 1 << O_STATCTRL__ClrCnt); + xlr_reg_update(priv->base_addr, R_STATCTRL, + 1 << O_STATCTRL__ClrCnt, 1 << O_STATCTRL__ClrCnt); + return 0; +} + +static int xlr_net_probe(struct platform_device *pdev) +{ + struct xlr_net_priv *priv = NULL; + struct net_device *ndev; + struct resource *res; + int mac, err; + + mac = pdev->id; + ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32); + if (!ndev) { + pr_err("Allocation of Ethernet device failed\n"); + return -ENOMEM; + } + + priv = netdev_priv(ndev); + priv->pdev = pdev; + priv->ndev = ndev; + priv->port_id = mac; + priv->nd = (struct xlr_net_data *)pdev->dev.platform_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + pr_err("No memory resource for MAC %d\n", mac); + err = -ENODEV; + goto err_gmac; + } + + ndev->base_addr = (unsigned long) devm_request_and_ioremap + (&pdev->dev, res); + if (!ndev->base_addr) { + dev_err(&pdev->dev, + "devm_request_and_ioremap failed\n"); + return -EBUSY; + } + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + pr_err("No irq resource for MAC %d\n", mac); + err = -ENODEV; + goto err_gmac; + } + ndev->irq = res->start; + + priv->mii_addr = priv->nd->mii_addr; + priv->serdes_addr = priv->nd->serdes_addr; + priv->pcs_addr = priv->nd->pcs_addr; + priv->gpio_addr = priv->nd->gpio_addr; + priv->base_addr = (u32 *) ndev->base_addr; + + mac_to_ndev[mac] = ndev; + ndev->netdev_ops = &xlr_netdev_ops; + ndev->watchdog_timeo = HZ; + + /* Setup Mac address and Rx mode */ + eth_hw_addr_random(ndev); + xlr_hw_set_mac_addr(ndev); + xlr_set_rx_mode(ndev); + + priv->num_rx_desc += MAX_NUM_DESC_SPILL; + SET_ETHTOOL_OPS(ndev, &xlr_ethtool_ops); + SET_NETDEV_DEV(ndev, &pdev->dev); + + /* Common registers, do one time initialization */ + if (mac == 0 || mac == 4) { + xlr_config_fifo_spill_area(priv); + /* Configure PDE to Round-Robin pkt distribution */ + xlr_config_pde(priv); + xlr_config_parser(priv); + } + /* Call init with respect to port */ + if (strcmp(res->name, "gmac") == 0) { + err = xlr_gmac_init(priv, pdev); + if (err) { + pr_err("gmac%d init failed\n", mac); + goto err_gmac; + } + } + + if (mac == 0 || mac == 4) + xlr_config_common(priv); + + err = register_netdev(ndev); + if (err) + goto err_netdev; + platform_set_drvdata(pdev, priv); + return 0; + +err_netdev: + mdiobus_free(priv->mii_bus); +err_gmac: + free_netdev(ndev); + return err; +} + +static int xlr_net_remove(struct platform_device *pdev) +{ + struct xlr_net_priv *priv = platform_get_drvdata(pdev); + unregister_netdev(priv->ndev); + mdiobus_unregister(priv->mii_bus); + mdiobus_free(priv->mii_bus); + free_netdev(priv->ndev); + return 0; +} + +static struct platform_driver xlr_net_driver = { + .probe = xlr_net_probe, + .remove = xlr_net_remove, + .driver = { + .name = "xlr-net", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(xlr_net_driver); + +MODULE_AUTHOR("Ganesan Ramalingam "); +MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_ALIAS("platform:xlr-net"); diff --git a/drivers/net/ethernet/netlogic/xlr_net.h b/drivers/net/ethernet/netlogic/xlr_net.h new file mode 100644 index 0000000..f91d27e --- /dev/null +++ b/drivers/net/ethernet/netlogic/xlr_net.h @@ -0,0 +1,1099 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* #define MAC_SPLIT_MODE */ + +#define MAC_SPACING 0x400 +#define XGMAC_SPACING 0x400 + +/* PE-MCXMAC register and bit field definitions */ +#define R_MAC_CONFIG_1 0x00 +#define O_MAC_CONFIG_1__srst 31 +#define O_MAC_CONFIG_1__simr 30 +#define O_MAC_CONFIG_1__hrrmc 18 +#define W_MAC_CONFIG_1__hrtmc 2 +#define O_MAC_CONFIG_1__hrrfn 16 +#define W_MAC_CONFIG_1__hrtfn 2 +#define O_MAC_CONFIG_1__intlb 8 +#define O_MAC_CONFIG_1__rxfc 5 +#define O_MAC_CONFIG_1__txfc 4 +#define O_MAC_CONFIG_1__srxen 3 +#define O_MAC_CONFIG_1__rxen 2 +#define O_MAC_CONFIG_1__stxen 1 +#define O_MAC_CONFIG_1__txen 0 +#define R_MAC_CONFIG_2 0x01 +#define O_MAC_CONFIG_2__prlen 12 +#define W_MAC_CONFIG_2__prlen 4 +#define O_MAC_CONFIG_2__speed 8 +#define W_MAC_CONFIG_2__speed 2 +#define O_MAC_CONFIG_2__hugen 5 +#define O_MAC_CONFIG_2__flchk 4 +#define O_MAC_CONFIG_2__crce 1 +#define O_MAC_CONFIG_2__fulld 0 +#define R_IPG_IFG 0x02 +#define O_IPG_IFG__ipgr1 24 +#define W_IPG_IFG__ipgr1 7 +#define O_IPG_IFG__ipgr2 16 +#define W_IPG_IFG__ipgr2 7 +#define O_IPG_IFG__mifg 8 +#define W_IPG_IFG__mifg 8 +#define O_IPG_IFG__ipgt 0 +#define W_IPG_IFG__ipgt 7 +#define R_HALF_DUPLEX 0x03 +#define O_HALF_DUPLEX__abebt 24 +#define W_HALF_DUPLEX__abebt 4 +#define O_HALF_DUPLEX__abebe 19 +#define O_HALF_DUPLEX__bpnb 18 +#define O_HALF_DUPLEX__nobo 17 +#define O_HALF_DUPLEX__edxsdfr 16 +#define O_HALF_DUPLEX__retry 12 +#define W_HALF_DUPLEX__retry 4 +#define O_HALF_DUPLEX__lcol 0 +#define W_HALF_DUPLEX__lcol 10 +#define R_MAXIMUM_FRAME_LENGTH 0x04 +#define O_MAXIMUM_FRAME_LENGTH__maxf 0 +#define W_MAXIMUM_FRAME_LENGTH__maxf 16 +#define R_TEST 0x07 +#define O_TEST__mbof 3 +#define O_TEST__rthdf 2 +#define O_TEST__tpause 1 +#define O_TEST__sstct 0 +#define R_MII_MGMT_CONFIG 0x08 +#define O_MII_MGMT_CONFIG__scinc 5 +#define O_MII_MGMT_CONFIG__spre 4 +#define O_MII_MGMT_CONFIG__clks 3 +#define W_MII_MGMT_CONFIG__clks 3 +#define R_MII_MGMT_COMMAND 0x09 +#define O_MII_MGMT_COMMAND__scan 1 +#define O_MII_MGMT_COMMAND__rstat 0 +#define R_MII_MGMT_ADDRESS 0x0A +#define O_MII_MGMT_ADDRESS__fiad 8 +#define W_MII_MGMT_ADDRESS__fiad 5 +#define O_MII_MGMT_ADDRESS__fgad 5 +#define W_MII_MGMT_ADDRESS__fgad 0 +#define R_MII_MGMT_WRITE_DATA 0x0B +#define O_MII_MGMT_WRITE_DATA__ctld 0 +#define W_MII_MGMT_WRITE_DATA__ctld 16 +#define R_MII_MGMT_STATUS 0x0C +#define R_MII_MGMT_INDICATORS 0x0D +#define O_MII_MGMT_INDICATORS__nvalid 2 +#define O_MII_MGMT_INDICATORS__scan 1 +#define O_MII_MGMT_INDICATORS__busy 0 +#define R_INTERFACE_CONTROL 0x0E +#define O_INTERFACE_CONTROL__hrstint 31 +#define O_INTERFACE_CONTROL__tbimode 27 +#define O_INTERFACE_CONTROL__ghdmode 26 +#define O_INTERFACE_CONTROL__lhdmode 25 +#define O_INTERFACE_CONTROL__phymod 24 +#define O_INTERFACE_CONTROL__hrrmi 23 +#define O_INTERFACE_CONTROL__rspd 16 +#define O_INTERFACE_CONTROL__hr100 15 +#define O_INTERFACE_CONTROL__frcq 10 +#define O_INTERFACE_CONTROL__nocfr 9 +#define O_INTERFACE_CONTROL__dlfct 8 +#define O_INTERFACE_CONTROL__enjab 0 +#define R_INTERFACE_STATUS 0x0F +#define O_INTERFACE_STATUS__xsdfr 9 +#define O_INTERFACE_STATUS__ssrr 8 +#define W_INTERFACE_STATUS__ssrr 5 +#define O_INTERFACE_STATUS__miilf 3 +#define O_INTERFACE_STATUS__locar 2 +#define O_INTERFACE_STATUS__sqerr 1 +#define O_INTERFACE_STATUS__jabber 0 +#define R_STATION_ADDRESS_LS 0x10 +#define R_STATION_ADDRESS_MS 0x11 + +/* A-XGMAC register and bit field definitions */ +#define R_XGMAC_CONFIG_0 0x00 +#define O_XGMAC_CONFIG_0__hstmacrst 31 +#define O_XGMAC_CONFIG_0__hstrstrctl 23 +#define O_XGMAC_CONFIG_0__hstrstrfn 22 +#define O_XGMAC_CONFIG_0__hstrsttctl 18 +#define O_XGMAC_CONFIG_0__hstrsttfn 17 +#define O_XGMAC_CONFIG_0__hstrstmiim 16 +#define O_XGMAC_CONFIG_0__hstloopback 8 +#define R_XGMAC_CONFIG_1 0x01 +#define O_XGMAC_CONFIG_1__hsttctlen 31 +#define O_XGMAC_CONFIG_1__hsttfen 30 +#define O_XGMAC_CONFIG_1__hstrctlen 29 +#define O_XGMAC_CONFIG_1__hstrfen 28 +#define O_XGMAC_CONFIG_1__tfen 26 +#define O_XGMAC_CONFIG_1__rfen 24 +#define O_XGMAC_CONFIG_1__hstrctlshrtp 12 +#define O_XGMAC_CONFIG_1__hstdlyfcstx 10 +#define W_XGMAC_CONFIG_1__hstdlyfcstx 2 +#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8 +#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2 +#define O_XGMAC_CONFIG_1__hstppen 7 +#define O_XGMAC_CONFIG_1__hstbytswp 6 +#define O_XGMAC_CONFIG_1__hstdrplt64 5 +#define O_XGMAC_CONFIG_1__hstprmscrx 4 +#define O_XGMAC_CONFIG_1__hstlenchk 3 +#define O_XGMAC_CONFIG_1__hstgenfcs 2 +#define O_XGMAC_CONFIG_1__hstpadmode 0 +#define W_XGMAC_CONFIG_1__hstpadmode 2 +#define R_XGMAC_CONFIG_2 0x02 +#define O_XGMAC_CONFIG_2__hsttctlfrcp 31 +#define O_XGMAC_CONFIG_2__hstmlnkflth 27 +#define O_XGMAC_CONFIG_2__hstalnkflth 26 +#define O_XGMAC_CONFIG_2__rflnkflt 24 +#define W_XGMAC_CONFIG_2__rflnkflt 2 +#define O_XGMAC_CONFIG_2__hstipgextmod 16 +#define W_XGMAC_CONFIG_2__hstipgextmod 5 +#define O_XGMAC_CONFIG_2__hstrctlfrcp 15 +#define O_XGMAC_CONFIG_2__hstipgexten 5 +#define O_XGMAC_CONFIG_2__hstmipgext 0 +#define W_XGMAC_CONFIG_2__hstmipgext 5 +#define R_XGMAC_CONFIG_3 0x03 +#define O_XGMAC_CONFIG_3__hstfltrfrm 31 +#define W_XGMAC_CONFIG_3__hstfltrfrm 16 +#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15 +#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16 +#define R_XGMAC_STATION_ADDRESS_LS 0x04 +#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0 +#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32 +#define R_XGMAC_STATION_ADDRESS_MS 0x05 +#define R_XGMAC_MAX_FRAME_LEN 0x08 +#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16 +#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14 +#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0 +#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16 +#define R_XGMAC_REV_LEVEL 0x0B +#define O_XGMAC_REV_LEVEL__revlvl 0 +#define W_XGMAC_REV_LEVEL__revlvl 15 +#define R_XGMAC_MIIM_COMMAND 0x10 +#define O_XGMAC_MIIM_COMMAND__hstldcmd 3 +#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0 +#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3 +#define R_XGMAC_MIIM_FILED 0x11 +#define O_XGMAC_MIIM_FILED__hststfield 30 +#define W_XGMAC_MIIM_FILED__hststfield 2 +#define O_XGMAC_MIIM_FILED__hstopfield 28 +#define W_XGMAC_MIIM_FILED__hstopfield 2 +#define O_XGMAC_MIIM_FILED__hstphyadx 23 +#define W_XGMAC_MIIM_FILED__hstphyadx 5 +#define O_XGMAC_MIIM_FILED__hstregadx 18 +#define W_XGMAC_MIIM_FILED__hstregadx 5 +#define O_XGMAC_MIIM_FILED__hsttafield 16 +#define W_XGMAC_MIIM_FILED__hsttafield 2 +#define O_XGMAC_MIIM_FILED__miimrddat 0 +#define W_XGMAC_MIIM_FILED__miimrddat 16 +#define R_XGMAC_MIIM_CONFIG 0x12 +#define O_XGMAC_MIIM_CONFIG__hstnopram 7 +#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0 +#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7 +#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13 +#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0 +#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32 +#define R_XGMAC_MIIM_INDICATOR 0x14 +#define O_XGMAC_MIIM_INDICATOR__miimphylf 4 +#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3 +#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2 +#define O_XGMAC_MIIM_INDICATOR__miimmon 1 +#define O_XGMAC_MIIM_INDICATOR__miimbusy 0 + +/* GMAC stats registers */ +#define R_RBYT 0x27 +#define R_RPKT 0x28 +#define R_RFCS 0x29 +#define R_RMCA 0x2A +#define R_RBCA 0x2B +#define R_RXCF 0x2C +#define R_RXPF 0x2D +#define R_RXUO 0x2E +#define R_RALN 0x2F +#define R_RFLR 0x30 +#define R_RCDE 0x31 +#define R_RCSE 0x32 +#define R_RUND 0x33 +#define R_ROVR 0x34 +#define R_TBYT 0x38 +#define R_TPKT 0x39 +#define R_TMCA 0x3A +#define R_TBCA 0x3B +#define R_TXPF 0x3C +#define R_TDFR 0x3D +#define R_TEDF 0x3E +#define R_TSCL 0x3F +#define R_TMCL 0x40 +#define R_TLCL 0x41 +#define R_TXCL 0x42 +#define R_TNCL 0x43 +#define R_TJBR 0x46 +#define R_TFCS 0x47 +#define R_TXCF 0x48 +#define R_TOVR 0x49 +#define R_TUND 0x4A +#define R_TFRG 0x4B + +/* Glue logic register and bit field definitions */ +#define R_MAC_ADDR0 0x50 +#define R_MAC_ADDR1 0x52 +#define R_MAC_ADDR2 0x54 +#define R_MAC_ADDR3 0x56 +#define R_MAC_ADDR_MASK2 0x58 +#define R_MAC_ADDR_MASK3 0x5A +#define R_MAC_FILTER_CONFIG 0x5C +#define O_MAC_FILTER_CONFIG__BROADCAST_EN 10 +#define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9 +#define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8 +#define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7 +#define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6 +#define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5 +#define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4 +#define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3 +#define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2 +#define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1 +#define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0 +#define R_HASH_TABLE_VECTOR 0x30 +#define R_TX_CONTROL 0x0A0 +#define O_TX_CONTROL__Tx15Halt 31 +#define O_TX_CONTROL__Tx14Halt 30 +#define O_TX_CONTROL__Tx13Halt 29 +#define O_TX_CONTROL__Tx12Halt 28 +#define O_TX_CONTROL__Tx11Halt 27 +#define O_TX_CONTROL__Tx10Halt 26 +#define O_TX_CONTROL__Tx9Halt 25 +#define O_TX_CONTROL__Tx8Halt 24 +#define O_TX_CONTROL__Tx7Halt 23 +#define O_TX_CONTROL__Tx6Halt 22 +#define O_TX_CONTROL__Tx5Halt 21 +#define O_TX_CONTROL__Tx4Halt 20 +#define O_TX_CONTROL__Tx3Halt 19 +#define O_TX_CONTROL__Tx2Halt 18 +#define O_TX_CONTROL__Tx1Halt 17 +#define O_TX_CONTROL__Tx0Halt 16 +#define O_TX_CONTROL__TxIdle 15 +#define O_TX_CONTROL__TxEnable 14 +#define O_TX_CONTROL__TxThreshold 0 +#define W_TX_CONTROL__TxThreshold 14 +#define R_RX_CONTROL 0x0A1 +#define O_RX_CONTROL__RGMII 10 +#define O_RX_CONTROL__SoftReset 2 +#define O_RX_CONTROL__RxHalt 1 +#define O_RX_CONTROL__RxEnable 0 +#define R_DESC_PACK_CTRL 0x0A2 +#define O_DESC_PACK_CTRL__ByteOffset 17 +#define W_DESC_PACK_CTRL__ByteOffset 3 +#define O_DESC_PACK_CTRL__PrePadEnable 16 +#define O_DESC_PACK_CTRL__MaxEntry 14 +#define W_DESC_PACK_CTRL__MaxEntry 2 +#define O_DESC_PACK_CTRL__RegularSize 0 +#define W_DESC_PACK_CTRL__RegularSize 14 +#define R_STATCTRL 0x0A3 +#define O_STATCTRL__OverFlowEn 4 +#define O_STATCTRL__GIG 3 +#define O_STATCTRL__Sten 2 +#define O_STATCTRL__ClrCnt 1 +#define O_STATCTRL__AutoZ 0 +#define R_L2ALLOCCTRL 0x0A4 +#define O_L2ALLOCCTRL__TxL2Allocate 9 +#define W_L2ALLOCCTRL__TxL2Allocate 9 +#define O_L2ALLOCCTRL__RxL2Allocate 0 +#define W_L2ALLOCCTRL__RxL2Allocate 9 +#define R_INTMASK 0x0A5 +#define O_INTMASK__Spi4TxError 28 +#define O_INTMASK__Spi4RxError 27 +#define O_INTMASK__RGMIIHalfDupCollision 27 +#define O_INTMASK__Abort 26 +#define O_INTMASK__Underrun 25 +#define O_INTMASK__DiscardPacket 24 +#define O_INTMASK__AsyncFifoFull 23 +#define O_INTMASK__TagFull 22 +#define O_INTMASK__Class3Full 21 +#define O_INTMASK__C3EarlyFull 20 +#define O_INTMASK__Class2Full 19 +#define O_INTMASK__C2EarlyFull 18 +#define O_INTMASK__Class1Full 17 +#define O_INTMASK__C1EarlyFull 16 +#define O_INTMASK__Class0Full 15 +#define O_INTMASK__C0EarlyFull 14 +#define O_INTMASK__RxDataFull 13 +#define O_INTMASK__RxEarlyFull 12 +#define O_INTMASK__RFreeEmpty 9 +#define O_INTMASK__RFEarlyEmpty 8 +#define O_INTMASK__P2PSpillEcc 7 +#define O_INTMASK__FreeDescFull 5 +#define O_INTMASK__FreeEarlyFull 4 +#define O_INTMASK__TxFetchError 3 +#define O_INTMASK__StatCarry 2 +#define O_INTMASK__MDInt 1 +#define O_INTMASK__TxIllegal 0 +#define R_INTREG 0x0A6 +#define O_INTREG__Spi4TxError 28 +#define O_INTREG__Spi4RxError 27 +#define O_INTREG__RGMIIHalfDupCollision 27 +#define O_INTREG__Abort 26 +#define O_INTREG__Underrun 25 +#define O_INTREG__DiscardPacket 24 +#define O_INTREG__AsyncFifoFull 23 +#define O_INTREG__TagFull 22 +#define O_INTREG__Class3Full 21 +#define O_INTREG__C3EarlyFull 20 +#define O_INTREG__Class2Full 19 +#define O_INTREG__C2EarlyFull 18 +#define O_INTREG__Class1Full 17 +#define O_INTREG__C1EarlyFull 16 +#define O_INTREG__Class0Full 15 +#define O_INTREG__C0EarlyFull 14 +#define O_INTREG__RxDataFull 13 +#define O_INTREG__RxEarlyFull 12 +#define O_INTREG__RFreeEmpty 9 +#define O_INTREG__RFEarlyEmpty 8 +#define O_INTREG__P2PSpillEcc 7 +#define O_INTREG__FreeDescFull 5 +#define O_INTREG__FreeEarlyFull 4 +#define O_INTREG__TxFetchError 3 +#define O_INTREG__StatCarry 2 +#define O_INTREG__MDInt 1 +#define O_INTREG__TxIllegal 0 +#define R_TXRETRY 0x0A7 +#define O_TXRETRY__CollisionRetry 6 +#define O_TXRETRY__BusErrorRetry 5 +#define O_TXRETRY__UnderRunRetry 4 +#define O_TXRETRY__Retries 0 +#define W_TXRETRY__Retries 4 +#define R_CORECONTROL 0x0A8 +#define O_CORECONTROL__ErrorThread 4 +#define W_CORECONTROL__ErrorThread 7 +#define O_CORECONTROL__Shutdown 2 +#define O_CORECONTROL__Speed 0 +#define W_CORECONTROL__Speed 2 +#define R_BYTEOFFSET0 0x0A9 +#define R_BYTEOFFSET1 0x0AA +#define R_L2TYPE_0 0x0F0 +#define O_L2TYPE__ExtraHdrProtoSize 26 +#define W_L2TYPE__ExtraHdrProtoSize 5 +#define O_L2TYPE__ExtraHdrProtoOffset 20 +#define W_L2TYPE__ExtraHdrProtoOffset 6 +#define O_L2TYPE__ExtraHeaderSize 14 +#define W_L2TYPE__ExtraHeaderSize 6 +#define O_L2TYPE__ProtoOffset 8 +#define W_L2TYPE__ProtoOffset 6 +#define O_L2TYPE__L2HdrOffset 2 +#define W_L2TYPE__L2HdrOffset 6 +#define O_L2TYPE__L2Proto 0 +#define W_L2TYPE__L2Proto 2 +#define R_L2TYPE_1 0xF0 +#define R_L2TYPE_2 0xF0 +#define R_L2TYPE_3 0xF0 +#define R_PARSERCONFIGREG 0x100 +#define O_PARSERCONFIGREG__CRCHashPoly 8 +#define W_PARSERCONFIGREG__CRCHashPoly 7 +#define O_PARSERCONFIGREG__PrePadOffset 4 +#define W_PARSERCONFIGREG__PrePadOffset 4 +#define O_PARSERCONFIGREG__UseCAM 2 +#define O_PARSERCONFIGREG__UseHASH 1 +#define O_PARSERCONFIGREG__UseProto 0 +#define R_L3CTABLE 0x140 +#define O_L3CTABLE__Offset0 25 +#define W_L3CTABLE__Offset0 7 +#define O_L3CTABLE__Len0 21 +#define W_L3CTABLE__Len0 4 +#define O_L3CTABLE__Offset1 14 +#define W_L3CTABLE__Offset1 7 +#define O_L3CTABLE__Len1 10 +#define W_L3CTABLE__Len1 4 +#define O_L3CTABLE__Offset2 4 +#define W_L3CTABLE__Offset2 6 +#define O_L3CTABLE__Len2 0 +#define W_L3CTABLE__Len2 4 +#define O_L3CTABLE__L3HdrOffset 26 +#define W_L3CTABLE__L3HdrOffset 6 +#define O_L3CTABLE__L4ProtoOffset 20 +#define W_L3CTABLE__L4ProtoOffset 6 +#define O_L3CTABLE__IPChksumCompute 19 +#define O_L3CTABLE__L4Classify 18 +#define O_L3CTABLE__L2Proto 16 +#define W_L3CTABLE__L2Proto 2 +#define O_L3CTABLE__L3ProtoKey 0 +#define W_L3CTABLE__L3ProtoKey 16 +#define R_L4CTABLE 0x160 +#define O_L4CTABLE__Offset0 21 +#define W_L4CTABLE__Offset0 6 +#define O_L4CTABLE__Len0 17 +#define W_L4CTABLE__Len0 4 +#define O_L4CTABLE__Offset1 11 +#define W_L4CTABLE__Offset1 6 +#define O_L4CTABLE__Len1 7 +#define W_L4CTABLE__Len1 4 +#define O_L4CTABLE__TCPChksumEnable 0 +#define R_CAM4X128TABLE 0x172 +#define O_CAM4X128TABLE__ClassId 7 +#define W_CAM4X128TABLE__ClassId 2 +#define O_CAM4X128TABLE__BucketId 1 +#define W_CAM4X128TABLE__BucketId 6 +#define O_CAM4X128TABLE__UseBucket 0 +#define R_CAM4X128KEY 0x180 +#define R_TRANSLATETABLE 0x1A0 +#define R_DMACR0 0x200 +#define O_DMACR0__Data0WrMaxCr 27 +#define W_DMACR0__Data0WrMaxCr 3 +#define O_DMACR0__Data0RdMaxCr 24 +#define W_DMACR0__Data0RdMaxCr 3 +#define O_DMACR0__Data1WrMaxCr 21 +#define W_DMACR0__Data1WrMaxCr 3 +#define O_DMACR0__Data1RdMaxCr 18 +#define W_DMACR0__Data1RdMaxCr 3 +#define O_DMACR0__Data2WrMaxCr 15 +#define W_DMACR0__Data2WrMaxCr 3 +#define O_DMACR0__Data2RdMaxCr 12 +#define W_DMACR0__Data2RdMaxCr 3 +#define O_DMACR0__Data3WrMaxCr 9 +#define W_DMACR0__Data3WrMaxCr 3 +#define O_DMACR0__Data3RdMaxCr 6 +#define W_DMACR0__Data3RdMaxCr 3 +#define O_DMACR0__Data4WrMaxCr 3 +#define W_DMACR0__Data4WrMaxCr 3 +#define O_DMACR0__Data4RdMaxCr 0 +#define W_DMACR0__Data4RdMaxCr 3 +#define R_DMACR1 0x201 +#define O_DMACR1__Data5WrMaxCr 27 +#define W_DMACR1__Data5WrMaxCr 3 +#define O_DMACR1__Data5RdMaxCr 24 +#define W_DMACR1__Data5RdMaxCr 3 +#define O_DMACR1__Data6WrMaxCr 21 +#define W_DMACR1__Data6WrMaxCr 3 +#define O_DMACR1__Data6RdMaxCr 18 +#define W_DMACR1__Data6RdMaxCr 3 +#define O_DMACR1__Data7WrMaxCr 15 +#define W_DMACR1__Data7WrMaxCr 3 +#define O_DMACR1__Data7RdMaxCr 12 +#define W_DMACR1__Data7RdMaxCr 3 +#define O_DMACR1__Data8WrMaxCr 9 +#define W_DMACR1__Data8WrMaxCr 3 +#define O_DMACR1__Data8RdMaxCr 6 +#define W_DMACR1__Data8RdMaxCr 3 +#define O_DMACR1__Data9WrMaxCr 3 +#define W_DMACR1__Data9WrMaxCr 3 +#define O_DMACR1__Data9RdMaxCr 0 +#define W_DMACR1__Data9RdMaxCr 3 +#define R_DMACR2 0x202 +#define O_DMACR2__Data10WrMaxCr 27 +#define W_DMACR2__Data10WrMaxCr 3 +#define O_DMACR2__Data10RdMaxCr 24 +#define W_DMACR2__Data10RdMaxCr 3 +#define O_DMACR2__Data11WrMaxCr 21 +#define W_DMACR2__Data11WrMaxCr 3 +#define O_DMACR2__Data11RdMaxCr 18 +#define W_DMACR2__Data11RdMaxCr 3 +#define O_DMACR2__Data12WrMaxCr 15 +#define W_DMACR2__Data12WrMaxCr 3 +#define O_DMACR2__Data12RdMaxCr 12 +#define W_DMACR2__Data12RdMaxCr 3 +#define O_DMACR2__Data13WrMaxCr 9 +#define W_DMACR2__Data13WrMaxCr 3 +#define O_DMACR2__Data13RdMaxCr 6 +#define W_DMACR2__Data13RdMaxCr 3 +#define O_DMACR2__Data14WrMaxCr 3 +#define W_DMACR2__Data14WrMaxCr 3 +#define O_DMACR2__Data14RdMaxCr 0 +#define W_DMACR2__Data14RdMaxCr 3 +#define R_DMACR3 0x203 +#define O_DMACR3__Data15WrMaxCr 27 +#define W_DMACR3__Data15WrMaxCr 3 +#define O_DMACR3__Data15RdMaxCr 24 +#define W_DMACR3__Data15RdMaxCr 3 +#define O_DMACR3__SpClassWrMaxCr 21 +#define W_DMACR3__SpClassWrMaxCr 3 +#define O_DMACR3__SpClassRdMaxCr 18 +#define W_DMACR3__SpClassRdMaxCr 3 +#define O_DMACR3__JumFrInWrMaxCr 15 +#define W_DMACR3__JumFrInWrMaxCr 3 +#define O_DMACR3__JumFrInRdMaxCr 12 +#define W_DMACR3__JumFrInRdMaxCr 3 +#define O_DMACR3__RegFrInWrMaxCr 9 +#define W_DMACR3__RegFrInWrMaxCr 3 +#define O_DMACR3__RegFrInRdMaxCr 6 +#define W_DMACR3__RegFrInRdMaxCr 3 +#define O_DMACR3__FrOutWrMaxCr 3 +#define W_DMACR3__FrOutWrMaxCr 3 +#define O_DMACR3__FrOutRdMaxCr 0 +#define W_DMACR3__FrOutRdMaxCr 3 +#define R_REG_FRIN_SPILL_MEM_START_0 0x204 +#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0 +#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32 +#define R_REG_FRIN_SPILL_MEM_START_1 0x205 +#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0 +#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3 +#define R_REG_FRIN_SPILL_MEM_SIZE 0x206 +#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0 +#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32 +#define R_FROUT_SPILL_MEM_START_0 0x207 +#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0 +#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32 +#define R_FROUT_SPILL_MEM_START_1 0x208 +#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0 +#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3 +#define R_FROUT_SPILL_MEM_SIZE 0x209 +#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0 +#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32 +#define R_CLASS0_SPILL_MEM_START_0 0x20A +#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0 +#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32 +#define R_CLASS0_SPILL_MEM_START_1 0x20B +#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0 +#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3 +#define R_CLASS0_SPILL_MEM_SIZE 0x20C +#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0 +#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32 +#define R_JUMFRIN_SPILL_MEM_START_0 0x20D +#define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0 +#define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32 +#define R_JUMFRIN_SPILL_MEM_START_1 0x20E +#define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0 +#define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3 +#define R_JUMFRIN_SPILL_MEM_SIZE 0x20F +#define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0 +#define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32 +#define R_CLASS1_SPILL_MEM_START_0 0x210 +#define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0 +#define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32 +#define R_CLASS1_SPILL_MEM_START_1 0x211 +#define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0 +#define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3 +#define R_CLASS1_SPILL_MEM_SIZE 0x212 +#define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0 +#define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32 +#define R_CLASS2_SPILL_MEM_START_0 0x213 +#define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0 +#define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32 +#define R_CLASS2_SPILL_MEM_START_1 0x214 +#define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0 +#define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3 +#define R_CLASS2_SPILL_MEM_SIZE 0x215 +#define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0 +#define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32 +#define R_CLASS3_SPILL_MEM_START_0 0x216 +#define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0 +#define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32 +#define R_CLASS3_SPILL_MEM_START_1 0x217 +#define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0 +#define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3 +#define R_CLASS3_SPILL_MEM_SIZE 0x218 +#define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0 +#define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32 +#define R_REG_FRIN1_SPILL_MEM_START_0 0x219 +#define R_REG_FRIN1_SPILL_MEM_START_1 0x21a +#define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b +#define R_SPIHNGY0 0x219 +#define O_SPIHNGY0__EG_HNGY_THRESH_0 24 +#define W_SPIHNGY0__EG_HNGY_THRESH_0 7 +#define O_SPIHNGY0__EG_HNGY_THRESH_1 16 +#define W_SPIHNGY0__EG_HNGY_THRESH_1 7 +#define O_SPIHNGY0__EG_HNGY_THRESH_2 8 +#define W_SPIHNGY0__EG_HNGY_THRESH_2 7 +#define O_SPIHNGY0__EG_HNGY_THRESH_3 0 +#define W_SPIHNGY0__EG_HNGY_THRESH_3 7 +#define R_SPIHNGY1 0x21A +#define O_SPIHNGY1__EG_HNGY_THRESH_4 24 +#define W_SPIHNGY1__EG_HNGY_THRESH_4 7 +#define O_SPIHNGY1__EG_HNGY_THRESH_5 16 +#define W_SPIHNGY1__EG_HNGY_THRESH_5 7 +#define O_SPIHNGY1__EG_HNGY_THRESH_6 8 +#define W_SPIHNGY1__EG_HNGY_THRESH_6 7 +#define O_SPIHNGY1__EG_HNGY_THRESH_7 0 +#define W_SPIHNGY1__EG_HNGY_THRESH_7 7 +#define R_SPIHNGY2 0x21B +#define O_SPIHNGY2__EG_HNGY_THRESH_8 24 +#define W_SPIHNGY2__EG_HNGY_THRESH_8 7 +#define O_SPIHNGY2__EG_HNGY_THRESH_9 16 +#define W_SPIHNGY2__EG_HNGY_THRESH_9 7 +#define O_SPIHNGY2__EG_HNGY_THRESH_10 8 +#define W_SPIHNGY2__EG_HNGY_THRESH_10 7 +#define O_SPIHNGY2__EG_HNGY_THRESH_11 0 +#define W_SPIHNGY2__EG_HNGY_THRESH_11 7 +#define R_SPIHNGY3 0x21C +#define O_SPIHNGY3__EG_HNGY_THRESH_12 24 +#define W_SPIHNGY3__EG_HNGY_THRESH_12 7 +#define O_SPIHNGY3__EG_HNGY_THRESH_13 16 +#define W_SPIHNGY3__EG_HNGY_THRESH_13 7 +#define O_SPIHNGY3__EG_HNGY_THRESH_14 8 +#define W_SPIHNGY3__EG_HNGY_THRESH_14 7 +#define O_SPIHNGY3__EG_HNGY_THRESH_15 0 +#define W_SPIHNGY3__EG_HNGY_THRESH_15 7 +#define R_SPISTRV0 0x21D +#define O_SPISTRV0__EG_STRV_THRESH_0 24 +#define W_SPISTRV0__EG_STRV_THRESH_0 7 +#define O_SPISTRV0__EG_STRV_THRESH_1 16 +#define W_SPISTRV0__EG_STRV_THRESH_1 7 +#define O_SPISTRV0__EG_STRV_THRESH_2 8 +#define W_SPISTRV0__EG_STRV_THRESH_2 7 +#define O_SPISTRV0__EG_STRV_THRESH_3 0 +#define W_SPISTRV0__EG_STRV_THRESH_3 7 +#define R_SPISTRV1 0x21E +#define O_SPISTRV1__EG_STRV_THRESH_4 24 +#define W_SPISTRV1__EG_STRV_THRESH_4 7 +#define O_SPISTRV1__EG_STRV_THRESH_5 16 +#define W_SPISTRV1__EG_STRV_THRESH_5 7 +#define O_SPISTRV1__EG_STRV_THRESH_6 8 +#define W_SPISTRV1__EG_STRV_THRESH_6 7 +#define O_SPISTRV1__EG_STRV_THRESH_7 0 +#define W_SPISTRV1__EG_STRV_THRESH_7 7 +#define R_SPISTRV2 0x21F +#define O_SPISTRV2__EG_STRV_THRESH_8 24 +#define W_SPISTRV2__EG_STRV_THRESH_8 7 +#define O_SPISTRV2__EG_STRV_THRESH_9 16 +#define W_SPISTRV2__EG_STRV_THRESH_9 7 +#define O_SPISTRV2__EG_STRV_THRESH_10 8 +#define W_SPISTRV2__EG_STRV_THRESH_10 7 +#define O_SPISTRV2__EG_STRV_THRESH_11 0 +#define W_SPISTRV2__EG_STRV_THRESH_11 7 +#define R_SPISTRV3 0x220 +#define O_SPISTRV3__EG_STRV_THRESH_12 24 +#define W_SPISTRV3__EG_STRV_THRESH_12 7 +#define O_SPISTRV3__EG_STRV_THRESH_13 16 +#define W_SPISTRV3__EG_STRV_THRESH_13 7 +#define O_SPISTRV3__EG_STRV_THRESH_14 8 +#define W_SPISTRV3__EG_STRV_THRESH_14 7 +#define O_SPISTRV3__EG_STRV_THRESH_15 0 +#define W_SPISTRV3__EG_STRV_THRESH_15 7 +#define R_TXDATAFIFO0 0x221 +#define O_TXDATAFIFO0__Tx0DataFifoStart 24 +#define W_TXDATAFIFO0__Tx0DataFifoStart 7 +#define O_TXDATAFIFO0__Tx0DataFifoSize 16 +#define W_TXDATAFIFO0__Tx0DataFifoSize 7 +#define O_TXDATAFIFO0__Tx1DataFifoStart 8 +#define W_TXDATAFIFO0__Tx1DataFifoStart 7 +#define O_TXDATAFIFO0__Tx1DataFifoSize 0 +#define W_TXDATAFIFO0__Tx1DataFifoSize 7 +#define R_TXDATAFIFO1 0x222 +#define O_TXDATAFIFO1__Tx2DataFifoStart 24 +#define W_TXDATAFIFO1__Tx2DataFifoStart 7 +#define O_TXDATAFIFO1__Tx2DataFifoSize 16 +#define W_TXDATAFIFO1__Tx2DataFifoSize 7 +#define O_TXDATAFIFO1__Tx3DataFifoStart 8 +#define W_TXDATAFIFO1__Tx3DataFifoStart 7 +#define O_TXDATAFIFO1__Tx3DataFifoSize 0 +#define W_TXDATAFIFO1__Tx3DataFifoSize 7 +#define R_TXDATAFIFO2 0x223 +#define O_TXDATAFIFO2__Tx4DataFifoStart 24 +#define W_TXDATAFIFO2__Tx4DataFifoStart 7 +#define O_TXDATAFIFO2__Tx4DataFifoSize 16 +#define W_TXDATAFIFO2__Tx4DataFifoSize 7 +#define O_TXDATAFIFO2__Tx5DataFifoStart 8 +#define W_TXDATAFIFO2__Tx5DataFifoStart 7 +#define O_TXDATAFIFO2__Tx5DataFifoSize 0 +#define W_TXDATAFIFO2__Tx5DataFifoSize 7 +#define R_TXDATAFIFO3 0x224 +#define O_TXDATAFIFO3__Tx6DataFifoStart 24 +#define W_TXDATAFIFO3__Tx6DataFifoStart 7 +#define O_TXDATAFIFO3__Tx6DataFifoSize 16 +#define W_TXDATAFIFO3__Tx6DataFifoSize 7 +#define O_TXDATAFIFO3__Tx7DataFifoStart 8 +#define W_TXDATAFIFO3__Tx7DataFifoStart 7 +#define O_TXDATAFIFO3__Tx7DataFifoSize 0 +#define W_TXDATAFIFO3__Tx7DataFifoSize 7 +#define R_TXDATAFIFO4 0x225 +#define O_TXDATAFIFO4__Tx8DataFifoStart 24 +#define W_TXDATAFIFO4__Tx8DataFifoStart 7 +#define O_TXDATAFIFO4__Tx8DataFifoSize 16 +#define W_TXDATAFIFO4__Tx8DataFifoSize 7 +#define O_TXDATAFIFO4__Tx9DataFifoStart 8 +#define W_TXDATAFIFO4__Tx9DataFifoStart 7 +#define O_TXDATAFIFO4__Tx9DataFifoSize 0 +#define W_TXDATAFIFO4__Tx9DataFifoSize 7 +#define R_TXDATAFIFO5 0x226 +#define O_TXDATAFIFO5__Tx10DataFifoStart 24 +#define W_TXDATAFIFO5__Tx10DataFifoStart 7 +#define O_TXDATAFIFO5__Tx10DataFifoSize 16 +#define W_TXDATAFIFO5__Tx10DataFifoSize 7 +#define O_TXDATAFIFO5__Tx11DataFifoStart 8 +#define W_TXDATAFIFO5__Tx11DataFifoStart 7 +#define O_TXDATAFIFO5__Tx11DataFifoSize 0 +#define W_TXDATAFIFO5__Tx11DataFifoSize 7 +#define R_TXDATAFIFO6 0x227 +#define O_TXDATAFIFO6__Tx12DataFifoStart 24 +#define W_TXDATAFIFO6__Tx12DataFifoStart 7 +#define O_TXDATAFIFO6__Tx12DataFifoSize 16 +#define W_TXDATAFIFO6__Tx12DataFifoSize 7 +#define O_TXDATAFIFO6__Tx13DataFifoStart 8 +#define W_TXDATAFIFO6__Tx13DataFifoStart 7 +#define O_TXDATAFIFO6__Tx13DataFifoSize 0 +#define W_TXDATAFIFO6__Tx13DataFifoSize 7 +#define R_TXDATAFIFO7 0x228 +#define O_TXDATAFIFO7__Tx14DataFifoStart 24 +#define W_TXDATAFIFO7__Tx14DataFifoStart 7 +#define O_TXDATAFIFO7__Tx14DataFifoSize 16 +#define W_TXDATAFIFO7__Tx14DataFifoSize 7 +#define O_TXDATAFIFO7__Tx15DataFifoStart 8 +#define W_TXDATAFIFO7__Tx15DataFifoStart 7 +#define O_TXDATAFIFO7__Tx15DataFifoSize 0 +#define W_TXDATAFIFO7__Tx15DataFifoSize 7 +#define R_RXDATAFIFO0 0x229 +#define O_RXDATAFIFO0__Rx0DataFifoStart 24 +#define W_RXDATAFIFO0__Rx0DataFifoStart 7 +#define O_RXDATAFIFO0__Rx0DataFifoSize 16 +#define W_RXDATAFIFO0__Rx0DataFifoSize 7 +#define O_RXDATAFIFO0__Rx1DataFifoStart 8 +#define W_RXDATAFIFO0__Rx1DataFifoStart 7 +#define O_RXDATAFIFO0__Rx1DataFifoSize 0 +#define W_RXDATAFIFO0__Rx1DataFifoSize 7 +#define R_RXDATAFIFO1 0x22A +#define O_RXDATAFIFO1__Rx2DataFifoStart 24 +#define W_RXDATAFIFO1__Rx2DataFifoStart 7 +#define O_RXDATAFIFO1__Rx2DataFifoSize 16 +#define W_RXDATAFIFO1__Rx2DataFifoSize 7 +#define O_RXDATAFIFO1__Rx3DataFifoStart 8 +#define W_RXDATAFIFO1__Rx3DataFifoStart 7 +#define O_RXDATAFIFO1__Rx3DataFifoSize 0 +#define W_RXDATAFIFO1__Rx3DataFifoSize 7 +#define R_RXDATAFIFO2 0x22B +#define O_RXDATAFIFO2__Rx4DataFifoStart 24 +#define W_RXDATAFIFO2__Rx4DataFifoStart 7 +#define O_RXDATAFIFO2__Rx4DataFifoSize 16 +#define W_RXDATAFIFO2__Rx4DataFifoSize 7 +#define O_RXDATAFIFO2__Rx5DataFifoStart 8 +#define W_RXDATAFIFO2__Rx5DataFifoStart 7 +#define O_RXDATAFIFO2__Rx5DataFifoSize 0 +#define W_RXDATAFIFO2__Rx5DataFifoSize 7 +#define R_RXDATAFIFO3 0x22C +#define O_RXDATAFIFO3__Rx6DataFifoStart 24 +#define W_RXDATAFIFO3__Rx6DataFifoStart 7 +#define O_RXDATAFIFO3__Rx6DataFifoSize 16 +#define W_RXDATAFIFO3__Rx6DataFifoSize 7 +#define O_RXDATAFIFO3__Rx7DataFifoStart 8 +#define W_RXDATAFIFO3__Rx7DataFifoStart 7 +#define O_RXDATAFIFO3__Rx7DataFifoSize 0 +#define W_RXDATAFIFO3__Rx7DataFifoSize 7 +#define R_RXDATAFIFO4 0x22D +#define O_RXDATAFIFO4__Rx8DataFifoStart 24 +#define W_RXDATAFIFO4__Rx8DataFifoStart 7 +#define O_RXDATAFIFO4__Rx8DataFifoSize 16 +#define W_RXDATAFIFO4__Rx8DataFifoSize 7 +#define O_RXDATAFIFO4__Rx9DataFifoStart 8 +#define W_RXDATAFIFO4__Rx9DataFifoStart 7 +#define O_RXDATAFIFO4__Rx9DataFifoSize 0 +#define W_RXDATAFIFO4__Rx9DataFifoSize 7 +#define R_RXDATAFIFO5 0x22E +#define O_RXDATAFIFO5__Rx10DataFifoStart 24 +#define W_RXDATAFIFO5__Rx10DataFifoStart 7 +#define O_RXDATAFIFO5__Rx10DataFifoSize 16 +#define W_RXDATAFIFO5__Rx10DataFifoSize 7 +#define O_RXDATAFIFO5__Rx11DataFifoStart 8 +#define W_RXDATAFIFO5__Rx11DataFifoStart 7 +#define O_RXDATAFIFO5__Rx11DataFifoSize 0 +#define W_RXDATAFIFO5__Rx11DataFifoSize 7 +#define R_RXDATAFIFO6 0x22F +#define O_RXDATAFIFO6__Rx12DataFifoStart 24 +#define W_RXDATAFIFO6__Rx12DataFifoStart 7 +#define O_RXDATAFIFO6__Rx12DataFifoSize 16 +#define W_RXDATAFIFO6__Rx12DataFifoSize 7 +#define O_RXDATAFIFO6__Rx13DataFifoStart 8 +#define W_RXDATAFIFO6__Rx13DataFifoStart 7 +#define O_RXDATAFIFO6__Rx13DataFifoSize 0 +#define W_RXDATAFIFO6__Rx13DataFifoSize 7 +#define R_RXDATAFIFO7 0x230 +#define O_RXDATAFIFO7__Rx14DataFifoStart 24 +#define W_RXDATAFIFO7__Rx14DataFifoStart 7 +#define O_RXDATAFIFO7__Rx14DataFifoSize 16 +#define W_RXDATAFIFO7__Rx14DataFifoSize 7 +#define O_RXDATAFIFO7__Rx15DataFifoStart 8 +#define W_RXDATAFIFO7__Rx15DataFifoStart 7 +#define O_RXDATAFIFO7__Rx15DataFifoSize 0 +#define W_RXDATAFIFO7__Rx15DataFifoSize 7 +#define R_XGMACPADCALIBRATION 0x231 +#define R_FREEQCARVE 0x233 +#define R_SPI4STATICDELAY0 0x240 +#define O_SPI4STATICDELAY0__DataLine7 28 +#define W_SPI4STATICDELAY0__DataLine7 4 +#define O_SPI4STATICDELAY0__DataLine6 24 +#define W_SPI4STATICDELAY0__DataLine6 4 +#define O_SPI4STATICDELAY0__DataLine5 20 +#define W_SPI4STATICDELAY0__DataLine5 4 +#define O_SPI4STATICDELAY0__DataLine4 16 +#define W_SPI4STATICDELAY0__DataLine4 4 +#define O_SPI4STATICDELAY0__DataLine3 12 +#define W_SPI4STATICDELAY0__DataLine3 4 +#define O_SPI4STATICDELAY0__DataLine2 8 +#define W_SPI4STATICDELAY0__DataLine2 4 +#define O_SPI4STATICDELAY0__DataLine1 4 +#define W_SPI4STATICDELAY0__DataLine1 4 +#define O_SPI4STATICDELAY0__DataLine0 0 +#define W_SPI4STATICDELAY0__DataLine0 4 +#define R_SPI4STATICDELAY1 0x241 +#define O_SPI4STATICDELAY1__DataLine15 28 +#define W_SPI4STATICDELAY1__DataLine15 4 +#define O_SPI4STATICDELAY1__DataLine14 24 +#define W_SPI4STATICDELAY1__DataLine14 4 +#define O_SPI4STATICDELAY1__DataLine13 20 +#define W_SPI4STATICDELAY1__DataLine13 4 +#define O_SPI4STATICDELAY1__DataLine12 16 +#define W_SPI4STATICDELAY1__DataLine12 4 +#define O_SPI4STATICDELAY1__DataLine11 12 +#define W_SPI4STATICDELAY1__DataLine11 4 +#define O_SPI4STATICDELAY1__DataLine10 8 +#define W_SPI4STATICDELAY1__DataLine10 4 +#define O_SPI4STATICDELAY1__DataLine9 4 +#define W_SPI4STATICDELAY1__DataLine9 4 +#define O_SPI4STATICDELAY1__DataLine8 0 +#define W_SPI4STATICDELAY1__DataLine8 4 +#define R_SPI4STATICDELAY2 0x242 +#define O_SPI4STATICDELAY0__TxStat1 8 +#define W_SPI4STATICDELAY0__TxStat1 4 +#define O_SPI4STATICDELAY0__TxStat0 4 +#define W_SPI4STATICDELAY0__TxStat0 4 +#define O_SPI4STATICDELAY0__RxControl 0 +#define W_SPI4STATICDELAY0__RxControl 4 +#define R_SPI4CONTROL 0x243 +#define O_SPI4CONTROL__StaticDelay 2 +#define O_SPI4CONTROL__LVDS_LVTTL 1 +#define O_SPI4CONTROL__SPI4Enable 0 +#define R_CLASSWATERMARKS 0x244 +#define O_CLASSWATERMARKS__Class0Watermark 24 +#define W_CLASSWATERMARKS__Class0Watermark 5 +#define O_CLASSWATERMARKS__Class1Watermark 16 +#define W_CLASSWATERMARKS__Class1Watermark 5 +#define O_CLASSWATERMARKS__Class3Watermark 0 +#define W_CLASSWATERMARKS__Class3Watermark 5 +#define R_RXWATERMARKS1 0x245 +#define O_RXWATERMARKS__Rx0DataWatermark 24 +#define W_RXWATERMARKS__Rx0DataWatermark 7 +#define O_RXWATERMARKS__Rx1DataWatermark 16 +#define W_RXWATERMARKS__Rx1DataWatermark 7 +#define O_RXWATERMARKS__Rx3DataWatermark 0 +#define W_RXWATERMARKS__Rx3DataWatermark 7 +#define R_RXWATERMARKS2 0x246 +#define O_RXWATERMARKS__Rx4DataWatermark 24 +#define W_RXWATERMARKS__Rx4DataWatermark 7 +#define O_RXWATERMARKS__Rx5DataWatermark 16 +#define W_RXWATERMARKS__Rx5DataWatermark 7 +#define O_RXWATERMARKS__Rx6DataWatermark 8 +#define W_RXWATERMARKS__Rx6DataWatermark 7 +#define O_RXWATERMARKS__Rx7DataWatermark 0 +#define W_RXWATERMARKS__Rx7DataWatermark 7 +#define R_RXWATERMARKS3 0x247 +#define O_RXWATERMARKS__Rx8DataWatermark 24 +#define W_RXWATERMARKS__Rx8DataWatermark 7 +#define O_RXWATERMARKS__Rx9DataWatermark 16 +#define W_RXWATERMARKS__Rx9DataWatermark 7 +#define O_RXWATERMARKS__Rx10DataWatermark 8 +#define W_RXWATERMARKS__Rx10DataWatermark 7 +#define O_RXWATERMARKS__Rx11DataWatermark 0 +#define W_RXWATERMARKS__Rx11DataWatermark 7 +#define R_RXWATERMARKS4 0x248 +#define O_RXWATERMARKS__Rx12DataWatermark 24 +#define W_RXWATERMARKS__Rx12DataWatermark 7 +#define O_RXWATERMARKS__Rx13DataWatermark 16 +#define W_RXWATERMARKS__Rx13DataWatermark 7 +#define O_RXWATERMARKS__Rx14DataWatermark 8 +#define W_RXWATERMARKS__Rx14DataWatermark 7 +#define O_RXWATERMARKS__Rx15DataWatermark 0 +#define W_RXWATERMARKS__Rx15DataWatermark 7 +#define R_FREEWATERMARKS 0x249 +#define O_FREEWATERMARKS__FreeOutWatermark 16 +#define W_FREEWATERMARKS__FreeOutWatermark 16 +#define O_FREEWATERMARKS__JumFrWatermark 8 +#define W_FREEWATERMARKS__JumFrWatermark 7 +#define O_FREEWATERMARKS__RegFrWatermark 0 +#define W_FREEWATERMARKS__RegFrWatermark 7 +#define R_EGRESSFIFOCARVINGSLOTS 0x24a + +#define CTRL_RES0 0 +#define CTRL_RES1 1 +#define CTRL_REG_FREE 2 +#define CTRL_JUMBO_FREE 3 +#define CTRL_CONT 4 +#define CTRL_EOP 5 +#define CTRL_START 6 +#define CTRL_SNGL 7 + +#define CTRL_B0_NOT_EOP 0 +#define CTRL_B0_EOP 1 + +#define R_ROUND_ROBIN_TABLE 0 +#define R_PDE_CLASS_0 0x300 +#define R_PDE_CLASS_1 0x302 +#define R_PDE_CLASS_2 0x304 +#define R_PDE_CLASS_3 0x306 + +#define R_MSG_TX_THRESHOLD 0x308 + +#define R_GMAC_JFR0_BUCKET_SIZE 0x320 +#define R_GMAC_RFR0_BUCKET_SIZE 0x321 +#define R_GMAC_TX0_BUCKET_SIZE 0x322 +#define R_GMAC_TX1_BUCKET_SIZE 0x323 +#define R_GMAC_TX2_BUCKET_SIZE 0x324 +#define R_GMAC_TX3_BUCKET_SIZE 0x325 +#define R_GMAC_JFR1_BUCKET_SIZE 0x326 +#define R_GMAC_RFR1_BUCKET_SIZE 0x327 + +#define R_XGS_TX0_BUCKET_SIZE 0x320 +#define R_XGS_TX1_BUCKET_SIZE 0x321 +#define R_XGS_TX2_BUCKET_SIZE 0x322 +#define R_XGS_TX3_BUCKET_SIZE 0x323 +#define R_XGS_TX4_BUCKET_SIZE 0x324 +#define R_XGS_TX5_BUCKET_SIZE 0x325 +#define R_XGS_TX6_BUCKET_SIZE 0x326 +#define R_XGS_TX7_BUCKET_SIZE 0x327 +#define R_XGS_TX8_BUCKET_SIZE 0x328 +#define R_XGS_TX9_BUCKET_SIZE 0x329 +#define R_XGS_TX10_BUCKET_SIZE 0x32A +#define R_XGS_TX11_BUCKET_SIZE 0x32B +#define R_XGS_TX12_BUCKET_SIZE 0x32C +#define R_XGS_TX13_BUCKET_SIZE 0x32D +#define R_XGS_TX14_BUCKET_SIZE 0x32E +#define R_XGS_TX15_BUCKET_SIZE 0x32F +#define R_XGS_JFR_BUCKET_SIZE 0x330 +#define R_XGS_RFR_BUCKET_SIZE 0x331 + +#define R_CC_CPU0_0 0x380 +#define R_CC_CPU1_0 0x388 +#define R_CC_CPU2_0 0x390 +#define R_CC_CPU3_0 0x398 +#define R_CC_CPU4_0 0x3a0 +#define R_CC_CPU5_0 0x3a8 +#define R_CC_CPU6_0 0x3b0 +#define R_CC_CPU7_0 0x3b8 + +#define XLR_GMAC_BLK_SZ (XLR_IO_GMAC_1_OFFSET - \ + XLR_IO_GMAC_0_OFFSET) + +/* Constants used for configuring the devices */ + +#define XLR_FB_STN 6 /* Bucket used for Tx freeback */ + +#define MAC_B2B_IPG 88 + +#define XLR_NET_PREPAD_LEN 32 + +/* frame sizes need to be cacheline aligned */ +#define MAX_FRAME_SIZE (1536 + XLR_NET_PREPAD_LEN) +#define MAX_FRAME_SIZE_JUMBO 9216 + +#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES +#define MAC_PREPAD 0 +#define BYTE_OFFSET 2 +#define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE + BYTE_OFFSET + \ + MAC_PREPAD + MAC_SKB_BACK_PTR_SIZE + SMP_CACHE_BYTES) +#define MAC_CRC_LEN 4 +#define MAX_NUM_MSGRNG_STN_CC 128 +#define MAX_MSG_SND_ATTEMPTS 100 /* 13 stns x 4 entry msg/stn + + headroom */ + +#define MAC_FRIN_TO_BE_SENT_THRESHOLD 16 + +#define MAX_NUM_DESC_SPILL 1024 +#define MAX_FRIN_SPILL (MAX_NUM_DESC_SPILL << 2) +#define MAX_FROUT_SPILL (MAX_NUM_DESC_SPILL << 2) +#define MAX_CLASS_0_SPILL (MAX_NUM_DESC_SPILL << 2) +#define MAX_CLASS_1_SPILL (MAX_NUM_DESC_SPILL << 2) +#define MAX_CLASS_2_SPILL (MAX_NUM_DESC_SPILL << 2) +#define MAX_CLASS_3_SPILL (MAX_NUM_DESC_SPILL << 2) + +enum { + SGMII_SPEED_10 = 0x00000000, + SGMII_SPEED_100 = 0x02000000, + SGMII_SPEED_1000 = 0x04000000, +}; + +enum tsv_rsv_reg { + TX_RX_64_BYTE_FRAME = 0x20, + TX_RX_64_127_BYTE_FRAME, + TX_RX_128_255_BYTE_FRAME, + TX_RX_256_511_BYTE_FRAME, + TX_RX_512_1023_BYTE_FRAME, + TX_RX_1024_1518_BYTE_FRAME, + TX_RX_1519_1522_VLAN_BYTE_FRAME, + + RX_BYTE_COUNTER = 0x27, + RX_PACKET_COUNTER, + RX_FCS_ERROR_COUNTER, + RX_MULTICAST_PACKET_COUNTER, + RX_BROADCAST_PACKET_COUNTER, + RX_CONTROL_FRAME_PACKET_COUNTER, + RX_PAUSE_FRAME_PACKET_COUNTER, + RX_UNKNOWN_OP_CODE_COUNTER, + RX_ALIGNMENT_ERROR_COUNTER, + RX_FRAME_LENGTH_ERROR_COUNTER, + RX_CODE_ERROR_COUNTER, + RX_CARRIER_SENSE_ERROR_COUNTER, + RX_UNDERSIZE_PACKET_COUNTER, + RX_OVERSIZE_PACKET_COUNTER, + RX_FRAGMENTS_COUNTER, + RX_JABBER_COUNTER, + RX_DROP_PACKET_COUNTER, + + TX_BYTE_COUNTER = 0x38, + TX_PACKET_COUNTER, + TX_MULTICAST_PACKET_COUNTER, + TX_BROADCAST_PACKET_COUNTER, + TX_PAUSE_CONTROL_FRAME_COUNTER, + TX_DEFERRAL_PACKET_COUNTER, + TX_EXCESSIVE_DEFERRAL_PACKET_COUNTER, + TX_SINGLE_COLLISION_PACKET_COUNTER, + TX_MULTI_COLLISION_PACKET_COUNTER, + TX_LATE_COLLISION_PACKET_COUNTER, + TX_EXCESSIVE_COLLISION_PACKET_COUNTER, + TX_TOTAL_COLLISION_COUNTER, + TX_PAUSE_FRAME_HONERED_COUNTER, + TX_DROP_FRAME_COUNTER, + TX_JABBER_FRAME_COUNTER, + TX_FCS_ERROR_COUNTER, + TX_CONTROL_FRAME_COUNTER, + TX_OVERSIZE_FRAME_COUNTER, + TX_UNDERSIZE_FRAME_COUNTER, + TX_FRAGMENT_FRAME_COUNTER, + + CARRY_REG_1 = 0x4c, + CARRY_REG_2 = 0x4d, +}; + +struct xlr_net_priv { + u32 __iomem *base_addr; + struct net_device *ndev; + struct mii_bus *mii_bus; + int num_rx_desc; + int phy_addr; /* PHY addr on MDIO bus */ + int pcs_id; /* PCS id on MDIO bus */ + int port_id; /* Port(gmac/xgmac) number, i.e 0-7 */ + u32 __iomem *mii_addr; + u32 __iomem *serdes_addr; + u32 __iomem *pcs_addr; + u32 __iomem *gpio_addr; + int phy_speed; + int port_type; + struct timer_list queue_timer; + int wakeup_q; + struct platform_device *pdev; + struct xlr_net_data *nd; + + u64 *frin_spill; + u64 *frout_spill; + u64 *class_0_spill; + u64 *class_1_spill; + u64 *class_2_spill; + u64 *class_3_spill; +}; + +extern void xlr_set_gmac_speed(struct xlr_net_priv *priv); -- 1.7.6 From ganesanr@broadcom.com Tue Feb 5 12:31:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 12:31:55 +0100 (CET) Received: from mms2.broadcom.com ([216.31.210.18]:2760 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823092Ab3BELbuTligd (ORCPT ); Tue, 5 Feb 2013 12:31:50 +0100 Received: from [10.9.208.53] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 05 Feb 2013 03:28:22 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 5 Feb 2013 03:31:37 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.1.355.2; Tue, 5 Feb 2013 03:31:37 -0800 Received: from lc-blr-152.ban.broadcom.com (lc-blr-152.ban.broadcom.com [10.132.129.187]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id AC22C40FE3; Tue, 5 Feb 2013 03:31:35 -0800 (PST) From: ganesanr@broadcom.com To: linux-mips@linux-mips.org, netdev@vger.kernel.org cc: "Ganesan Ramalingam" Subject: [PATCH v2 2/2] MIPS: Netlogic: Platform changes for XLR/XLS gmac Date: Tue, 5 Feb 2013 17:01:30 +0530 Message-ID: <1360063890-17623-1-git-send-email-ganesanr@broadcom.com> X-Mailer: git-send-email 1.7.6 MIME-Version: 1.0 X-WSS-ID: 7D0E335C3SK791210-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-archive-position: 35706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ganesanr@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 10907 Lines: 331 From: Ganesan Ramalingam Add platform code to create network interface (xlr-net) for XLR/XLS boards. Signed-off-by: Ganesan Ramalingam --- This patch has to be merged through MIPS tree. This patch depends on patch [PATCH v2 1/2] NET: ethernet/netlogic: Netlogic XLR/XLS GMAC driver. arch/mips/include/asm/netlogic/xlr/platform_net.h | 46 +++++ arch/mips/netlogic/xlr/Makefile | 3 +- arch/mips/netlogic/xlr/fmn.c | 2 + arch/mips/netlogic/xlr/platform_net.c | 222 +++++++++++++++++++++ 4 files changed, 272 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/xlr/platform_net.h create mode 100644 arch/mips/netlogic/xlr/platform_net.c diff --git a/arch/mips/include/asm/netlogic/xlr/platform_net.h b/arch/mips/include/asm/netlogic/xlr/platform_net.h new file mode 100644 index 0000000..29deeea --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/platform_net.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +struct xlr_net_data { + int cpu_mask; + u32 __iomem *mii_addr; + u32 __iomem *serdes_addr; + u32 __iomem *pcs_addr; + u32 __iomem *gpio_addr; + int phy_interface; + int rfr_station; + int tx_stnid; + int *bucket_size; + int phy_addr; + struct xlr_fmn_info *gmac_fmn_info; +}; diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile index 05902bc..ff7ed2e 100644 --- a/arch/mips/netlogic/xlr/Makefile +++ b/arch/mips/netlogic/xlr/Makefile @@ -1,2 +1,3 @@ -obj-y += fmn.o fmn-config.o setup.o platform.o platform-flash.o +obj-y += fmn.o fmn-config.o setup.o platform.o \ + platform-flash.o platform_net.o obj-$(CONFIG_SMP) += wakeup.o diff --git a/arch/mips/netlogic/xlr/fmn.c b/arch/mips/netlogic/xlr/fmn.c index 4d74f03..d93e11a 100644 --- a/arch/mips/netlogic/xlr/fmn.c +++ b/arch/mips/netlogic/xlr/fmn.c @@ -33,6 +33,7 @@ */ #include +#include #include #include #include @@ -190,6 +191,7 @@ int nlm_register_fmn_handler(int start_stnid, int end_stnid, start_stnid, end_stnid); return 0; } +EXPORT_SYMBOL(nlm_register_fmn_handler); void nlm_setup_fmn_irq(void) { diff --git a/arch/mips/netlogic/xlr/platform_net.c b/arch/mips/netlogic/xlr/platform_net.c new file mode 100644 index 0000000..f6626a3 --- /dev/null +++ b/arch/mips/netlogic/xlr/platform_net.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2003-2012 Broadcom Corporation + * All Rights Reserved + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * 1. Redistributions of source code must retain the above copyright + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the Broadcom + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Linux Net */ +#define MAX_NUM_GMAC 8 +#define MAX_NUM_XLS_GMAC 8 +#define MAX_NUM_XLR_GMAC 4 + + +static u32 xlr_gmac_offsets[] = { + NETLOGIC_IO_GMAC_0_OFFSET, NETLOGIC_IO_GMAC_1_OFFSET, + NETLOGIC_IO_GMAC_2_OFFSET, NETLOGIC_IO_GMAC_3_OFFSET, + NETLOGIC_IO_GMAC_4_OFFSET, NETLOGIC_IO_GMAC_5_OFFSET, + NETLOGIC_IO_GMAC_6_OFFSET, NETLOGIC_IO_GMAC_7_OFFSET +}; + +static u32 xlr_gmac_irqs[] = { PIC_GMAC_0_IRQ, PIC_GMAC_1_IRQ, + PIC_GMAC_2_IRQ, PIC_GMAC_3_IRQ, + PIC_GMAC_4_IRQ, PIC_GMAC_5_IRQ, + PIC_GMAC_6_IRQ, PIC_GMAC_7_IRQ +}; + +static struct xlr_net_data ndata[MAX_NUM_GMAC]; +static struct resource xlr_net_res[8][2]; +static struct platform_device xlr_net_dev[8]; +static u32 __iomem *gmac0_addr; +static u32 __iomem *gmac4_addr; +static u32 __iomem *gpio_addr; + +static void config_mac(struct xlr_net_data *nd, int phy, u32 __iomem *serdes, + u32 __iomem *pcs, int rfr, int tx, int *bkt_size, + struct xlr_fmn_info *gmac_fmn_info, int phy_addr) +{ + nd->cpu_mask = nlm_current_node()->coremask; + nd->phy_interface = phy; + nd->rfr_station = rfr; + nd->tx_stnid = tx; + nd->mii_addr = gmac0_addr; + nd->serdes_addr = serdes; + nd->pcs_addr = pcs; + nd->gpio_addr = gpio_addr; + + nd->bucket_size = bkt_size; + nd->gmac_fmn_info = gmac_fmn_info; + nd->phy_addr = phy_addr; +} + +static void net_device_init(int id, struct resource *res, int offset, int irq) +{ + res[0].name = "gmac"; + res[0].start = CPHYSADDR(nlm_mmio_base(offset)); + res[0].end = res[0].start + 0xfff; + res[0].flags = IORESOURCE_MEM; + + res[1].name = "gmac"; + res[1].start = irq; + res[1].end = irq; + res[1].flags = IORESOURCE_IRQ; + + xlr_net_dev[id].name = "xlr-net"; + xlr_net_dev[id].id = id; + xlr_net_dev[id].num_resources = 2; + xlr_net_dev[id].resource = res; + xlr_net_dev[id].dev.platform_data = &ndata[id]; +} + +static void xls_gmac_init(void) +{ + int mac; + + gmac4_addr = ioremap(CPHYSADDR( + nlm_mmio_base(NETLOGIC_IO_GMAC_4_OFFSET)), 0xfff); + /* Passing GPIO base for serdes init. Only needed on sgmii ports*/ + gpio_addr = ioremap(CPHYSADDR( + nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET)), 0xfff); + + switch (nlm_prom_info.board_major_version) { + case 12: + /* first block RGMII or XAUI, use RGMII */ + config_mac(&ndata[0], + PHY_INTERFACE_MODE_RGMII, + gmac0_addr, /* serdes */ + gmac0_addr, /* pcs */ + FMN_STNID_GMACRFR_0, + FMN_STNID_GMAC0_TX0, + xlr_board_fmn_config.bucket_size, + &xlr_board_fmn_config.gmac[0], + 0); + + net_device_init(0, xlr_net_res[0], xlr_gmac_offsets[0], + xlr_gmac_irqs[0]); + platform_device_register(&xlr_net_dev[0]); + + /* second block is XAUI, not supported yet */ + break; + default: + /* default XLS config, all ports SGMII */ + for (mac = 0; mac < 4; mac++) { + config_mac(&ndata[mac], + PHY_INTERFACE_MODE_SGMII, + gmac0_addr, /* serdes */ + gmac0_addr, /* pcs */ + FMN_STNID_GMACRFR_0, + FMN_STNID_GMAC0_TX0 + mac, + xlr_board_fmn_config.bucket_size, + &xlr_board_fmn_config.gmac[0], + /* PHY address according to chip/board */ + mac + 0x10); + + net_device_init(mac, xlr_net_res[mac], + xlr_gmac_offsets[mac], + xlr_gmac_irqs[mac]); + platform_device_register(&xlr_net_dev[mac]); + } + + for (mac = 4; mac < MAX_NUM_XLS_GMAC; mac++) { + config_mac(&ndata[mac], + PHY_INTERFACE_MODE_SGMII, + gmac4_addr, /* serdes */ + gmac4_addr, /* pcs */ + FMN_STNID_GMAC1_FR_0, + FMN_STNID_GMAC1_TX0 + mac - 4, + xlr_board_fmn_config.bucket_size, + &xlr_board_fmn_config.gmac[1], + /* PHY address according to chip/board */ + mac + 0x10); + + net_device_init(mac, xlr_net_res[mac], + xlr_gmac_offsets[mac], + xlr_gmac_irqs[mac]); + platform_device_register(&xlr_net_dev[mac]); + } + } +} + +static void xlr_gmac_init(void) +{ + int mac; + + /* assume all GMACs for now */ + for (mac = 0; mac < MAX_NUM_XLR_GMAC; mac++) { + config_mac(&ndata[mac], + PHY_INTERFACE_MODE_RGMII, + 0, + 0, + FMN_STNID_GMACRFR_0, + FMN_STNID_GMAC0_TX0, + xlr_board_fmn_config.bucket_size, + &xlr_board_fmn_config.gmac[0], + mac); + + net_device_init(mac, xlr_net_res[mac], xlr_gmac_offsets[mac], + xlr_gmac_irqs[mac]); + platform_device_register(&xlr_net_dev[mac]); + } +} + +static int __init xlr_net_init(void) +{ + gmac0_addr = ioremap(CPHYSADDR( + nlm_mmio_base(NETLOGIC_IO_GMAC_0_OFFSET)), 0xfff); + + if (nlm_chip_is_xls()) + xls_gmac_init(); + else + xlr_gmac_init(); + + return 0; +} + +arch_initcall(xlr_net_init); -- 1.7.6 From bhutchings@solarflare.com Tue Feb 5 20:48:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 20:48:30 +0100 (CET) Received: from webmail.solarflare.com ([12.187.104.25]:17760 "EHLO webmail.solarflare.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824405Ab3BETs1dBYp0 (ORCPT ); Tue, 5 Feb 2013 20:48:27 +0100 Received: from [10.17.20.137] (10.17.20.137) by ocex02.SolarFlarecom.com (10.20.40.31) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 5 Feb 2013 11:48:18 -0800 Message-ID: <1360093696.2857.18.camel@bwh-desktop.uk.solarflarecom.com> Subject: Re: [PATCH v2 1/2] NET: ethernet/netlogic: Netlogic XLR/XLS GMAC driver From: Ben Hutchings To: CC: , Date: Tue, 5 Feb 2013 19:48:16 +0000 In-Reply-To: <1360063819-17555-1-git-send-email-ganesanr@broadcom.com> References: <1360063819-17555-1-git-send-email-ganesanr@broadcom.com> Organization: Solarflare Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3 (3.2.3-3.fc16) Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-Originating-IP: [10.17.20.137] X-TM-AS-Product-Ver: SMEX-10.0.0.1412-7.000.1014-19612.005 X-TM-AS-Result: No--17.535400-0.000000-31 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-archive-position: 35707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhutchings@solarflare.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2969 Lines: 95 On Tue, 2013-02-05 at 17:00 +0530, ganesanr@broadcom.com wrote: > From: Ganesan Ramalingam > > Add support for the Network Accelerator Engine on Netlogic XLR/XLS > MIPS SoCs. The XLR/XLS NAE blocks can be configured as one 10G > interface or four 1G interfaces. This driver supports blocks > with 1G ports. > > Signed-off-by: Ganesan Ramalingam > --- > This patch has to be merged through netdev tree. > > Changes since v1: > * Implementing ethtool using phylib > * Free skb buf incase of nlm_fmn_send() fail > * Use of ndo_get_stats64 instead of ndo_get_stats > * Watchdog timeo fix [...] > +static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats) > +{ > + struct xlr_net_priv *priv = netdev_priv(ndev); > + > + stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER); > + stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER); > + stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER); > + stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER); > + stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER); > + stats->rx_dropped = xlr_nae_rdreg(priv->base_addr, > + RX_DROP_PACKET_COUNTER); > + stats->tx_dropped = xlr_nae_rdreg(priv->base_addr, > + TX_DROP_FRAME_COUNTER); [...] But these are still 32-bit counters in hardware, yes? So I think you need to arrange to poll at least the byte counters every few seconds and maintain the higher bits in software e.g.: struct xlr_stats { spinlock_t lock; struct timer timer; u64 rx_bytes; u64 tx_bytes; ... }; static void xlr_poll_stats(struct xlr_net_priv *priv) { struct xlr_stats = &priv->stats; u32 counter; spin_lock_bh(&stats->lock); counter = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER); stats->rx_bytes += (u32)(counter - stats->rx_bytes); counter = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER); stats->tx_bytes += (u32)(counter - stats->tx_bytes); ... spin_unlock_bh(&stats->lock); } static void xlr_poll_stats_timer(void *data) { struct xlr_net_priv *priv = data; xlr_poll_stats(priv); mod_timer(&priv->stats.timer, jiffies + 2 * HZ); } static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats) { struct xlr_net_priv *priv = netdev_priv(ndev); xlr_poll_stats(priv); ... } static int xlr_net_probe(struct platform_device *pdev) { ... spin_lock_init(&priv->stats.lock); setup_timer(&priv->stats.timer, xlr_poll_stats_timer, priv); ... } Plus add_timer() and del_timer_sync() when starting/stopping the interface. Also you need to clear the software stats if you have to reset the hardware. All of which is a fair amount of work but you can't avoid it if the hardware counters just aren't wide enough. Ben. -- Ben Hutchings, Staff Engineer, Solarflare Not speaking for my employer; that's the marketing department's job. They asked us to note that Solarflare product names are trademarked. From sjhill@mips.com Tue Feb 5 23:52:17 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 23:52:18 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:49917 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823690Ab3BEWwRlwsWj (ORCPT ); Tue, 5 Feb 2013 23:52:17 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1U2rN2-0008Ky-3q; Tue, 05 Feb 2013 16:52:08 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com, ddaney.cavm@gmail.com Subject: [PATCH 0/4] Add support for microMIPS instructions Date: Tue, 5 Feb 2013 16:51:59 -0600 Message-Id: <1360104723-29529-1-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1119 Lines: 28 From: "Steven J. Hill" These patches add support for the microMIPS ISA. The kernel can simultaneously support classic and microMIPS instructions using the micro assembler. All microMIPS instructions for the micro assembler have the 'MM_' prefix. Steven J. Hill (4): MIPS: microMIPS: Add instruction formats. MIPS: microMIPS: uasm: Split 'uasm.c' into two files. MIPS: microMIPS: uasm: Add microMIPS micro assembler support. MIPS: microMIPS: Add instruction utility macros. arch/mips/Kconfig | 4 + arch/mips/include/asm/mipsregs.h | 18 ++ arch/mips/include/asm/uasm.h | 66 ++++-- arch/mips/include/uapi/asm/inst.h | 449 +++++++++++++++++++++++++++++++++++++ arch/mips/mm/Makefile | 4 +- arch/mips/mm/uasm-micromips.c | 220 ++++++++++++++++++ arch/mips/mm/uasm-mips.c | 196 ++++++++++++++++ arch/mips/mm/uasm.c | 326 +++++++-------------------- 8 files changed, 1010 insertions(+), 273 deletions(-) create mode 100644 arch/mips/mm/uasm-micromips.c create mode 100644 arch/mips/mm/uasm-mips.c -- 1.7.9.5 From sjhill@mips.com Tue Feb 5 23:52:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 23:52:37 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:49914 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823099Ab3BEWwSBeB50 (ORCPT ); Tue, 5 Feb 2013 23:52:18 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1U2rN4-0008Ky-1q; Tue, 05 Feb 2013 16:52:10 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com, ddaney.cavm@gmail.com Subject: [PATCH 1/4] MIPS: microMIPS: Add instruction formats. Date: Tue, 5 Feb 2013 16:52:00 -0600 Message-Id: <1360104723-29529-2-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360104723-29529-1-git-send-email-sjhill@mips.com> References: <1360104723-29529-1-git-send-email-sjhill@mips.com> X-archive-position: 35709 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 13396 Lines: 494 From: "Steven J. Hill" Add structures for all the microMIPS instructions. Also add the enumerations for all the bit fields for opcodes, functions, etc. Signed-off-by: Steven J. Hill --- arch/mips/include/uapi/asm/inst.h | 449 +++++++++++++++++++++++++++++++++++++ 1 file changed, 449 insertions(+) diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index 50b3d12..6a7f02f8 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -7,6 +7,7 @@ * * Copyright (C) 1996, 2000 by Ralf Baechle * Copyright (C) 2006 by Thiemo Seufer + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #ifndef _UAPI_ASM_INST_H #define _UAPI_ASM_INST_H @@ -193,6 +194,236 @@ enum lx_func { }; /* + * (microMIPS) Major opcodes. + */ +enum mm_major_op { + mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, + mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, + mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, + mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, + mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, + mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, + mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, + mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, + mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, + mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, + mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, + mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, + mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, + mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, + mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, + mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, +}; + +/* + * (microMIPS) POOL32I minor opcodes. + */ +enum mm_32i_minor_op { + mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, + mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, + mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, + mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, + mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, + mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, + mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, + mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, + mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, +}; + +/* + * (microMIPS) POOL32A minor opcodes. + */ +enum mm_32a_minor_op { + mm_sll32_op = 0x000, + mm_ins_op = 0x00c, + mm_ext_op = 0x02c, + mm_pool32axf_op = 0x03c, + mm_srl32_op = 0x040, + mm_sra_op = 0x080, + mm_rotr_op = 0x0c0, + mm_lwxs_op = 0x118, + mm_addu32_op = 0x150, + mm_subu32_op = 0x1d0, + mm_and_op = 0x250, + mm_or32_op = 0x290, + mm_xor32_op = 0x310, +}; + +/* + * (microMIPS) POOL32B functions. + */ +enum mm_32b_func { + mm_lwc2_func = 0x0, + mm_lwp_func = 0x1, + mm_ldc2_func = 0x2, + mm_ldp_func = 0x4, + mm_lwm32_func = 0x5, + mm_cache_func = 0x6, + mm_ldm_func = 0x7, + mm_swc2_func = 0x8, + mm_swp_func = 0x9, + mm_sdc2_func = 0xa, + mm_sdp_func = 0xc, + mm_swm32_func = 0xd, + mm_sdm_func = 0xf, +}; + +/* + * (microMIPS) POOL32C functions. + */ +enum mm_32c_func { + mm_pref_func = 0x2, + mm_ll_func = 0x3, + mm_swr_func = 0x9, + mm_sc_func = 0xb, + mm_lwu_func = 0xe, +}; + +/* + * (microMIPS) POOL32AXF minor opcodes. + */ +enum mm_32axf_minor_op { + mm_mfc0_op = 0x003, + mm_mtc0_op = 0x00b, + mm_tlbp_op = 0x00d, + mm_jalr_op = 0x03c, + mm_tlbr_op = 0x04d, + mm_jalrhb_op = 0x07c, + mm_tlbwi_op = 0x08d, + mm_tlbwr_op = 0x0cd, + mm_jalrs_op = 0x13c, + mm_jalrshb_op = 0x17c, + mm_syscall_op = 0x22d, + mm_eret_op = 0x3cd, +}; + +/* + * (microMIPS) POOL32F minor opcodes. + */ +enum mm_32f_minor_op { + mm_32f_00_op = 0x00, + mm_32f_01_op = 0x01, + mm_32f_02_op = 0x02, + mm_32f_10_op = 0x08, + mm_32f_11_op = 0x09, + mm_32f_12_op = 0x0a, + mm_32f_20_op = 0x10, + mm_32f_30_op = 0x18, + mm_32f_40_op = 0x20, + mm_32f_41_op = 0x21, + mm_32f_42_op = 0x22, + mm_32f_50_op = 0x28, + mm_32f_51_op = 0x29, + mm_32f_52_op = 0x2a, + mm_32f_60_op = 0x30, + mm_32f_70_op = 0x38, + mm_32f_73_op = 0x3b, + mm_32f_74_op = 0x3c, +}; + +/* + * (microMIPS) POOL32F secondary minor opcodes. + */ +enum mm_32f_10_minor_op { + mm_lwxc1_op = 0x1, + mm_swxc1_op, + mm_ldxc1_op, + mm_sdxc1_op, + mm_luxc1_op, + mm_suxc1_op, +}; + +enum mm_32f_func { + mm_lwxc1_func = 0x048, + mm_swxc1_func = 0x088, + mm_ldxc1_func = 0x0c8, + mm_sdxc1_func = 0x108, +}; + +/* + * (microMIPS) POOL32F secondary minor opcodes. + */ +enum mm_32f_40_minor_op { + mm_fmovf_op, + mm_fmovt_op, +}; + +/* + * (microMIPS) POOL32F secondary minor opcodes. + */ +enum mm_32f_60_minor_op { + mm_fadd_op, + mm_fsub_op, + mm_fmul_op, + mm_fdiv_op, +}; + +/* + * (microMIPS) POOL32F secondary minor opcodes. + */ +enum mm_32f_70_minor_op { + mm_fmovn_op, + mm_fmovz_op, +}; + +/* + * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. + */ +enum mm_32f_73_minor_op { + mm_fmov0_op = 0x01, + mm_fcvtl_op = 0x04, + mm_movf0_op = 0x05, + mm_frsqrt_op = 0x08, + mm_ffloorl_op = 0x0c, + mm_fabs0_op = 0x0d, + mm_fcvtw_op = 0x24, + mm_movt0_op = 0x25, + mm_fsqrt_op = 0x28, + mm_ffloorw_op = 0x2c, + mm_fneg0_op = 0x2d, + mm_cfc1_op = 0x40, + mm_frecip_op = 0x48, + mm_fceill_op = 0x4c, + mm_fcvtd0_op = 0x4d, + mm_ctc1_op = 0x60, + mm_fceilw_op = 0x6c, + mm_fcvts0_op = 0x6d, + mm_mfc1_op = 0x80, + mm_fmov1_op = 0x81, + mm_movf1_op = 0x85, + mm_ftruncl_op = 0x8c, + mm_fabs1_op = 0x8d, + mm_mtc1_op = 0xa0, + mm_movt1_op = 0xa5, + mm_ftruncw_op = 0xac, + mm_fneg1_op = 0xad, + mm_froundl_op = 0xcc, + mm_fcvtd1_op = 0xcd, + mm_froundw_op = 0xec, + mm_fcvts1_op = 0xed, +}; + +/* + * (microMIPS) POOL16C minor opcodes. + */ +enum mm_16c_minor_op { + mm_lwm16_op = 0x04, + mm_swm16_op = 0x05, + mm_jr16_op = 0x18, + mm_jrc_op = 0x1a, + mm_jalr16_op = 0x1c, + mm_jalrs16_op = 0x1e, +}; + +/* + * (microMIPS) POOL16D minor opcodes. + */ +enum mm_16d_minor_op { + mm_addius5_func, + mm_addiusp_func, +}; + +/* * Damn ... bitfields depend from byteorder :-( */ #ifdef __MIPSEB__ @@ -311,6 +542,204 @@ struct v_format { /* MDMX vector format */ ;))))))) }; +/* + * microMIPS instruction formats (32-bit length) + * + * NOTE: + * Parenthesis denote whether the format is a microMIPS instruction or + * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. + */ +struct fb_format { /* FPU branch format (MIPS32) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int bc : 5, + BITFIELD_FIELD(unsigned int cc : 3, + BITFIELD_FIELD(unsigned int flag : 2, + BITFIELD_FIELD(signed int simmediate : 16, + ;))))) +}; + +struct fp0_format { /* FPU multiply and add format (MIPS32) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int fmt : 5, + BITFIELD_FIELD(unsigned int ft : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int fd : 5, + BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int ft : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int fd : 5, + BITFIELD_FIELD(unsigned int fmt : 3, + BITFIELD_FIELD(unsigned int op : 2, + BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int op : 5, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int fd : 5, + BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int fmt : 2, + BITFIELD_FIELD(unsigned int op : 8, + BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int fd : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int cc : 3, + BITFIELD_FIELD(unsigned int zero : 2, + BITFIELD_FIELD(unsigned int fmt : 2, + BITFIELD_FIELD(unsigned int op : 3, + BITFIELD_FIELD(unsigned int func : 6, + ;)))))))) +}; + +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int fmt : 3, + BITFIELD_FIELD(unsigned int op : 7, + BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int cc : 3, + BITFIELD_FIELD(unsigned int fmt : 3, + BITFIELD_FIELD(unsigned int cond : 4, + BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int index : 5, + BITFIELD_FIELD(unsigned int base : 5, + BITFIELD_FIELD(unsigned int fd : 5, + BITFIELD_FIELD(unsigned int op : 5, + BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int fr : 5, + BITFIELD_FIELD(unsigned int ft : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int fd : 5, + BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int ft : 5, + BITFIELD_FIELD(unsigned int fs : 5, + BITFIELD_FIELD(unsigned int fd : 5, + BITFIELD_FIELD(unsigned int fr : 5, + BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_i_format { /* Immediate format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(unsigned int rs : 5, + BITFIELD_FIELD(signed int simmediate : 16, + ;)))) +}; + +struct mm_m_format { /* Multi-word load/store format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rd : 5, + BITFIELD_FIELD(unsigned int base : 5, + BITFIELD_FIELD(unsigned int func : 4, + BITFIELD_FIELD(signed int simmediate : 12, + ;))))) +}; + +struct mm_x_format { /* Scaled indexed load format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int index : 5, + BITFIELD_FIELD(unsigned int base : 5, + BITFIELD_FIELD(unsigned int rd : 5, + BITFIELD_FIELD(unsigned int func : 11, + ;))))) +}; + +/* + * microMIPS instruction formats (16-bit length) + */ +struct mm_b0_format { /* Unconditional branch format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(signed int simmediate : 10, + BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;))) +}; + +struct mm_b1_format { /* Conditional branch format (microMIPS) */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rs : 3, + BITFIELD_FIELD(signed int simmediate : 7, + BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;)))) +}; + +struct mm16_m_format { /* Multi-word load/store format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int func : 4, + BITFIELD_FIELD(unsigned int rlist : 2, + BITFIELD_FIELD(unsigned int imm : 4, + BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;))))) +}; + +struct mm16_rb_format { /* Signed immediate format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rt : 3, + BITFIELD_FIELD(unsigned int base : 3, + BITFIELD_FIELD(signed int simmediate : 4, + BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;))))) +}; + +struct mm16_r3_format { /* Load from global pointer format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rt : 3, + BITFIELD_FIELD(signed int simmediate : 7, + BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;)))) +}; + +struct mm16_r5_format { /* Load/store from stack pointer format */ + BITFIELD_FIELD(unsigned int opcode : 6, + BITFIELD_FIELD(unsigned int rt : 5, + BITFIELD_FIELD(signed int simmediate : 5, + BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;)))) +}; + union mips_instruction { unsigned int word; unsigned short halfword[2]; @@ -325,6 +754,26 @@ union mips_instruction { struct b_format b_format; struct ps_format ps_format; struct v_format v_format; + struct fb_format fb_format; + struct fp0_format fp0_format; + struct mm_fp0_format mm_fp0_format; + struct fp1_format fp1_format; + struct mm_fp1_format mm_fp1_format; + struct mm_fp2_format mm_fp2_format; + struct mm_fp3_format mm_fp3_format; + struct mm_fp4_format mm_fp4_format; + struct mm_fp5_format mm_fp5_format; + struct fp6_format fp6_format; + struct mm_fp6_format mm_fp6_format; + struct mm_i_format mm_i_format; + struct mm_m_format mm_m_format; + struct mm_x_format mm_x_format; + struct mm_b0_format mm_b0_format; + struct mm_b1_format mm_b1_format; + struct mm16_m_format mm16_m_format ; + struct mm16_rb_format mm16_rb_format; + struct mm16_r3_format mm16_r3_format; + struct mm16_r5_format mm16_r5_format; }; #endif /* _UAPI_ASM_INST_H */ -- 1.7.9.5 From sjhill@mips.com Tue Feb 5 23:52:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 23:52:59 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:49919 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824757Ab3BEWwSZjLb0 (ORCPT ); Tue, 5 Feb 2013 23:52:18 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1U2rN5-0008Ky-FW; Tue, 05 Feb 2013 16:52:11 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com, ddaney.cavm@gmail.com Subject: [PATCH 2/4] MIPS: microMIPS: uasm: Split 'uasm.c' into two files. Date: Tue, 5 Feb 2013 16:52:01 -0600 Message-Id: <1360104723-29529-3-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360104723-29529-1-git-send-email-sjhill@mips.com> References: <1360104723-29529-1-git-send-email-sjhill@mips.com> X-archive-position: 35710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 31296 Lines: 905 From: "Steven J. Hill" Split 'uasm.c' into two files. The new file 'uasm-mips.c' has the functions specific to the classic MIPS ISA. The 'uasm.c' file contains common code that can be used by classic or other ISAs that could be supported by the kernel. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/uasm.h | 62 ++++---- arch/mips/mm/Makefile | 2 +- arch/mips/mm/uasm-mips.c | 196 +++++++++++++++++++++++++ arch/mips/mm/uasm.c | 326 ++++++++++-------------------------------- 4 files changed, 313 insertions(+), 273 deletions(-) create mode 100644 arch/mips/mm/uasm-mips.c diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 058e941..f7d8f15 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -6,7 +6,7 @@ * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer * Copyright (C) 2005 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2012 MIPS Technologies, Inc. + * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. */ #include @@ -22,44 +22,57 @@ #define UASM_EXPORT_SYMBOL(sym) #endif +#define _UASM_ISA_CLASSIC 0 + +#ifndef UASM_ISA +#define UASM_ISA _UASM_ISA_CLASSIC +#endif + +#if (UASM_ISA == _UASM_ISA_CLASSIC) +#define ISAOPC(op) uasm_i##op +#define ISAFUNC(x) x +#else +#error Unsupported micro-assembler ISA!!! +#endif + #define Ip_u1u2u3(op) \ void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) +ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) #define Ip_u2u1u3(op) \ void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) +ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) #define Ip_u3u1u2(op) \ void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) +ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) #define Ip_u1u2s3(op) \ void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) +ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) #define Ip_u2s3u1(op) \ void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) +ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c) #define Ip_u2u1s3(op) \ void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) +ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) #define Ip_u2u1msbu3(op) \ void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ +ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ unsigned int d) #define Ip_u1u2(op) \ -void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) +void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) #define Ip_u1s2(op) \ -void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b) +void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, signed int b) -#define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a) +#define Ip_u1(op) void __uasminit ISAOPC(op)(u32 **buf, unsigned int a) -#define Ip_0(op) void __uasminit uasm_i##op(u32 **buf) +#define Ip_0(op) void __uasminit ISAOPC(op)(u32 **buf) Ip_u2u1s3(_addiu); Ip_u3u1u2(_addu); @@ -132,14 +145,15 @@ struct uasm_label { int lab; }; -void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid); +void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, + int lid); #ifdef CONFIG_64BIT -int uasm_in_compat_space_p(long addr); +int ISAFUNC(uasm_in_compat_space_p)(long addr); #endif -int uasm_rel_hi(long val); -int uasm_rel_lo(long val); -void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); -void UASM_i_LA(u32 **buf, unsigned int rs, long addr); +int ISAFUNC(uasm_rel_hi)(long val); +int ISAFUNC(uasm_rel_lo)(long val); +void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr); +void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr); #define UASM_L_LA(lb) \ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ @@ -196,27 +210,27 @@ static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1, unsigned int a2, unsigned int a3) { if (a3 < 32) - uasm_i_drotr(p, a1, a2, a3); + ISAOPC(_drotr)(p, a1, a2, a3); else - uasm_i_drotr32(p, a1, a2, a3 - 32); + ISAOPC(_drotr32)(p, a1, a2, a3 - 32); } static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, unsigned int a2, unsigned int a3) { if (a3 < 32) - uasm_i_dsll(p, a1, a2, a3); + ISAOPC(_dsll)(p, a1, a2, a3); else - uasm_i_dsll32(p, a1, a2, a3 - 32); + ISAOPC(_dsll32)(p, a1, a2, a3 - 32); } static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1, unsigned int a2, unsigned int a3) { if (a3 < 32) - uasm_i_dsrl(p, a1, a2, a3); + ISAOPC(_dsrl)(p, a1, a2, a3); else - uasm_i_dsrl32(p, a1, a2, a3 - 32); + ISAOPC(_dsrl32)(p, a1, a2, a3 - 32); } /* Handle relocations. */ diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 1dcec30..9e90c21 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -4,7 +4,7 @@ obj-y += cache.o dma-default.o extable.o fault.o \ gup.o init.o mmap.o page.o page-funcs.o \ - tlbex.o tlbex-fault.o uasm.o + tlbex.o tlbex-fault.o uasm-mips.o obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o obj-$(CONFIG_64BIT) += pgtable-64.o diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c new file mode 100644 index 0000000..e78e74d --- /dev/null +++ b/arch/mips/mm/uasm-mips.c @@ -0,0 +1,196 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * A small micro-assembler. It is intentionally kept simple, does only + * support a subset of instructions, and does not try to hide pipeline + * effects like branch delay slots. + * + * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer + * Copyright (C) 2005, 2007 Maciej W. Rozycki + * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#define RS_MASK 0x1f +#define RS_SH 21 +#define RT_MASK 0x1f +#define RT_SH 16 +#define SCIMM_MASK 0xfffff +#define SCIMM_SH 6 + +/* This macro sets the non-variable bits of an instruction. */ +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RS_SH \ + | (c) << RT_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) + +#include "uasm.c" + +static struct insn insn_table[] __uasminitdata = { + { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, + { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, + { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, + { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, + { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, + { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, + { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, + { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, + { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, + { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, + { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, + { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, + { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, + { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, + { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, + { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, + { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, + { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, + { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, + { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, + { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, + { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, + { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, + { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, + { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, + { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, + { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, + { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, + { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, + { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, + { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, + { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, + { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, + { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, + { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, + { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, + { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, + { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, + { insn_invalid, 0, 0 } +}; + +#undef M + +static inline __uasminit u32 build_bimm(s32 arg) +{ + WARN(arg > 0x1ffff || arg < -0x20000, + KERN_WARNING "Micro-assembler field overflow\n"); + + WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); + + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); +} + +static inline __uasminit u32 build_jimm(u32 arg) +{ + WARN(arg & ~(JIMM_MASK << 2), + KERN_WARNING "Micro-assembler field overflow\n"); + + return (arg >> 2) & JIMM_MASK; +} + +/* + * The order of opcode arguments is implicitly left to right, + * starting with RS and ending with FUNC or IMM. + */ +static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) +{ + struct insn *ip = NULL; + unsigned int i; + va_list ap; + u32 op; + + for (i = 0; insn_table[i].opcode != insn_invalid; i++) + if (insn_table[i].opcode == opc) { + ip = &insn_table[i]; + break; + } + + if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) + panic("Unsupported Micro-assembler instruction %d", opc); + + op = ip->match; + va_start(ap, opc); + if (ip->fields & RS) + op |= build_rs(va_arg(ap, u32)); + if (ip->fields & RT) + op |= build_rt(va_arg(ap, u32)); + if (ip->fields & RD) + op |= build_rd(va_arg(ap, u32)); + if (ip->fields & RE) + op |= build_re(va_arg(ap, u32)); + if (ip->fields & SIMM) + op |= build_simm(va_arg(ap, s32)); + if (ip->fields & UIMM) + op |= build_uimm(va_arg(ap, u32)); + if (ip->fields & BIMM) + op |= build_bimm(va_arg(ap, s32)); + if (ip->fields & JIMM) + op |= build_jimm(va_arg(ap, u32)); + if (ip->fields & FUNC) + op |= build_func(va_arg(ap, u32)); + if (ip->fields & SET) + op |= build_set(va_arg(ap, u32)); + if (ip->fields & SCIMM) + op |= build_scimm(va_arg(ap, u32)); + va_end(ap); + + **buf = op; + (*buf)++; +} + +static inline void __uasminit +__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) +{ + long laddr = (long)lab->addr; + long raddr = (long)rel->addr; + + switch (rel->type) { + case R_MIPS_PC16: + *rel->addr |= build_bimm(laddr - (raddr + 4)); + break; + + default: + panic("Unsupported Micro-assembler relocation %d", + rel->type); + } +} diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 942ff6c..7eb5e43 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -10,17 +10,9 @@ * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer * Copyright (C) 2005, 2007 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. */ -#include -#include -#include - -#include -#include -#include -#include - enum fields { RS = 0x001, RT = 0x002, @@ -37,10 +29,6 @@ enum fields { #define OP_MASK 0x3f #define OP_SH 26 -#define RS_MASK 0x1f -#define RS_SH 21 -#define RT_MASK 0x1f -#define RT_SH 16 #define RD_MASK 0x1f #define RD_SH 11 #define RE_MASK 0x1f @@ -53,8 +41,6 @@ enum fields { #define FUNC_SH 0 #define SET_MASK 0x7 #define SET_SH 0 -#define SCIMM_MASK 0xfffff -#define SCIMM_SH 6 enum opcode { insn_invalid, @@ -77,85 +63,6 @@ struct insn { enum fields fields; }; -/* This macro sets the non-variable bits of an instruction. */ -#define M(a, b, c, d, e, f) \ - ((a) << OP_SH \ - | (b) << RS_SH \ - | (c) << RT_SH \ - | (d) << RD_SH \ - | (e) << RE_SH \ - | (f) << FUNC_SH) - -static struct insn insn_table[] __uasminitdata = { - { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, - { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, - { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, - { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, - { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, - { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, - { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, - { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, - { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, - { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, - { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, - { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, - { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, - { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, - { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, - { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, - { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, - { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, - { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, - { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, - { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, - { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, - { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, - { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, - { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, - { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, - { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, - { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, - { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, - { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, - { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, - { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, - { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, - { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, - { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, - { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, - { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, - { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, - { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, - { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, - { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, - { insn_invalid, 0, 0 } -}; - -#undef M - static inline __uasminit u32 build_rs(u32 arg) { WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); @@ -199,24 +106,6 @@ static inline __uasminit u32 build_uimm(u32 arg) return arg & IMM_MASK; } -static inline __uasminit u32 build_bimm(s32 arg) -{ - WARN(arg > 0x1ffff || arg < -0x20000, - KERN_WARNING "Micro-assembler field overflow\n"); - - WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); - - return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); -} - -static inline __uasminit u32 build_jimm(u32 arg) -{ - WARN(arg & ~(JIMM_MASK << 2), - KERN_WARNING "Micro-assembler field overflow\n"); - - return (arg >> 2) & JIMM_MASK; -} - static inline __uasminit u32 build_scimm(u32 arg) { WARN(arg & ~SCIMM_MASK, @@ -239,55 +128,7 @@ static inline __uasminit u32 build_set(u32 arg) return arg & SET_MASK; } -/* - * The order of opcode arguments is implicitly left to right, - * starting with RS and ending with FUNC or IMM. - */ -static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) -{ - struct insn *ip = NULL; - unsigned int i; - va_list ap; - u32 op; - - for (i = 0; insn_table[i].opcode != insn_invalid; i++) - if (insn_table[i].opcode == opc) { - ip = &insn_table[i]; - break; - } - - if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) - panic("Unsupported Micro-assembler instruction %d", opc); - - op = ip->match; - va_start(ap, opc); - if (ip->fields & RS) - op |= build_rs(va_arg(ap, u32)); - if (ip->fields & RT) - op |= build_rt(va_arg(ap, u32)); - if (ip->fields & RD) - op |= build_rd(va_arg(ap, u32)); - if (ip->fields & RE) - op |= build_re(va_arg(ap, u32)); - if (ip->fields & SIMM) - op |= build_simm(va_arg(ap, s32)); - if (ip->fields & UIMM) - op |= build_uimm(va_arg(ap, u32)); - if (ip->fields & BIMM) - op |= build_bimm(va_arg(ap, s32)); - if (ip->fields & JIMM) - op |= build_jimm(va_arg(ap, u32)); - if (ip->fields & FUNC) - op |= build_func(va_arg(ap, u32)); - if (ip->fields & SET) - op |= build_set(va_arg(ap, u32)); - if (ip->fields & SCIMM) - op |= build_scimm(va_arg(ap, u32)); - va_end(ap); - - **buf = op; - (*buf)++; -} +static void __uasminit build_insn(u32 **buf, enum opcode opc, ...); #define I_u1u2u3(op) \ Ip_u1u2u3(op) \ @@ -445,7 +286,7 @@ I_u3u1u2(_ldx) #ifdef CONFIG_CPU_CAVIUM_OCTEON #include -void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b, +void __uasminit ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, unsigned int c) { if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) @@ -457,21 +298,21 @@ void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b, else build_insn(buf, insn_pref, c, a, b); } -UASM_EXPORT_SYMBOL(uasm_i_pref); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref)); #else I_u2s3u1(_pref) #endif /* Handle labels. */ -void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) +void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) { (*lab)->addr = addr; (*lab)->lab = lid; (*lab)++; } -UASM_EXPORT_SYMBOL(uasm_build_label); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); -int __uasminit uasm_in_compat_space_p(long addr) +int __uasminit ISAFUNC(uasm_in_compat_space_p)(long addr) { /* Is this address in 32bit compat space? */ #ifdef CONFIG_64BIT @@ -480,7 +321,7 @@ int __uasminit uasm_in_compat_space_p(long addr) return 1; #endif } -UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); static int __uasminit uasm_rel_highest(long val) { @@ -500,77 +341,66 @@ static int __uasminit uasm_rel_higher(long val) #endif } -int __uasminit uasm_rel_hi(long val) +int __uasminit ISAFUNC(uasm_rel_hi)(long val) { return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; } -UASM_EXPORT_SYMBOL(uasm_rel_hi); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); -int __uasminit uasm_rel_lo(long val) +int __uasminit ISAFUNC(uasm_rel_lo)(long val) { return ((val & 0xffff) ^ 0x8000) - 0x8000; } -UASM_EXPORT_SYMBOL(uasm_rel_lo); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); -void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) +void __uasminit ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) { - if (!uasm_in_compat_space_p(addr)) { - uasm_i_lui(buf, rs, uasm_rel_highest(addr)); + if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { + ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); if (uasm_rel_higher(addr)) - uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr)); - if (uasm_rel_hi(addr)) { - uasm_i_dsll(buf, rs, rs, 16); - uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr)); - uasm_i_dsll(buf, rs, rs, 16); + ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr)); + if (ISAFUNC(uasm_rel_hi(addr))) { + ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); + ISAFUNC(uasm_i_daddiu)(buf, rs, rs, + ISAFUNC(uasm_rel_hi)(addr)); + ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); } else - uasm_i_dsll32(buf, rs, rs, 0); + ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0); } else - uasm_i_lui(buf, rs, uasm_rel_hi(addr)); + ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr))); } -UASM_EXPORT_SYMBOL(UASM_i_LA_mostly); +UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); -void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr) +void __uasminit ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) { - UASM_i_LA_mostly(buf, rs, addr); - if (uasm_rel_lo(addr)) { - if (!uasm_in_compat_space_p(addr)) - uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr)); + ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); + if (ISAFUNC(uasm_rel_lo(addr))) { + if (!ISAFUNC(uasm_in_compat_space_p)(addr)) + ISAFUNC(uasm_i_daddiu)(buf, rs, rs, + ISAFUNC(uasm_rel_lo(addr))); else - uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr)); + ISAFUNC(uasm_i_addiu)(buf, rs, rs, + ISAFUNC(uasm_rel_lo(addr))); } } -UASM_EXPORT_SYMBOL(UASM_i_LA); +UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); /* Handle relocations. */ void __uasminit -uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) +ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid) { (*rel)->addr = addr; (*rel)->type = R_MIPS_PC16; (*rel)->lab = lid; (*rel)++; } -UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); static inline void __uasminit -__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) -{ - long laddr = (long)lab->addr; - long raddr = (long)rel->addr; - - switch (rel->type) { - case R_MIPS_PC16: - *rel->addr |= build_bimm(laddr - (raddr + 4)); - break; - - default: - panic("Unsupported Micro-assembler relocation %d", - rel->type); - } -} +__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab); void __uasminit -uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) +ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, struct uasm_label *lab) { struct uasm_label *l; @@ -579,40 +409,40 @@ uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) if (rel->lab == l->lab) __resolve_relocs(rel, l); } -UASM_EXPORT_SYMBOL(uasm_resolve_relocs); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); void __uasminit -uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off) +ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, long off) { for (; rel->lab != UASM_LABEL_INVALID; rel++) if (rel->addr >= first && rel->addr < end) rel->addr += off; } -UASM_EXPORT_SYMBOL(uasm_move_relocs); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); void __uasminit -uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off) +ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, long off) { for (; lab->lab != UASM_LABEL_INVALID; lab++) if (lab->addr >= first && lab->addr < end) lab->addr += off; } -UASM_EXPORT_SYMBOL(uasm_move_labels); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); void __uasminit -uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first, +ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first, u32 *end, u32 *target) { long off = (long)(target - first); memcpy(target, first, (end - first) * sizeof(u32)); - uasm_move_relocs(rel, first, end, off); - uasm_move_labels(lab, first, end, off); + ISAFUNC(uasm_move_relocs(rel, first, end, off)); + ISAFUNC(uasm_move_labels(lab, first, end, off)); } -UASM_EXPORT_SYMBOL(uasm_copy_handler); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); -int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) +int __uasminit ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) { for (; rel->lab != UASM_LABEL_INVALID; rel++) { if (rel->addr == addr @@ -623,88 +453,88 @@ int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) return 0; } -UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); /* Convenience functions for labeled branches. */ void __uasminit -uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) +ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_bltz(p, reg, 0); + ISAFUNC(uasm_i_bltz)(p, reg, 0); } -UASM_EXPORT_SYMBOL(uasm_il_bltz); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); void __uasminit -uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) +ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_b(p, 0); + ISAFUNC(uasm_i_b)(p, 0); } -UASM_EXPORT_SYMBOL(uasm_il_b); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); void __uasminit -uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) +ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_beqz(p, reg, 0); + ISAFUNC(uasm_i_beqz)(p, reg, 0); } -UASM_EXPORT_SYMBOL(uasm_il_beqz); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); void __uasminit -uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) +ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_beqzl(p, reg, 0); + ISAFUNC(uasm_i_beqzl)(p, reg, 0); } -UASM_EXPORT_SYMBOL(uasm_il_beqzl); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); void __uasminit -uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, +ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, unsigned int reg2, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_bne(p, reg1, reg2, 0); + ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); } -UASM_EXPORT_SYMBOL(uasm_il_bne); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); void __uasminit -uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) +ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_bnez(p, reg, 0); + ISAFUNC(uasm_i_bnez)(p, reg, 0); } -UASM_EXPORT_SYMBOL(uasm_il_bnez); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); void __uasminit -uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) +ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_bgezl(p, reg, 0); + ISAFUNC(uasm_i_bgezl)(p, reg, 0); } -UASM_EXPORT_SYMBOL(uasm_il_bgezl); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); void __uasminit -uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) +ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_bgez(p, reg, 0); + ISAFUNC(uasm_i_bgez)(p, reg, 0); } -UASM_EXPORT_SYMBOL(uasm_il_bgez); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); void __uasminit -uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, +ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, unsigned int bit, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_bbit0(p, reg, bit, 0); + ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); } -UASM_EXPORT_SYMBOL(uasm_il_bbit0); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); void __uasminit -uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, +ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, unsigned int bit, int lid) { uasm_r_mips_pc16(r, *p, lid); - uasm_i_bbit1(p, reg, bit, 0); + ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); } -UASM_EXPORT_SYMBOL(uasm_il_bbit1); +UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1)); -- 1.7.9.5 From sjhill@mips.com Tue Feb 5 23:52:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 23:53:20 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:49920 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824761Ab3BEWwSmiYHS (ORCPT ); Tue, 5 Feb 2013 23:52:18 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1U2rN6-0008Ky-6k; Tue, 05 Feb 2013 16:52:12 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com, ddaney.cavm@gmail.com Subject: [PATCH 3/4] MIPS: microMIPS: uasm: Add microMIPS micro assembler support. Date: Tue, 5 Feb 2013 16:52:02 -0600 Message-Id: <1360104723-29529-4-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360104723-29529-1-git-send-email-sjhill@mips.com> References: <1360104723-29529-1-git-send-email-sjhill@mips.com> X-archive-position: 35711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 9886 Lines: 299 From: "Steven J. Hill" Add new file 'uasm-micromips.c' that allows the micro assembler to generate microMIPS ISA code. It can be included in the kernel alongside the classic ISA as long as the platform supports the microMIPS ISA. Signed-off-by: Steven J. Hill --- arch/mips/Kconfig | 4 + arch/mips/include/asm/uasm.h | 4 + arch/mips/mm/Makefile | 2 + arch/mips/mm/uasm-micromips.c | 220 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 230 insertions(+) create mode 100644 arch/mips/mm/uasm-micromips.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 47e3310..95ecc0a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -351,6 +351,7 @@ config MIPS_SEAD3 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_SMARTMIPS + select SYS_SUPPORTS_MICROMIPS select USB_ARCH_HAS_EHCI select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO @@ -2117,6 +2118,9 @@ config SYS_SUPPORTS_HIGHMEM config SYS_SUPPORTS_SMARTMIPS bool +config SYS_SUPPORTS_MICROMIPS + bool + config ARCH_FLATMEM_ENABLE def_bool y depends on !NUMA && !CPU_LOONGSON2 diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index f7d8f15..f924b87 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -23,6 +23,7 @@ #endif #define _UASM_ISA_CLASSIC 0 +#define _UASM_ISA_MICROMIPS 1 #ifndef UASM_ISA #define UASM_ISA _UASM_ISA_CLASSIC @@ -31,6 +32,9 @@ #if (UASM_ISA == _UASM_ISA_CLASSIC) #define ISAOPC(op) uasm_i##op #define ISAFUNC(x) x +#elif (UASM_ISA == _UASM_ISA_MICROMIPS) +#define ISAOPC(op) MM_uasm_i##op +#define ISAFUNC(x) MM_##x #else #error Unsupported micro-assembler ISA!!! #endif diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 9e90c21..e87aae1 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -22,3 +22,5 @@ obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o + +obj-$(CONFIG_SYS_SUPPORTS_MICROMIPS) += uasm-micromips.o diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c new file mode 100644 index 0000000..476d50c --- /dev/null +++ b/arch/mips/mm/uasm-micromips.c @@ -0,0 +1,220 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * A small micro-assembler. It is intentionally kept simple, does only + * support a subset of instructions, and does not try to hide pipeline + * effects like branch delay slots. + * + * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer + * Copyright (C) 2005, 2007 Maciej W. Rozycki + * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. + */ + +#include +#include +#include + +#include +#include +#include +#define UASM_ISA _UASM_ISA_MICROMIPS +#include + +#define RS_MASK 0x1f +#define RS_SH 16 +#define RT_MASK 0x1f +#define RT_SH 21 +#define SCIMM_MASK 0x3ff +#define SCIMM_SH 16 + +/* This macro sets the non-variable bits of an instruction. */ +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RT_SH \ + | (c) << RS_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) + +/* Define these when we are not the ISA the kernel is being compiled with. */ +#ifndef CONFIG_CPU_MICROMIPS +#define MM_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off) +#define MM_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off) +#define MM_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off) +#define MM_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off) +#endif + +#include "uasm.c" + +static struct insn insn_table_MM[] __uasminitdata = { + { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, + { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, + { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_beql, 0, 0 }, + { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM }, + { insn_bgezl, 0, 0 }, + { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM }, + { insn_bltzl, 0, 0 }, + { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, + { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, + { insn_daddu, 0, 0 }, + { insn_daddiu, 0, 0 }, + { insn_dmfc0, 0, 0 }, + { insn_dmtc0, 0, 0 }, + { insn_dsll, 0, 0 }, + { insn_dsll32, 0, 0 }, + { insn_dsra, 0, 0 }, + { insn_dsrl, 0, 0 }, + { insn_dsrl32, 0, 0 }, + { insn_drotr, 0, 0 }, + { insn_drotr32, 0, 0 }, + { insn_dsubu, 0, 0 }, + { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 }, + { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE }, + { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE }, + { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM }, + { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS }, + { insn_ld, 0, 0 }, + { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM }, + { insn_lld, 0, 0 }, + { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, + { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, + { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM }, + { insn_rfe, 0, 0 }, + { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM }, + { insn_scd, 0, 0 }, + { insn_sd, 0, 0 }, + { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD }, + { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD }, + { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD }, + { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, + { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, + { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, + { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, + { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, + { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, + { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 }, + { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD }, + { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, + { insn_dins, 0, 0 }, + { insn_dinsm, 0, 0 }, + { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM}, + { insn_bbit0, 0, 0 }, + { insn_bbit1, 0, 0 }, + { insn_lwx, 0, 0 }, + { insn_ldx, 0, 0 }, + { insn_invalid, 0, 0 } +}; + +#undef M + +static inline __uasminit u32 build_bimm(s32 arg) +{ + WARN(arg > 0xffff || arg < -0x10000, + KERN_WARNING "Micro-assembler field overflow\n"); + + WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); + + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff); +} + +static inline __uasminit u32 build_jimm(u32 arg) +{ + WARN(arg & ~(JIMM_MASK << 2), + KERN_WARNING "Micro-assembler field overflow\n"); + + return (arg >> 1) & JIMM_MASK; +} + +/* + * The order of opcode arguments is implicitly left to right, + * starting with RS and ending with FUNC or IMM. + */ +static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) +{ + struct insn *ip = NULL; + unsigned int i; + va_list ap; + u32 op; + + for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++) + if (insn_table_MM[i].opcode == opc) { + ip = &insn_table_MM[i]; + break; + } + + if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) + panic("Unsupported Micro-assembler instruction %d", opc); + + op = ip->match; + va_start(ap, opc); + if (ip->fields & RS) { + if (opc == insn_mfc0 || opc == insn_mtc0) + op |= build_rt(va_arg(ap, u32)); + else + op |= build_rs(va_arg(ap, u32)); + } + if (ip->fields & RT) { + if (opc == insn_mfc0 || opc == insn_mtc0) + op |= build_rs(va_arg(ap, u32)); + else + op |= build_rt(va_arg(ap, u32)); + } + if (ip->fields & RD) + op |= build_rd(va_arg(ap, u32)); + if (ip->fields & RE) + op |= build_re(va_arg(ap, u32)); + if (ip->fields & SIMM) + op |= build_simm(va_arg(ap, s32)); + if (ip->fields & UIMM) + op |= build_uimm(va_arg(ap, u32)); + if (ip->fields & BIMM) + op |= build_bimm(va_arg(ap, s32)); + if (ip->fields & JIMM) + op |= build_jimm(va_arg(ap, u32)); + if (ip->fields & FUNC) + op |= build_func(va_arg(ap, u32)); + if (ip->fields & SET) + op |= build_set(va_arg(ap, u32)); + if (ip->fields & SCIMM) + op |= build_scimm(va_arg(ap, u32)); + va_end(ap); + +#ifdef CONFIG_CPU_LITTLE_ENDIAN + **buf = ((op & 0xffff) << 16) | (op >> 16); +#else + **buf = op; +#endif + (*buf)++; +} + +static inline void __uasminit +__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) +{ + long laddr = (long)lab->addr; + long raddr = (long)rel->addr; + + switch (rel->type) { + case R_MIPS_PC16: +#ifdef CONFIG_CPU_LITTLE_ENDIAN + *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16); +#else + *rel->addr |= build_bimm(laddr - (raddr + 4)); +#endif + break; + + default: + panic("Unsupported Micro-assembler relocation %d", + rel->type); + } +} -- 1.7.9.5 From sjhill@mips.com Tue Feb 5 23:52:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Feb 2013 23:53:37 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:49923 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824764Ab3BEWwTHBA7C (ORCPT ); Tue, 5 Feb 2013 23:52:19 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1U2rN6-0008Ky-Sg; Tue, 05 Feb 2013 16:52:12 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com, ddaney.cavm@gmail.com Subject: [PATCH 4/4] MIPS: microMIPS: Add instruction utility macros. Date: Tue, 5 Feb 2013 16:52:03 -0600 Message-Id: <1360104723-29529-5-git-send-email-sjhill@mips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360104723-29529-1-git-send-email-sjhill@mips.com> References: <1360104723-29529-1-git-send-email-sjhill@mips.com> X-archive-position: 35712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@mips.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1342 Lines: 43 From: "Steven J. Hill" Add two new macros for microMIPS. One checks if an exception was taken in either microMIPS or classic MIPS mode. The other checks if a microMIPS instruction is 16-bit or 32-bit in length. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mipsregs.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index f206ef2..13e1d68 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -622,6 +622,24 @@ #ifndef __ASSEMBLY__ /* + * Macros for handling the ISA mode bit for microMIPS. + */ +#define get_isa16_mode(x) ((x) & 0x1) +#define msk_isa16_mode(x) ((x) & ~0x1) +#define set_isa16_mode(x) do { (x) |= 0x1; } while(0) + +/* + * microMIPS instructions can be 16-bit or 32-bit in length. This + * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. + */ +static inline int mm_insn_16bit(u16 insn) +{ + u16 opcode = (insn >> 10) & 0x7; + + return ((opcode >= 1 && opcode <= 3) ? 1 : 0); +} + +/* * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit * performance counter number encoded into bits 1 ... 5 of the instruction. -- 1.7.9.5 From gleb@redhat.com Wed Feb 6 13:08:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Feb 2013 13:08:32 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:43202 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817544Ab3BFMI36Q4um convert rfc822-to-8bit (ORCPT ); Wed, 6 Feb 2013 13:08:29 +0100 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r16C8Oa5029179 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 6 Feb 2013 07:08:25 -0500 Received: from dhcp-1-237.tlv.redhat.com (dhcp-4-26.tlv.redhat.com [10.35.4.26]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id r16C8LRK015845; Wed, 6 Feb 2013 07:08:22 -0500 Received: by dhcp-1-237.tlv.redhat.com (Postfix, from userid 13519) id 2A2D018D47A; Wed, 6 Feb 2013 14:08:21 +0200 (IST) Date: Wed, 6 Feb 2013 14:08:21 +0200 From: Gleb Natapov To: Sanjay Lal Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH v2 07/18] KVM/MIPS32: MMU/TLB operations for the Guest. Message-ID: <20130206120820.GN23213@redhat.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-8-git-send-email-sanjayl@kymasys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=cp1255 Content-Disposition: inline Content-Transfer-Encoding: 8BIT In-Reply-To: <1353551656-23579-8-git-send-email-sanjayl@kymasys.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-archive-position: 35713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gleb@redhat.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 28542 Lines: 986 On Wed, Nov 21, 2012 at 06:34:05PM -0800, Sanjay Lal wrote: > - Note that this file is statically linked with the rest of the host kernel (KSEG0). This is because kernel modules are > loaded into mapped space on MIPS and we want to make sure that we don't get any host kernel TLB faults while > manipulating TLBs. > - Virtual Guest TLBs are implemented as 64 entry array regardless of the number of host TLB entries. > - Shadow TLBs map Guest virtual addresses to Host physical addresses. > > - TLB miss handling details: > Guest KSEG0 TLBMISS (0x40000000 – 0x60000000): Transparent to the Guest. > Guest KSEG2/3 (0x60000000 – 0x80000000) & Guest UM TLBMISS (0x00000000 – 0x40000000) > Lookup in Guest/Virtual TLB > If an entry doesn’t match > deliver appropriate TLBMISS LD/ST exception to the guest > If entry does exist in the Guest TLB and is NOT Valid > Deliver TLB invalid exception to the guest > If entry does exist in the Guest TLB and is VALID > Inject the TLB entry into the Shadow TLB > > Signed-off-by: Sanjay Lal > --- > arch/mips/kvm/kvm_tlb.c | 932 ++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 932 insertions(+) > create mode 100644 arch/mips/kvm/kvm_tlb.c > > diff --git a/arch/mips/kvm/kvm_tlb.c b/arch/mips/kvm/kvm_tlb.c > new file mode 100644 > index 0000000..2d24333 > --- /dev/null > +++ b/arch/mips/kvm/kvm_tlb.c > @@ -0,0 +1,932 @@ > +/* > +* This file is subject to the terms and conditions of the GNU General Public > +* License. See the file "COPYING" in the main directory of this archive > +* for more details. > +* > +* KVM/MIPS TLB handling, this file is part of the Linux host kernel so that > +* TLB handlers run from KSEG0 > +* > +* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. > +* Authors: Sanjay Lal > +*/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +#undef CONFIG_MIPS_MT > +#include > +#define CONFIG_MIPS_MT > + > +#define KVM_GUEST_PC_TLB 0 > +#define KVM_GUEST_SP_TLB 1 > + > +#define PRIx64 "llx" > + > +/* Use VZ EntryHi.EHINV to invalidate TLB entries */ > +#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) > + > +atomic_t kvm_mips_instance; > +EXPORT_SYMBOL(kvm_mips_instance); > + > +/* These function pointers are initialized once the KVM module is loaded */ > +pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn); > +EXPORT_SYMBOL(kvm_mips_gfn_to_pfn); > + > +void (*kvm_mips_release_pfn_clean) (pfn_t pfn); > +EXPORT_SYMBOL(kvm_mips_release_pfn_clean); > + > +bool(*kvm_mips_is_error_pfn) (pfn_t pfn); > +EXPORT_SYMBOL(kvm_mips_is_error_pfn); > + > +uint32_t kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu) > +{ > + return vcpu->arch.guest_kernel_asid[smp_processor_id()] & ASID_MASK; > +} > + > + > +uint32_t kvm_mips_get_user_asid(struct kvm_vcpu *vcpu) > +{ > + return vcpu->arch.guest_user_asid[smp_processor_id()] & ASID_MASK; > +} > + > +inline uint32_t kvm_mips_get_commpage_asid (struct kvm_vcpu *vcpu) > +{ > + return vcpu->kvm->arch.commpage_tlb; > +} > + > + > +/* > + * Structure defining an tlb entry data set. > + */ > + > +void kvm_mips_dump_host_tlbs(void) > +{ > + struct kvm_mips_tlb tlb; > + int i; > + ulong flags; > + unsigned long old_entryhi; > + unsigned long old_pagemask; > + > + local_irq_save(flags); > + > + old_entryhi = read_c0_entryhi(); > + old_pagemask = read_c0_pagemask(); > + > + printk("HOST TLBs:\n"); > + printk("ASID: %#lx\n", read_c0_entryhi() & ASID_MASK); > + > + for (i = 0; i < current_cpu_data.tlbsize; i++) { > + write_c0_index(i); > + mtc0_tlbw_hazard(); > + > + tlb_read(); > + tlbw_use_hazard(); > + > + tlb.tlb_hi = read_c0_entryhi(); > + tlb.tlb_lo0 = read_c0_entrylo0(); > + tlb.tlb_lo1 = read_c0_entrylo1(); > + tlb.tlb_mask = read_c0_pagemask(); > + > + printk("TLB%c%3d Hi 0x%08lx ", > + (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*', > + i, tlb.tlb_hi); > + printk("Lo0=0x%09" PRIx64 " %c%c attr %lx ", > + (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo0), > + (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ', > + (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ', > + (tlb.tlb_lo0 >> 3) & 7); > + printk("Lo1=0x%09" PRIx64 " %c%c attr %lx sz=%lx\n", > + (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo1), > + (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ', > + (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ', > + (tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask); > + } > + write_c0_entryhi(old_entryhi); > + write_c0_pagemask(old_pagemask); > + mtc0_tlbw_hazard(); > + local_irq_restore(flags); > +} > + > +void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu) > +{ > + int i; > + struct kvm_mips_tlb tlb; > + struct mips_coproc *cop0 __unused = vcpu->arch.cop0; > + > + printk("Guest TLBs:\n"); > + printk("Guest EntryHi: %#lx\n", kvm_read_c0_guest_entryhi(cop0)); > + > + for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) { > + tlb = vcpu->arch.guest_tlb[i]; > + printk("TLB%c%3d Hi 0x%08lx ", > + (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*', > + i, tlb.tlb_hi); > + printk("Lo0=0x%09" PRIx64 " %c%c attr %lx ", > + (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo0), > + (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ', > + (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ', > + (tlb.tlb_lo0 >> 3) & 7); > + printk("Lo1=0x%09" PRIx64 " %c%c attr %lx sz=%lx\n", > + (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo1), > + (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ', > + (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ', > + (tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask); > + } > +} > + > +void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu) > +{ > + int i; > + volatile struct kvm_mips_tlb tlb; > + > + printk("Shadow TLBs:\n"); > + for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) { > + tlb = vcpu->arch.shadow_tlb[smp_processor_id()][i]; > + printk("TLB%c%3d Hi 0x%08lx ", > + (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*', > + i, tlb.tlb_hi); > + printk("Lo0=0x%09" PRIx64 " %c%c attr %lx ", > + (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo0), > + (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ', > + (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ', > + (tlb.tlb_lo0 >> 3) & 7); > + printk("Lo1=0x%09" PRIx64 " %c%c attr %lx sz=%lx\n", > + (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo1), > + (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ', > + (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ', > + (tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask); > + } > +} > + > +static void kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) > +{ > + pfn_t pfn; > + > + if (kvm->arch.guest_pmap[gfn] != KVM_INVALID_PAGE) > + return; > + > + pfn = kvm_mips_gfn_to_pfn(kvm, gfn); This call should be in srcu read section since it access memory slots which are srcu protected. You should test with RCU debug enabled. > + > + if (kvm_mips_is_error_pfn(pfn)) { > + panic("Couldn't get pfn for gfn %#" PRIx64 "!\n", gfn); > + } I think this panic can be triggered by userspace by removing the slot while guest is running. Also please drop parentheses around single statements through the code, this is Linux coding style. > + > + kvm->arch.guest_pmap[gfn] = pfn; > + return; > +} > + > +/* Translate guest KSEG0 addresses to Host PA */ > +ulong kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu, ulong gva) > +{ > + gfn_t gfn; > + uint32_t offset = gva & ~PAGE_MASK; > + struct kvm *kvm = vcpu->kvm; > + > + if (KVM_GUEST_KSEGX(gva) != KVM_GUEST_KSEG0) { > + kvm_err("%s/%p: Invalid gva: %#lx\n", __func__, > + __builtin_return_address(0), gva); > + return KVM_INVALID_PAGE; > + } > + > + gfn = (KVM_GUEST_CPHYSADDR(gva) >> PAGE_SHIFT); > + > + if (gfn >= kvm->arch.guest_pmap_npages) { > + kvm_err("%s: Invalid gfn: %#llx, GVA: %#lx\n", __func__, gfn, > + gva); > + return KVM_INVALID_PAGE; > + } > + kvm_mips_map_page(vcpu->kvm, gfn); > + return (kvm->arch.guest_pmap[gfn] << PAGE_SHIFT) + offset; > +} > + > +/* XXXKYMA: Must be called with interrupts disabled */ > +/* set flush_dcache_mask == 0 if no dcache flush required */ > +int > +kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, ulong entryhi, > + ulong entrylo0, ulong entrylo1, int flush_dcache_mask) > +{ > + ulong flags; > + ulong old_entryhi; > + volatile int idx; > + int debug __unused = 0; > + > + local_irq_save(flags); > + > + > + old_entryhi = read_c0_entryhi(); > + write_c0_entryhi(entryhi); > + mtc0_tlbw_hazard(); > + > + tlb_probe(); > + tlb_probe_hazard(); > + idx = read_c0_index(); > + > + if (idx > current_cpu_data.tlbsize) { > + kvm_err("%s: Invalid Index: %d\n", __func__, idx); > + kvm_mips_dump_host_tlbs(); > + return -1; > + } > + > + if (idx < 0) { > + idx = read_c0_random() % current_cpu_data.tlbsize; > + write_c0_index(idx); > + mtc0_tlbw_hazard(); > + } > + write_c0_entrylo0(entrylo0); > + write_c0_entrylo1(entrylo1); > + mtc0_tlbw_hazard(); > + > + tlb_write_indexed(); > + tlbw_use_hazard(); > + > +#ifdef DEBUG > + if (debug) { > + kvm_debug("@ %#lx idx: %2d [entryhi(R): %#lx] " > + "entrylo0(R): 0x%08lx, entrylo1(R): 0x%08lx\n", > + vcpu->arch.pc, idx, read_c0_entryhi(), > + read_c0_entrylo0(), read_c0_entrylo1()); > + } > +#endif > + > + /* Flush D-cache */ > + if (flush_dcache_mask) { > + if (entrylo0 & MIPS3_PG_V) { > + ++vcpu->stat.flush_dcache_exits; > + flush_data_cache_page((entryhi & VPN2_MASK) & ~flush_dcache_mask); > + } > + if (entrylo1 & MIPS3_PG_V) { > + ++vcpu->stat.flush_dcache_exits; > + flush_data_cache_page(((entryhi & VPN2_MASK) & ~flush_dcache_mask) | > + (0x1 << PAGE_SHIFT)); > + } > + } > + > + /* Restore old ASID */ > + write_c0_entryhi(old_entryhi); > + mtc0_tlbw_hazard(); > + tlbw_use_hazard(); > + local_irq_restore(flags); > + return 0; > +} > + > + > +/* XXXKYMA: Must be called with interrupts disabled */ > +int kvm_mips_handle_kseg0_tlb_fault(ulong badvaddr, struct kvm_vcpu *vcpu) > +{ > + gfn_t gfn; > + pfn_t pfn0, pfn1; > + ulong vaddr = 0; > + ulong entryhi = 0, entrylo0 = 0, entrylo1 = 0; > + int even; > + struct kvm *kvm = vcpu->kvm; > + const int flush_dcache_mask = 0; > + > + > + if (KVM_GUEST_KSEGX(badvaddr) != KVM_GUEST_KSEG0) { > + kvm_err("%s: Invalid BadVaddr: %#lx\n", __func__, badvaddr); > + kvm_mips_dump_host_tlbs(); > + return -1; > + } > + > + gfn = (KVM_GUEST_CPHYSADDR(badvaddr) >> PAGE_SHIFT); > + if (gfn >= kvm->arch.guest_pmap_npages) { > + kvm_err("%s: Invalid gfn: %#llx, BadVaddr: %#lx\n", __func__, > + gfn, badvaddr); > + kvm_mips_dump_host_tlbs(); > + return -1; > + } > + even = !(gfn & 0x1); > + vaddr = badvaddr & (PAGE_MASK << 1); > + > + kvm_mips_map_page(vcpu->kvm, gfn); > + kvm_mips_map_page(vcpu->kvm, gfn ^ 0x1); > + > + if (even) { > + pfn0 = kvm->arch.guest_pmap[gfn]; > + pfn1 = kvm->arch.guest_pmap[gfn ^ 0x1]; > + } else { > + pfn0 = kvm->arch.guest_pmap[gfn ^ 0x1]; > + pfn1 = kvm->arch.guest_pmap[gfn]; > + } > + > + entryhi = (vaddr | kvm_mips_get_kernel_asid(vcpu)); > + entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) | (1 << 2) | > + (0x1 << 1); > + entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) | (1 << 2) | > + (0x1 << 1); > + > + return kvm_mips_host_tlb_write(vcpu, entryhi, entrylo0, entrylo1, > + flush_dcache_mask); > +} > + > +int kvm_mips_handle_commpage_tlb_fault(ulong badvaddr, struct kvm_vcpu *vcpu) > +{ > + pfn_t pfn0, pfn1; > + ulong flags, old_entryhi = 0, vaddr = 0; > + ulong entrylo0 = 0, entrylo1 = 0; > + int debug __unused = 0; > + > + > + pfn0 = CPHYSADDR(vcpu->arch.kseg0_commpage) >> PAGE_SHIFT; > + pfn1 = 0; > + entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) | (1 << 2) | > + (0x1 << 1); > + entrylo1 = 0; > + > + local_irq_save(flags); > + > + old_entryhi = read_c0_entryhi(); > + vaddr = badvaddr & (PAGE_MASK << 1); > + write_c0_entryhi(vaddr | kvm_mips_get_kernel_asid(vcpu)); > + mtc0_tlbw_hazard(); > + write_c0_entrylo0(entrylo0); > + mtc0_tlbw_hazard(); > + write_c0_entrylo1(entrylo1); > + mtc0_tlbw_hazard(); > + write_c0_index(kvm_mips_get_commpage_asid(vcpu)); > + mtc0_tlbw_hazard(); > + tlb_write_indexed(); > + mtc0_tlbw_hazard(); > + tlbw_use_hazard(); > + > +#ifdef DEBUG > + kvm_debug ("@ %#lx idx: %2d [entryhi(R): %#lx] entrylo0 (R): 0x%08lx, entrylo1(R): 0x%08lx\n", > + vcpu->arch.pc, read_c0_index(), read_c0_entryhi(), > + read_c0_entrylo0(), read_c0_entrylo1()); > +#endif > + > + /* Restore old ASID */ > + write_c0_entryhi(old_entryhi); > + mtc0_tlbw_hazard(); > + tlbw_use_hazard(); > + local_irq_restore(flags); > + > + return 0; > +} > + > +int > +kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, > + struct kvm_mips_tlb *tlb, ulong *hpa0, > + ulong *hpa1) > +{ > + pfn_t pfn0, pfn1; > + ulong entryhi = 0, entrylo0 = 0, entrylo1 = 0; > + struct kvm *kvm = vcpu->kvm; > + > + > + if ((tlb->tlb_hi & VPN2_MASK) == 0) { > + pfn0 = 0; > + pfn1 = 0; > + } else { > + kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo0) >> PAGE_SHIFT); > + kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo1) >> PAGE_SHIFT); > + > + pfn0 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo0) >> PAGE_SHIFT]; > + pfn1 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo1) >> PAGE_SHIFT]; > + } > + > + if (hpa0) > + *hpa0 = pfn0 << PAGE_SHIFT; > + > + if (hpa1) > + *hpa1 = pfn1 << PAGE_SHIFT; > + > + /* Get attributes from the Guest TLB */ > + entryhi = (tlb->tlb_hi & VPN2_MASK) | (KVM_GUEST_KERNEL_MODE(vcpu) ? > + kvm_mips_get_kernel_asid(vcpu) : kvm_mips_get_user_asid(vcpu)); > + entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) | > + (tlb->tlb_lo0 & MIPS3_PG_D) | (tlb->tlb_lo0 & MIPS3_PG_V); > + entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) | > + (tlb->tlb_lo1 & MIPS3_PG_D) | (tlb->tlb_lo1 & MIPS3_PG_V); > + > +#ifdef DEBUG > + kvm_debug("@ %#lx tlb_lo0: 0x%08lx tlb_lo1: 0x%08lx\n", vcpu->arch.pc, > + tlb->tlb_lo0, tlb->tlb_lo1); > +#endif > + > + return kvm_mips_host_tlb_write(vcpu, entryhi, entrylo0, entrylo1, > + tlb->tlb_mask); > +} > + > +int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, ulong entryhi) > +{ > + int i; > + int index = -1; > + struct kvm_mips_tlb *tlb = vcpu->arch.guest_tlb; > + > + > + for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) { > + if (((TLB_VPN2(tlb[i]) & ~tlb[i].tlb_mask) == ((entryhi & VPN2_MASK) & ~tlb[i].tlb_mask)) && > + (TLB_IS_GLOBAL(tlb[i]) || (TLB_ASID(tlb[i]) == (entryhi & ASID_MASK)))) { > + index = i; > + break; > + } > + } > + > +#ifdef DEBUG > + kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n", > + __func__, entryhi, index, tlb[i].tlb_lo0, tlb[i].tlb_lo1); > +#endif > + > + return index; > +} > + > +int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, ulong vaddr) > +{ > + ulong old_entryhi, flags; > + volatile int idx; > + > + > + local_irq_save(flags); > + > + old_entryhi = read_c0_entryhi(); > + > + if (KVM_GUEST_KERNEL_MODE(vcpu)) > + write_c0_entryhi((vaddr & VPN2_MASK) | kvm_mips_get_kernel_asid(vcpu)); > + else { > + write_c0_entryhi((vaddr & VPN2_MASK) | kvm_mips_get_user_asid(vcpu)); > + } > + > + mtc0_tlbw_hazard(); > + > + tlb_probe(); > + tlb_probe_hazard(); > + idx = read_c0_index(); > + > + /* Restore old ASID */ > + write_c0_entryhi(old_entryhi); > + mtc0_tlbw_hazard(); > + tlbw_use_hazard(); > + > + local_irq_restore(flags); > + > +#ifdef DEBUG > + kvm_debug("Host TLB lookup, %#lx, idx: %2d\n", vaddr, idx); > +#endif > + > + return idx; > +} > + > +int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, ulong va) > +{ > + int idx; > + ulong flags, old_entryhi; > + > + local_irq_save(flags); > + > + > + old_entryhi = read_c0_entryhi(); > + > + write_c0_entryhi((va & VPN2_MASK) | kvm_mips_get_user_asid(vcpu)); > + mtc0_tlbw_hazard(); > + > + tlb_probe(); > + tlb_probe_hazard(); > + idx = read_c0_index(); > + > + if (idx >= current_cpu_data.tlbsize) > + BUG(); > + > + if (idx > 0) { > + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); > + mtc0_tlbw_hazard(); > + > + write_c0_entrylo0(0); > + mtc0_tlbw_hazard(); > + > + write_c0_entrylo1(0); > + mtc0_tlbw_hazard(); > + > + tlb_write_indexed(); > + mtc0_tlbw_hazard(); > + } > + > + write_c0_entryhi(old_entryhi); > + mtc0_tlbw_hazard(); > + tlbw_use_hazard(); > + > + local_irq_restore(flags); > + > +#ifdef DEBUG > + if (idx > 0) { > + kvm_debug("%s: Invalidated entryhi %#lx @ idx %d\n", __func__, > + (va & VPN2_MASK) | (vcpu->arch.asid_map[va & ASID_MASK] & ASID_MASK), idx); > + } > +#endif > + > + return 0; > +} > + > +/* XXXKYMA: Fix Guest USER/KERNEL no longer share the same ASID*/ > +int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index) > +{ > + ulong flags, old_entryhi; > + > + if (index >= current_cpu_data.tlbsize) > + BUG(); > + > + local_irq_save(flags); > + > + > + old_entryhi = read_c0_entryhi(); > + > + write_c0_entryhi(UNIQUE_ENTRYHI(index)); > + mtc0_tlbw_hazard(); > + > + write_c0_index(index); > + mtc0_tlbw_hazard(); > + > + write_c0_entrylo0(0); > + mtc0_tlbw_hazard(); > + > + write_c0_entrylo1(0); > + mtc0_tlbw_hazard(); > + > + tlb_write_indexed(); > + mtc0_tlbw_hazard(); > + tlbw_use_hazard(); > + > + write_c0_entryhi(old_entryhi); > + mtc0_tlbw_hazard(); > + tlbw_use_hazard(); > + > + local_irq_restore(flags); > + > + return 0; > +} > + > +void kvm_mips_flush_host_tlb(int skip_kseg0) > +{ > + unsigned long flags; > + unsigned long old_entryhi, entryhi; > + unsigned long old_pagemask; > + int entry = 0; > + int maxentry = current_cpu_data.tlbsize; > + > + > + local_irq_save(flags); > + > + old_entryhi = read_c0_entryhi(); > + old_pagemask = read_c0_pagemask(); > + > + /* Blast 'em all away. */ > + for (entry = 0; entry < maxentry; entry++) { > + > + write_c0_index(entry); > + mtc0_tlbw_hazard(); > + > + if (skip_kseg0) { > + tlb_read(); > + tlbw_use_hazard(); > + > + entryhi = read_c0_entryhi(); > + > + /* Don't blow away guest kernel entries */ > + if (KVM_GUEST_KSEGX(entryhi) == KVM_GUEST_KSEG0) { > + continue; > + } > + } > + > + /* Make sure all entries differ. */ > + write_c0_entryhi(UNIQUE_ENTRYHI(entry)); > + mtc0_tlbw_hazard(); > + write_c0_entrylo0(0); > + mtc0_tlbw_hazard(); > + write_c0_entrylo1(0); > + mtc0_tlbw_hazard(); > + > + tlb_write_indexed(); > + mtc0_tlbw_hazard(); > + } > + > + tlbw_use_hazard(); > + > + write_c0_entryhi(old_entryhi); > + write_c0_pagemask(old_pagemask); > + mtc0_tlbw_hazard(); > + tlbw_use_hazard(); > + > + local_irq_restore(flags); > +} > + > +void > +kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, > + struct kvm_vcpu *vcpu) > +{ > + unsigned long asid = asid_cache(cpu); > + > + if (!((asid += ASID_INC) & ASID_MASK)) { > + if (cpu_has_vtag_icache) { > + flush_icache_all(); > + } > + > + kvm_local_flush_tlb_all(); /* start new asid cycle */ > + > + if (!asid) /* fix version if needed */ > + asid = ASID_FIRST_VERSION; > + } > + > + cpu_context(cpu, mm) = asid_cache(cpu) = asid; > +} > + > +void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu) > +{ > + unsigned long flags; > + unsigned long old_entryhi; > + unsigned long old_pagemask; > + int entry = 0; > + int cpu = smp_processor_id(); > + > + local_irq_save(flags); > + > + old_entryhi = read_c0_entryhi(); > + old_pagemask = read_c0_pagemask(); > + > + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { > + write_c0_index(entry); > + mtc0_tlbw_hazard(); > + tlb_read(); > + tlbw_use_hazard(); > + > + vcpu->arch.shadow_tlb[cpu][entry].tlb_hi = read_c0_entryhi(); > + vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0 = read_c0_entrylo0(); > + vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1 = read_c0_entrylo1(); > + vcpu->arch.shadow_tlb[cpu][entry].tlb_mask = read_c0_pagemask(); > + } > + > + write_c0_entryhi(old_entryhi); > + write_c0_pagemask(old_pagemask); > + mtc0_tlbw_hazard(); > + > + local_irq_restore(flags); > + > +} > + > +void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu) > +{ > + unsigned long flags; > + unsigned long old_ctx; > + int entry; > + int cpu = smp_processor_id(); > + > + local_irq_save(flags); > + > + old_ctx = read_c0_entryhi(); > + > + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { > + write_c0_entryhi(vcpu->arch.shadow_tlb[cpu][entry].tlb_hi); > + mtc0_tlbw_hazard(); > + write_c0_entrylo0(vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0); > + write_c0_entrylo1(vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1); > + > + write_c0_index(entry); > + mtc0_tlbw_hazard(); > + > + tlb_write_indexed(); > + tlbw_use_hazard(); > + } > + > + tlbw_use_hazard(); > + write_c0_entryhi(old_ctx); > + mtc0_tlbw_hazard(); > + local_irq_restore(flags); > +} > + > + > +void kvm_local_flush_tlb_all(void) > +{ > + unsigned long flags; > + unsigned long old_ctx; > + int entry = 0; > + > + local_irq_save(flags); > + /* Save old context and create impossible VPN2 value */ > + old_ctx = read_c0_entryhi(); > + write_c0_entrylo0(0); > + write_c0_entrylo1(0); > + > + /* Blast 'em all away. */ > + while (entry < current_cpu_data.tlbsize) { > + /* Make sure all entries differ. */ > + write_c0_entryhi(UNIQUE_ENTRYHI(entry)); > + write_c0_index(entry); > + mtc0_tlbw_hazard(); > + tlb_write_indexed(); > + entry++; > + } > + tlbw_use_hazard(); > + write_c0_entryhi(old_ctx); > + mtc0_tlbw_hazard(); > + > + local_irq_restore(flags); > +} > + > +void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu) > +{ > + int cpu, entry; > + > + for_each_possible_cpu(cpu) { > + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { > + vcpu->arch.shadow_tlb[cpu][entry].tlb_hi = > + UNIQUE_ENTRYHI(entry); > + vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0 = 0x0; > + vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1 = 0x0; > + vcpu->arch.shadow_tlb[cpu][entry].tlb_mask = > + read_c0_pagemask(); > +#ifdef DEBUG > + kvm_debug > + ("shadow_tlb[%d][%d]: tlb_hi: %#lx, lo0: %#lx, lo1: %#lx\n", > + cpu, entry, > + vcpu->arch.shadow_tlb[cpu][entry].tlb_hi, > + vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0, > + vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1); > +#endif > + } > + } > +} > + > +/* Restore ASID once we are scheduled back after preemption */ > +void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) > +{ > + ulong flags; > + int newasid = 0; > + > +#ifdef DEBUG > + kvm_debug("%s: vcpu %p, cpu: %d\n", __func__, vcpu, cpu); > +#endif > + > + /* Alocate new kernel and user ASIDs if needed */ > + > + local_irq_save(flags); > + > + if (((vcpu->arch. > + guest_kernel_asid[cpu] ^ asid_cache(cpu)) & ASID_VERSION_MASK)) { > + kvm_get_new_mmu_context(&vcpu->arch.guest_kernel_mm, cpu, vcpu); > + vcpu->arch.guest_kernel_asid[cpu] = > + vcpu->arch.guest_kernel_mm.context.asid[cpu]; > + kvm_get_new_mmu_context(&vcpu->arch.guest_user_mm, cpu, vcpu); > + vcpu->arch.guest_user_asid[cpu] = > + vcpu->arch.guest_user_mm.context.asid[cpu]; > + newasid++; > + > + kvm_info("[%d]: cpu_context: %#lx\n", cpu, > + cpu_context(cpu, current->mm)); > + kvm_info("[%d]: Allocated new ASID for Guest Kernel: %#x\n", > + cpu, vcpu->arch.guest_kernel_asid[cpu]); > + kvm_info("[%d]: Allocated new ASID for Guest User: %#x\n", cpu, > + vcpu->arch.guest_user_asid[cpu]); > + } > + > + if (vcpu->arch.last_sched_cpu != cpu) { > + kvm_info("[%d->%d]KVM VCPU[%d] switch\n", > + vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id); > + } > + > + /* Only reload shadow host TLB if new ASIDs haven't been allocated */ > +#if 0 > + if ((atomic_read(&kvm_mips_instance) > 1) && !newasid) { > + kvm_mips_flush_host_tlb(0); > + kvm_shadow_tlb_load(vcpu); > + } > +#endif > + > + if (!newasid) { > + /* If we preempted while the guest was executing, then reload the pre-empted ASID */ > + if (current->flags & PF_VCPU) { > + write_c0_entryhi(vcpu->arch. > + preempt_entryhi & ASID_MASK); > + ehb(); > + } > + } else { > + /* New ASIDs were allocated for the VM */ > + > + /* Were we in guest context? If so then the pre-empted ASID is no longer > + * valid, we need to set it to what it should be based on the mode of > + * the Guest (Kernel/User) > + */ > + if (current->flags & PF_VCPU) { > + if (KVM_GUEST_KERNEL_MODE(vcpu)) > + write_c0_entryhi(vcpu->arch. > + guest_kernel_asid[cpu] & > + ASID_MASK); > + else > + write_c0_entryhi(vcpu->arch. > + guest_user_asid[cpu] & > + ASID_MASK); > + ehb(); > + } > + } > + > + local_irq_restore(flags); > + > +} > + > +/* ASID can change if another task is scheduled during preemption */ > +void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) > +{ > + ulong flags __unused; > + uint32_t cpu __unused; > + > + local_irq_save(flags); > + > + cpu = smp_processor_id(); > + > + > + vcpu->arch.preempt_entryhi = read_c0_entryhi(); > + vcpu->arch.last_sched_cpu = cpu; > + > +#if 0 > + if ((atomic_read(&kvm_mips_instance) > 1)) { > + kvm_shadow_tlb_put(vcpu); > + } > +#endif > + > + if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) & > + ASID_VERSION_MASK)) { > + kvm_debug("%s: Dropping MMU Context: %#lx\n", __func__, > + cpu_context(cpu, current->mm)); > + drop_mmu_context(current->mm, cpu); > + } > + write_c0_entryhi(cpu_asid(cpu, current->mm)); > + ehb(); > + > + local_irq_restore(flags); > +} > + > +uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu) > +{ > + uint32_t inst; > + struct mips_coproc *cop0 __unused = vcpu->arch.cop0; > + int index; > + ulong paddr, flags; > + > + if (KVM_GUEST_KSEGX((ulong) opc) < KVM_GUEST_KSEG0 || > + KVM_GUEST_KSEGX((ulong) opc) == KVM_GUEST_KSEG23) { > + local_irq_save(flags); > + index = kvm_mips_host_tlb_lookup(vcpu, (ulong) opc); > + if (index >= 0) { > + inst = *(opc); Here and in some more places below you access __user memory. Shouldn't you use get_user() to access it? What prevents the kernel crash by access fault here if userspace remaps the memory to be non-readable? Hmm, may be it uses guest translation here so it cannot happen, but still, sparse will not be happy and kvm_mips_translate_guest_kseg0_to_hpa() case below uses host translation anyway. > + } else { > + index = > + kvm_mips_guest_tlb_lookup(vcpu, > + ((ulong) opc & VPN2_MASK) > + | > + (kvm_read_c0_guest_entryhi > + (cop0) & ASID_MASK)); > + if (index < 0) { > + kvm_err > + ("%s: get_user_failed for %p, vcpu: %p, ASID: %#lx\n", > + __func__, opc, vcpu, read_c0_entryhi()); > + kvm_mips_dump_host_tlbs(); > + local_irq_restore(flags); > + return KVM_INVALID_INST; > + } > + kvm_mips_handle_mapped_seg_tlb_fault(vcpu, > + &vcpu->arch. > + guest_tlb[index], > + NULL, NULL); > + inst = *(opc); > + } > + local_irq_restore(flags); > + } else if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) { > + paddr = > + kvm_mips_translate_guest_kseg0_to_hpa(vcpu, (ulong) opc); > + inst = *(uint32_t *) CKSEG0ADDR(paddr); > + } else { > + kvm_err("%s: illegal address: %p\n", __func__, opc); > + return KVM_INVALID_INST; > + } > + > + return inst; > +} > + > +EXPORT_SYMBOL(kvm_local_flush_tlb_all); > +EXPORT_SYMBOL(kvm_shadow_tlb_put); > +EXPORT_SYMBOL(kvm_mips_handle_mapped_seg_tlb_fault); > +EXPORT_SYMBOL(kvm_mips_handle_commpage_tlb_fault); > +EXPORT_SYMBOL(kvm_mips_init_shadow_tlb); > +EXPORT_SYMBOL(kvm_mips_dump_host_tlbs); > +EXPORT_SYMBOL(kvm_mips_handle_kseg0_tlb_fault); > +EXPORT_SYMBOL(kvm_mips_host_tlb_lookup); > +EXPORT_SYMBOL(kvm_mips_flush_host_tlb); > +EXPORT_SYMBOL(kvm_mips_guest_tlb_lookup); > +EXPORT_SYMBOL(kvm_mips_host_tlb_inv); > +EXPORT_SYMBOL(kvm_mips_translate_guest_kseg0_to_hpa); > +EXPORT_SYMBOL(kvm_shadow_tlb_load); > +EXPORT_SYMBOL(kvm_mips_dump_shadow_tlbs); > +EXPORT_SYMBOL(kvm_mips_dump_guest_tlbs); > +EXPORT_SYMBOL(kvm_get_inst); > +EXPORT_SYMBOL(kvm_arch_vcpu_load); > +EXPORT_SYMBOL(kvm_arch_vcpu_put); > + > -- > 1.7.11.3 > > -- > To unsubscribe from this list: send the line "unsubscribe kvm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Gleb. From sshtylyov@mvista.com Wed Feb 6 13:09:02 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Feb 2013 13:09:06 +0100 (CET) Received: from mail-lb0-f172.google.com ([209.85.217.172]:65386 "EHLO mail-lb0-f172.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817544Ab3BFMJCQ60-I (ORCPT ); Wed, 6 Feb 2013 13:09:02 +0100 Received: by mail-lb0-f172.google.com with SMTP id n8so1127794lbj.31 for ; Wed, 06 Feb 2013 04:08:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:date:from:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=wgSoAVQ9+kOPm2tWRd+QQ5h/ltl+rAde41vl7U+oJQw=; b=NZmcsSn2vHMSxhDylthQmdhQ7gzE7r7t9zqQttkjBdSC2B6+JjsJtZcOs9y2ZaOTww pjYRnNgNOi5HILgWDmTPTx7gE+203Klet3alk/ASoogjWAILLeDHVGqAM8RalACpYjr0 6SVe0TC9Ut1SZmgC3/GrjYsl7oRyd8WrFL3uDcsglIbfG92VcvphjkZ+WIQmq1zPt9i1 V2r2KVk1D0hqNzLKcS2Bf/6XxkH1tP73Y603CF+B+Gf3ThDJxn4WeaGLxMBrY8cEutfh dNa61V+RYL1FYZc2h1ACgJQnvxEafmVI64vBvvEUMX0GhRKgE/exzh1ivSW6RIBq8Mkz FfXQ== X-Received: by 10.152.113.165 with SMTP id iz5mr26508653lab.50.1360152536725; Wed, 06 Feb 2013 04:08:56 -0800 (PST) Received: from [192.168.2.2] (ppp91-79-91-246.pppoe.mtu-net.ru. [91.79.91.246]) by mx.google.com with ESMTPS id f2sm7725851lbz.4.2013.02.06.04.08.54 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 06 Feb 2013 04:08:55 -0800 (PST) Message-ID: <511247C1.2010401@mvista.com> Date: Wed, 06 Feb 2013 16:08:33 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org, cernekee@gmail.com, kevink@paralogos.com, ddaney.cavm@gmail.com Subject: Re: [PATCH 4/4] MIPS: microMIPS: Add instruction utility macros. References: <1360104723-29529-1-git-send-email-sjhill@mips.com> <1360104723-29529-5-git-send-email-sjhill@mips.com> In-Reply-To: <1360104723-29529-5-git-send-email-sjhill@mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQmU9q72YL0bR7pm+zCUgp1Aln9u005d8R4cbK9PT96dsctRNGZJwU8wBi6EZ6xQZohYvF+o X-archive-position: 35714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1271 Lines: 43 Hello. On 06-02-2013 2:52, Steven J. Hill wrote: > From: "Steven J. Hill" > Add two new macros for microMIPS. One checks if an exception was > taken in either microMIPS or classic MIPS mode. The other checks > if a microMIPS instruction is 16-bit or 32-bit in length. > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/mipsregs.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h > index f206ef2..13e1d68 100644 > --- a/arch/mips/include/asm/mipsregs.h > +++ b/arch/mips/include/asm/mipsregs.h > @@ -622,6 +622,24 @@ > #ifndef __ASSEMBLY__ > > /* > + * Macros for handling the ISA mode bit for microMIPS. > + */ > +#define get_isa16_mode(x) ((x) & 0x1) > +#define msk_isa16_mode(x) ((x) & ~0x1) > +#define set_isa16_mode(x) do { (x) |= 0x1; } while(0) > + > +/* > + * microMIPS instructions can be 16-bit or 32-bit in length. This > + * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. > + */ > +static inline int mm_insn_16bit(u16 insn) > +{ > + u16 opcode = (insn >> 10) & 0x7; > + > + return ((opcode >= 1 && opcode <= 3) ? 1 : 0); Parens are not really necessary there, are they? WBR, Sergei From gleb@redhat.com Wed Feb 6 14:11:20 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Feb 2013 14:11:22 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:16830 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822501Ab3BFNLUJXOu7 (ORCPT ); Wed, 6 Feb 2013 14:11:20 +0100 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r16DBGVm019133 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 6 Feb 2013 08:11:16 -0500 Received: from dhcp-1-237.tlv.redhat.com (dhcp-4-26.tlv.redhat.com [10.35.4.26]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id r16DBFUC004693; Wed, 6 Feb 2013 08:11:15 -0500 Received: by dhcp-1-237.tlv.redhat.com (Postfix, from userid 13519) id 4FE7E18D479; Wed, 6 Feb 2013 15:11:14 +0200 (IST) Date: Wed, 6 Feb 2013 15:11:14 +0200 From: Gleb Natapov To: Sanjay Lal Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH v2 02/18] KVM/MIPS32: Arch specific KVM data structures. Message-ID: <20130206131114.GA7837@redhat.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-3-git-send-email-sanjayl@kymasys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1353551656-23579-3-git-send-email-sanjayl@kymasys.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-archive-position: 35715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gleb@redhat.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1578 Lines: 36 On Wed, Nov 21, 2012 at 06:34:00PM -0800, Sanjay Lal wrote: > +struct kvm_mips_callbacks { > + int (*handle_cop_unusable) (struct kvm_vcpu *vcpu); > + int (*handle_tlb_mod) (struct kvm_vcpu *vcpu); > + int (*handle_tlb_ld_miss) (struct kvm_vcpu *vcpu); > + int (*handle_tlb_st_miss) (struct kvm_vcpu *vcpu); > + int (*handle_addr_err_st) (struct kvm_vcpu *vcpu); > + int (*handle_addr_err_ld) (struct kvm_vcpu *vcpu); > + int (*handle_syscall) (struct kvm_vcpu *vcpu); > + int (*handle_res_inst) (struct kvm_vcpu *vcpu); > + int (*handle_break) (struct kvm_vcpu *vcpu); > + int (*vm_init) (struct kvm *kvm); > + int (*vcpu_init) (struct kvm_vcpu *vcpu); > + int (*vcpu_setup) (struct kvm_vcpu *vcpu); > + gpa_t(*gva_to_gpa) (gva_t gva); > + void (*queue_timer_int) (struct kvm_vcpu *vcpu); > + void (*dequeue_timer_int) (struct kvm_vcpu *vcpu); > + void (*queue_io_int) (struct kvm_vcpu *vcpu, > + struct kvm_mips_interrupt *irq); > + void (*dequeue_io_int) (struct kvm_vcpu *vcpu, > + struct kvm_mips_interrupt *irq); > + int (*irq_deliver) (struct kvm_vcpu *vcpu, unsigned int priority, > + uint32_t cause); > + int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority, > + uint32_t cause); > + int (*vcpu_ioctl_get_regs) (struct kvm_vcpu *vcpu, > + struct kvm_regs *regs); > + int (*vcpu_ioctl_set_regs) (struct kvm_vcpu *vcpu, > + struct kvm_regs *regs); > +}; You haven't addressed Avi's comment about dropping the interaction and adding it later, when other HW is supported and the best way to do the split is known. -- Gleb. From gleb@redhat.com Wed Feb 6 14:17:20 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Feb 2013 14:17:21 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:13658 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823089Ab3BFNRUb8Eh5 (ORCPT ); Wed, 6 Feb 2013 14:17:20 +0100 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r16DHHij020997 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 6 Feb 2013 08:17:17 -0500 Received: from dhcp-1-237.tlv.redhat.com (dhcp-4-26.tlv.redhat.com [10.35.4.26]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id r16DHGcr007247; Wed, 6 Feb 2013 08:17:16 -0500 Received: by dhcp-1-237.tlv.redhat.com (Postfix, from userid 13519) id C8EC118D479; Wed, 6 Feb 2013 15:17:15 +0200 (IST) Date: Wed, 6 Feb 2013 15:17:15 +0200 From: Gleb Natapov To: Sanjay Lal Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH v2 09/18] KVM/MIPS32: COP0 accesses profiling. Message-ID: <20130206131715.GB7837@redhat.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-10-git-send-email-sanjayl@kymasys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1353551656-23579-10-git-send-email-sanjayl@kymasys.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-archive-position: 35716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gleb@redhat.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2350 Lines: 100 On Wed, Nov 21, 2012 at 06:34:07PM -0800, Sanjay Lal wrote: > > Signed-off-by: Sanjay Lal > --- > arch/mips/kvm/kvm_mips_stats.c | 81 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 81 insertions(+) > create mode 100644 arch/mips/kvm/kvm_mips_stats.c > > diff --git a/arch/mips/kvm/kvm_mips_stats.c b/arch/mips/kvm/kvm_mips_stats.c > new file mode 100644 > index 0000000..e442a26 > --- /dev/null > +++ b/arch/mips/kvm/kvm_mips_stats.c > @@ -0,0 +1,81 @@ > +/* > +* This file is subject to the terms and conditions of the GNU General Public > +* License. See the file "COPYING" in the main directory of this archive > +* for more details. > +* > +* KVM/MIPS: COP0 access histogram > +* > +* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. > +* Authors: Sanjay Lal > +*/ > + > +#include > + > +char *kvm_mips_exit_types_str[MAX_KVM_MIPS_EXIT_TYPES] = { > + "WAIT", > + "CACHE", > + "Signal", > + "Interrupt", > + "COP0/1 Unusable", > + "TLB Mod", > + "TLB Miss (LD)", > + "TLB Miss (ST)", > + "Address Err (ST)", > + "Address Error (LD)", > + "System Call", > + "Reserved Inst", > + "Break Inst", > + "D-Cache Flushes", > +}; > + > +char *kvm_cop0_str[N_MIPS_COPROC_REGS] = { > + "Index", > + "Random", > + "EntryLo0", > + "EntryLo1", > + "Context", > + "PG Mask", > + "Wired", > + "HWREna", > + "BadVAddr", > + "Count", > + "EntryHI", > + "Compare", > + "Status", > + "Cause", > + "EXC PC", > + "PRID", > + "Config", > + "LLAddr", > + "Watch Lo", > + "Watch Hi", > + "X Context", > + "Reserved", > + "Impl Dep", > + "Debug", > + "DEPC", > + "PerfCnt", > + "ErrCtl", > + "CacheErr", > + "TagLo", > + "TagHi", > + "ErrorEPC", > + "DESAVE" > +}; > + > +int kvm_mips_dump_stats(struct kvm_vcpu *vcpu) > +{ > + int i, j __unused; > +#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS > + printk("\nKVM VCPU[%d] COP0 Access Profile:\n", vcpu->vcpu_id); > + for (i = 0; i < N_MIPS_COPROC_REGS; i++) { > + for (j = 0; j < N_MIPS_COPROC_SEL; j++) { > + if (vcpu->arch.cop0->stat[i][j]) > + printk("%s[%d]: %lu\n", kvm_cop0_str[i], j, > + vcpu->arch.cop0->stat[i][j]); > + } > + } > +#endif > + > + return 0; > +} You need to use ftrace event for that. Much more flexible with perf integration and no need to recompile to enabled/disable. -- Gleb. From gleb@redhat.com Wed Feb 6 15:18:03 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Feb 2013 15:18:08 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:57515 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825735Ab3BFOSDwj-3m (ORCPT ); Wed, 6 Feb 2013 15:18:03 +0100 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r16EG9MW005095 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 6 Feb 2013 09:18:00 -0500 Received: from dhcp-1-237.tlv.redhat.com (dhcp-4-26.tlv.redhat.com [10.35.4.26]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id r16DKIcc003858; Wed, 6 Feb 2013 08:20:23 -0500 Received: by dhcp-1-237.tlv.redhat.com (Postfix, from userid 13519) id 423DB18D479; Wed, 6 Feb 2013 15:20:18 +0200 (IST) Date: Wed, 6 Feb 2013 15:20:18 +0200 From: Gleb Natapov To: Sanjay Lal Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH v2 11/18] KVM/MIPS32: Routines to handle specific traps/exceptions while executing the guest. Message-ID: <20130206132018.GC7837@redhat.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-12-git-send-email-sanjayl@kymasys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1353551656-23579-12-git-send-email-sanjayl@kymasys.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-archive-position: 35717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gleb@redhat.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 616 Lines: 27 On Wed, Nov 21, 2012 at 06:34:09PM -0800, Sanjay Lal wrote: > +static gpa_t kvm_trap_emul_gva_to_gpa_cb(gva_t gva) > +{ > + gpa_t gpa; > + uint32_t kseg = KSEGX(gva); > + > + if ((kseg == CKSEG0) || (kseg == CKSEG1)) You seems to be using KVM_GUEST_KSEGX variants on gva in all other places. Why not here? > + gpa = CPHYSADDR(gva); > + else { > + printk("%s: cannot find GPA for GVA: %#lx\n", __func__, gva); > + kvm_mips_dump_host_tlbs(); > + gpa = KVM_INVALID_ADDR; > + } > + > +#ifdef DEBUG > + kvm_debug("%s: gva %#lx, gpa: %#llx\n", __func__, gva, gpa); > +#endif > + > + return gpa; > +} > + -- Gleb. From folkert@vanheusden.com Wed Feb 6 17:05:12 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Feb 2013 17:05:13 +0100 (CET) Received: from keetweej.vanheusden.com ([80.101.105.103]:41972 "EHLO keetweej.vanheusden.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827497Ab3BFQFM2LcFe (ORCPT ); Wed, 6 Feb 2013 17:05:12 +0100 Received: from belle.intranet.vanheusden.com (unknown [192.168.64.100]) by keetweej.vanheusden.com (Postfix) with ESMTP id 629CC15FB05 for ; Wed, 6 Feb 2013 17:05:11 +0100 (CET) Received: by belle.intranet.vanheusden.com (Postfix, from userid 1000) id 141E4945E7; Wed, 6 Feb 2013 17:05:10 +0100 (CET) Date: Wed, 6 Feb 2013 17:05:10 +0100 From: folkert To: linux-mips@linux-mips.org Subject: prom start Message-ID: <20130206160508.GR2118@belle.intranet.vanheusden.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Organization: www.unixexpert.nl X-Chameleon-Return-To: folkert@vanheusden.com X-Xfmail-Return-To: folkert@vanheusden.com X-Phonenumber: +31-6-41278122 X-URL: http://www.vanheusden.com/ X-PGP-KeyID: 1F28D8AE X-GPG-fingerprint: AC89 09CE 41F2 00B4 FCF2 B174 3019 0E8C 1F28 D8AE X-Key: http://pgp.surfnet.nl:11371/pks/lookup?op=get&search=0x1F28D8AE Read-Receipt-To: Reply-By: Sat Feb 2 10:16:14 CET 2013 X-Message-Flag: www.unixexpert.nl User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: folkert@vanheusden.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 723 Lines: 19 Hi, Is this mailing list also meant for generic mips questions? (if not: any suggestions for one that is?) If so: I'mm experimenting a bit with mips, specifically on SGI hardware (Indigo). Now it seems all mips systems have the prom at 0xbfc00000. But how does it start? The first 0x3c0 bytes seem to be nonsense. Somewhere on the web I found that 0xbfc00884 is the starting point but after single stepping 5 instructions, the program counter jumps to 0x00000000 so I don't think that's the right one either. Also, reading the first 4 bytes from bfc00000 and using that as a pointer seems to be invalid too: 0bf000f0. Anyone with insights regarding the booting of the prom on sgi systems? Regards, Folkert van Heusden From davem@davemloft.net Wed Feb 6 21:11:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Feb 2013 21:11:44 +0100 (CET) Received: from shards.monkeyblade.net ([149.20.54.216]:40672 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827506Ab3BFULlmsUvQ (ORCPT ); Wed, 6 Feb 2013 21:11:41 +0100 Received: from localhost (nat-pool-rdu.redhat.com [66.187.233.202]) (Authenticated sender: davem-davemloft) by shards.monkeyblade.net (Postfix) with ESMTPSA id 5D0DD58426F; Wed, 6 Feb 2013 12:11:41 -0800 (PST) Date: Wed, 06 Feb 2013 15:11:36 -0500 (EST) Message-Id: <20130206.151136.28894146016087360.davem@davemloft.net> To: ganesanr@broadcom.com Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH v2 1/2] NET: ethernet/netlogic: Netlogic XLR/XLS GMAC driver From: David Miller In-Reply-To: <1360063819-17555-1-git-send-email-ganesanr@broadcom.com> References: <1360063819-17555-1-git-send-email-ganesanr@broadcom.com> X-Mailer: Mew version 6.5 on Emacs 24.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-archive-position: 35719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2429 Lines: 78 From: ganesanr@broadcom.com Date: Tue, 5 Feb 2013 17:00:19 +0530 > +config NETLOGIC_XLR_NET > + tristate "Netlogic XLR/XLS network device" > + default y > + select PHYLIB > + depends on CPU_XLR > + ---help--- > + This driver support Netlogic XLR/XLS on chip gigabit > + Ethernet. No individual device driver should default to 'y'. Vendor guards, yes, can default to 'y', but not individual drivers. > +/* > + * The readl/writel implementation byteswaps on XLR/XLS, so > + * we need to use __raw_ IO to read the NAE registers > + * because they are in the big-endian MMIO area on the SoC. > + */ Comments in the networking are to be formatted: /* Like * this. */ Please fix this up in your entire driver. > +/* > + * Table of net_device pointers indexed by port, this will be used to > + * lookup the net_device corresponding to a port by the message ring handler. > + * > + * Maximum ports in XLR/XLS is 8(8 GMAC on XLS, 4 GMAC + 2 XGMAC on XLR) > + */ > +static struct net_device *mac_to_ndev[8]; Make this a dynamic data structure, a parent device that the individual netdevs are hung off of, it can still be an array. That way you can have a bonafide struct device instance and associated hierarchy of devices in the kernel device list. Also avoid this strange and non-standard usage of "MAC" as an integer port index. The canonical meaning of MAC is the link-layer address of the device. > + > +static inline struct sk_buff *mac_get_skb_back_ptr(void *addr) > +{ > + struct sk_buff **back_ptr; > + > + /* this function should be used only for newly allocated packets. > + * It assumes the first cacheline is for the back pointer related > + * book keeping info. > + */ > + back_ptr = (struct sk_buff **)(addr - MAC_SKB_BACK_PTR_SIZE); > + return *back_ptr; > +} Use the skb->cb[] control block rather than mis-using the skb data area for storing internal driver state. > + paddr = virt_to_bus(addr); virt_to_bus() is verboten, use the proper DMA APIs. I don't care if this is a specialized driver for a special platform. > + addr = bus_to_virt(msg->msg0 & 0xffffffffffULL); bus_to_virt() is verbotten, use the proper DMA APIs and store correct references to packets in a translation data structure in your per-netdev software state. > +static void __maybe_unused xlr_wakeup_queue(unsigned long dev) This is really unused, just delete it. That's enough for me, this driver needs a lot of work. From ddaney.cavm@gmail.com Thu Feb 7 20:43:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Feb 2013 20:43:53 +0100 (CET) Received: from mail-pa0-f41.google.com ([209.85.220.41]:33613 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827530Ab3BGTnvFdrNP (ORCPT ); Thu, 7 Feb 2013 20:43:51 +0100 Received: by mail-pa0-f41.google.com with SMTP id fb11so1594058pad.14 for ; Thu, 07 Feb 2013 11:43:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=x/ZEH/QZO8THtPcAQNJlgcCSEWTEdzjh18h0FVER7So=; b=PkmI8ONiG8NntCHM031cdTV2G1DqZDhhdfWEunihpvo1VH/6jORYr3fAPdHMXhZ5vE KePfeEHivt1ngo77spePpzBVlPuEH726tsW3dsNID23AEITE0BfOyvvQwmYJa6/1/20L NoVjYs21ThGojbk3zvHwUBadr2eSGUP5NdATVwZUO8OJu+7rI2S7eo8ttAuPdusOLWEM X9XXS5WrrzahUBik34sP0+sPS/hIpRuwCNTY7LaWLI6xbD4FZF4KDQfqI2G2uQfcBBtD g7BUfkyAImCBBZMuJ5j6HxZzBOR6io9XJLevd4vhFtIVzPv3TVUDFdgftF4a+Gx86oC2 yX4A== X-Received: by 10.66.83.165 with SMTP id r5mr9095407pay.3.1360266224039; Thu, 07 Feb 2013 11:43:44 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id o5sm48216756pay.5.2013.02.07.11.43.42 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 07 Feb 2013 11:43:43 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r17JgfFS017797; Thu, 7 Feb 2013 11:42:41 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r17JgcfJ017795; Thu, 7 Feb 2013 11:42:38 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Sanjay Lal , kvm@vger.kernel.org Subject: [RFC PATCH] MIPS/kvm: Add asm/kvm.h Date: Thu, 7 Feb 2013 11:42:34 -0800 Message-Id: <1360266154-17761-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-archive-position: 35720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3020 Lines: 126 From: David Daney Uniform definitions for both 32-bit and 64-bit MIPS machines. Signed-off-by: David Daney Cc: Sanjay Lal Cc: kvm@vger.kernel.org --- Previously Sanjay posted a version of asm/kvm.h that worked only for 32-bit MIPS machines. Since the MIPS kernel port also supports 64-bit CPUs, we need a virtual machine interface that can handle both 32 and 64 bit environments. Surly we will need to extend this, but I thought it may be a good starting point for future enhancements. Please comment. arch/mips/include/uapi/asm/kvm.h | 94 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 arch/mips/include/uapi/asm/kvm.h diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h new file mode 100644 index 0000000..caca51d --- /dev/null +++ b/arch/mips/include/uapi/asm/kvm.h @@ -0,0 +1,94 @@ +#ifndef _ASM_MIPS_KVM_H +#define _ASM_MIPS_KVM_H +/* + * KVM MIPS specific structures and definitions. + * + * Some parts derived from the x86 version of this file. + */ + +/* for KVM_GET_REGS and KVM_SET_REGS */ +/* + * If Config[AT] is zero (32-bit CPU), the register contents are + * stored in the lower 32-bits of the struct kvm_regs fields and sign + * extended to 64-bits. + */ +struct kvm_regs { + /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ + __u64 gpr[32]; + __u64 hi, lo; + __u64 pc; +}; + +/* for KVM_GET_FPU and KVM_SET_FPU */ +/* + * If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs + * are zero filled. + */ +struct kvm_fpu { + __u64 fpr[32]; + __u32 fir; + __u32 fccr; + __u32 fexr; + __u32 fenr; + __u32 fcsr; + __u32 pad; +}; + + +/* + * For MIPS, we use the same APIs as x86, where 'msr' corresponds to a + * CP0 register. The index field is broken down as follows: + * + * bits[2..0] - Register 'sel' index. + * bits[7..3] - Register 'rd' index. + * bits[15..8] - Must be zero. + * bits[31..16] - 0 -> CP0 registers. + * + * Other sets registers may be added in the future. Each set would + * have its own identifier in bits[31..16]. + * + * For MSRs that are narrower than 64-bits, the value is stored in the + * low order bits of the data field, and sign extended to 64-bits. + */ +#define KVM_MIPS_MSR_CP0 0 +struct kvm_msr_entry { + __u32 index; + __u32 reserved; + __u64 data; +}; + +/* for KVM_GET_MSRS and KVM_SET_MSRS */ +struct kvm_msrs { + __u32 nmsrs; /* number of msrs in entries */ + __u32 pad; + + struct kvm_msr_entry entries[0]; +}; + +/* for KVM_GET_MSR_INDEX_LIST */ +struct kvm_msr_list { + __u32 nmsrs; /* number of msrs in entries */ + __u32 indices[0]; +}; + +/* + * KVM MIPS specific structures and definitions + * + */ +struct kvm_debug_exit_arch { + __u64 epc; +}; + +/* for KVM_SET_GUEST_DEBUG */ +struct kvm_guest_debug_arch { +}; + +/* definition of registers in kvm_run */ +struct kvm_sync_regs { +}; + +/* dummy definition */ +struct kvm_sregs { +}; + +#endif /* _ASM_MIPS_KVM_H */ -- 1.7.11.7 From juhosg@openwrt.org Thu Feb 7 21:28:26 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Feb 2013 21:28:27 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:53264 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827522Ab3BGU20QHn0g (ORCPT ); Thu, 7 Feb 2013 21:28:26 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 8D4D025E1FF; Thu, 7 Feb 2013 21:28:19 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2JmOHkUQYUPb; Thu, 7 Feb 2013 21:28:19 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 5111C25E1F1; Thu, 7 Feb 2013 21:28:19 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos Subject: [PATCH 1/3] MIPS: pci-ar71xx: use dynamically allocated PCI controller structure Date: Thu, 7 Feb 2013 21:28:14 +0100 Message-Id: <1360268896-13434-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6953 Lines: 221 Signed-off-by: Gabor Juhos --- arch/mips/pci/pci-ar71xx.c | 84 ++++++++++++++++++++++++++++---------------- 1 file changed, 53 insertions(+), 31 deletions(-) diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index 69e0bb4..44dc5bf 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -48,8 +48,12 @@ #define AR71XX_PCI_IRQ_COUNT 5 -static DEFINE_SPINLOCK(ar71xx_pci_lock); -static void __iomem *ar71xx_pcicfg_base; +struct ar71xx_pci_controller { + void __iomem *cfg_base; + spinlock_t lock; + int irq; + struct pci_controller pci_ctrl; +}; /* Byte lane enable bits */ static const u8 ar71xx_pci_ble_table[4][4] = { @@ -92,9 +96,18 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, return ret; } -static int ar71xx_pci_check_error(int quiet) +static inline struct ar71xx_pci_controller * +pci_bus_to_ar71xx_controller(struct pci_bus *bus) { - void __iomem *base = ar71xx_pcicfg_base; + struct pci_controller *hose; + + hose = (struct pci_controller *) bus->sysdata; + return container_of(hose, struct ar71xx_pci_controller, pci_ctrl); +} + +static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet) +{ + void __iomem *base = apc->cfg_base; u32 pci_err; u32 ahb_err; @@ -129,9 +142,10 @@ static int ar71xx_pci_check_error(int quiet) return !!(ahb_err | pci_err); } -static inline void ar71xx_pci_local_write(int where, int size, u32 value) +static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc, + int where, int size, u32 value) { - void __iomem *base = ar71xx_pcicfg_base; + void __iomem *base = apc->cfg_base; u32 ad_cbe; value = value << (8 * (where & 3)); @@ -147,7 +161,8 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 cmd) { - void __iomem *base = ar71xx_pcicfg_base; + struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); + void __iomem *base = apc->cfg_base; u32 addr; addr = ar71xx_pci_bus_addr(bus, devfn, where); @@ -156,13 +171,14 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), base + AR71XX_PCI_REG_CFG_CBE); - return ar71xx_pci_check_error(1); + return ar71xx_pci_check_error(apc, 1); } static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { - void __iomem *base = ar71xx_pcicfg_base; + struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); + void __iomem *base = apc->cfg_base; unsigned long flags; u32 data; int err; @@ -171,7 +187,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, ret = PCIBIOS_SUCCESSFUL; data = ~0; - spin_lock_irqsave(&ar71xx_pci_lock, flags); + spin_lock_irqsave(&apc->lock, flags); err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, AR71XX_PCI_CFG_CMD_READ); @@ -180,7 +196,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, else data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); - spin_unlock_irqrestore(&ar71xx_pci_lock, flags); + spin_unlock_irqrestore(&apc->lock, flags); *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; @@ -190,7 +206,8 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { - void __iomem *base = ar71xx_pcicfg_base; + struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); + void __iomem *base = apc->cfg_base; unsigned long flags; int err; int ret; @@ -198,7 +215,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, value = value << (8 * (where & 3)); ret = PCIBIOS_SUCCESSFUL; - spin_lock_irqsave(&ar71xx_pci_lock, flags); + spin_lock_irqsave(&apc->lock, flags); err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, AR71XX_PCI_CFG_CMD_WRITE); @@ -207,7 +224,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, else __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); - spin_unlock_irqrestore(&ar71xx_pci_lock, flags); + spin_unlock_irqrestore(&apc->lock, flags); return ret; } @@ -231,12 +248,6 @@ static struct resource ar71xx_pci_mem_resource = { .flags = IORESOURCE_MEM }; -static struct pci_controller ar71xx_pci_controller = { - .pci_ops = &ar71xx_pci_ops, - .mem_resource = &ar71xx_pci_mem_resource, - .io_resource = &ar71xx_pci_io_resource, -}; - static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) { void __iomem *base = ath79_reset_base; @@ -294,7 +305,7 @@ static struct irq_chip ar71xx_pci_irq_chip = { .irq_mask_ack = ar71xx_pci_irq_mask, }; -static void ar71xx_pci_irq_init(int irq) +static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) { void __iomem *base = ath79_reset_base; int i; @@ -309,7 +320,7 @@ static void ar71xx_pci_irq_init(int irq) irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, handle_level_irq); - irq_set_chained_handler(irq, ar71xx_pci_irq_handler); + irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler); } static void ar71xx_pci_reset(void) @@ -336,20 +347,27 @@ static void ar71xx_pci_reset(void) static int ar71xx_pci_probe(struct platform_device *pdev) { + struct ar71xx_pci_controller *apc; struct resource *res; - int irq; u32 t; + apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller), + GFP_KERNEL); + if (!apc) + return -ENOMEM; + + spin_lock_init(&apc->lock); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); if (!res) return -EINVAL; - ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res); - if (!ar71xx_pcicfg_base) + apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res); + if (!apc->cfg_base) return -ENOMEM; - irq = platform_get_irq(pdev, 0); - if (irq < 0) + apc->irq = platform_get_irq(pdev, 0); + if (apc->irq < 0) return -EINVAL; ar71xx_pci_reset(); @@ -357,14 +375,18 @@ static int ar71xx_pci_probe(struct platform_device *pdev) /* setup COMMAND register */ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; - ar71xx_pci_local_write(PCI_COMMAND, 4, t); + ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t); /* clear bus errors */ - ar71xx_pci_check_error(1); + ar71xx_pci_check_error(apc, 1); + + ar71xx_pci_irq_init(apc); - ar71xx_pci_irq_init(irq); + apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; + apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource; + apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource; - register_pci_controller(&ar71xx_pci_controller); + register_pci_controller(&apc->pci_ctrl); return 0; } -- 1.7.10 From juhosg@openwrt.org Thu Feb 7 21:28:26 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Feb 2013 21:28:50 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:53265 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827529Ab3BGU20Qx3oA (ORCPT ); Thu, 7 Feb 2013 21:28:26 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id C3B2025E1F1; Thu, 7 Feb 2013 21:28:19 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id r8f-74oaVapo; Thu, 7 Feb 2013 21:28:19 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 85E2225E1FE; Thu, 7 Feb 2013 21:28:19 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos Subject: [PATCH 2/3] MIPS: pci-ar71xx: remove static PCI IO/MEM resources Date: Thu, 7 Feb 2013 21:28:15 +0100 Message-Id: <1360268896-13434-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360268896-13434-1-git-send-email-juhosg@openwrt.org> References: <1360268896-13434-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35722 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3155 Lines: 111 Signed-off-by: Gabor Juhos --- arch/mips/ath79/pci.c | 12 +++++++++++- arch/mips/pci/pci-ar71xx.c | 40 ++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 17 deletions(-) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 942e3f9..ea8aa10 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -117,7 +117,7 @@ static struct platform_device * ath79_register_pci_ar71xx(void) { struct platform_device *pdev; - struct resource res[2]; + struct resource res[4]; memset(res, 0, sizeof(res)); @@ -130,6 +130,16 @@ ath79_register_pci_ar71xx(void) res[1].start = ATH79_CPU_IRQ_IP2; res[1].end = ATH79_CPU_IRQ_IP2; + res[2].name = "io_base"; + res[2].flags = IORESOURCE_IO; + res[2].start = 0; + res[2].end = 0; + + res[3].name = "mem_base"; + res[3].flags = IORESOURCE_MEM; + res[3].start = AR71XX_PCI_MEM_BASE; + res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1; + pdev = platform_device_register_simple("ar71xx-pci", -1, res, ARRAY_SIZE(res)); return pdev; diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index 44dc5bf..e48dddb 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -53,6 +53,8 @@ struct ar71xx_pci_controller { spinlock_t lock; int irq; struct pci_controller pci_ctrl; + struct resource io_res; + struct resource mem_res; }; /* Byte lane enable bits */ @@ -234,20 +236,6 @@ static struct pci_ops ar71xx_pci_ops = { .write = ar71xx_pci_write_config, }; -static struct resource ar71xx_pci_io_resource = { - .name = "PCI IO space", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO, -}; - -static struct resource ar71xx_pci_mem_resource = { - .name = "PCI memory space", - .start = AR71XX_PCI_MEM_BASE, - .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) { void __iomem *base = ath79_reset_base; @@ -370,6 +358,26 @@ static int ar71xx_pci_probe(struct platform_device *pdev) if (apc->irq < 0) return -EINVAL; + res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base"); + if (!res) + return -EINVAL; + + apc->io_res.parent = res; + apc->io_res.name = "PCI IO space"; + apc->io_res.start = res->start; + apc->io_res.end = res->end; + apc->io_res.flags = IORESOURCE_IO; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base"); + if (!res) + return -EINVAL; + + apc->mem_res.parent = res; + apc->mem_res.name = "PCI memory space"; + apc->mem_res.start = res->start; + apc->mem_res.end = res->end; + apc->mem_res.flags = IORESOURCE_MEM; + ar71xx_pci_reset(); /* setup COMMAND register */ @@ -383,8 +391,8 @@ static int ar71xx_pci_probe(struct platform_device *pdev) ar71xx_pci_irq_init(apc); apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; - apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource; - apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource; + apc->pci_ctrl.mem_resource = &apc->mem_res; + apc->pci_ctrl.io_resource = &apc->io_res; register_pci_controller(&apc->pci_ctrl); -- 1.7.10 From juhosg@openwrt.org Thu Feb 7 21:29:46 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Feb 2013 21:29:47 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:53290 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827522Ab3BGU3qJEFEG (ORCPT ); Thu, 7 Feb 2013 21:29:46 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id E376D25E1FF; Thu, 7 Feb 2013 21:29:40 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id j8jeAWm28Fdw; Thu, 7 Feb 2013 21:29:40 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 9DC6025E1F1; Thu, 7 Feb 2013 21:29:40 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos Subject: [PATCH 3/3] MIPS: pci-ar71xx: move irq base to the controller structure Date: Thu, 7 Feb 2013 21:29:38 +0100 Message-Id: <1360268978-13570-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360268896-13434-1-git-send-email-juhosg@openwrt.org> References: <1360268896-13434-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35723 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3100 Lines: 101 Signed-off-by: Gabor Juhos --- arch/mips/pci/pci-ar71xx.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index e48dddb..412ec02 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -52,6 +52,7 @@ struct ar71xx_pci_controller { void __iomem *cfg_base; spinlock_t lock; int irq; + int irq_base; struct pci_controller pci_ctrl; struct resource io_res; struct resource mem_res; @@ -238,23 +239,26 @@ static struct pci_ops ar71xx_pci_ops = { static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) { + struct ar71xx_pci_controller *apc; void __iomem *base = ath79_reset_base; u32 pending; + apc = irq_get_handler_data(irq); + pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); if (pending & AR71XX_PCI_INT_DEV0) - generic_handle_irq(ATH79_PCI_IRQ(0)); + generic_handle_irq(apc->irq_base + 0); else if (pending & AR71XX_PCI_INT_DEV1) - generic_handle_irq(ATH79_PCI_IRQ(1)); + generic_handle_irq(apc->irq_base + 1); else if (pending & AR71XX_PCI_INT_DEV2) - generic_handle_irq(ATH79_PCI_IRQ(2)); + generic_handle_irq(apc->irq_base + 2); else if (pending & AR71XX_PCI_INT_CORE) - generic_handle_irq(ATH79_PCI_IRQ(4)); + generic_handle_irq(apc->irq_base + 4); else spurious_interrupt(); @@ -262,10 +266,14 @@ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) static void ar71xx_pci_irq_unmask(struct irq_data *d) { - unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; + struct ar71xx_pci_controller *apc; + unsigned int irq; void __iomem *base = ath79_reset_base; u32 t; + apc = irq_data_get_irq_chip_data(d); + irq = d->irq - apc->irq_base; + t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); @@ -275,10 +283,14 @@ static void ar71xx_pci_irq_unmask(struct irq_data *d) static void ar71xx_pci_irq_mask(struct irq_data *d) { - unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; + struct ar71xx_pci_controller *apc; + unsigned int irq; void __iomem *base = ath79_reset_base; u32 t; + apc = irq_data_get_irq_chip_data(d); + irq = d->irq - apc->irq_base; + t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); @@ -303,11 +315,15 @@ static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); - for (i = ATH79_PCI_IRQ_BASE; - i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) + apc->irq_base = ATH79_PCI_IRQ_BASE; + for (i = apc->irq_base; + i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) { irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, handle_level_irq); + irq_set_chip_data(i, apc); + } + irq_set_handler_data(apc->irq, apc); irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler); } -- 1.7.10 From juhosg@openwrt.org Thu Feb 7 21:32:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Feb 2013 21:32:43 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:53331 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827522Ab3BGUcmYV-pa (ORCPT ); Thu, 7 Feb 2013 21:32:42 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 4EB1525E201; Thu, 7 Feb 2013 21:32:37 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kq2WZx28m1mr; Thu, 7 Feb 2013 21:32:37 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id C57C025E1F1; Thu, 7 Feb 2013 21:32:36 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos Subject: [PATCH 1/2] ath79: add ATH79_CPU_IRQ() macro Date: Thu, 7 Feb 2013 21:32:23 +0100 Message-Id: <1360269144-13853-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35724 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 8555 Lines: 270 Remove the individual ATH79_CPU_IRQ_* constants and use the new macro instead of those. Signed-off-by: Gabor Juhos --- arch/mips/ath79/dev-usb.c | 12 ++++++------ arch/mips/ath79/dev-wmac.c | 8 ++++---- arch/mips/ath79/irq.c | 32 ++++++++++++++++---------------- arch/mips/ath79/pci.c | 6 +++--- arch/mips/include/asm/mach-ath79/irq.h | 9 ++------- 5 files changed, 31 insertions(+), 36 deletions(-) diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index bd2bc10..2e04197 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -111,7 +111,7 @@ static void __init ath79_usb_setup(void) platform_device_register(&ath79_ohci_device); ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, - AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB); + AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3)); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; platform_device_register(&ath79_ehci_device); } @@ -136,7 +136,7 @@ static void __init ar7240_usb_setup(void) iounmap(usb_ctrl_base); ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, - AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB); + AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3)); platform_device_register(&ath79_ohci_device); } @@ -152,7 +152,7 @@ static void __init ar724x_usb_setup(void) mdelay(10); ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, - AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3)); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -169,7 +169,7 @@ static void __init ar913x_usb_setup(void) mdelay(10); ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, - AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3)); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -186,7 +186,7 @@ static void __init ar933x_usb_setup(void) mdelay(10); ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, - AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3)); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -212,7 +212,7 @@ static void __init ar934x_usb_setup(void) udelay(1000); ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, - AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3)); ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index d6d893c..4f6c4e3 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -55,8 +55,8 @@ static void __init ar913x_wmac_setup(void) ath79_wmac_resources[0].start = AR913X_WMAC_BASE; ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; - ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; - ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; + ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); + ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); } @@ -83,8 +83,8 @@ static void __init ar933x_wmac_setup(void) ath79_wmac_resources[0].start = AR933X_WMAC_BASE; ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; - ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; - ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; + ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); + ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); if (t & AR933X_BOOTSTRAP_REF_CLK_40) diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index 219cfa1..2934895 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -114,7 +114,7 @@ static void __init ath79_misc_irq_init(void) handle_level_irq); } - irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); + irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler); } static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) @@ -147,7 +147,7 @@ static void ar934x_ip2_irq_init(void) irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); - irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); + irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); } asmlinkage void plat_irq_dispatch(void) @@ -157,22 +157,22 @@ asmlinkage void plat_irq_dispatch(void) pending = read_c0_status() & read_c0_cause() & ST0_IM; if (pending & STATUSF_IP7) - do_IRQ(ATH79_CPU_IRQ_TIMER); + do_IRQ(ATH79_CPU_IRQ(7)); else if (pending & STATUSF_IP2) ath79_ip2_handler(); else if (pending & STATUSF_IP4) - do_IRQ(ATH79_CPU_IRQ_GE0); + do_IRQ(ATH79_CPU_IRQ(4)); else if (pending & STATUSF_IP5) - do_IRQ(ATH79_CPU_IRQ_GE1); + do_IRQ(ATH79_CPU_IRQ(5)); else if (pending & STATUSF_IP3) ath79_ip3_handler(); else if (pending & STATUSF_IP6) - do_IRQ(ATH79_CPU_IRQ_MISC); + do_IRQ(ATH79_CPU_IRQ(6)); else spurious_interrupt(); @@ -188,60 +188,60 @@ asmlinkage void plat_irq_dispatch(void) static void ar71xx_ip2_handler(void) { ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); - do_IRQ(ATH79_CPU_IRQ_IP2); + do_IRQ(ATH79_CPU_IRQ(2)); } static void ar724x_ip2_handler(void) { ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); - do_IRQ(ATH79_CPU_IRQ_IP2); + do_IRQ(ATH79_CPU_IRQ(2)); } static void ar913x_ip2_handler(void) { ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); - do_IRQ(ATH79_CPU_IRQ_IP2); + do_IRQ(ATH79_CPU_IRQ(2)); } static void ar933x_ip2_handler(void) { ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); - do_IRQ(ATH79_CPU_IRQ_IP2); + do_IRQ(ATH79_CPU_IRQ(2)); } static void ar934x_ip2_handler(void) { - do_IRQ(ATH79_CPU_IRQ_IP2); + do_IRQ(ATH79_CPU_IRQ(2)); } static void ar71xx_ip3_handler(void) { ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ_USB); + do_IRQ(ATH79_CPU_IRQ(3)); } static void ar724x_ip3_handler(void) { ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ_USB); + do_IRQ(ATH79_CPU_IRQ(3)); } static void ar913x_ip3_handler(void) { ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ_USB); + do_IRQ(ATH79_CPU_IRQ(3)); } static void ar933x_ip3_handler(void) { ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ_USB); + do_IRQ(ATH79_CPU_IRQ(3)); } static void ar934x_ip3_handler(void) { ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ_USB); + do_IRQ(ATH79_CPU_IRQ(3)); } void __init arch_init_irq(void) diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index ea8aa10..4350c25 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -127,8 +127,8 @@ ath79_register_pci_ar71xx(void) res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; res[1].flags = IORESOURCE_IRQ; - res[1].start = ATH79_CPU_IRQ_IP2; - res[1].end = ATH79_CPU_IRQ_IP2; + res[1].start = ATH79_CPU_IRQ(2); + res[1].end = ATH79_CPU_IRQ(2); res[2].name = "io_base"; res[2].flags = IORESOURCE_IO; @@ -208,7 +208,7 @@ int __init ath79_register_pci(void) AR724X_PCI_MEM_BASE, AR724X_PCI_MEM_SIZE, 0, - ATH79_CPU_IRQ_IP2); + ATH79_CPU_IRQ(2)); } else if (soc_is_ar9342() || soc_is_ar9344()) { u32 bootstrap; diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 158ad7f..3dda4c2 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -12,6 +12,8 @@ #define MIPS_CPU_IRQ_BASE 0 #define NR_IRQS 48 +#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) + #define ATH79_MISC_IRQ_BASE 8 #define ATH79_MISC_IRQ_COUNT 32 #define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x)) @@ -24,13 +26,6 @@ #define ATH79_IP2_IRQ_COUNT 2 #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) -#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) -#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) -#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) -#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) -#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) -#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7) - #define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) #define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) #define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) -- 1.7.10 From juhosg@openwrt.org Thu Feb 7 21:32:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Feb 2013 21:33:02 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:53334 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827531Ab3BGUcnD5gpd (ORCPT ); Thu, 7 Feb 2013 21:32:43 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id E816A25E203; Thu, 7 Feb 2013 21:32:37 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yft5PsHitNj9; Thu, 7 Feb 2013 21:32:37 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 7924425E1F1; Thu, 7 Feb 2013 21:32:37 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos Subject: [PATCH 2/2] ath79: remove ATH79_MISC_IRQ_* defines Date: Thu, 7 Feb 2013 21:32:24 +0100 Message-Id: <1360269144-13853-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360269144-13853-1-git-send-email-juhosg@openwrt.org> References: <1360269144-13853-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35725 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3024 Lines: 87 Use the ATH79_MISC_IRQ() macro instead. Signed-off-by: Gabor Juhos --- arch/mips/ath79/dev-common.c | 6 +++--- arch/mips/ath79/dev-usb.c | 2 +- arch/mips/ath79/irq.c | 2 +- arch/mips/include/asm/mach-ath79/irq.h | 13 ------------- 4 files changed, 5 insertions(+), 18 deletions(-) diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c index ea3a814..9be1465 100644 --- a/arch/mips/ath79/dev-common.c +++ b/arch/mips/ath79/dev-common.c @@ -36,7 +36,7 @@ static struct resource ath79_uart_resources[] = { static struct plat_serial8250_port ath79_uart_data[] = { { .mapbase = AR71XX_UART_BASE, - .irq = ATH79_MISC_IRQ_UART, + .irq = ATH79_MISC_IRQ(3), .flags = AR71XX_UART_FLAGS, .iotype = UPIO_MEM32, .regshift = 2, @@ -62,8 +62,8 @@ static struct resource ar933x_uart_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = ATH79_MISC_IRQ_UART, - .end = ATH79_MISC_IRQ_UART, + .start = ATH79_MISC_IRQ(3), + .end = ATH79_MISC_IRQ(3), .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index 2e04197..bcb165b 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -107,7 +107,7 @@ static void __init ath79_usb_setup(void) mdelay(900); ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, - AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI); + AR71XX_OHCI_SIZE, ATH79_MISC_IRQ(6)); platform_device_register(&ath79_ohci_device); ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index 2934895..df88d49 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -265,7 +265,7 @@ void __init arch_init_irq(void) BUG(); } - cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + cp0_perfcount_irq = ATH79_MISC_IRQ(5); mips_cpu_irq_init(); ath79_misc_irq_init(); diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 3dda4c2..23e2bba 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -26,19 +26,6 @@ #define ATH79_IP2_IRQ_COUNT 2 #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) -#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) -#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) -#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) -#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3) -#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4) -#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) -#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) -#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) -#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8) -#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9) -#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10) -#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12) - #include_next #endif /* __ASM_MACH_ATH79_IRQ_H */ -- 1.7.10 From wim@iguana.be Thu Feb 7 23:29:32 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Feb 2013 23:29:32 +0100 (CET) Received: from ns1.pc-advies.be ([83.149.101.17]:34173 "EHLO spo001.leaseweb.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6827531Ab3BGW3cLYvsr (ORCPT ); Thu, 7 Feb 2013 23:29:32 +0100 Received: from wimvs by spo001.leaseweb.com with local (Exim 4.50) id 1U3ZyB-0007MT-Ec; Thu, 07 Feb 2013 23:29:27 +0100 Date: Thu, 7 Feb 2013 23:29:27 +0100 From: Wim Van Sebroeck To: Hauke Mehrtens Cc: linux-watchdog@vger.kernel.org, zajec5@gmail.com, linux-mips@linux-mips.org Subject: Re: [PATCH v4 0/5] watchdog: bcm47xx_wdt.c: add support for SoCs with PMU Message-ID: <20130207222927.GA28281@spo001.leaseweb.com> References: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1358010851-28077-1-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.4.1i X-archive-position: 35726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 379 Lines: 14 Hi Hauke > This patch series improves the functions for setting the watchdog > driver for bcm47xx based SoCs using ssb and bcma. This makes the > watchdog driver use the platform device provided by bcma or ssb. > > This code is currently based on the linux-watchdog/master tree by > Wim Van Sebroeck. V5 patches have been added to linux-watchdog-next. Kind regards, Wim. From florian@openwrt.org Fri Feb 8 11:48:15 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Feb 2013 11:48:17 +0100 (CET) Received: from zmc.proxad.net ([212.27.53.206]:35964 "EHLO zmc.proxad.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6818020Ab3BHKsPfRrOC (ORCPT ); Fri, 8 Feb 2013 11:48:15 +0100 Received: from localhost (localhost [127.0.0.1]) by zmc.proxad.net (Postfix) with ESMTP id D867A1B43C1; Fri, 8 Feb 2013 11:48:14 +0100 (CET) X-Virus-Scanned: amavisd-new at localhost Received: from zmc.proxad.net ([127.0.0.1]) by localhost (zmc.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lPSpyWiHGz59; Fri, 8 Feb 2013 11:48:14 +0100 (CET) Received: from flexo.iliad.local (freebox.vlq16.iliad.fr [213.36.7.13]) by zmc.proxad.net (Postfix) with ESMTPSA id 31C2EC194E3; Fri, 8 Feb 2013 11:48:14 +0100 (CET) From: Florian Fainelli To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, blogic@openwrt.org, Florian Fainelli Subject: [PATCH] MIPS: SMTC: fix implicit declaration of set_vi_handler Date: Fri, 8 Feb 2013 11:45:14 +0100 Message-Id: <1360320314-9255-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 896 Lines: 32 This patch fixes the following implicit declaration while building with MIPS SMTC support enabled: arch/mips/kernel/smtc.c: In function 'setup_cross_vpe_interrupts': arch/mips/kernel/smtc.c:1205:2: error: implicit declaration of function 'set_vi_handler' [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors Signed-off-by: Florian Fainelli --- Ralf, John, This is applicable to both mips-for-linux-next and master. arch/mips/kernel/smtc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 1c152a9..7186222 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -41,6 +41,7 @@ #include #include #include +#include /* * SMTC Kernel needs to manipulate low-level CPU interrupt mask -- 1.7.10.4 From florian@openwrt.org Fri Feb 8 11:56:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Feb 2013 11:56:44 +0100 (CET) Received: from mail-wg0-f43.google.com ([74.125.82.43]:41816 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822501Ab3BHK4nTPPgN (ORCPT ); Fri, 8 Feb 2013 11:56:43 +0100 Received: by mail-wg0-f43.google.com with SMTP id e12so2860813wge.22 for ; Fri, 08 Feb 2013 02:56:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:message-id:date:from:organization:user-agent :mime-version:to:cc:subject:references:in-reply-to:content-type; bh=5LVpgDT62+99OAzRGVWb/YTS9d6+ma5SvB4zE+gXf+g=; b=gMnhu/ss3Dxz23q9v4NId+j8rYuxiRmqcXvhIPAIbTrV9osJ2a3ABZXvhVaZ4As6ui AWULavf2q741gRIgyUnqjUY1HQyxYEn1RJ/Vh7I7eEm6VDjIFGOaPA8dP6NDwXlPCNLd cm6l5gJ2p618hZgXC3thAhy124N2wdMb3m74sBPYT0YTfUCirKVf/2FWlo7Cn/njsH5o 4nNArCNhTXuwyOjqO4D/iPoaqkBZTD/Z3tEqiUlpHItR0G4G93xIac64rfqRWLkqs8/8 IHGFK1701o8Fl9wjcvpdUkj3x5Y7E8XngkXW7OVtpvWISfxG6Y1X/uZgKiNTD0h8Gndz pfVQ== X-Received: by 10.180.99.72 with SMTP id eo8mr1544436wib.34.1360320997552; Fri, 08 Feb 2013 02:56:37 -0800 (PST) Received: from ?IPv6:2a01:e34:ec0d:40e0:200:5aff:fe70:ca64? ([2a01:e34:ec0d:40e0:200:5aff:fe70:ca64]) by mx.google.com with ESMTPS id m6sm14692921wic.2.2013.02.08.02.56.35 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 08 Feb 2013 02:56:36 -0800 (PST) Message-ID: <5114D932.5050509@openwrt.org> Date: Fri, 08 Feb 2013 11:53:38 +0100 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: Florian Fainelli CC: linux-mips@linux-mips.org, ralf@linux-mips.org, blogic@openwrt.org Subject: Re: [PATCH] MIPS: SMTC: fix implicit declaration of set_vi_handler References: <1360320314-9255-1-git-send-email-florian@openwrt.org> In-Reply-To: <1360320314-9255-1-git-send-email-florian@openwrt.org> Content-Type: multipart/mixed; boundary="------------090507080502090101030103" X-archive-position: 35728 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 14774 Lines: 217 This is a multi-part message in MIME format. --------------090507080502090101030103 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 02/08/2013 11:45 AM, Florian Fainelli wrote: > This patch fixes the following implicit declaration while building with > MIPS SMTC support enabled: > > arch/mips/kernel/smtc.c: In function 'setup_cross_vpe_interrupts': > arch/mips/kernel/smtc.c:1205:2: error: implicit declaration of function > 'set_vi_handler' [-Werror=implicit-function-declaration] > cc1: all warnings being treated as errors And attached the config file to reproduce the build failure. -- Florian --------------090507080502090101030103 Content-Type: application/gzip; name="config-fail.gz" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="config-fail.gz" H4sICLzMFFECA2NvbmZpZy1mYWlsAIxcT3PbNtO/91Nw3PfQzjS1LStOPO/4AIKghIokaACU ZF84is0kmtqSR5Lb5ts/uyAlgRRA55DExm8BLID9DzC//vJrQN5265fFbvm4eH7+EXyrVtVm sauegq/L5+r/g0gEmdABi7j+E4iT5ertv/OX5es2uPrz858XHzaP18Gk2qyq54CuV1+X396g 93K9+uXXX6jIYj4qU56r2x+/QMOvQbp4/L5cVcG2eq4e22QPImNllBIg/TWwupYkoWOW3gfL bbBa76Dr7khA5Cd3ux5/unEiIU2Hn+ZzH3Z95cEMK1SEJNFunNBxGTGqNNFcZH6av8jDQw/6 MPw0vHDiCck0v/NAivSwlQiRjVQfU3uKS5vEXnkK6z49GsVIdOUcNWMU+sgJ45nyTzuVw0vP fmfzvFQ6HAwu+uGPTjhPYXqVuzExY1JPnZga8ZLng0Ef+KkP/NwDXnmG5eG9ZiWVY56xXgoi U5a8M4boH+NdAjWDWfoIEq51wlQhe0dhmRaK9JGEfOQdJOOlhwkjNnp+deNT0xofenE+kULz SSnDj57zmMkyB/lxYpRMeZGWgmomMlhJWiREC/kTtJLFTLKMwsIFkZFbqJO0nCfyXYq8h6Kx luUo56LkWcQlo9qh1XKmWFqOWMYkp6XKeZYIOrE1nEjYyjFRJU/EaFAWnu3qkl0PHbPt5xnP GB+NNUzTAShJeCgJyEXEEnJ/JFCwnKgUKddlLEnKQH15ppk8UhgGUnIPTEwBpmUc0SMaCqFL SWbHFsqm0DKcWC1K0qalvSxwRyWJIlnq8noYctc+IkkmMirGeLzWyjIGfCOaEjRVsDRrUffK bBkjMrkvcwkrstjhnwcfb46/GksbioxrcT3sNKeKnhhlVAGfJclAJkQupO45I65I44f3/NQN Jcm5PRnNC1TikoGQkcwxIBLU1qKhaW+AKnLkRFmDeAi6g7TXOy5GrNRJuKd3cMLlHXJjLQka RpyebDJolcKNOAI55eVIXw/n8zn+fGGxOIODBSVTOaGsI3Asia8GndGTS5BykOZSjXmsb6/r iAjYakVDre3FfleDUl56dnePD7rngsD1sNPRSTHwUmRsSiLihWX66eLiwsFY6+gecDtOBb+1 uH544IfNCvthT+96bW6sXphlHQ7MnLZ1xz+s+2oA5qKcMJmxxENiLMoJCY78zihjkFLw0qyc EU3Hxh4eAuwmFN/9eK2OobUZxhaRyRRMf8GUS1dyAuqk+AMrh5PQ7nQELq8noTu0OpBcD9sk DUEsJHjAlMxNuC9kBIb88vKoOrAysPioJR3lMdvSAbANDy1H3wo70Ub25iwq0hzNQxsFa1/G tkXYN9YqWtN37KouIzCFYcIif4YARCrNvVE0orprdlLtkRCILjTXYwlRNs9GJ71gASSOT/ic 5hCkCQJb+w6bGmx9WoaETpQW+U8QyzuYryc7SnN/hJCPYWU+X9oyLHikCnIHjYP2GD45MGZ8 yl1qaSDGT4VF3WfUo21jCE1SlnoO48BSJ/KIIQKEXuCdUDSsziyByKsESMj7MhWRrcL7TinJ CnLa3m4Arx2xsibPbTMwNa1hE7i5mpuudrc6sOGgTKBrp91RhWHSEQQncw0el0XWknLwxGWu zciwdep2aB2dSMERenPf3vPvlABw1aNbyywUme1hp1zqUosyLFTLqKnUFZ+xmIAalSmGYSnP DA+3w4ub62NPLUkGXhzjNxNN4B64xVMKpfZHSrQGW+GmSxjJjCVxwrEUYLIhfHB5z9Q6K/il LHKfdWh0ziuvFpJJc16H3fh8At0OjvyNH8rhZwdv0H5pPKNNeenJeQEafLzwQ9c+6LITVrSx wfC9kINIdJrjB0slHm5h0IOES8bSHLUqYy3/1rRPRVJkmkh3xamhcmITNmeevFESNTauyMU9 o6g8R35RvyKW75dkHTBI3ASkFXzoCQZHu+/Olb49O39efjl/WT+9PVfb8/8rMsydJNgkotj5 n4+mVHfWshloMWdCWrYgLHgSaQ4dwRagdStVPaUJNUamUviMK3l7PQYbbJ6D301Bl2zDxiF9 ARM5hdNBBiGdu70a/NJSK9wDDhb07MzaB5JMmVRgVLD5WO+ygJIUWriEFddUh07l6IF3DWeD hIAM3FDyYCdBbUQcgfYUliwcx/cIy2GWflz0WLWxUBpP9vbst9V6Vf1+ZicnLcMw5Tk9acB/ qU5aWiAUn5fpXcEKj/EakyxK3BgpIqdhN5t3qAGA4wFZO4Ss8HOwffuy/bHdVS9HOXKQdxNV ENhcipC5ITUWs3bGZ6LPqHREVIcyBKoem7I6ovaDtWo4SFKhwGJHdbZvlqeXL9Vm61qh5uBG wQgBo3bdQLRtFwQloLeqRD2Uh00Dk32uF9u/gx0MHyxWT8F2t9htg8Xj4/pttVuuvnXmwUiH gJ0B01av/Fj1VhFuI2Wgg0DhNm2aqAkWMVoBmeFE0iJQjsWBnSwBc1lY7OKoSNGijEkmCts0 HBtLMF3x7aXlti2MzYmH8ZpI6Xpf3WtrWC2NZfWOkgka4jY6Cfik/sGxrkSgJY2btP/yo+UV RlIUubs+DrEDnZjcDk9fC+kp6IDymwKEK1IueDTiERjWDGyltiO5BlEahBZiqXtIGcyErYCq Lr2heTV8uv1ujEEFHCwlrQm6SDm1rKxsl/jCZAKUU+MjZNT2GZKkMI4SBWgu+LTv65fq/Ovz erNcrM6fqn/O16/V6t/N7ny3eVv9ff7lbfn8VD4tN+e7xeZbtfuAF1XVc7kZlNU38IePHwZ/ Xn4636zXAC2ed4uz07kk1m9gfzBkuPDAoz18FJDIeAC38EQ9bgBArwsAbP7g7+VyDEdG0Z2C 5BgX2YQ6e9GipcjBnGCeDibRJOytk6tdwt6mQ2cYFvIIyyQaJ98qKdTdzD8kcV9STABQ96lL UsEC5klhGeRuTTS0QZbEsDzJ7CqdyieyzCFbghWlHbftRUMIhsq4SOwMrNBsbk2VCxtVfJSR JLaE1Jhlu8E4CLtBNUnl0Uty18lBJsaiVrpV8w6jl12PZBoL4H2awp4K2qn+5NXm63rzslg9 VgH7p1qBXyDgISh6BvBFdpXRGt7B0zStsdL4jdr9WHXRu4LLtskwSaAuQzlxWYuEtKoqKinc ZSSVCE99SYqYJ+C/fDGGqClacf3ExAhuK/sXFoeArfa1Wivkq3t3A0HJtBMwdXKt7Z3Cczrc s8B0Y5bkra20QQ6hVROguEbOOVjKli4YzOT0x7V0kv0ZgRPEaA9SXJSZJqB2DOFKhLuVBRHV tCpnlMetGrqIigQiFVwwqqg0nNS5AhXTD18W2+op+LuW0dfN+uvyuY5TDseBZE3g+14Uidtx eumCIsaz2ArPJaT+qNL2SRm1V6g6txcd5lvVNNPU1CyxouYq69U0RYZ4dyuargfQHrk5Bc/l eN1dSXpIcjw2dU/pjDywrLe/DrLdbavgk4QRiU+dcahGzsaEt3T46Ls1G0mu70/iw3yx2S3x ciPQP16rtvEhUnNtlhdNSUaZc4dVBDH1gdQytDFvNdfJhAjU4/cKs15j6PZuUdTBTCaElRbt WyPQtoS3qwF7jMZ3PfmXq+cew7l6ujYT3J49VYsnUITKikVwSHMna2QHonfIXuy4yOBoIxq8 D3P2ncFRMV9nG2z3NppUMwaHJmaZuYe16lqMPbTLzuZQwrdtsH5FGdgGv4Hj+CPIaUo5+SNg XMHf5i9Nfz+e13hWV/Ypb3mctvuJREp41lJZ04wG0u0+AIWdQY/ZlGtPigctWqU9DgpBLqZe DKIXP0YUj3wow5pOWLh8cZoW7Sviq/bCqe9FQBNb4fDuWBK8StQOScypsf+qx7fd4stzZZ6C BSak2FlKhZY2NXedHYdzBGDwDI4JI82cs3akIFl9N7NXCCQfM7y3cBvF2k1Btud+u1XPmXJF XXcGMBtOZsVtEjSkDucOSXW+/rfaBBA3Lb5VLxA27YW2ZbPSUmIOnTLfJQ/WzSUMW4eG9oOA Q+ksq3b/rjd/g/ezpjgYRTphun3xhi1lxInLyBcZn9vU+PsJ7QGdxzJFBy09r7bwtvHemVcw y83yvL6bopBYt1r3dhzSpEK3jQOgMQ9h3zkrTyoJnXFzDIJQP1VrdDNoQ0H02IGBuwyFYg6E JgRyoajDUZ7l3o3gOe8DRyi/LC3c74xwJWZiz41YHjnT6QwkVUx4Ow7BvS+J+6bBYMzz0o3X nGJQ7seNROgiyzxPywzRe7gZBO+4mhCy8wzDS/zTw4aM9YyYSOGRWaMJtofDxdB839wepohy v+ZgL/hx1BerHGhoEdqR8d7E7fHbs8e3L8vHs/boafSxE8dZ4jS99ski1uzxDgGfW/bS5ON7 Y5NA+9K8k0TZxJBAaY+BALGOKM19mKLaVwJx23RQZOp5wOt+/5cMtLMQpS3THkoejVrOpm4p +QjcjcK4rCeFNEKjrMr/NCFZ+flicHlnD3lsLUdT6V51xGjGXPXwJGk924JfB54tnXt2hyTu s557HsQmJHeHMpAcNsbac20rMp/mMcZwAz66buRwF+v4tnF5d2/VWwUO77wJz1sV6oa6pOHd 7Uu3caxDR2Os6GkrxF0CWluWGtuNy7jzswlRYeTqp+Kwp5OKHdxqdpc4WsP4tHFUz9ppjfCh weS0Hf5lqYvJSPqduVn8HW5LLwkdiwnrpbiL7/pHwPcNvRTx3U8QYaB6EojS58V2u/y6fOx8 WICdaKJaERY2YH7PO9KBzZryLGLzU8DI//C0PZ6dthVXA/sQmiZTR/M8BagJuta5y4Ka5g7G oPXawVciZl1JYCk+BvNuLnYjzofAexT2pr2T5tC4qaUcLRp1W5EQ7DUxabwTFjnLpmrGOxzu nYP9pkbG5hbKLmLNbTy8SzpRdLCrtrtOIQn5zyd6xDJPKpFC+O9RCkrcnbj0vIYM3faRQPYz l7krHcFAWBat8HbG8XJeOVowobBa4bdO8ds04Q1ep0nl9ydEfNpKwuIRWnDX89KEhwY6St++ paTyPtcwYO7FKD5L8YF6wnNbeg/wSeJen+iex1VVPW2D3Tr4UgXVCvPSJ8xJg5RQQ2Cf/4yn xO06ZTzhid8I3eQemeAe9Wb5GFfgHjCmJ8uJqn+Wj1UQbZb/1BWq41uK5WPTHIhuUljUZfi6 dFya5OfsfPtluTr/vt69Pr99O7OjjqlO81g5wyRIx0nSug3KZT12zGVqXpV2rrbjWfOa0Gra k/Ls5HEqiJkkB4rWqw1zvuCu+NQTbDQEbCo95XrzTPcetmDKleeri8NNfF7gSJx6hsL6sRoD ixFezsaeqtWTOa1WAQD+yRjtfPSxz/91u8yrI4gHlPYUeQGF6c17caxj+qloaoqM71AR+emU wnBebEGm0vopkLkJ0pvFavts3GmQLH60SqVmQtgYq+oHLWEygd1U3cbOJyOx9miWD+BeRMaR dzil4sidNqjU2wkZhsjfv3/dB3n16waSnkuRnscQg3wPHr8vX4Ong+raOxbz7sn/xSD+N5dE bklBUT28X2mfd8zRlZpb2s4VgUWFDxpDkk3A2EV6XF62z6aDDnrRYZeDDv7Zu2ldJq5/lrL9 NVFn8byzGNM2cG0TH/q1BuHPfbNkGhys7VwPm59GSken7WA/yWlroXnS5Q3kxq/0wo+RED+d OxHDdPH6itXCRvaM3zPCuHgE89SyT4YrkeawMtxzTHV9EoRvcuu3wa3eTXNzmetl1WxfOZVl 5jHFZqyE6M5eGGZV9fz1w+N6tVssV+DHgbSxtZZ6tQdK6cePl37lTfp2PB/3ofCnDzZWboAc nvjy5fbvD2L1geJJnDj21iCRoKMr7xQZuGW/0cpYFzejJ3kUyeCrMUwv1ct688O3dzWlWwaK kB8jtaahnCXmDlqNBUQC5q10hyBkYfOKc3DRngtRfG+VOl837ylGScHMxPZdoOfjreaK0XXr GLt3bQ/jhYpSeMD48a3vo+8EH8fdlb7gvoEph0i8hwbniwi9ub7oJSlSlvYSUDFDxUs9z+j3 ZInwfLFx4EWG/ZuTvYdPU9ZLoOaf/aeFBvD0/hga66ck+I7PgZmXSO23+Xt47inG0wjMKeZ6 NJpGvmJZKSDkLJke9y5o3L8hnQ2t7fJy++gKEsGIQ4CKXy6qq2R6MfBc+I1Jpj3OoLauKQfj pbn/o3JBh57CapyaNNGJsowmQhUSP9SW/hh5nONHvZ67Svykx3M9SgddVa4vFFmOrm/79vq6 3uzs7aqR8uaKzt0BBA0/XV6crKd+X1v9t9gGfLXdbd5ezFun7ffFBnzKDoNcnCnA2/XgCY5q +Yo/7pMu8ryrNosgzkck+LrcvPwL3YKn9b+r5/XiKaifzltX0uaNfNR+JBCd8qOo4ntfdlzq 4Uml4nihYQ8iCRyyeTPkytigg/0xNHTv/B8Zpk2PtKczZrWQPEw6g2C5oIwPN5+G6YZb8/Fg 8Bvs199/BLvFa/VHQKMPcD6/20d2sAKR5/mqrGHdCwvlITgML/uHH/XDznpTfQhYEi6TIjvZ S/gZ82RPpmVIEjEa+S5QDIGiWA3Db83c8qH3srntyIbKefN+7KXVHlNnMzd/75EOD0SditUp ScJD+KeHRua90gmbMUvYlLVC4Jov7bspMqhJfM07Yf/kdD4Kr2r6fqLhe0RhNh/8DM0ctlp4 HB8b+AfYC+zVrJzjt+Ko1f6ZxrnvP8dAFMa4mXvClT1B75kR72OQGia0nz3C6adeBhqCEuLD fqKbd0a5GfYRpNPeZabTIu05zijXkDWKnvnxJhcksIdC0tRjglI2IsZ0Z2zmqzMfaBL4gd73 0/QvNdeD9wiuegmKWI1pr0hq7okpa+UoFJg97q67gBGJexCPQnmBxs/Nry5vLntYZhDa+dG4 0Bjh1K/E/GSjyBMW1gY279lSfGzPRS9OLj0fM9a2VbMe6Vf36ccr+hnUbOAnujOHgl9hXvQR kdJzPgf8HduY5H0DRPTq5uN//fiF9uOZ8v7vSKa790lfHcyk79izPP18cXHZ6+N6BD/u3zw6 Zoni4j1p7hEyoaJalrz/l1BH0PemI3IlxWl/GhOlng+85Ihpf8oQF6rzaXf93pYxFlxe3QyD 3+LlpprBn99dEX7MJcMLLffYDVhmQrmNZMeMHy9smhJ/5w64dT0Wisx87HeInKIiTe+Pv7K7 giSQeMrulWpMnU/8WoVe856IEdeX5ymh+EjEHhWbNHHL2nSeeC4eYQ6MSUXivaLHj1S8V1oI YlCr5f8au7bmRnVl/Vdc52mth32WrxnnVM2DAGEUcwsCjPNCZTmeiWtN4pTj1K7590ctYRuB WqyHuVjdEkLo0pK6v0/8h5rOgfIivjVHKbbJ7TqLJbDjAaK+K9yI3bZYL/p9lncQ27HD31+A I8j/ezjvXkfktHs9nPe789fJeMjX+N2IRX25pHeY9aFrjZHTll5ZCo0pRYL3dPXJbPJvtKaz +m5S3y1MoTx5ALdiud4rSxp7SVbP3ESLBirFVhlZBfJtGiRJjFzaN+URj6Q51fyJmiQ4rs78 zqAzFBACQJmW36Uxcwdy6ZOP+LmcTCbdM5braYHIKR0nDAVBYyWawyPJQwRrLA8nqICiEuxV XOJRhSzR6u2RyHI/Ud8Qg5hz7G3jZAnxOp/ZmZsPamDPYd7DxoitlbNVEs/QwqrBusFra1WL Ce43QsKKeqSuVuK17SU366DmX9AsjfkEi3FV4pldPB8Ql/5AzYRto9WLYm3rRfcY+oRnduVr PcbTR6Hymw1ZOpCrOZ25PSicmn37eBF74HlqL49GRUg1j3Cxbx2sO62I5q3Np4hhW1argQoE 2oVSkE6MKGGtDPKoU/s8mNFMUWwQKTHPAGzlYOml2amDVVgWIRh4e4jMqCrdzRyt9UM0UFpE spKG+u1iGWGeS3yN4Nbw9XY68CDxFBInWsWjsJrX2M4WZF1j0VAsczP92675crmYiPxIjDB/ Wi7nVTdYxVDyNtNv3MXvyRh5f5+SMB6YGGOScxrpxp1KMk+OfDlbTgd69lLselqxMdVy+e3+ TjOuVJLl5Dum0/Vwa8Ql85h2LKywLszLcStjsmZ6GFFQd7r4bYjlQeLiVqYKUqHxqoM92X+m 2rK2Hyv2nzPM4nsM0ZXwMVyhJnFF43rQiIFgsJxqs+9SbGaQY0sQ5Yl56GXLyd39wMM87Z2z u/F8oPtwSjWfc/gtNrKLgVwsJJ1T7fvpeDYZyqVjPzB+j51cMD65R0T+QIPzDmApj9z7ifm7 05S56OGJKOZ+gmSUwvnQ0OQ5zE2aVSCShJFTD44Zrl8aBCRNt5HoSdiivUKufF2ISIqR6YUV 9krkNChybeyqlIFceo6QDGwu8oQHzNEmltydLZaTgT5Y6pOR+Fnj8NYgFatc4nbCh7X5pSl4 w56weATf88xtGbA0NbVLGmwhmvmtucplbCRSLG4oJF+OZxVkM+80Iq8ru+4Y5CoO0tYpBCmZ C1fX7cRHWG/0pBD8dtsJLhMGPNHTSpZTzqmeCANBT7lsTJrUNvD98ltVIdVnbhoWXC+pmTm7 BcUS/J6EaCPxXFhqlXl+DeFIN5+MJxMXza8MCqydhWFUOyx3iDzuua1qKXK8ZzbON535k7As wYKUkHiGNGM8MgbGAGIXaTlHq983h9nfiEAs8cqlohXXKxXSsELCfpUYifoFFx/Wv6KXftWj zQHcp//oh6n+Cf7Xn/v96Px60TIMlA1ykFVGFZwDmLoY92L9/tCLazZHnEZB6JKU4VIvK+sV WxGOzBXBVmghHawjUcec7x9fZ/RWn8VpkevRhCKh9n2AigQXfsTDA5TgdM6jpUWDS9iOdURS i1JE8oxVXaWr9+8vQAg7APrLj2flqqLnTgpOlY+VMb1OOSkqVMrFmBTmVvUd4BntOtvv3+6W 3co/JFt7E9BySG6KHFAfDffLU3nXdIuj6bdewiIX9ecAsmZRkdHMuU0hKdxANZKtJp3wdvk6 wfPpRfqusL+SUdepgGb6kYxMELvU8XxqhKIEqfi7wZbsZBOTScqRexqpINZTu0JGNhYprCmZ WNqsRQgpOG/YislctIwViajRO8l9fT4978QIaflzXeat1klucxKv4pxDudy1bh/K/KLQmsg3 /TShd0sG7AIdjhBi+O+XdZpvuY4sUqYXWGgIkWfSUcWM/aZunC9F9BIbN7zp4k5vPLF0x8r/ xUM5KJKnBNsU1yuOXC8p0FIWr42QKOVaYWQ1vsGnw/Ovvp99U7/ldNFG4b8ltpq5+05SbN5F tzXirC4gguL73CRtcB+uKsaHXFCTe/0rPr7/BzREinw9eW1iuClrCot8rw54gVdYv+RqJVqa 4QH5Oo2Yu26M2GaNhnh/h2YeQa6iGq1mGD/kZAVt9S9Uh9TgXGKwqAw5L88vFBtIjLWwuBWm qeluTAxThWHSNiiviQrjgyWYV282u78zn16LTWMI9j8CybKxxUnlrviTmtGuy+7MzabI3TVi PwW8bxamKTd11TTlRtWGQ+woYU8vuZQ0T0e7X8fdP8bi8rSeLJZLBbSK2aZq1yYhT1Fgg5aR +vzyItGnxIiTD/78X/yR0M0Mjdow3JRiZBU8Fx9dcusE7UbeTHCqKQnVHG4tCqRE/G83mBs4 XE5FyImDZIXwEiMgGHcA4JczhVSvZtvj+2H3OeKHX4fd8X3kPO/++RDm4l6bk7jpxkvsGkmv OOd0fH7ZHd9Gnx/7HQRtj0jkEM1z1NXhLtXu++vX+fDj613SoNhCQXwP91EAodh2IZ4eIBUT d4VuiUAhh+Cf2WxR1TkX22zz0AlyV8I4uTO8nAg5oydOtRiP8XcIAZUZCeQGGUNk8u08dzZF TsVA/kDiJ4Aoxu4PQKeslgszhERGVxa2q4h6jJgoeFR86+n54xW6mWHYlysCmO3mSzeMiywv oCcXIXeQayqx9wPOJeTAyaNJnRQ5mNSNZ4T5SMlcK1pt44SrYpBweHcdAtFVHboe2iiu2FAf f0nPdDHiLtE7WBMZXEDa/izGVV/YeH1DJGCe6RkBMyHaFGLGuDJ8JUEbgk0TUVxU9UQ97HpN P3A1z4KCmz8C5ElyMd0FLKcAeW/VckL5STjgWjp92yzJ6f+NZNVE/wb2h5f9x/795XMkJiPp F/e32Em2XN7fnn+32w5yroi3MvjJiIfLteq0/yVZNQ/vP07PEKsgHWG0QjbmF40QLjphc/R2 ndcD042w9T3N8ve4wsC6TNRAY2OYYKVikk+Nl7ZSmGdstWpBkUNB+enw86eppEZZ2UnmSa2t 1qChDysGVFiDDiX/QvU6GIdVO+jeJpULlNMNcvLwIUHyPkdn1QhQwtf7i/hPvD//OECQyUjx LYz+gLZS0NR/4k0FO0vWiQJt+eYAUDtzWIidljPxd8ycTsjgFQ7VrRWEZyvh0i9aSYGbJ3xr Tmzi6r//z+m8G7fi+0HFjOEgJMbTJ8ghDHNfhQHoD5PpOqrFNbkTDthOrwtGpQ+EeQ2DKmal jMrvR2YIixhq2vFlS8XABezDjqxTIiD/d+sE6R6fTJd31soIlcVkMqiymA2pfJtPrSo8X0++ 5WRpVYrmy3ygwqAyWwyqLO7tKjy6mw7U2HmcL8d2lSxduGN765WzMUIje2u86Xw87/UIsWWH KUH/8G0ICRvCBCkqj/E0JOZhWhggN8vDSdi/pmcB55E6gEMsGimOIkOh0WF3On4ef5xHwe+P /ek/5ejn1/7TfPYgduyduCb9hJF/HN7l9q03DtxwDSyaF2DSWyqwbXZS5c9ax54Vmk7o9YFN xd46KlATKtu/Hc/7j9Nxdw2N/6NNQPOn/nYSvppGos9kSf8cNft4+/z5L8qR/FNqe84R9mGY ifyMPiLmI/jzYmt6ghAPMcwhKwLIFqQiGyS4FLw1urnkK/qXOEjDefn1KkrU0nTR4ANKrOIB 0fKJ953WSJSXkM0ssjkmyyjjFLCiEPkDLqpw0crnaE2d3PK4mIX9rJdm4w2pDnHbPAMspHII aAe/PhemKPNbuE1eN4GpBAniqjn8ECUw1OCxSHTybplwiQyV/neZT4yOhfLgrNEX3z7ucMco QW/R16RAr6LlAZze0uSOoiQtqBJZQIegCBCbfY52DB/Q5/1+x3afd696jLbPewxtSiyDXf+C cHLo0YYOzXhyf3c3xqpQeL6pBl7C//JJ/pcw7JByFdQ5Umop8qLdL+91TWW6fO6/Xo4Svvn2 uBuXQhMB3KZXcOs14tUnhV1yEJkoWT8jSVCcdRhgWnjLAEml+ZFAwm1kmMISpEYFwafavXch 9lmhU+MsffKfXovcLnhdOfpEBXOxhdId5/EhTnxcFlhF0nsCm1UontXBRRR7uwdfzUO3hr+k NMQR4166hHtXGFjttrjJgbxIrHWduaWjyAuxJmRbS5WuX7KbbpgdrzJO3QJoBbqiNrtNA5PU r/wTBsymxGYGHSXLYMPaLzErHCSWsKmWBCsGuh20ZKUCkJzNexmLACSMwef4pEyKrPMat2nI YXgHCpMVInElfZDp8PixIDzQB/ElTX1b81HdRQX9GlcN8we5PePJ+Oi5PJWBwxm00a66F5Id 22P8jKwiSXqj2LoBk2R2vbhV1oNOuguI60hrXoTSM6qkBrL0G0hmZJlFUlz2GFdzq/QOl2a2 h6Y47RjwB6LLH16iP8XmrctVDjIxxxbTy8cgKACaEevkDCvNTdE8iUfwxQGvX9hflxueptfn 3T86U5+8JWfZo2Lg7Z2TqmvMupmbugy3YjqElVgMbYXHcL3EbrguwH4zkrU18qjguaKBaxmk GfCGQk7NuSciEHQsPlSbHQTY5NKa8Agil/XDEEo8RbeBXEAXMbgJQT4nCbnxYhOgIfWB15BF qCpbACXFGiJJZsTK3wPJ1RSvWJbdAgLgqDRPo+66AAqLvAcJ2UK2ikVbwTqVGPmsNXldkrCg 38ftKkDZwuqJFQsjEkaseGzwMGkh77EutELKIrinROWqGRLnQdTEpgH0SxiuetPE0iOOrPuN fJFYir9xOSGHOQ1BDZzuWSFGgcGme8fcUbE9SGnIG2NJJoNxlZXXHR5yAy/5uIBbUhI9Ygfk 8Bz4Npa6kDyJYECGlKYDVWZAYZAy4Cf3cXDSpp2Ab1jsNDFLu/lyqmNYNICSyyIuI4tQmqfS W8n2tRQlNwTR214fuyWCdpBSSXBsa5CVRSj33ww7FFI6bkY9YVswEiI2v0SDVdO8R7GzQ0lW KmoK+Bbdo+yWimS3z0UXlQMciFXvxnohNw30E9mJUZ0bITXw93Qr03l7xUkPSNQAUmxRVMRp GzEdALI6yrqqlBsNQLtEjN21h9BJXD5ZTbNMRiI+UJzCvuHtsuo0NRIDpjcztCdDv4jVmiTb Lutw7F2lq4ykwYCOav1IjhDZ/l3ewG1MYG7wpWK3FC23MAySrMs76DbJSkcjUHJhLrkZKS0Y YJxI15Fsu2g/kdNgCZ5mVrXLS+ErnkaXiHjvw5x5N7/OhOZJmgCUKsc+pLy1Xq88jRQPfuPz zFrYSXliikakJAu3N+rTm+XZ4D+LySEcmq0B6RD4AZDQKLgpA4rJIEnWlra5uDpa2lc+8gnm K8y9TBHIma/a9ruv0+H828SwtaYYIlNzFiC+LeUrSYsM9MVWXavQ5xZ+vtvTiIHJ53oucWOr l+j2yZWg+/T743wc7Y6n/eh4Gr3uf33sT63rEqkszIeV6KStW5B28rSfLizefqrY+rosDSSA CSLpZwrEZrenD4l91Sxe9RMlq1Q/OSKxmPv6NWnSNQznRtRlIzNmrD3G5Q5CmiyGUlb+ZLrE rn0bnbgIrfJU/ovXBXaojwUtqOH58h/PVjop8oDGrk3FOFbI1/l1/34G+pP9y4i+76BngZfc fw/n1xH5/DzuDlLkPZ+fNaT6pmZuZHvmyi7m9JGVfWx8eQn4dnzpYOM3T3Ssb+kiJ0VXMcc/ AXUdjX5FpYbZxv5d7RWqDJj5gYRVRl4w6IBh9AoceGDZyd9g5vzcf55NzZm5s6m1vBUMXJtC 5M3t4oVlBDI3IBKL1jU0fRZ5YuDZCgcNBKfnpjFd3A1ozKbWMnhAJgPygWcIjcVkah2eq2xy b9XYpJ0i1Oc8fLzql+WX6dw0k5G4cJhlCAiTY274EMK23vjM3g1cAjgPjNh1eL4YUrA2pEe5 Tez3ZtmuxjogT8Q6l3KxfyIDHYJSexE0SzEnq+t0bG2pfJN0G7zx63z7OO0/PxVZVb91/BBz TG1U0JPyy3T31PfyyJ7fX45vo/jr7e/9SfHJXOiy+h0MUOvSDDmWaC3L0oIemluuirwxNvCu G2wM/V1CbzM/rr/dLyqM25VkjWHs93HwD3+fnk+/R6fj1/nwvtcIanMgt8nahKBxcqWIUSy+ sHmpFQtCh0JGyY0i1mIYF9tP2H1mG04j/fVcsfayHOti7gQbRW6dT8YexjgEXja52JMbm1ms FJ06zKb2DU6jEjKXOtvlsMoce64YlNlG9Oz+8x2GPvobBhpqXfRcE/J89dRFYFIpdYW4szVi GYOB0FA2KowgUTyNnCBu6jdxHhSRY9OBw0BrHRz3wSZGjoHAoVqGJ7V39bzp9nqawhW/tDH0 aK3re4+t+9k41O9yL+PisqfuEEIHEoq62W7LBvXlrS9cibVUxVAlqy5LtIdBdRkpLeSmfF3q CHssyyXEI+ke2/w/uhEnG/+gAAA= --------------090507080502090101030103-- From ddaney.cavm@gmail.com Fri Feb 8 18:37:03 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Feb 2013 18:37:05 +0100 (CET) Received: from mail-da0-f42.google.com ([209.85.210.42]:41782 "EHLO mail-da0-f42.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823899Ab3BHRhDyjRyd (ORCPT ); Fri, 8 Feb 2013 18:37:03 +0100 Received: by mail-da0-f42.google.com with SMTP id z17so1916184dal.29 for ; Fri, 08 Feb 2013 09:36:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=i3ns2P73+eYkZfGJdsk225D8ev3lCcZZ31Dhvnl78kA=; b=CJaBnwui32NqoXvNITiI3HU9380HxtwMMdOzalMcGaGxqR9XNMeRJG9F6R9RxSnB/r 8zLifp7+eiB6wiop2SRanqTry1jH+tKX4KhHrL/2bIsVr0E+8YlH9qmQoEhuggmRE6/s meFwLVqQp8HNEvfhGL/p9TV3XCDZ/YZANcwj3GC6gqPI5w1Xo1rkDFzmil8z1HRhHO6L TINSzRriDptpBm9zpsIlSrfFb0voaURNgIs1OxRD3OwIplpxNqGJyuivR231Ozeu/GIx 2BWmlKQgbMJY16FLILCC2lIFaVa9FwzuxJ/BRx9BaBlXSQEwAdhja2k6NQ1F4s+fDAbF pi5Q== X-Received: by 10.66.84.10 with SMTP id u10mr19471597pay.24.1360345016247; Fri, 08 Feb 2013 09:36:56 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id y9sm56010099paw.1.2013.02.08.09.36.54 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 08 Feb 2013 09:36:55 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r18Harj1020648; Fri, 8 Feb 2013 09:36:53 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r18HaqFd020647; Fri, 8 Feb 2013 09:36:52 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h Date: Fri, 8 Feb 2013 09:36:51 -0800 Message-Id: <1360345011-20614-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-archive-position: 35729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2666 Lines: 80 From: David Daney The internal codes are not part of the kernel's abi. Signed-off-by: David Daney --- The transition of break.h to /uapi/asm happened in 3.8rc, so it is not too late to prevent this crap from escaping to the kernel's userspace ABI. arch/mips/include/asm/break.h | 27 +++++++++++++++++++++++++++ arch/mips/include/uapi/asm/break.h | 12 +++--------- 2 files changed, 30 insertions(+), 9 deletions(-) create mode 100644 arch/mips/include/asm/break.h diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h new file mode 100644 index 0000000..67b6f72 --- /dev/null +++ b/arch/mips/include/asm/break.h @@ -0,0 +1,27 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 2003 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_BREAK_H +#define __ASM_BREAK_H + +#ifdef __UAPI_ASM_BREAK_H +#error "Error: Do not directly include " +#endif +#include + +/* + * Break codes used internally to the kernel. + */ +#define BRK_BUG 512 /* Used by BUG() */ +#define BRK_KDB 513 /* Used in KDB_ENTER() */ +#define BRK_MEMU 514 /* Used by FPU emulator */ +#define BRK_KPROBE_BP 515 /* Kprobe break */ +#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */ +#define BRK_MULOVF 1023 /* Multiply overflow */ + +#endif /* __ASM_BREAK_H */ diff --git a/arch/mips/include/uapi/asm/break.h b/arch/mips/include/uapi/asm/break.h index 9161e68..ede4baa 100644 --- a/arch/mips/include/uapi/asm/break.h +++ b/arch/mips/include/uapi/asm/break.h @@ -6,8 +6,8 @@ * Copyright (C) 1995, 2003 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ -#ifndef __ASM_BREAK_H -#define __ASM_BREAK_H +#ifndef __UAPI_ASM_BREAK_H +#define __UAPI_ASM_BREAK_H /* * The following break codes are or were in use for specific purposes in @@ -27,11 +27,5 @@ #define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ -#define BRK_BUG 512 /* Used by BUG() */ -#define BRK_KDB 513 /* Used in KDB_ENTER() */ -#define BRK_MEMU 514 /* Used by FPU emulator */ -#define BRK_KPROBE_BP 515 /* Kprobe break */ -#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */ -#define BRK_MULOVF 1023 /* Multiply overflow */ -#endif /* __ASM_BREAK_H */ +#endif /* __UAPI_ASM_BREAK_H */ -- 1.7.11.7 From ronny.meeus@gmail.com Sat Feb 9 14:23:30 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Feb 2013 14:23:30 +0100 (CET) Received: from mail-ie0-f181.google.com ([209.85.223.181]:38149 "EHLO mail-ie0-f181.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6826533Ab3BINXaIrkvu (ORCPT ); Sat, 9 Feb 2013 14:23:30 +0100 Received: by mail-ie0-f181.google.com with SMTP id 17so6058902iea.26 for ; Sat, 09 Feb 2013 05:23:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:mime-version:from:date:message-id:subject:to :content-type; bh=CX4qdacUOc/rXRhAKOCa+4p7eRGfwYh4Z5L+jaDFp80=; b=UnGUvwRwEGY+oEJIkJvnCfZtLWgNt73aOBlBKRySeAP+Oyk6FjQlkolpR0MU+T+O2s Fg2IcTskrdp85Sovx2NYXbCTWiH/Ha2Wad/R8DsIRdAoic76QBXARhTnaATlqD65W6xI m+whf9J7hA65bBe6W8DRM7fHSJRbzODJkh0+qbCZ02BFPYe+t7BNkud/z1hP8FNKk+hR kXXVEG0CvFlLeUFwA/e118eODzkytB+BpJX/qoYJr5shYLovzblYAT2AgyLvnIAus2Ol iXBBDoO6zJOWwq0DDhjNqi+Cj2TtbKkFm+PnGnPbB6FTLZuT/7mt/h6Ljo8Wk1LKQlD7 o87w== X-Received: by 10.50.88.200 with SMTP id bi8mr7599596igb.52.1360416203403; Sat, 09 Feb 2013 05:23:23 -0800 (PST) MIME-Version: 1.0 Received: by 10.42.85.83 with HTTP; Sat, 9 Feb 2013 05:23:03 -0800 (PST) From: Ronny Meeus Date: Sat, 9 Feb 2013 14:23:03 +0100 Message-ID: Subject: Reserving a part of the system ram. To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ronny.meeus@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 676 Lines: 20 Hello I have a board that has 4Gb of RAM which can completely be used by Linux, except for a 64Mb block located just below the 2G boundary. This block will be used to implement a kind of persistent storage. On PPC we do this with a memreserve in the device tree but this does not seem to work on MIPS. Another option I found is the memmap kernel parameter, which can also be used the reserve a piece of memory that is reserved (something like memmap=size$addres would do the trick, but no luck, this is also not supported. This is the Linux version I'm using for my project: Linux version 2.6.32.27-Cavium-Octeon What is the correct way to make this work? Thanks, Ronny From juhosg@openwrt.org Sat Feb 9 19:58:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Feb 2013 19:58:06 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:52492 "EHLO mail.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827458Ab3BIS6FH9Rn1 (ORCPT ); Sat, 9 Feb 2013 19:58:05 +0100 Received: from localhost (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id ACDD925E6D7; Sat, 9 Feb 2013 19:57:58 +0100 (CET) Received: from mail.szarvasnet.hu ([127.0.0.1]) by localhost (phoenix3.szarvasnet.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FVuFozMAtQhN; Sat, 9 Feb 2013 19:57:58 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 4ED7225DC0A; Sat, 9 Feb 2013 19:57:58 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos Subject: [PATCH] MIPS: ath79: use dynamically allocated USB platform devices Date: Sat, 9 Feb 2013 19:57:52 +0100 Message-Id: <1360436272-10854-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35731 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6460 Lines: 200 The current code uses static resources and static platform device instances for the possible USB controllers in the system. These static variables contains initial values which leads to data segment pollution. Remove the static variables and use dynamically allocated structures instead. Signed-off-by: Gabor Juhos --- arch/mips/ath79/dev-usb.c | 111 +++++++++++++++++++++------------------------ 1 file changed, 51 insertions(+), 60 deletions(-) diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index bcb165b..02124d0 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -25,29 +25,11 @@ #include "common.h" #include "dev-usb.h" -static struct resource ath79_ohci_resources[2]; - -static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); +static u64 ath79_usb_dmamask = DMA_BIT_MASK(32); static struct usb_ohci_pdata ath79_ohci_pdata = { }; -static struct platform_device ath79_ohci_device = { - .name = "ohci-platform", - .id = -1, - .resource = ath79_ohci_resources, - .num_resources = ARRAY_SIZE(ath79_ohci_resources), - .dev = { - .dma_mask = &ath79_ohci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &ath79_ohci_pdata, - }, -}; - -static struct resource ath79_ehci_resources[2]; - -static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); - static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { .has_synopsys_hc_bug = 1, }; @@ -57,22 +39,16 @@ static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { .has_tt = 1, }; -static struct platform_device ath79_ehci_device = { - .name = "ehci-platform", - .id = -1, - .resource = ath79_ehci_resources, - .num_resources = ARRAY_SIZE(ath79_ehci_resources), - .dev = { - .dma_mask = &ath79_ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static void __init ath79_usb_init_resource(struct resource res[2], - unsigned long base, - unsigned long size, - int irq) +static void __init ath79_usb_register(const char *name, int id, + unsigned long base, unsigned long size, + int irq, const void *data, + size_t data_size) { + struct resource res[2]; + struct platform_device *pdev; + + memset(res, 0, sizeof(res)); + res[0].flags = IORESOURCE_MEM; res[0].start = base; res[0].end = base + size - 1; @@ -80,6 +56,19 @@ static void __init ath79_usb_init_resource(struct resource res[2], res[1].flags = IORESOURCE_IRQ; res[1].start = irq; res[1].end = irq; + + pdev = platform_device_register_resndata(NULL, name, id, + res, ARRAY_SIZE(res), + data, data_size); + + if (IS_ERR(pdev)) { + pr_err("ath79: unable to register USB at %08lx, err=%d\n", + base, (int) PTR_ERR(pdev)); + return; + } + + pdev->dev.dma_mask = &ath79_usb_dmamask; + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); } #define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ @@ -106,14 +95,15 @@ static void __init ath79_usb_setup(void) mdelay(900); - ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, - AR71XX_OHCI_SIZE, ATH79_MISC_IRQ(6)); - platform_device_register(&ath79_ohci_device); + ath79_usb_register("ohci-platform", -1, + AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE, + ATH79_MISC_IRQ(6), + &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); - ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, - AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3)); - ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; - platform_device_register(&ath79_ehci_device); + ath79_usb_register("ehci-platform", -1, + AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE, + ATH79_CPU_IRQ(3), + &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1)); } static void __init ar7240_usb_setup(void) @@ -135,9 +125,10 @@ static void __init ar7240_usb_setup(void) iounmap(usb_ctrl_base); - ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, - AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3)); - platform_device_register(&ath79_ohci_device); + ath79_usb_register("ohci-platform", -1, + AR7240_OHCI_BASE, AR7240_OHCI_SIZE, + ATH79_CPU_IRQ(3), + &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); } static void __init ar724x_usb_setup(void) @@ -151,10 +142,10 @@ static void __init ar724x_usb_setup(void) ath79_device_reset_clear(AR724X_RESET_USB_PHY); mdelay(10); - ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, - AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3)); - ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; - platform_device_register(&ath79_ehci_device); + ath79_usb_register("ehci-platform", -1, + AR724X_EHCI_BASE, AR724X_EHCI_SIZE, + ATH79_CPU_IRQ(3), + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); } static void __init ar913x_usb_setup(void) @@ -168,10 +159,10 @@ static void __init ar913x_usb_setup(void) ath79_device_reset_clear(AR913X_RESET_USB_PHY); mdelay(10); - ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, - AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3)); - ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; - platform_device_register(&ath79_ehci_device); + ath79_usb_register("ehci-platform", -1, + AR913X_EHCI_BASE, AR913X_EHCI_SIZE, + ATH79_CPU_IRQ(3), + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); } static void __init ar933x_usb_setup(void) @@ -185,10 +176,10 @@ static void __init ar933x_usb_setup(void) ath79_device_reset_clear(AR933X_RESET_USB_PHY); mdelay(10); - ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, - AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3)); - ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; - platform_device_register(&ath79_ehci_device); + ath79_usb_register("ehci-platform", -1, + AR933X_EHCI_BASE, AR933X_EHCI_SIZE, + ATH79_CPU_IRQ(3), + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); } static void __init ar934x_usb_setup(void) @@ -211,10 +202,10 @@ static void __init ar934x_usb_setup(void) ath79_device_reset_clear(AR934X_RESET_USB_HOST); udelay(1000); - ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, - AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3)); - ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; - platform_device_register(&ath79_ehci_device); + ath79_usb_register("ehci-platform", -1, + AR934X_EHCI_BASE, AR934X_EHCI_SIZE, + ATH79_CPU_IRQ(3), + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); } void __init ath79_register_usb(void) -- 1.7.10 From ralf@linux-mips.org Sun Feb 10 13:56:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Feb 2013 13:56:28 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36149 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6824793Ab3BJM41UemYA (ORCPT ); Sun, 10 Feb 2013 13:56:27 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r1ACuQ1P014520; Sun, 10 Feb 2013 13:56:26 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r1ACuPeo014480; Sun, 10 Feb 2013 13:56:25 +0100 Date: Sun, 10 Feb 2013 13:56:25 +0100 From: Ralf Baechle To: folkert Cc: linux-mips@linux-mips.org Subject: Re: prom start Message-ID: <20130210125625.GA32552@linux-mips.org> References: <20130206160508.GR2118@belle.intranet.vanheusden.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130206160508.GR2118@belle.intranet.vanheusden.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35732 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1261 Lines: 26 On Wed, Feb 06, 2013 at 05:05:10PM +0100, folkert wrote: > Is this mailing list also meant for generic mips questions? (if not: any > suggestions for one that is?) > > If so: I'mm experimenting a bit with mips, specifically on SGI hardware > (Indigo). Now it seems all mips systems have the prom at 0xbfc00000. But > how does it start? The first 0x3c0 bytes seem to be nonsense. Somewhere > on the web I found that 0xbfc00884 is the starting point but after > single stepping 5 instructions, the program counter jumps to 0x00000000 > so I don't think that's the right one either. Also, reading the first 4 > bytes from bfc00000 and using that as a pointer seems to be invalid too: > 0bf000f0. > Anyone with insights regarding the booting of the prom on sgi systems? All MIPS processors start execution at 0xbfc00000 after a hardware reset or NMI. 0xbfc00884 is not an address that has any specific meaning in the processor architecture itself. I think it's being used in the GXemul documentation just for sake of an example. If your disassembler defaults to like MIPS I / R3000 it won't disassemble all instructions for the MIPS III R4000 processor. I'd expect some cache initialization code right at 0xbfc00000 and that could would be affected. Ralf From folkert@vanheusden.com Sun Feb 10 17:43:46 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Feb 2013 17:43:47 +0100 (CET) Received: from keetweej.vanheusden.com ([80.101.105.103]:55531 "EHLO keetweej.vanheusden.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827437Ab3BJQnqmWKRe (ORCPT ); Sun, 10 Feb 2013 17:43:46 +0100 Received: from belle.intranet.vanheusden.com (unknown [192.168.64.100]) by keetweej.vanheusden.com (Postfix) with ESMTP id C177E15FA43; Sun, 10 Feb 2013 17:43:45 +0100 (CET) Received: by belle.intranet.vanheusden.com (Postfix, from userid 1000) id A41C593510; Sun, 10 Feb 2013 17:43:45 +0100 (CET) Date: Sun, 10 Feb 2013 17:43:45 +0100 From: folkert To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: prom start Message-ID: <20130210164344.GE8791@belle.intranet.vanheusden.com> References: <20130206160508.GR2118@belle.intranet.vanheusden.com> <20130210125625.GA32552@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130210125625.GA32552@linux-mips.org> Organization: www.unixexpert.nl X-Chameleon-Return-To: folkert@vanheusden.com X-Xfmail-Return-To: folkert@vanheusden.com X-Phonenumber: +31-6-41278122 X-URL: http://www.vanheusden.com/ X-PGP-KeyID: 1F28D8AE X-GPG-fingerprint: AC89 09CE 41F2 00B4 FCF2 B174 3019 0E8C 1F28 D8AE X-Key: http://pgp.surfnet.nl:11371/pks/lookup?op=get&search=0x1F28D8AE Read-Receipt-To: Reply-By: Sat Feb 9 18:32:07 CET 2013 X-Message-Flag: PGP key-id: 0x1f28d8ae - consider encrypting your e-mail to me with PGP! User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35733 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: folkert@vanheusden.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2131 Lines: 48 Hi, > > Is this mailing list also meant for generic mips questions? (if not: any > > suggestions for one that is?) > > > > If so: I'mm experimenting a bit with mips, specifically on SGI hardware > > (Indigo). Now it seems all mips systems have the prom at 0xbfc00000. But > > how does it start? The first 0x3c0 bytes seem to be nonsense. Somewhere > > on the web I found that 0xbfc00884 is the starting point but after > > single stepping 5 instructions, the program counter jumps to 0x00000000 > > so I don't think that's the right one either. Also, reading the first 4 > > bytes from bfc00000 and using that as a pointer seems to be invalid too: > > 0bf000f0. > > Anyone with insights regarding the booting of the prom on sgi systems? > > All MIPS processors start execution at 0xbfc00000 after a hardware reset > or NMI. 0xbfc00884 is not an address that has any specific meaning in > the processor architecture itself. I think it's being used in the GXemul > documentation just for sake of an example. Yes that seems to be the case. If I start at 0xbfc00000 it looks meaningful. > If your disassembler defaults to like MIPS I / R3000 it won't disassemble > all instructions for the MIPS III R4000 processor. I'd expect some > cache initialization code right at 0xbfc00000 and that could would be > affected. I'm not entirely sure yet. My D-A (well, an emulator to be honest) implements the mips as described in MD00086 (by Mips technologies) of June 2003 and at the bottom that document acknowledges the MIPS R3000, 4000, 5000 and 10000. It's really fun to do, writing that mips code. All new to me. I'm at the point that it emulates enough of the prom that it reaches points where it gets even more interesting: undocumented hardware (0xbfa00030 and 0xbfa01004 anyone?) and fiddeling with COP0. Folkert van Heusden -- Curious about the inner workings of your car? Then check O2OO: it'll tell you all that there is to know about your car's engine! http://www.vanheusden.com/O2OO/ ---------------------------------------------------------------------- Phone: +31-6-41278122, PGP-key: 1F28D8AE, www.vanheusden.com From ronny.meeus@gmail.com Mon Feb 11 20:00:46 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Feb 2013 20:00:47 +0100 (CET) Received: from mail-ie0-f173.google.com ([209.85.223.173]:33708 "EHLO mail-ie0-f173.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827591Ab3BKTAqyJp0q (ORCPT ); Mon, 11 Feb 2013 20:00:46 +0100 Received: by mail-ie0-f173.google.com with SMTP id 9so8111905iec.4 for ; Mon, 11 Feb 2013 11:00:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; bh=lGcg6h7LfQp/SWaLLJcAMAL6YyoeAxY48Zc1GXXVlSw=; b=UyOTGHgPLGDGjYsOgHx7GHV2tfDNh1mRZ7eb9/bezFIqmF3Vvd8UN1L5YxDgHSdhF8 NN0/Khc3xKA1VYPW7uiCQwS1z251GZBdPcF0XnIHJquwvjc8Xqt6AclpxFlzKz1j9h/x k22xw0QMJ3GbwbGA9OP/ESk5MvDY6XKlnctwoyyjnTnw2uS0L5Krw3lH8vOQEqn3tZQt ++OyXZQiJUvnuVsbn8sL03VQX9AdH/Dh5q9CocJFQ76ofqTCmFnx43U92Dl9YorABJfM vZILoulyWaPhUcH3LY3pF9kx220cSoeckUjgtSKiKXBGfuHMWLyfv5Zd1J7sqMt4I2FA DThA== X-Received: by 10.43.111.201 with SMTP id ep9mr8206375icc.43.1360609240130; Mon, 11 Feb 2013 11:00:40 -0800 (PST) MIME-Version: 1.0 Received: by 10.42.85.83 with HTTP; Mon, 11 Feb 2013 11:00:20 -0800 (PST) In-Reply-To: References: From: Ronny Meeus Date: Mon, 11 Feb 2013 20:00:20 +0100 Message-ID: Subject: Re: Reserving a part of the system ram. To: linux-mips@linux-mips.org Cc: David Daney Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35734 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ronny.meeus@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4171 Lines: 114 On Sat, Feb 9, 2013 at 2:23 PM, Ronny Meeus wrote: > Hello > > I have a board that has 4Gb of RAM which can completely be used by > Linux, except for a 64Mb block located just below the 2G boundary. > This block will be used to implement a kind of persistent storage. > > On PPC we do this with a memreserve in the device tree but this does > not seem to work on MIPS. > Another option I found is the memmap kernel parameter, which can also > be used the reserve a piece of memory that is reserved (something like > memmap=size$addres would do the trick, but no luck, this is also not > supported. > > This is the Linux version I'm using for my project: > Linux version 2.6.32.27-Cavium-Octeon > > What is the correct way to make this work? > > Thanks, > Ronny Hello I had a look to the code over the weekend and I was able to understand how it works. Today I changed the code and it looks like it works. The change I have made can be found in the patch below. The clue is that the complete memory of the Cavium board is managed/known by uboot. It creates a bootmemory structure that is used by Linux to configure its memory during init. It basically allocates blocks of 4MB from this bootmem until the size specified in the mem parameter is reached. If 0 is passed to the mem command line parameter, it allocates all available memory. Uboot knows already about the memreserves done in the device tree so the only thing that was missing is to allocate the memory specified in the memreserves from the bootmemory. Once this was done, Linux does not touch the memreserved memory anymore. The patch below is not a Linux patch, but a uboot one. Is this way of working a standard solution or is it dedicated to Mips or Cavium? Regards, Ronny diff --git a/arch/mips/cpu/octeon/commands/cmd_octeon_linux.c b/arch/mips/cpu/octeon/commands/cmd_octeon_linux.c --- a/arch/mips/cpu/octeon/commands/cmd_octeon_linux.c +++ b/arch/mips/cpu/octeon/commands/cmd_octeon_linux.c @@ -189,6 +189,8 @@ int do_bootoctlinux(cmd_tbl_t * cmdtp, i */ cvmx_bootmem_phy_named_block_free(OCTEON_LINUX_RESERVED_MEM_NAME, 0); + octeon_alloc_memreserves_from_bootmem(); + if (((Elf32_Ehdr *)addr)->e_ident[EI_CLASS] == ELFCLASS32) { if (alloc_elf32_image(addr)) { entry_addr = load_elf_image(addr); diff --git a/arch/mips/cpu/octeon/octeon_fdt.c b/arch/mips/cpu/octeon/octeon_fdt.c --- a/arch/mips/cpu/octeon/octeon_fdt.c +++ b/arch/mips/cpu/octeon/octeon_fdt.c @@ -344,3 +344,30 @@ int __board_fixup_fdt(void) } int board_fixup_fdt(void) __attribute__((weak, alias("__board_fixup_fdt"))); + + +void octeon_alloc_memreserves_from_bootmem(void) +{ + uint64_t addr, size; + int j, err; + char name[32]; + int total = fdt_num_mem_rsv(working_fdt); + for (j = 0; j < total; j++) { + int64_t mem = 0; + err = fdt_get_mem_rsv(working_fdt, j, &addr, &size); + if (err < 0) { + printf("libfdt fdt_get_mem_rsv(): %s\n", + fdt_strerror(err)); + return err; + } + sprintf(name,"fdt_memreserve%d",j); + printf("alloc_bootmem %16s %08x%08x %08x%08x\n",name, + (u32)(addr >> 32),(u32)(addr & 0xffffffff), + (u32)(size >> 32),(u32)(size & 0xffffffff)); + mem = cvmx_bootmem_phy_named_block_alloc(size,addr,addr+size,0,name,0); + if (mem < 0) { + printf("Named allocation failed!\n"); + } + } +} + diff --git a/arch/mips/include/asm/arch-octeon/octeon_fdt.h b/arch/mips/include/asm/arch-octeon/octeon_fdt.h --- a/arch/mips/include/asm/arch-octeon/octeon_fdt.h +++ b/arch/mips/include/asm/arch-octeon/octeon_fdt.h @@ -77,5 +77,6 @@ int octeon_fdt_patch(void *fdt, const char *fdt_key, const char *trim_name); int board_fixup_fdt(void); void octeon_fixup_fdt(void); +void octeon_alloc_memreserves_from_bootmem(void); -#endif /* __OCTEON_FDT_H__ */ \ No newline at end of file +#endif /* __OCTEON_FDT_H__ */ From aaro.koskinen@iki.fi Mon Feb 11 22:52:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Feb 2013 22:52:30 +0100 (CET) Received: from filtteri1.pp.htv.fi ([213.243.153.184]:53790 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827599Ab3BKVw1CFc89 (ORCPT ); Mon, 11 Feb 2013 22:52:27 +0100 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id 49AE821B655; Mon, 11 Feb 2013 23:52:06 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp4.welho.com ([213.243.153.38]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id ber-KRvdomFQ; Mon, 11 Feb 2013 23:52:05 +0200 (EET) Received: from blackmetal.pp.htv.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp4.welho.com (Postfix) with ESMTP id CA3415BC005; Mon, 11 Feb 2013 23:52:05 +0200 (EET) From: Aaro Koskinen To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Aaro Koskinen Subject: [PATCH] MIPS: early_printk: drop __init annotations Date: Mon, 11 Feb 2013 23:51:49 +0200 Message-Id: <1360619509-6576-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3581 Lines: 118 We cannot use __init for earlyprintk code or data, since the kernel parameter "keep_bootcon" allows leaving the boot console enabled. Currently MIPS will crash/hang/die if you use keep_bootcon. The patch fixes it at least on Lemote FuLoong mini-PC. Changes for other boards were done based on what I could find with grep... Signed-off-by: Aaro Koskinen --- arch/mips/bcm63xx/early_printk.c | 4 ++-- arch/mips/kernel/early_printk.c | 5 ++--- arch/mips/loongson1/common/prom.c | 2 +- arch/mips/sgi-ip27/ip27-console.c | 2 +- arch/mips/txx9/generic/setup.c | 8 ++++---- 5 files changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c index bf353c9..aa8f7f9 100644 --- a/arch/mips/bcm63xx/early_printk.c +++ b/arch/mips/bcm63xx/early_printk.c @@ -10,7 +10,7 @@ #include #include -static void __init wait_xfered(void) +static void wait_xfered(void) { unsigned int val; @@ -22,7 +22,7 @@ static void __init wait_xfered(void) } while (1); } -void __init prom_putchar(char c) +void prom_putchar(char c) { wait_xfered(); bcm_uart0_writel(c, UART_FIFO_REG); diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c index 9ae813e..9e6440e 100644 --- a/arch/mips/kernel/early_printk.c +++ b/arch/mips/kernel/early_printk.c @@ -14,8 +14,7 @@ extern void prom_putchar(char); -static void __init -early_console_write(struct console *con, const char *s, unsigned n) +static void early_console_write(struct console *con, const char *s, unsigned n) { while (n-- && *s) { if (*s == '\n') @@ -25,7 +24,7 @@ early_console_write(struct console *con, const char *s, unsigned n) } } -static struct console early_console __initdata = { +static struct console early_console = { .name = "early", .write = early_console_write, .flags = CON_PRINTBUFFER | CON_BOOT, diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c index 1f8e49f..54dee09 100644 --- a/arch/mips/loongson1/common/prom.c +++ b/arch/mips/loongson1/common/prom.c @@ -73,7 +73,7 @@ void __init prom_free_prom_memory(void) #define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset)) -void __init prom_putchar(char c) +void prom_putchar(char c) { int timeout; diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c index 984e561..b952d5b 100644 --- a/arch/mips/sgi-ip27/ip27-console.c +++ b/arch/mips/sgi-ip27/ip27-console.c @@ -31,7 +31,7 @@ static inline struct ioc3_uartregs *console_uart(void) return &ioc3->sregs.uarta; } -void __init prom_putchar(char c) +void prom_putchar(char c) { struct ioc3_uartregs *uart = console_uart(); diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 560fe89..5524f2c 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -513,19 +513,19 @@ void __init txx9_sio_init(unsigned long baseaddr, int irq, } #ifdef CONFIG_EARLY_PRINTK -static void __init null_prom_putchar(char c) +static void null_prom_putchar(char c) { } -void (*txx9_prom_putchar)(char c) __initdata = null_prom_putchar; +void (*txx9_prom_putchar)(char c) = null_prom_putchar; -void __init prom_putchar(char c) +void prom_putchar(char c) { txx9_prom_putchar(c); } static void __iomem *early_txx9_sio_port; -static void __init early_txx9_sio_putchar(char c) +static void early_txx9_sio_putchar(char c) { #define TXX9_SICISR 0x0c #define TXX9_SITFIFO 0x1c -- 1.7.10.4 From minyard@acm.org Tue Feb 12 21:42:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Feb 2013 21:42:22 +0100 (CET) Received: from vms173007pub.verizon.net ([206.46.173.7]:63569 "EHLO vms173007pub.verizon.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827608Ab3BLUmTxlVgh (ORCPT ); Tue, 12 Feb 2013 21:42:19 +0100 Received: from wf-rch.minyard.home ([unknown] [173.74.121.95]) by vms173007.mailsrvcs.net (Sun Java(tm) System Messaging Server 7u2-7.02 32bit (built Apr 16 2009)) with ESMTPA id <0MI400A4TK5RXCJ1@vms173007.mailsrvcs.net> for linux-mips@linux-mips.org; Tue, 12 Feb 2013 14:41:56 -0600 (CST) Received: from i.minyard.home (i2.minyard.home [192.168.27.116]) by wf-rch.minyard.home (Postfix) with ESMTP id 020DC1F93D for ; Tue, 12 Feb 2013 14:41:50 -0600 (CST) Received: by i.minyard.home (Postfix, from userid 1000) id 40EBD80EE3; Tue, 12 Feb 2013 14:41:51 -0600 (CST) From: minyard@acm.org To: linux-mips@linux-mips.org Subject: [PATCH 0/2] mips: Add some kdump fail-safes for kernel memory Date: Tue, 12 Feb 2013 14:41:46 -0600 Message-id: <1360701708-21371-1-git-send-email-minyard@acm.org> X-Mailer: git-send-email 1.7.4.1 X-archive-position: 35736 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: minyard@acm.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 435 Lines: 10 I was having some trouble with kdump on Octeon, and due to the way memory is handled there the MIPS kernel's assumptions about memory were not correct. The first patch adds a fail-safes to make sure kernel memory is in the memory map. That way it appears in /proc/iomem. The second patch reserve the elfcorehdr from kdump if it appears in the kernel's managed memory. That way it won't get clobbered by the kernel if that happens. From minyard@acm.org Tue Feb 12 21:42:22 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Feb 2013 21:42:40 +0100 (CET) Received: from vms173001pub.verizon.net ([206.46.173.1]:38400 "EHLO vms173001pub.verizon.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827610Ab3BLUmWNlrhZ (ORCPT ); Tue, 12 Feb 2013 21:42:22 +0100 Received: from wf-rch.minyard.home ([unknown] [173.74.121.95]) by vms173001.mailsrvcs.net (Sun Java(tm) System Messaging Server 7u2-7.02 32bit (built Apr 16 2009)) with ESMTPA id <0MI4001PXK5S7P35@vms173001.mailsrvcs.net>; Tue, 12 Feb 2013 14:41:57 -0600 (CST) Received: from i.minyard.home (i2.minyard.home [192.168.27.116]) by wf-rch.minyard.home (Postfix) with ESMTP id 1F6401F957; Tue, 12 Feb 2013 14:41:50 -0600 (CST) Received: by i.minyard.home (Postfix, from userid 1000) id A625F80D94; Tue, 12 Feb 2013 14:41:51 -0600 (CST) From: minyard@acm.org To: linux-mips@linux-mips.org Cc: Corey Minyard , Ralf Baechle Subject: [PATCH 2/2] mips: reserve elfcorehdr Date: Tue, 12 Feb 2013 14:41:48 -0600 Message-id: <1360701708-21371-3-git-send-email-minyard@acm.org> X-Mailer: git-send-email 1.7.4.1 In-reply-to: <1360701708-21371-1-git-send-email-minyard@acm.org> References: <1360701708-21371-1-git-send-email-minyard@acm.org> X-archive-position: 35737 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: minyard@acm.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2306 Lines: 75 From: Corey Minyard /proc/vmcore wasn't showing up in kdump kernels. It turns that that for Octeon, the memory used by elfcorehdr wasn't being set aside properly and it was getting clobbered before /proc/vmcore could get it. So reserve the memory if it shows up in a memory area managed by the kernel. Signed-off-by: Corey Minyard Acked-by: David Daney Cc: Ralf Baechle --- arch/mips/kernel/setup.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 39 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 5346250..795f437 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -480,6 +480,37 @@ static int __init early_parse_mem(char *p) } early_param("mem", early_parse_mem); +#ifdef CONFIG_PROC_VMCORE +unsigned long setup_elfcorehdr, setup_elfcorehdr_size; +static int __init early_parse_elfcorehdr(char *p) +{ + int i; + + setup_elfcorehdr = memparse(p, &p); + + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long start = boot_mem_map.map[i].addr; + unsigned long end = (boot_mem_map.map[i].addr + + boot_mem_map.map[i].size); + if (setup_elfcorehdr >= start && setup_elfcorehdr < end) { + /* + * Reserve from the elf core header to the end of + * the memory segment, that should all be kdump + * reserved memory. + */ + setup_elfcorehdr_size = end - setup_elfcorehdr; + break; + } + } + /* + * If we don't find it in the memory map, then we shouldn't + * have to worry about it, as the new kernel won't use it. + */ + return 0; +} +early_param("elfcorehdr", early_parse_elfcorehdr); +#endif + static void __init arch_mem_addpart(phys_t mem, phys_t end, int type) { phys_t size; @@ -547,6 +578,14 @@ static void __init arch_mem_init(char **cmdline_p) } bootmem_init(); +#ifdef CONFIG_PROC_VMCORE + if (setup_elfcorehdr && setup_elfcorehdr_size) { + printk(KERN_INFO "kdump reserved memory at %lx-%lx\n", + setup_elfcorehdr, setup_elfcorehdr_size); + reserve_bootmem(setup_elfcorehdr, setup_elfcorehdr_size, + BOOTMEM_DEFAULT); + } +#endif #ifdef CONFIG_KEXEC if (crashk_res.start != crashk_res.end) reserve_bootmem(crashk_res.start, -- 1.7.4.1 From minyard@acm.org Tue Feb 12 21:42:33 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Feb 2013 21:43:04 +0100 (CET) Received: from vms173013pub.verizon.net ([206.46.173.13]:57025 "EHLO vms173013pub.verizon.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827604Ab3BLUmdNmEPK (ORCPT ); Tue, 12 Feb 2013 21:42:33 +0100 Received: from wf-rch.minyard.home ([unknown] [173.74.121.95]) by vms173013.mailsrvcs.net (Sun Java(tm) System Messaging Server 7u2-7.02 32bit (built Apr 16 2009)) with ESMTPA id <0MI40056XK5SS9D0@vms173013.mailsrvcs.net>; Tue, 12 Feb 2013 14:41:57 -0600 (CST) Received: from i.minyard.home (i2.minyard.home [192.168.27.116]) by wf-rch.minyard.home (Postfix) with ESMTP id 2B7D71F95B; Tue, 12 Feb 2013 14:41:51 -0600 (CST) Received: by i.minyard.home (Postfix, from userid 1000) id 6BBCF8069A; Tue, 12 Feb 2013 14:41:51 -0600 (CST) From: minyard@acm.org To: linux-mips@linux-mips.org Cc: Corey Minyard , Ralf Baechle Subject: [PATCH 1/2] mips: Make sure kernel memory is in iomem Date: Tue, 12 Feb 2013 14:41:47 -0600 Message-id: <1360701708-21371-2-git-send-email-minyard@acm.org> X-Mailer: git-send-email 1.7.4.1 In-reply-to: <1360701708-21371-1-git-send-email-minyard@acm.org> References: <1360701708-21371-1-git-send-email-minyard@acm.org> X-archive-position: 35738 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: minyard@acm.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2581 Lines: 86 From: Corey Minyard Kernel memory isn't necessarily added to the memory tables, so it wouldn't show up in /proc/iomem. This was breaking kdump, which requires these memory addresses to work correctly. Signed-off-by: Corey Minyard Acked-by: David Daney Cc: Ralf Baechle --- arch/mips/kernel/setup.c | 52 +++++++++++++++++++++++++++------------------ 1 files changed, 31 insertions(+), 21 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 8c41187..5346250 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -480,34 +480,44 @@ static int __init early_parse_mem(char *p) } early_param("mem", early_parse_mem); -static void __init arch_mem_init(char **cmdline_p) +static void __init arch_mem_addpart(phys_t mem, phys_t end, int type) { - phys_t init_mem, init_end, init_size; + phys_t size; + int i; + + size = end - mem; + if (!size) + return; + + /* Make sure it is in the boot_mem_map */ + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (mem >= boot_mem_map.map[i].addr && + mem < (boot_mem_map.map[i].addr + + boot_mem_map.map[i].size)) + return; + } + add_memory_region(mem, size, type); +} +static void __init arch_mem_init(char **cmdline_p) +{ extern void plat_mem_setup(void); /* call board setup routine */ plat_mem_setup(); - init_mem = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT; - init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT; - init_size = init_end - init_mem; - if (init_size) { - /* Make sure it is in the boot_mem_map */ - int i, found; - found = 0; - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (init_mem >= boot_mem_map.map[i].addr && - init_mem < (boot_mem_map.map[i].addr + - boot_mem_map.map[i].size)) { - found = 1; - break; - } - } - if (!found) - add_memory_region(init_mem, init_size, - BOOT_MEM_INIT_RAM); - } + /* + * Make sure all kernel memory is in the maps. The "UP" and + * "DOWN" are opposite for initdata since if it crosses over + * into another memory section you don't want that to be + * freed when the initdata is freed. + */ + arch_mem_addpart(PFN_DOWN(__pa_symbol(&_text)) << PAGE_SHIFT, + PFN_UP(__pa_symbol(&_edata)) << PAGE_SHIFT, + BOOT_MEM_RAM); + arch_mem_addpart(PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT, + PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT, + BOOT_MEM_INIT_RAM); pr_info("Determined physical RAM map:\n"); print_memory_map(); -- 1.7.4.1 From kumba@gentoo.org Sun Feb 10 04:54:49 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Feb 2013 15:23:35 +0100 (CET) Received: from qmta09.westchester.pa.mail.comcast.net ([76.96.62.96]:60189 "EHLO qmta09.westchester.pa.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816607Ab3BJDytx6MYe (ORCPT ); Sun, 10 Feb 2013 04:54:49 +0100 Received: from omta20.westchester.pa.mail.comcast.net ([76.96.62.71]) by qmta09.westchester.pa.mail.comcast.net with comcast id yTgb1k0031YDfWL59TujZv; Sun, 10 Feb 2013 03:54:43 +0000 Received: from [192.168.1.13] ([69.251.154.25]) by omta20.westchester.pa.mail.comcast.net with comcast id yTuh1k00F0Z8pnp3gTuigU; Sun, 10 Feb 2013 03:54:42 +0000 Message-ID: <51171A08.20302@gentoo.org> Date: Sat, 09 Feb 2013 22:54:48 -0500 From: Joshua Kinard User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: prom start References: <20130206160508.GR2118@belle.intranet.vanheusden.com> In-Reply-To: <20130206160508.GR2118@belle.intranet.vanheusden.com> X-Enigmail-Version: 1.5 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="----enig2PGLTWBNJCWMINDHNICSC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=comcast.net; s=q20121106; t=1360468483; bh=mwMbqKzT8reVObD521VYpEapjt4P6oXsuuKLVsTyiTs=; h=Received:Received:Message-ID:Date:From:MIME-Version:To:Subject: Content-Type; b=A6Pnef17wXtTz0SdqtHPNOKbeJBDoA680cghQQi3DSeCkLKYN+d8idZkzydIvGNku Yc5gYzGboMTwHLqk944x7AmKZjOWaBYYbcXXuT3wcHOguJH+zmyMxmcT8HffI47oIR Y0uNH6Yl70I3au+aU2+4QFfTqOdaxIAATTpoE0hzooP4AvUlu+5L0WJOu4uf+zO/G+ It+dAaKIfI63w3yEodpOPL2OXk0WmUdJ+Mjrcav6zGQ6wwRW/GiTGZ3PGkXslUJjz+ rL6HdD9xD/uRHYdK4MluGs/JoXCLd0lAszsOgb6/26Ylt/HMMyTUYg0F5vyGvBr/+y 8hjokYCS5fXOQ== X-archive-position: 35739 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3074 Lines: 94 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) ------enig2PGLTWBNJCWMINDHNICSC Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On 02/06/2013 11:05 AM, folkert wrote: > Hi, >=20 > Is this mailing list also meant for generic mips questions? (if not: an= y > suggestions for one that is?) >=20 > If so: I'mm experimenting a bit with mips, specifically on SGI hardware= > (Indigo). Now it seems all mips systems have the prom at 0xbfc00000. Bu= t > how does it start? The first 0x3c0 bytes seem to be nonsense. Somewhere= > on the web I found that 0xbfc00884 is the starting point but after > single stepping 5 instructions, the program counter jumps to 0x00000000= > so I don't think that's the right one either. Also, reading the first 4= > bytes from bfc00000 and using that as a pointer seems to be invalid too= : > 0bf000f0. > Anyone with insights regarding the booting of the prom on sgi systems? >=20 >=20 > Regards, >=20 > Folkert van Heusden The first Indigo? IP12? Or the Indigo2 series (IP22, IP26, or IP28)? ARCS (the SGI prom) is a bit of black magic and voodoo. It also terrifie= s the priests of Ancient Mu. You might want to hunt down copies of the PROM images for other SGI syste= ms, such as IP22, IP32 (O2), IP30 (Octane) (the latter two are on certain IRI= X media) and analyze those in a disassembler and see if you can discern something from there. You might also try gxemul and see if it can boot one of those proms (it's= a machine emulator like Qemu, but has some code tailored to SGI hardware in= it). Might give you some additional insight. Would be curious about your results if you can learn anything else from i= t via your own work. --=20 Joshua Kinard Gentoo/MIPS kumba@gentoo.org 4096R/D25D95E3 2011-03-28 "The past tempts us, the present confuses us, the future frightens us. A= nd our lives slip away, moment by moment, lost in that vast, terrible in-bet= ween." --Emperor Turhan, Centauri Republic ------enig2PGLTWBNJCWMINDHNICSC Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (MingW32) iQIcBAEBAgAGBQJRFxoPAAoJENsjoH7SXZXj6F8P/3DUdC+viQBkxZ0hR7Eoq269 g1WMRyRRsCVLbFSBThAiMoEPcFuZFdgn8KZMEgvMaCiUOCiMPCnSQL5MU7j4ffea 1eOyswMXjhsNXMq+WCOgQjrj/B0rT/a8qFNwSBbSUGY2I/a7Cmqpp3p8HnmIoIMa qdE3bbopb/Q0bTQ/DGQitqy8NiGIthbEu24af+wwOuu8DVhaoSlhSTAnljYJ3BgO /u4cgMmI060IjVg9CCzw4u68USBy68E7N3RO1eeoJuyxyBN11y4US4g8fxXHWDUb drHOGsfVR2bx26WMt4nlO2VHHbAX7pU46weR6bubet2Oal252o7pe5KzH/DrU94z Clqhs/A3/XgAq+8Vhbx2ab+Jv103MKeY2dgXpyfstg6fLpKdT/CUKWuPpRLOD9y+ hiKj89/Q7pkF2EETlJYpWM0TEtqI8USi4SMR6rgfmhQSDEEN199iHdPNoDIpTiG7 LA2py3YOHU3g2JmCIroelWZua1nL+Mw6QDHrFrlAsCebje5cdvEe8EAcyJOG2QOP yGTeuZSy2Eo/khSelYvgxDfUoyyun6m07OoOqpOLorDzbdO4A02YKg45WsDHC/wp 3H3iD4FfvxgAn9RjXxHBpRE4k6h0CTRjpZdmm12RSAKWYR2DNLOftq5TgI2ytTC3 k915PNZwKb0qgDmps7hB =q0OC -----END PGP SIGNATURE----- ------enig2PGLTWBNJCWMINDHNICSC-- From svetoslav@neykov.name Wed Feb 13 22:40:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Feb 2013 22:40:46 +0100 (CET) Received: from mail-ea0-f180.google.com ([209.85.215.180]:51464 "EHLO mail-ea0-f180.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827617Ab3BMVkpZapIu (ORCPT ); Wed, 13 Feb 2013 22:40:45 +0100 Received: by mail-ea0-f180.google.com with SMTP id c1so611536eaa.39 for ; Wed, 13 Feb 2013 13:40:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=NsdTmCFeDY2OsKfm1Ucnm3sB7JC/BeEi7XRPr3uNUK8=; b=nrJik+uni5sj38e7yjIjUil0WCPejGPl1+z5vXZPEBcVNACyUe/ORMPSNUKxclYZ8p fI/ew4p+sVKKylFr/mOOKqMF7+YAQwSU6DIhYvLDxo+5hMKyvYhOJhXKhBoIBGDt5A0V 5Q89LCyV9f+kSv9Dc0/J2LeW9U0+ad9lrmIn13QpAizGUS4qBsRoFv60SZmdqEVA383p Sb3/71+rNteJgCMZPVBedkCsIg8III/CQXlL7ylRj2Ok1j9Raz/gUkUtuSfPrQ9l2xr/ Y8e6sE05fVB5wSaSg0CA3kb941FZcZY6med0+kKI/Z+x2aM1PLJCMoyduEjQfUstzLyy NDdA== X-Received: by 10.14.182.71 with SMTP id n47mr8752774eem.11.1360791639635; Wed, 13 Feb 2013 13:40:39 -0800 (PST) Received: from localhost.localdomain ([77.70.100.51]) by mx.google.com with ESMTPS id r4sm30921681eeo.12.2013.02.13.13.40.37 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Feb 2013 13:40:38 -0800 (PST) From: Svetoslav Neykov To: Ralf Baechle , Alexander Shishkin , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: [PATCH 0/5] Chipidea driver support for the AR933x platform Date: Wed, 13 Feb 2013 23:38:53 +0200 Message-Id: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQlGbbaQ4KBAtr0UG70sqsVkbeNcXhNl/Gfo65R/VUp6+HyU5gxuU+O1Vn6EwBfWpoTE/rs0 X-archive-position: 35740 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: svetoslav@neykov.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1189 Lines: 26 Add support for the usb controller in AR933x platform. The processor is big-endian so all multi-byte values of the usb descriptors must be converted explicitly. Another difference is that the controller supports both host and device modes but not OTG. The patches are tested on WR703n router running OpenWRT trunk. Svetoslav Neykov (5): usb: chipidea: big-endian support usb: chipidea: flags to force usb mode (host/device) usb: chipidea: Don't access OTG related registers usb: chipidea: AR933x platform support for the chipidea driver usb: chipidea: Fix incorrect check of function return value arch/mips/ath79/dev-usb.c | 19 ++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 + drivers/usb/chipidea/Makefile | 1 + drivers/usb/chipidea/ci13xxx_ar933x.c | 73 +++++++++++++++++++++ drivers/usb/chipidea/core.c | 26 ++++++-- drivers/usb/chipidea/udc.c | 83 ++++++++++++++---------- include/linux/usb/chipidea.h | 2 + 7 files changed, 164 insertions(+), 43 deletions(-) create mode 100644 drivers/usb/chipidea/ci13xxx_ar933x.c -- 1.7.9.5 From svetoslav@neykov.name Wed Feb 13 22:41:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Feb 2013 22:41:12 +0100 (CET) Received: from mail-ee0-f44.google.com ([74.125.83.44]:59469 "EHLO mail-ee0-f44.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827627Ab3BMVlFS3I3Z (ORCPT ); Wed, 13 Feb 2013 22:41:05 +0100 Received: by mail-ee0-f44.google.com with SMTP id l10so953999eei.31 for ; Wed, 13 Feb 2013 13:41:00 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=JGf43I2JYRg975wQDaa2KePFFzAFZ74m/bpqIgCsU98=; b=NfwVTpNye9HggMTsnLL0tv6ndXKjomZOuInOwmN77A5TdfI+rdol3iDbkUrm1OTjc0 bKnU+QumKaZhLUxjj1Iz2viCNJsOrzoXcQA9R2GgBXbueGaqdrLJnqaMctww6YBwf6LD ef9hAND8J6RLW8pr17pRB1k7NuyG+8/UTA5A50TgYdy/8j+WNPVxaNB8gDUpWNlXtkty TEt6VdkAD9Bl0DXG1J7ICFy2Vsz1ni96O+luAJPP1SsNXezRJEkY6u5oXu9EY6q25mJD JMHn+cIXF4yHtOtBL0pegB1DZ19hi2WWt9Ec3V300/B1lHwkLIYWui3tZl0J7MlCVP2Y EAIg== X-Received: by 10.14.207.200 with SMTP id n48mr8988091eeo.4.1360791659465; Wed, 13 Feb 2013 13:40:59 -0800 (PST) Received: from localhost.localdomain ([77.70.100.51]) by mx.google.com with ESMTPS id r4sm30921681eeo.12.2013.02.13.13.40.57 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Feb 2013 13:40:58 -0800 (PST) From: Svetoslav Neykov To: Ralf Baechle , Alexander Shishkin , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: [PATCH 1/5] usb: chipidea: big-endian support Date: Wed, 13 Feb 2013 23:38:54 +0200 Message-Id: <1360791538-6332-2-git-send-email-svetoslav@neykov.name> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> X-Gm-Message-State: ALoCoQnxGNWYwx+6Mp2mcp9v50Olt9nxxeQ4witOmBAnso0NTeSITsBiubPEwuQb/YeI0psiGDQg X-archive-position: 35741 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: svetoslav@neykov.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6641 Lines: 167 Convert between big-endian and little-endian format when accessing the usb controller structures which are little-endian by specification. Fix cases where the little-endian memory layout is taken for granted. The patch doesn't have any effect on the already supported little-endian architectures. Signed-off-by: Svetoslav Neykov --- drivers/usb/chipidea/core.c | 2 +- drivers/usb/chipidea/udc.c | 59 +++++++++++++++++++++++-------------------- 2 files changed, 32 insertions(+), 29 deletions(-) diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index aebf695..3cefb4c 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -181,7 +181,7 @@ static int hw_device_init(struct ci13xxx *ci, void __iomem *base) ci->hw_bank.cap = ci->hw_bank.abs; ci->hw_bank.cap += ci->platdata->capoffset; - ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap); + ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xFF); hw_alloc_regmap(ci, false); reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index 2f45bba..78ac5e5 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -432,10 +432,10 @@ static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq) return -ENOMEM; memset(mReq->zptr, 0, sizeof(*mReq->zptr)); - mReq->zptr->next = TD_TERMINATE; - mReq->zptr->token = TD_STATUS_ACTIVE; + mReq->zptr->next = cpu_to_le32(TD_TERMINATE); + mReq->zptr->token = cpu_to_le32(TD_STATUS_ACTIVE); if (!mReq->req.no_interrupt) - mReq->zptr->token |= TD_IOC; + mReq->zptr->token |= cpu_to_le32(TD_IOC); } ret = usb_gadget_map_request(&ci->gadget, &mReq->req, mEp->dir); if (ret) @@ -446,32 +446,35 @@ static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq) * TODO - handle requests which spawns into several TDs */ memset(mReq->ptr, 0, sizeof(*mReq->ptr)); - mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES); - mReq->ptr->token &= TD_TOTAL_BYTES; - mReq->ptr->token |= TD_STATUS_ACTIVE; + mReq->ptr->token = cpu_to_le32(length << ffs_nr(TD_TOTAL_BYTES)); + mReq->ptr->token &= cpu_to_le32(TD_TOTAL_BYTES); + mReq->ptr->token |= cpu_to_le32(TD_STATUS_ACTIVE); if (mReq->zptr) { - mReq->ptr->next = mReq->zdma; + mReq->ptr->next = cpu_to_le32(mReq->zdma); } else { - mReq->ptr->next = TD_TERMINATE; + mReq->ptr->next = cpu_to_le32(TD_TERMINATE); if (!mReq->req.no_interrupt) - mReq->ptr->token |= TD_IOC; + mReq->ptr->token |= cpu_to_le32(TD_IOC); + } + mReq->ptr->page[0] = cpu_to_le32(mReq->req.dma); + for (i = 1; i < 5; i++) { + u32 page = mReq->req.dma + i * CI13XXX_PAGE_SIZE; + page &= ~TD_RESERVED_MASK; + mReq->ptr->page[i] = cpu_to_le32(page); } - mReq->ptr->page[0] = mReq->req.dma; - for (i = 1; i < 5; i++) - mReq->ptr->page[i] = - (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK; if (!list_empty(&mEp->qh.queue)) { struct ci13xxx_req *mReqPrev; int n = hw_ep_bit(mEp->num, mEp->dir); int tmp_stat; + u32 next = mReq->dma & TD_ADDR_MASK; mReqPrev = list_entry(mEp->qh.queue.prev, struct ci13xxx_req, queue); if (mReqPrev->zptr) - mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK; + mReqPrev->zptr->next = cpu_to_le32(next); else - mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK; + mReqPrev->ptr->next = cpu_to_le32(next); wmb(); if (hw_read(ci, OP_ENDPTPRIME, BIT(n))) goto done; @@ -485,9 +488,9 @@ static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq) } /* QH configuration */ - mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */ - mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */ - mEp->qh.ptr->cap |= QH_ZLT; + mEp->qh.ptr->td.next = cpu_to_le32(mReq->dma); /* TERMINATE = 0 */ + mEp->qh.ptr->td.token &= cpu_to_le32(~TD_STATUS); /* clear status */ + mEp->qh.ptr->cap |= cpu_to_le32(QH_ZLT); wmb(); /* synchronize before ep prime */ @@ -509,11 +512,11 @@ static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq) if (mReq->req.status != -EALREADY) return -EINVAL; - if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0) + if ((cpu_to_le32(TD_STATUS_ACTIVE) & mReq->ptr->token) != 0) return -EBUSY; if (mReq->zptr) { - if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0) + if ((cpu_to_le32(TD_STATUS_ACTIVE) & mReq->zptr->token) != 0) return -EBUSY; dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma); mReq->zptr = NULL; @@ -523,7 +526,7 @@ static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq) usb_gadget_unmap_request(&mEp->ci->gadget, &mReq->req, mEp->dir); - mReq->req.status = mReq->ptr->token & TD_STATUS; + mReq->req.status = le32_to_cpu(mReq->ptr->token) & TD_STATUS; if ((TD_STATUS_HALTED & mReq->req.status) != 0) mReq->req.status = -1; else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0) @@ -531,7 +534,7 @@ static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq) else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0) mReq->req.status = -1; - mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES; + mReq->req.actual = le32_to_cpu(mReq->ptr->token) & TD_TOTAL_BYTES; mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES); mReq->req.actual = mReq->req.length - mReq->req.actual; mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual; @@ -801,7 +804,7 @@ __acquires(mEp->lock) if (retval < 0) break; list_del_init(&mReq->queue); - dbg_done(_usb_addr(mEp), mReq->ptr->token, retval); + dbg_done(_usb_addr(mEp), le32_to_cpu(mReq->ptr->token), retval); if (mReq->req.complete != NULL) { spin_unlock(mEp->lock); if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) && @@ -1045,15 +1048,15 @@ static int ep_enable(struct usb_ep *ep, mEp->qh.ptr->cap = 0; if (mEp->type == USB_ENDPOINT_XFER_CONTROL) - mEp->qh.ptr->cap |= QH_IOS; + mEp->qh.ptr->cap |= cpu_to_le32(QH_IOS); else if (mEp->type == USB_ENDPOINT_XFER_ISOC) - mEp->qh.ptr->cap &= ~QH_MULT; + mEp->qh.ptr->cap &= cpu_to_le32(~QH_MULT); else - mEp->qh.ptr->cap &= ~QH_ZLT; + mEp->qh.ptr->cap &= cpu_to_le32(~QH_ZLT); mEp->qh.ptr->cap |= - (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT; - mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */ + cpu_to_le32((mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT); + mEp->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */ /* * Enable endpoints in the HW other than ep0 as ep0 -- 1.7.9.5 From svetoslav@neykov.name Wed Feb 13 22:41:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Feb 2013 22:41:36 +0100 (CET) Received: from mail-ea0-f170.google.com ([209.85.215.170]:47207 "EHLO mail-ea0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827628Ab3BMVlfJOohr (ORCPT ); Wed, 13 Feb 2013 22:41:35 +0100 Received: by mail-ea0-f170.google.com with SMTP id a11so644292eaa.15 for ; Wed, 13 Feb 2013 13:41:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=Pknm0aZkCVZhEqJsUMCwq6O5DE+Xz6wQPjN+mPAvKd0=; b=ih1bMroGldHWt3s7Cu35/wZJvq1pcvXHAMGlWuJZoFL4KYisiW0BE2jcapVqV/yoV7 wZ4j/qGrEGYw/HbSksF3dDCeJDMBb+GN+olZRFOf9EQWPs4A5BG22pZvcI7uuUF0u4aN cvtCrPJ6xlzcGqqLHkbTWUJofkBMz8A6vC4mM3Y5nTb1PKjF010Vhc8nh3ymIODHteEB 2ye+waYLRGIECBcYvAWZReiDwXSZzF+JrnCx/vbhquqjcDanOGpBh25/OtIKJ7OW4Vz2 C8GwCHv8Tu1/RM90krw/Ff4PNonyGJyUhW2caLh3ToPUm5iOmWc1PjkeXLfzmev1Uzhx AogA== X-Received: by 10.14.207.200 with SMTP id n48mr8993630eeo.4.1360791689503; Wed, 13 Feb 2013 13:41:29 -0800 (PST) Received: from localhost.localdomain ([77.70.100.51]) by mx.google.com with ESMTPS id r4sm30921681eeo.12.2013.02.13.13.41.27 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Feb 2013 13:41:28 -0800 (PST) From: Svetoslav Neykov To: Ralf Baechle , Alexander Shishkin , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: [PATCH 2/5] usb: chipidea: flags to force usb mode (host/device) Date: Wed, 13 Feb 2013 23:38:55 +0200 Message-Id: <1360791538-6332-3-git-send-email-svetoslav@neykov.name> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> X-Gm-Message-State: ALoCoQk/yweb5DjzecT2RKvcApN1ulpOHNEMXvIO3/soDEMGGsgftOX3piwMjE1vrQvYKaiHKurm X-archive-position: 35742 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: svetoslav@neykov.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2772 Lines: 77 The chipidea controller in the AR933x SOC supports both host and device modes but not OTG. Which USB mode is used depends on a pin state (GIPO13) during boot - HIGH for host, LOW for device mode. Currently if both host and device modes are available, the code assumes OTG support. Add flags to allow the platform code for force a specific mode based on the pin state. Signed-off-by: Svetoslav Neykov --- drivers/usb/chipidea/core.c | 22 +++++++++++++++++----- include/linux/usb/chipidea.h | 2 ++ 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 3cefb4c..85c72e5 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -398,6 +398,8 @@ static int ci_hdrc_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; int ret; + bool force_host_mode; + bool force_device_mode; if (!dev->platform_data) { dev_err(dev, "platform data missing\n"); @@ -459,21 +461,31 @@ static int ci_hdrc_probe(struct platform_device *pdev) if (ret) dev_info(dev, "doesn't support gadget\n"); - if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { + force_host_mode = ci->platdata->flags & CI13XXX_FORCE_HOST_MODE; + force_device_mode = ci->platdata->flags & CI13XXX_FORCE_DEVICE_MODE; + if ((!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) || + (force_host_mode && !ci->roles[CI_ROLE_HOST]) || + (force_device_mode && !ci->roles[CI_ROLE_GADGET])) { dev_err(dev, "no supported roles\n"); ret = -ENODEV; goto rm_wq; } - if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { + if (!force_host_mode && !force_device_mode && + ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { ci->is_otg = true; /* ID pin needs 1ms debouce time, we delay 2ms for safe */ mdelay(2); ci->role = ci_otg_role(ci); } else { - ci->role = ci->roles[CI_ROLE_HOST] - ? CI_ROLE_HOST - : CI_ROLE_GADGET; + if (force_host_mode) + ci->role = CI_ROLE_HOST; + else if (force_device_mode) + ci->role = CI_ROLE_GADGET; + else + ci->role = ci->roles[CI_ROLE_HOST] + ? CI_ROLE_HOST + : CI_ROLE_GADGET; } ret = ci_role_start(ci, ci->role); diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index 544825d..e6f44d2 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -19,6 +19,8 @@ struct ci13xxx_platform_data { #define CI13XXX_REQUIRE_TRANSCEIVER BIT(1) #define CI13XXX_PULLUP_ON_VBUS BIT(2) #define CI13XXX_DISABLE_STREAMING BIT(3) +#define CI13XXX_FORCE_HOST_MODE BIT(5) +#define CI13XXX_FORCE_DEVICE_MODE BIT(6) #define CI13XXX_CONTROLLER_RESET_EVENT 0 #define CI13XXX_CONTROLLER_STOPPED_EVENT 1 -- 1.7.9.5 From svetoslav@neykov.name Wed Feb 13 22:41:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Feb 2013 22:41:55 +0100 (CET) Received: from mail-ee0-f42.google.com ([74.125.83.42]:44877 "EHLO mail-ee0-f42.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827630Ab3BMVlk2TfNC (ORCPT ); Wed, 13 Feb 2013 22:41:40 +0100 Received: by mail-ee0-f42.google.com with SMTP id b47so916501eek.29 for ; Wed, 13 Feb 2013 13:41:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=oewUzHaKjVOZA3iVWdw78z1AzhMIuDJ1W7s5lz/FSgE=; b=ldbhLuaiZnPEw9yZ2/ZGWy2NhHDO3QOOcPdXpYfwxCKMVYWXUbnt/7jmYLB+luYiEU XOLHdH9jNOb26Ed4LGbnrBlubptHHUjvQd3822FSDL7GJCCY9UF4MTVgeKCAj1rzuj0E 8i8gGLQ7tW/zUlPrckO715ys/RNYxD44FeRzJHKCL3FEmHkNdjJDA/a45EG2PxTzXUSt g4Txja3Mkno7JcrUWnLd+pGR3Yf5j0eTosNdA0iMlXus+AtPj6gEGUhdqfBrmW88TfLg 1puFpQBsVnH3wg39FugShKipWtpjwRwHaxDsO6fnDDky3h1eweDCcDTOULvxQVnj/ZG8 1V9Q== X-Received: by 10.14.175.129 with SMTP id z1mr9670228eel.7.1360791694970; Wed, 13 Feb 2013 13:41:34 -0800 (PST) Received: from localhost.localdomain ([77.70.100.51]) by mx.google.com with ESMTPS id r4sm30921681eeo.12.2013.02.13.13.41.32 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Feb 2013 13:41:34 -0800 (PST) From: Svetoslav Neykov To: Ralf Baechle , Alexander Shishkin , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: [PATCH 3/5] usb: chipidea: Don't access OTG related registers Date: Wed, 13 Feb 2013 23:38:56 +0200 Message-Id: <1360791538-6332-4-git-send-email-svetoslav@neykov.name> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> X-Gm-Message-State: ALoCoQmTryZrVJcxwX2Wjl6qxRnT1yhwFWVv0odeh3LMaFPDSfdj+C/d6UtXJ/q908XpuA03j4+f X-archive-position: 35743 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: svetoslav@neykov.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2219 Lines: 75 According to the datasheet the chipidea controller in AR933x doesn't expose OTG and TEST registers. If no OTG support is detected don't call functions which access those registers. Signed-off-by: Svetoslav Neykov --- drivers/usb/chipidea/udc.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index 78ac5e5..9fda4d8 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -1395,7 +1395,10 @@ static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active) if (is_active) { pm_runtime_get_sync(&_gadget->dev); hw_device_reset(ci, USBMODE_CM_DC); - hw_enable_vbus_intr(ci); + + if (ci->is_otg) + hw_enable_vbus_intr(ci); + hw_device_state(ci, ci->ep0out->qh.dma); } else { hw_device_state(ci, 0); @@ -1572,7 +1575,8 @@ static int ci13xxx_start(struct usb_gadget *gadget, if (ci->vbus_active) { if (ci->platdata->flags & CI13XXX_REGS_SHARED) { hw_device_reset(ci, USBMODE_CM_DC); - hw_enable_vbus_intr(ci); + if (ci->is_otg) + hw_enable_vbus_intr(ci); } } else { pm_runtime_put_sync(&ci->gadget.dev); @@ -1680,11 +1684,13 @@ static irqreturn_t udc_irq(struct ci13xxx *ci) retval = IRQ_NONE; } - intr = hw_read(ci, OP_OTGSC, ~0); - hw_write(ci, OP_OTGSC, ~0, intr); + if (ci->is_otg) { + intr = hw_read(ci, OP_OTGSC, ~0); + hw_write(ci, OP_OTGSC, ~0, intr); - if (intr & (OTGSC_AVVIE & OTGSC_AVVIS)) - queue_work(ci->wq, &ci->vbus_work); + if (intr & (OTGSC_AVVIE & OTGSC_AVVIS)) + queue_work(ci->wq, &ci->vbus_work); + } spin_unlock(&ci->lock); @@ -1761,7 +1767,8 @@ static int udc_start(struct ci13xxx *ci) retval = hw_device_reset(ci, USBMODE_CM_DC); if (retval) goto put_transceiver; - hw_enable_vbus_intr(ci); + if (ci->is_otg) + hw_enable_vbus_intr(ci); } retval = device_register(&ci->gadget.dev); @@ -1824,7 +1831,8 @@ static void udc_stop(struct ci13xxx *ci) if (ci == NULL) return; - hw_disable_vbus_intr(ci); + if (ci->is_otg) + hw_disable_vbus_intr(ci); cancel_work_sync(&ci->vbus_work); usb_del_gadget_udc(&ci->gadget); -- 1.7.9.5 From svetoslav@neykov.name Wed Feb 13 22:41:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Feb 2013 22:42:15 +0100 (CET) Received: from mail-ee0-f52.google.com ([74.125.83.52]:46135 "EHLO mail-ee0-f52.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827627Ab3BMVluJ5FQ7 (ORCPT ); Wed, 13 Feb 2013 22:41:50 +0100 Received: by mail-ee0-f52.google.com with SMTP id b15so890561eek.25 for ; Wed, 13 Feb 2013 13:41:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=e6ZDUDAfvSj5JIXH4vVLgIqrQ1yO9c9KORTPiVUweSw=; b=o8Sm5tBc/o+z1sOxFzner4aUPE7JV9UEJ9ixGEzrrNNTKi0u0W0W9t7aSsFTCjmNyx B1FFmdWHdoYPSTlE/Zf6YhdUdssiQyfR0plySDgph3Jr7rfcTsmbdtFAZiRE2/vUrE8R 1wJadrfxm2cSBiTCuyvSHN7DXt+vU68APbcxuQC2wcXeNp/yt5091fmQndKc8NGEccqX fFmIk4KTUFx3Urp/QFoABZxLfWiPfZ/iXMInbX3Fp+6mLyI5ABkW/biVBXfDtPxLzLga GgYNY0pHEvd6732TxEFsNld8PlBm9XuYYNaAMoPYL6hXXL9wANqah6tywtOcqIY7JBog P6Sw== X-Received: by 10.14.173.196 with SMTP id v44mr78848493eel.29.1360791704746; Wed, 13 Feb 2013 13:41:44 -0800 (PST) Received: from localhost.localdomain ([77.70.100.51]) by mx.google.com with ESMTPS id r4sm30921681eeo.12.2013.02.13.13.41.42 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Feb 2013 13:41:44 -0800 (PST) From: Svetoslav Neykov To: Ralf Baechle , Alexander Shishkin , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: [PATCH 4/5] usb: chipidea: AR933x platform support for the chipidea driver Date: Wed, 13 Feb 2013 23:38:57 +0200 Message-Id: <1360791538-6332-5-git-send-email-svetoslav@neykov.name> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> X-Gm-Message-State: ALoCoQkIk3TYbLo3RTZYZHWMeIcWjiIEkYV6TDPzzRfUlRea91z+piMadHLQCVhsYR4Ei7U+JCgC X-archive-position: 35744 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: svetoslav@neykov.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5088 Lines: 160 Support host and device usb modes for the chipidea controller in AR933x. The controller doesn't support OTG functionality so the platform code forces one of the modes based on the state of GPIO13 pin at startup. Signed-off-by: Svetoslav Neykov --- arch/mips/ath79/dev-usb.c | 19 ++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 + drivers/usb/chipidea/Makefile | 1 + drivers/usb/chipidea/ci13xxx_ar933x.c | 73 ++++++++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 drivers/usb/chipidea/ci13xxx_ar933x.c diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index bd2bc10..52966b3 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -174,8 +174,27 @@ static void __init ar913x_usb_setup(void) platform_device_register(&ath79_ehci_device); } +static void __init ar933x_usb_setup_ctrl_config(void) +{ + void __iomem *usb_ctrl_base, *usb_config_reg; + u32 usb_config; + + usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE); + usb_config_reg = usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG; + usb_config = __raw_readl(usb_config_reg); + usb_config &= ~AR933X_USB_CONFIG_HOST_ONLY; + __raw_writel(usb_config, usb_config_reg); + iounmap(usb_ctrl_base); +} + static void __init ar933x_usb_setup(void) { + u32 bootstrap; + + bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + if (!(bootstrap & AR933X_BOOTSTRAP_USB_MODE_HOST)) + ar933x_usb_setup_ctrl_config(); + ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE); mdelay(10); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index a5e0f17..13eb2d9 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -297,6 +297,7 @@ #define AR934X_RESET_USB_PHY BIT(4) #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR933X_BOOTSTRAP_USB_MODE_HOST BIT(3) #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) @@ -315,6 +316,8 @@ #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) #define AR934X_BOOTSTRAP_DDR1 BIT(0) +#define AR933X_USB_CONFIG_HOST_ONLY BIT(8) + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile index d92ca32..196b7b4 100644 --- a/drivers/usb/chipidea/Makefile +++ b/drivers/usb/chipidea/Makefile @@ -10,6 +10,7 @@ ci_hdrc-$(CONFIG_USB_CHIPIDEA_DEBUG) += debug.o # Glue/Bridge layers go here obj-$(CONFIG_USB_CHIPIDEA) += ci13xxx_msm.o +obj-$(CONFIG_USB_CHIPIDEA) += ci13xxx_ar933x.o # PCI doesn't provide stubs, need to check ifneq ($(CONFIG_PCI),) diff --git a/drivers/usb/chipidea/ci13xxx_ar933x.c b/drivers/usb/chipidea/ci13xxx_ar933x.c new file mode 100644 index 0000000..046a4b6 --- /dev/null +++ b/drivers/usb/chipidea/ci13xxx_ar933x.c @@ -0,0 +1,73 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ci.h" + +static struct ci13xxx_platform_data ci13xxx_ar933x_platdata = { + .name = "ci13xxx_ar933x", + .flags = 0, + .capoffset = DEF_CAPOFFSET +}; + +static int __devinit ci13xxx_ar933x_probe(struct platform_device *pdev) +{ + u32 bootstrap; + struct platform_device *plat_ci; + + dev_dbg(&pdev->dev, "ci13xxx_ar933x_probe\n"); + + bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + if (bootstrap & AR933X_BOOTSTRAP_USB_MODE_HOST) + ci13xxx_ar933x_platdata.flags = CI13XXX_FORCE_HOST_MODE; + else + ci13xxx_ar933x_platdata.flags = CI13XXX_FORCE_DEVICE_MODE; + + plat_ci = ci13xxx_add_device(&pdev->dev, + pdev->resource, pdev->num_resources, + &ci13xxx_ar933x_platdata); + if (IS_ERR(plat_ci)) { + dev_err(&pdev->dev, "ci13xxx_add_device failed!\n"); + return PTR_ERR(plat_ci); + } + + platform_set_drvdata(pdev, plat_ci); + + pm_runtime_no_callbacks(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + return 0; +} + +static int __devexit ci13xxx_ar933x_remove(struct platform_device *pdev) +{ + struct platform_device *plat_ci = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + ci13xxx_remove_device(plat_ci); + + return 0; +} + +static struct platform_driver ci13xxx_ar933x_driver = { + .probe = ci13xxx_ar933x_probe, + .remove = __devexit_p(ci13xxx_ar933x_remove), + .driver = { .name = "ehci-platform", }, +}; + +module_platform_driver(ci13xxx_ar933x_driver); + +MODULE_ALIAS("platform:ar933x_hsusb"); +MODULE_LICENSE("GPL v2"); -- 1.7.9.5 From svetoslav@neykov.name Wed Feb 13 22:41:54 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Feb 2013 22:42:35 +0100 (CET) Received: from mail-ea0-f174.google.com ([209.85.215.174]:52613 "EHLO mail-ea0-f174.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827634Ab3BMVlylES-H (ORCPT ); Wed, 13 Feb 2013 22:41:54 +0100 Received: by mail-ea0-f174.google.com with SMTP id 1so704186eaa.5 for ; Wed, 13 Feb 2013 13:41:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=I9sm0k6KtQm/xVCR0WJ3PqH9MM0hhMCmIRfdS/BESuA=; b=mM10tgWfEZxaiek2FdfkDfD7y152VQETUa49AKZFJfzfsWk93BP79HJWcNNns6nB3s HhPoVF5HFJeFpuN2z5+5XX0OSg6RaTbR7cjK2EpO9hl9kYuZZI9aVMBdayu8e4G1AUs/ oP9aSfmOUT26BlsT3Vlpf9cvJbfFUQboqff3hPnUqEVvgAl2GTEH0acfF/Wd+N9CZhfH BdE0taJeUjQvicjrUtxur6mAM7+uFzpBdSYfOBo3heyFk8tX3iuqZj0NWYDL7k/3Ht9G md8MYy+LaXx5UxK5bs4nB7xHY0hRL4a5nmAZKTbw8nUnOlzo17JbJNfs/5Ke2X0/Z7DZ Bpwg== X-Received: by 10.14.216.198 with SMTP id g46mr8950871eep.30.1360791709289; Wed, 13 Feb 2013 13:41:49 -0800 (PST) Received: from localhost.localdomain ([77.70.100.51]) by mx.google.com with ESMTPS id r4sm30921681eeo.12.2013.02.13.13.41.47 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Feb 2013 13:41:48 -0800 (PST) From: Svetoslav Neykov To: Ralf Baechle , Alexander Shishkin , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: [PATCH 5/5] usb: chipidea: Fix incorrect check of function return value Date: Wed, 13 Feb 2013 23:38:58 +0200 Message-Id: <1360791538-6332-6-git-send-email-svetoslav@neykov.name> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> X-Gm-Message-State: ALoCoQl2HkEobsfuZ+fwi4bfzzBNKTSJaO/6wdd9FOQ7dFiML5HUmzd+Aq/B/q6mRQOGv3n1ssCS X-archive-position: 35745 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: svetoslav@neykov.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 642 Lines: 23 Use the correct variable to check for the return value of the last function. Signed-off-by: Svetoslav Neykov --- drivers/usb/chipidea/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 85c72e5..8442305 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -413,7 +413,7 @@ static int ci_hdrc_probe(struct platform_device *pdev) } base = devm_request_and_ioremap(dev, res); - if (!res) { + if (!base) { dev_err(dev, "can't request and ioremap resource\n"); return -ENOMEM; } -- 1.7.9.5 From Steven.Hill@imgtec.com Thu Feb 14 06:44:26 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Feb 2013 06:44:28 +0100 (CET) Received: from multi.imgtec.com ([194.200.65.239]:38517 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816409Ab3BNFo05xN2S convert rfc822-to-8bit (ORCPT ); Thu, 14 Feb 2013 06:44:26 +0100 From: Steven Hill To: "linux-mips@linux-mips.org" CC: "ralf@linux-mips.org" , "cernekee@gmail.com" , "kevink@paralogos.com" , "ddaney.cavm@gmail.com" Subject: RE: [PATCH 0/4] Add support for microMIPS instructions Thread-Topic: [PATCH 0/4] Add support for microMIPS instructions Thread-Index: AQHOA/Nyf2y5wT7vJ0yVzexg00UU9Jh45Cqb Date: Thu, 14 Feb 2013 05:42:56 +0000 Message-ID: <0573B2AE5BBFFC408CC8740092293B5ACA59E5@bamail02.ba.imgtec.org> References: <1360104723-29529-1-git-send-email-sjhill@mips.com> In-Reply-To: <1360104723-29529-1-git-send-email-sjhill@mips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.64.117] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01181__2013_02_14_05_44_21 X-archive-position: 35746 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 78 Lines: 5 Hello. Could I please get some feedback on this patchset? Thank you. -Steve From matiasbaruchinsaurralde@gmail.com Thu Feb 14 07:10:36 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Feb 2013 07:10:40 +0100 (CET) Received: from mail-qa0-f47.google.com ([209.85.216.47]:58044 "EHLO mail-qa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816409Ab3BNGKgJ0O57 (ORCPT ); Thu, 14 Feb 2013 07:10:36 +0100 Received: by mail-qa0-f47.google.com with SMTP id j8so2478942qah.20 for ; Wed, 13 Feb 2013 22:10:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:in-reply-to:references:date:message-id :subject:from:to:content-type; bh=VX4gbsMzQIyIEF0KbJtEq1vZqQpyOKa0DOMCeSYv3o8=; b=wd3VW5H+ilqqyr9Lm4xITFrKctSBUsCC6PEJwmsYEk3ZsJ+JtVYNEgo7ctTvbf4wOo Xq8aY6yGsPQwpMf1PYLlLkdnP9jO21Lx4T3lE/mPC4ZIWmrh53NIAB6e2sGlYr2wyz92 Gg8FiwNhuvLJ/MRDZ+B1z4l2JXdCDIWjDDwXP1waGg6lWQYuM1lu0YrDs0SaPD4kjOOz NyonWJVJAeg0DRpvA5JmdukfWn/Zup91mJL3Lr7Z2qAAlVQVorb5z4LoWg9SH6qkodqM W7IIRh0GAxCubm1U+AbQ04kjd+BLAhVf2CdUOLq8dkuUABRtPG5fng8i9GCJKLoBan+y g/UQ== MIME-Version: 1.0 X-Received: by 10.229.176.99 with SMTP id bd35mr2291092qcb.115.1360822230175; Wed, 13 Feb 2013 22:10:30 -0800 (PST) Received: by 10.49.108.104 with HTTP; Wed, 13 Feb 2013 22:10:29 -0800 (PST) In-Reply-To: References: Date: Thu, 14 Feb 2013 03:10:29 -0300 Message-ID: Subject: ALI From: =?ISO-8859-1?B?TWF07WFz?= To: Linux-MIPS , mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35747 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matiasbaruchinsaurralde@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 87 Lines: 4 Hello, have you got any experience with ALi M3329*? Just got a board with it. Thanks! From mgr@pengutronix.de Thu Feb 14 10:01:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Feb 2013 10:01:57 +0100 (CET) Received: from metis.ext.pengutronix.de ([92.198.50.35]:37285 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823082Ab3BNJBzw5ix- (ORCPT ); Thu, 14 Feb 2013 10:01:55 +0100 Received: from ptx.hi.pengutronix.de ([2001:6f8:1178:2:5054:ff:fec0:8e10] ident=Debian-exim) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1U5uhF-0007Xg-Nf; Thu, 14 Feb 2013 10:01:37 +0100 Received: from mgr by ptx.hi.pengutronix.de with local (Exim 4.72) (envelope-from ) id 1U5uhC-0005wQ-9x; Thu, 14 Feb 2013 10:01:34 +0100 Date: Thu, 14 Feb 2013 10:01:34 +0100 From: Michael Grzeschik To: Svetoslav Neykov Cc: Ralf Baechle , Alexander Shishkin , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" , linux-mips@linux-mips.org, linux-usb@vger.kernel.org Subject: Re: [PATCH 2/5] usb: chipidea: flags to force usb mode (host/device) Message-ID: <20130214090134.GI21362@pengutronix.de> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <1360791538-6332-3-git-send-email-svetoslav@neykov.name> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1360791538-6332-3-git-send-email-svetoslav@neykov.name> X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-IRC: #ptxdist @freenode X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-Uptime: 09:53:06 up 166 days, 17:27, 12 users, load average: 0.09, 0.09, 0.09 User-Agent: Mutt/1.5.20 (2009-06-14) X-SA-Exim-Connect-IP: 2001:6f8:1178:2:5054:ff:fec0:8e10 X-SA-Exim-Mail-From: mgr@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-mips@linux-mips.org X-archive-position: 35748 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mgr@pengutronix.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3402 Lines: 90 Hi Svetoslav, On Wed, Feb 13, 2013 at 11:38:55PM +0200, Svetoslav Neykov wrote: > The chipidea controller in the AR933x SOC supports both host and device modes but not OTG. > Which USB mode is used depends on a pin state (GIPO13) during boot - HIGH for host, LOW for device mode. > Currently if both host and device modes are available, the code assumes OTG support. Add flags to allow > the platform code for force a specific mode based on the pin state. > > Signed-off-by: Svetoslav Neykov > --- > drivers/usb/chipidea/core.c | 22 +++++++++++++++++----- > include/linux/usb/chipidea.h | 2 ++ > 2 files changed, 19 insertions(+), 5 deletions(-) > > diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c > index 3cefb4c..85c72e5 100644 > --- a/drivers/usb/chipidea/core.c > +++ b/drivers/usb/chipidea/core.c > @@ -398,6 +398,8 @@ static int ci_hdrc_probe(struct platform_device *pdev) > struct resource *res; > void __iomem *base; > int ret; > + bool force_host_mode; > + bool force_device_mode; > > if (!dev->platform_data) { > dev_err(dev, "platform data missing\n"); > @@ -459,21 +461,31 @@ static int ci_hdrc_probe(struct platform_device *pdev) > if (ret) > dev_info(dev, "doesn't support gadget\n"); > > - if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { > + force_host_mode = ci->platdata->flags & CI13XXX_FORCE_HOST_MODE; > + force_device_mode = ci->platdata->flags & CI13XXX_FORCE_DEVICE_MODE; > + if ((!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) || > + (force_host_mode && !ci->roles[CI_ROLE_HOST]) || > + (force_device_mode && !ci->roles[CI_ROLE_GADGET])) { > dev_err(dev, "no supported roles\n"); > ret = -ENODEV; > goto rm_wq; > } > > - if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { > + if (!force_host_mode && !force_device_mode && > + ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { > ci->is_otg = true; > /* ID pin needs 1ms debouce time, we delay 2ms for safe */ > mdelay(2); > ci->role = ci_otg_role(ci); > } else { > - ci->role = ci->roles[CI_ROLE_HOST] > - ? CI_ROLE_HOST > - : CI_ROLE_GADGET; > + if (force_host_mode) > + ci->role = CI_ROLE_HOST; > + else if (force_device_mode) > + ci->role = CI_ROLE_GADGET; > + else > + ci->role = ci->roles[CI_ROLE_HOST] > + ? CI_ROLE_HOST > + : CI_ROLE_GADGET; > } > > ret = ci_role_start(ci, ci->role); > diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h > index 544825d..e6f44d2 100644 > --- a/include/linux/usb/chipidea.h > +++ b/include/linux/usb/chipidea.h > @@ -19,6 +19,8 @@ struct ci13xxx_platform_data { > #define CI13XXX_REQUIRE_TRANSCEIVER BIT(1) > #define CI13XXX_PULLUP_ON_VBUS BIT(2) > #define CI13XXX_DISABLE_STREAMING BIT(3) > +#define CI13XXX_FORCE_HOST_MODE BIT(5) > +#define CI13XXX_FORCE_DEVICE_MODE BIT(6) > > #define CI13XXX_CONTROLLER_RESET_EVENT 0 > #define CI13XXX_CONTROLLER_STOPPED_EVENT 1 We already discuss such functionality: https://patchwork-mail1.kernel.org/patch/2092051/ Regards, Michael -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | From alexander.shishkin@linux.intel.com Thu Feb 14 12:07:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Feb 2013 12:07:14 +0100 (CET) Received: from mga14.intel.com ([143.182.124.37]:62945 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823072Ab3BNLHLPTpip (ORCPT ); Thu, 14 Feb 2013 12:07:11 +0100 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 14 Feb 2013 03:07:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,664,1355126400"; d="scan'208";a="256891527" Received: from um.fi.intel.com (HELO localhost) ([10.237.72.164]) by azsmga001.ch.intel.com with ESMTP; 14 Feb 2013 03:06:59 -0800 From: Alexander Shishkin To: Svetoslav Neykov , Ralf Baechle , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: Re: [PATCH 5/5] usb: chipidea: Fix incorrect check of function return value In-Reply-To: <1360791538-6332-6-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <1360791538-6332-6-git-send-email-svetoslav@neykov.name> User-Agent: Notmuch/0.12+187~ga2502b0 (http://notmuchmail.org) Emacs/23.4.1 (x86_64-pc-linux-gnu) Date: Thu, 14 Feb 2013 13:08:36 +0200 Message-ID: <87a9r7b1aj.fsf@ashishki-desk.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-archive-position: 35749 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexander.shishkin@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 200 Lines: 9 Svetoslav Neykov writes: > Use the correct variable to check for the return value of the last function. This one is fixed already by Julia Lawall: 5c6e9bf0 Regards, -- Alex From alexander.shishkin@linux.intel.com Thu Feb 14 12:21:54 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Feb 2013 12:22:10 +0100 (CET) Received: from mga02.intel.com ([134.134.136.20]:20704 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823072Ab3BNLVyKZtOh (ORCPT ); Thu, 14 Feb 2013 12:21:54 +0100 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 14 Feb 2013 03:21:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,664,1355126400"; d="scan'208";a="285674811" Received: from um.fi.intel.com (HELO localhost) ([10.237.72.164]) by orsmga002.jf.intel.com with ESMTP; 14 Feb 2013 03:21:42 -0800 From: Alexander Shishkin To: Svetoslav Neykov , Ralf Baechle , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: Re: [PATCH 4/5] usb: chipidea: AR933x platform support for the chipidea driver In-Reply-To: <1360791538-6332-5-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <1360791538-6332-5-git-send-email-svetoslav@neykov.name> User-Agent: Notmuch/0.12+187~ga2502b0 (http://notmuchmail.org) Emacs/23.4.1 (x86_64-pc-linux-gnu) Date: Thu, 14 Feb 2013 13:23:19 +0200 Message-ID: <877gmbb0m0.fsf@ashishki-desk.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-archive-position: 35750 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexander.shishkin@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 4333 Lines: 124 Svetoslav Neykov writes: > Support host and device usb modes for the chipidea controller in AR933x. > The controller doesn't support OTG functionality so the platform code > forces one of the modes based on the state of GPIO13 pin at startup. Some comments below. > > Signed-off-by: Svetoslav Neykov > --- > arch/mips/ath79/dev-usb.c | 19 ++++++ > arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 + > drivers/usb/chipidea/Makefile | 1 + > drivers/usb/chipidea/ci13xxx_ar933x.c | 73 ++++++++++++++++++++++++ > 4 files changed, 96 insertions(+) > create mode 100644 drivers/usb/chipidea/ci13xxx_ar933x.c > > diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c > index bd2bc10..52966b3 100644 > --- a/arch/mips/ath79/dev-usb.c > +++ b/arch/mips/ath79/dev-usb.c > @@ -174,8 +174,27 @@ static void __init ar913x_usb_setup(void) > platform_device_register(&ath79_ehci_device); > } > > +static void __init ar933x_usb_setup_ctrl_config(void) > +{ > + void __iomem *usb_ctrl_base, *usb_config_reg; > + u32 usb_config; > + > + usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE); > + usb_config_reg = usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG; > + usb_config = __raw_readl(usb_config_reg); > + usb_config &= ~AR933X_USB_CONFIG_HOST_ONLY; > + __raw_writel(usb_config, usb_config_reg); > + iounmap(usb_ctrl_base); > +} > + > static void __init ar933x_usb_setup(void) > { > + u32 bootstrap; > + > + bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); > + if (!(bootstrap & AR933X_BOOTSTRAP_USB_MODE_HOST)) > + ar933x_usb_setup_ctrl_config(); > + > ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE); > mdelay(10); > > diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h > index a5e0f17..13eb2d9 100644 > --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h > +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h > @@ -297,6 +297,7 @@ > #define AR934X_RESET_USB_PHY BIT(4) > #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) > > +#define AR933X_BOOTSTRAP_USB_MODE_HOST BIT(3) > #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) > > #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) > @@ -315,6 +316,8 @@ > #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) > #define AR934X_BOOTSTRAP_DDR1 BIT(0) > > +#define AR933X_USB_CONFIG_HOST_ONLY BIT(8) > + > #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) > #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) > #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) > diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile > index d92ca32..196b7b4 100644 > --- a/drivers/usb/chipidea/Makefile > +++ b/drivers/usb/chipidea/Makefile > @@ -10,6 +10,7 @@ ci_hdrc-$(CONFIG_USB_CHIPIDEA_DEBUG) += debug.o > # Glue/Bridge layers go here > > obj-$(CONFIG_USB_CHIPIDEA) += ci13xxx_msm.o > +obj-$(CONFIG_USB_CHIPIDEA) += ci13xxx_ar933x.o The problem is that this will only compile for mips target, so you should probably change the Makefile to only compile it for mips. > > # PCI doesn't provide stubs, need to check > ifneq ($(CONFIG_PCI),) > diff --git a/drivers/usb/chipidea/ci13xxx_ar933x.c b/drivers/usb/chipidea/ci13xxx_ar933x.c > new file mode 100644 > index 0000000..046a4b6 > --- /dev/null > +++ b/drivers/usb/chipidea/ci13xxx_ar933x.c > @@ -0,0 +1,73 @@ > +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "ci.h" > + > +static struct ci13xxx_platform_data ci13xxx_ar933x_platdata = { > + .name = "ci13xxx_ar933x", > + .flags = 0, > + .capoffset = DEF_CAPOFFSET > +}; > + > +static int __devinit ci13xxx_ar933x_probe(struct platform_device *pdev) __devinit/__devexit/__devexit_p() are gone from the kernel. Regards, -- Alex From alexander.shishkin@linux.intel.com Thu Feb 14 12:44:00 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Feb 2013 12:44:01 +0100 (CET) Received: from mga03.intel.com ([143.182.124.21]:35174 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823126Ab3BNLoAToZdr (ORCPT ); Thu, 14 Feb 2013 12:44:00 +0100 Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga101.ch.intel.com with ESMTP; 14 Feb 2013 03:43:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,665,1355126400"; d="scan'208";a="202309498" Received: from um.fi.intel.com (HELO localhost) ([10.237.72.164]) by AZSMGA002.ch.intel.com with ESMTP; 14 Feb 2013 03:43:49 -0800 From: Alexander Shishkin To: Svetoslav Neykov , Ralf Baechle , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: Re: [PATCH 3/5] usb: chipidea: Don't access OTG related registers In-Reply-To: <1360791538-6332-4-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <1360791538-6332-4-git-send-email-svetoslav@neykov.name> User-Agent: Notmuch/0.12+187~ga2502b0 (http://notmuchmail.org) Emacs/23.4.1 (x86_64-pc-linux-gnu) Date: Thu, 14 Feb 2013 13:45:26 +0200 Message-ID: <874nhfazl5.fsf@ashishki-desk.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-archive-position: 35751 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexander.shishkin@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1035 Lines: 29 Svetoslav Neykov writes: > According to the datasheet the chipidea controller in AR933x doesn't expose OTG and TEST registers. > If no OTG support is detected don't call functions which access those registers. > > Signed-off-by: Svetoslav Neykov > --- > drivers/usb/chipidea/udc.c | 24 ++++++++++++++++-------- > 1 file changed, 16 insertions(+), 8 deletions(-) > > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c > index 78ac5e5..9fda4d8 100644 > --- a/drivers/usb/chipidea/udc.c > +++ b/drivers/usb/chipidea/udc.c > @@ -1395,7 +1395,10 @@ static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active) > if (is_active) { > pm_runtime_get_sync(&_gadget->dev); > hw_device_reset(ci, USBMODE_CM_DC); > - hw_enable_vbus_intr(ci); > + > + if (ci->is_otg) > + hw_enable_vbus_intr(ci); It might be easier on the eyes if you move the "if (ci->is_otg)" check inside hw_enable_vbus_intr(). But otherwise looks sensible. Regards, -- Alex From juhosg@openwrt.org Thu Feb 14 15:19:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Feb 2013 15:19:40 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:60547 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823080Ab3BNOTjTo4y9 (ORCPT ); Thu, 14 Feb 2013 15:19:39 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id G56qhYG9OGOO; Thu, 14 Feb 2013 15:19:24 +0100 (CET) Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 7EAEB284467; Thu, 14 Feb 2013 15:19:24 +0100 (CET) Message-ID: <511CF27F.3080604@openwrt.org> Date: Thu, 14 Feb 2013 15:19:43 +0100 From: Gabor Juhos MIME-Version: 1.0 To: Svetoslav Neykov CC: Ralf Baechle , Alexander Shishkin , Greg Kroah-Hartman , John Crispin , Alan Stern , "Luis R. Rodriguez" , linux-mips@linux-mips.org, linux-usb@vger.kernel.org Subject: Re: [PATCH 4/5] usb: chipidea: AR933x platform support for the chipidea driver References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <1360791538-6332-5-git-send-email-svetoslav@neykov.name> In-Reply-To: <1360791538-6332-5-git-send-email-svetoslav@neykov.name> X-Enigmail-Version: 1.5 Content-Type: text/plain; charset=ISO-8859-2 Content-Transfer-Encoding: 7bit X-archive-position: 35752 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3474 Lines: 113 Hi Svetoslav, > Support host and device usb modes for the chipidea controller in AR933x. > The controller doesn't support OTG functionality so the platform code > forces one of the modes based on the state of GPIO13 pin at startup. > > Signed-off-by: Svetoslav Neykov > --- <...> > diff --git a/drivers/usb/chipidea/ci13xxx_ar933x.c b/drivers/usb/chipidea/ci13xxx_ar933x.c > new file mode 100644 > index 0000000..046a4b6 > --- /dev/null > +++ b/drivers/usb/chipidea/ci13xxx_ar933x.c > @@ -0,0 +1,73 @@ > +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "ci.h" > + > +static struct ci13xxx_platform_data ci13xxx_ar933x_platdata = { > + .name = "ci13xxx_ar933x", > + .flags = 0, > + .capoffset = DEF_CAPOFFSET > +}; Static data only works if there are only one USB IP in the SoCs. It is true for the AR9330 SoC, but newer SoCs may have more. Please use a dynamically allocated structure and fill that in the probe routine. > + > +static int __devinit ci13xxx_ar933x_probe(struct platform_device *pdev) > +{ > + u32 bootstrap; > + struct platform_device *plat_ci; > + > + dev_dbg(&pdev->dev, "ci13xxx_ar933x_probe\n"); > + > + bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); > + if (bootstrap & AR933X_BOOTSTRAP_USB_MODE_HOST) > + ci13xxx_ar933x_platdata.flags = CI13XXX_FORCE_HOST_MODE; > + else > + ci13xxx_ar933x_platdata.flags = CI13XXX_FORCE_DEVICE_MODE; This bootstrap setting is only valid for the AR933x SoCs. It would be better to move this code into the SoC specific USB device registration code, and use platform data to pass that information to this driver. > + > + plat_ci = ci13xxx_add_device(&pdev->dev, > + pdev->resource, pdev->num_resources, > + &ci13xxx_ar933x_platdata); > + if (IS_ERR(plat_ci)) { > + dev_err(&pdev->dev, "ci13xxx_add_device failed!\n"); > + return PTR_ERR(plat_ci); > + } > + > + platform_set_drvdata(pdev, plat_ci); > + > + pm_runtime_no_callbacks(&pdev->dev); > + pm_runtime_enable(&pdev->dev); > + > + return 0; > +} > + > +static int __devexit ci13xxx_ar933x_remove(struct platform_device *pdev) > +{ > + struct platform_device *plat_ci = platform_get_drvdata(pdev); > + > + pm_runtime_disable(&pdev->dev); > + ci13xxx_remove_device(plat_ci); > + > + return 0; > +} > + > +static struct platform_driver ci13xxx_ar933x_driver = { > + .probe = ci13xxx_ar933x_probe, > + .remove = __devexit_p(ci13xxx_ar933x_remove), > + .driver = { .name = "ehci-platform", }, This name is used by the ehci-platform driver. You should pick a different one for this driver. Additionally, the device registration code in 'arch/mips/ath79/dev-usb.c' must be adjusted as well. > +}; > + > +module_platform_driver(ci13xxx_ar933x_driver); > + > +MODULE_ALIAS("platform:ar933x_hsusb"); The driver part of the MODULE_ALIAS string should match with the driver name. You should use this instead ci13xxx_ar933x_driver > +MODULE_LICENSE("GPL v2"); Regards, Gabor From juhosg@openwrt.org Fri Feb 15 15:38:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:38:32 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58566 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823126Ab3BOOibFFl8N (ORCPT ); Fri, 15 Feb 2013 15:38:31 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 07Ar_s5T08rv; Fri, 15 Feb 2013 15:38:19 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id E9E4A2801AE; Fri, 15 Feb 2013 15:38:18 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos Subject: [PATCH 00/11] MIPS: ath79: add support for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:14 +0100 Message-Id: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35753 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2192 Lines: 44 This series adds support for the Qualcomm Atheros QCA955[68] SoCs and for the AP136-010 reference board The series depends on the following patch: MIPS: ath79: use dynamically allocated USB platform devices https://patchwork.linux-mips.org/patch/4933/ Gabor Juhos (11): MIPS: ath79: add early printk support for the QCA955X SoCs MIPS: ath79: add SoC detection code for the QCA955X SoCs MIPS: ath79: add clock setup code for the QCA955X SoCs MIPS: ath79: add IRQ handling code for the QCA955X SoCs MIPS: ath79: add GPIO setup code for the QCA955X SoCs MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set,clear} MIPS: ath79: register UART for the QCA955X SoCs MIPS: ath79: add WMAC registration code for the QCA955X SoCs MIPS: ath79: add PCI controller registration code for the QCA9558 SoC MIPS: ath79: add USB controller registration code for the QCA955X SoCs MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board arch/mips/ath79/Kconfig | 20 ++- arch/mips/ath79/Makefile | 1 + arch/mips/ath79/clock.c | 78 ++++++++++++ arch/mips/ath79/common.c | 4 + arch/mips/ath79/dev-common.c | 3 +- arch/mips/ath79/dev-usb.c | 15 +++ arch/mips/ath79/dev-wmac.c | 20 +++ arch/mips/ath79/early_printk.c | 2 + arch/mips/ath79/gpio.c | 4 +- arch/mips/ath79/irq.c | 110 +++++++++++++++-- arch/mips/ath79/mach-ap136.c | 156 ++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + arch/mips/ath79/pci.c | 36 ++++++ arch/mips/ath79/setup.c | 18 ++- arch/mips/configs/ath79_defconfig | 1 + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 96 +++++++++++++++ arch/mips/include/asm/mach-ath79/ath79.h | 17 +++ arch/mips/include/asm/mach-ath79/irq.h | 6 +- 18 files changed, 576 insertions(+), 12 deletions(-) create mode 100644 arch/mips/ath79/mach-ap136.c -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:38:51 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58577 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827501Ab3BOOibGGcXP (ORCPT ); Fri, 15 Feb 2013 15:38:31 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mjuJUfVBZ77c; Fri, 15 Feb 2013 15:38:20 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id D1E642801AE; Fri, 15 Feb 2013 15:38:19 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 02/11] MIPS: ath79: add SoC detection code for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:16 +0100 Message-Id: <1360939105-23591-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35754 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3161 Lines: 115 Also add 'soc_is_qca955[68x]' helper functions and a Kconfig symbol for the SoC family. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/Kconfig | 4 ++++ arch/mips/ath79/setup.c | 18 +++++++++++++++++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ arch/mips/include/asm/mach-ath79/ath79.h | 17 +++++++++++++++++ 4 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index f44feee..cffdc8e 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -88,6 +88,10 @@ config SOC_AR934X select PCI_AR724X if PCI def_bool n +config SOC_QCA955X + select USB_ARCH_HAS_EHCI + def_bool n + config PCI_AR724X def_bool n diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 60d212e..d5b3c90 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -164,13 +164,29 @@ static void __init ath79_detect_sys_type(void) rev = id & AR934X_REV_ID_REVISION_MASK; break; + case REV_ID_MAJOR_QCA9556: + ath79_soc = ATH79_SOC_QCA9556; + chip = "9556"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9558: + ath79_soc = ATH79_SOC_QCA9558; + chip = "9558"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + default: panic("ath79: unknown SoC, id:0x%08x", id); } ath79_soc_rev = rev; - sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + if (soc_is_qca955x()) + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", + chip, rev); + else + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); pr_info("SoC: %s\n", ath79_sys_type); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index d02c2d4..63a9f2b 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -392,6 +392,8 @@ #define AR934X_REV_ID_REVISION_MASK 0xf +#define QCA955X_REV_ID_REVISION_MASK 0xf + /* * SPI block */ diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h index 4f248c3..1557934 100644 --- a/arch/mips/include/asm/mach-ath79/ath79.h +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -32,6 +32,8 @@ enum ath79_soc_type { ATH79_SOC_AR9341, ATH79_SOC_AR9342, ATH79_SOC_AR9344, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, }; extern enum ath79_soc_type ath79_soc; @@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void) return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); } +static inline int soc_is_qca9556(void) +{ + return ath79_soc == ATH79_SOC_QCA9556; +} + +static inline int soc_is_qca9558(void) +{ + return ath79_soc == ATH79_SOC_QCA9558; +} + +static inline int soc_is_qca955x(void) +{ + return soc_is_qca9556() || soc_is_qca9558(); +} + extern void __iomem *ath79_ddr_base; extern void __iomem *ath79_pll_base; extern void __iomem *ath79_reset_base; -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:39:16 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58574 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827505Ab3BOOibNIlLP (ORCPT ); Fri, 15 Feb 2013 15:38:31 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L96xSFJzxZfw; Fri, 15 Feb 2013 15:38:19 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 46BAD280213; Fri, 15 Feb 2013 15:38:19 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 01/11] MIPS: ath79: add early printk support for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:15 +0100 Message-Id: <1360939105-23591-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35755 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1402 Lines: 41 The patch allows to see kernel messages on the QCA955X SoCs in early boot stage. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/early_printk.c | 2 ++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c index dc938cb..b955faf 100644 --- a/arch/mips/ath79/early_printk.c +++ b/arch/mips/ath79/early_printk.c @@ -74,6 +74,8 @@ static void prom_putchar_init(void) case REV_ID_MAJOR_AR9341: case REV_ID_MAJOR_AR9342: case REV_ID_MAJOR_AR9344: + case REV_ID_MAJOR_QCA9556: + case REV_ID_MAJOR_QCA9558: _prom_putchar = prom_putchar_ar71xx; break; diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index a77f6ee..d02c2d4 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -370,6 +370,8 @@ #define REV_ID_MAJOR_AR9341 0x0120 #define REV_ID_MAJOR_AR9342 0x1120 #define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:39:41 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58586 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827506Ab3BOOibdCss5 (ORCPT ); Fri, 15 Feb 2013 15:38:31 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b1Dcv167nEEL; Fri, 15 Feb 2013 15:38:20 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 5BCAF2801AE; Fri, 15 Feb 2013 15:38:20 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 03/11] MIPS: ath79: add clock setup code for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:17 +0100 Message-Id: <1360939105-23591-4-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35756 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 6367 Lines: 175 The patch adds code to get various clock frequencies from the PLLs used in the QCA955x SoCs. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 39 ++++++++++++ 2 files changed, 117 insertions(+) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index 579f452..555e603 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(void) iounmap(dpll_base); } +static void __init qca955x_clocks_init(void) +{ + u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; + u32 cpu_pll, ddr_pll; + u32 bootstrap; + + bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); + if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) + ath79_ref_clk.rate = 40 * 1000 * 1000; + else + ath79_ref_clk.rate = 25 * 1000 * 1000; + + pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); + out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; + ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; + nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & + QCA955X_PLL_CPU_CONFIG_NINT_MASK; + frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; + + cpu_pll = nint * ath79_ref_clk.rate / ref_div; + cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); + cpu_pll /= (1 << out_div); + + pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); + out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; + ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; + nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & + QCA955X_PLL_DDR_CONFIG_NINT_MASK; + frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; + + ddr_pll = nint * ath79_ref_clk.rate / ref_div; + ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); + ddr_pll /= (1 << out_div); + + clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); + + postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & + QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; + + if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) + ath79_cpu_clk.rate = ath79_ref_clk.rate; + else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) + ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); + else + ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & + QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; + + if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) + ath79_ddr_clk.rate = ath79_ref_clk.rate; + else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) + ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); + else + ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & + QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; + + if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) + ath79_ahb_clk.rate = ath79_ref_clk.rate; + else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) + ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); + else + ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); + + ath79_wdt_clk.rate = ath79_ref_clk.rate; + ath79_uart_clk.rate = ath79_ref_clk.rate; +} + void __init ath79_clocks_init(void) { if (soc_is_ar71xx()) @@ -307,6 +383,8 @@ void __init ath79_clocks_init(void) ar933x_clocks_init(); else if (soc_is_ar934x()) ar934x_clocks_init(); + else if (soc_is_qca955x()) + qca955x_clocks_init(); else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 63a9f2b..7b00e12 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -225,6 +225,41 @@ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + /* * USB_CONFIG block */ @@ -264,6 +299,8 @@ #define AR934X_RESET_REG_BOOTSTRAP 0xb0 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 + #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) #define MISC_INT_TIMER3 BIT(9) @@ -341,6 +378,8 @@ #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) #define AR934X_BOOTSTRAP_DDR1 BIT(0) +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:40:00 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58590 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827515Ab3BOOibxuSWN (ORCPT ); Fri, 15 Feb 2013 15:38:31 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3XSO-2JOHyW3; Fri, 15 Feb 2013 15:38:21 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id E563A2802DD; Fri, 15 Feb 2013 15:38:20 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 04/11] MIPS: ath79: add IRQ handling code for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:18 +0100 Message-Id: <1360939105-23591-5-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35757 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7209 Lines: 246 The IRQ routing in the QCA955x SoCs is slightly different from the routing implemented in the already supported SoCs. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/irq.c | 110 ++++++++++++++++++++++-- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++++++ arch/mips/include/asm/mach-ath79/irq.h | 6 +- 3 files changed, 140 insertions(+), 8 deletions(-) diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index df88d49..b0f85a6 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -103,7 +103,10 @@ static void __init ath79_misc_irq_init(void) if (soc_is_ar71xx() || soc_is_ar913x()) ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; - else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) + else if (soc_is_ar724x() || + soc_is_ar933x() || + soc_is_ar934x() || + soc_is_qca955x()) ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; else BUG(); @@ -150,6 +153,88 @@ static void ar934x_ip2_irq_init(void) irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); } +static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) +{ + u32 status; + + disable_irq_nosync(irq); + + status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); + status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; + + if (status == 0) { + spurious_interrupt(); + goto enable; + } + + if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP2_IRQ(0)); + } + + if (status & QCA955X_EXT_INT_WMAC_ALL) { + /* TODO: flsuh DDR? */ + generic_handle_irq(ATH79_IP2_IRQ(1)); + } + +enable: + enable_irq(irq); +} + +static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc) +{ + u32 status; + + disable_irq_nosync(irq); + + status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); + status &= QCA955X_EXT_INT_PCIE_RC2_ALL | + QCA955X_EXT_INT_USB1 | + QCA955X_EXT_INT_USB2; + + if (status == 0) { + spurious_interrupt(); + goto enable; + } + + if (status & QCA955X_EXT_INT_USB1) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(0)); + } + + if (status & QCA955X_EXT_INT_USB2) { + /* TODO: flsuh DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(1)); + } + + if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(2)); + } + +enable: + enable_irq(irq); +} + +static void qca955x_irq_init(void) +{ + int i; + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &dummy_irq_chip, + handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); + + for (i = ATH79_IP3_IRQ_BASE; + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &dummy_irq_chip, + handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); +} + asmlinkage void plat_irq_dispatch(void) { unsigned long pending; @@ -185,6 +270,17 @@ asmlinkage void plat_irq_dispatch(void) * Issue a flush in the handlers to ensure that the driver sees * the update. */ + +static void ath79_default_ip2_handler(void) +{ + do_IRQ(ATH79_CPU_IRQ(2)); +} + +static void ath79_default_ip3_handler(void) +{ + do_IRQ(ATH79_CPU_IRQ(3)); +} + static void ar71xx_ip2_handler(void) { ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); @@ -209,11 +305,6 @@ static void ar933x_ip2_handler(void) do_IRQ(ATH79_CPU_IRQ(2)); } -static void ar934x_ip2_handler(void) -{ - do_IRQ(ATH79_CPU_IRQ(2)); -} - static void ar71xx_ip3_handler(void) { ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); @@ -259,8 +350,11 @@ void __init arch_init_irq(void) ath79_ip2_handler = ar933x_ip2_handler; ath79_ip3_handler = ar933x_ip3_handler; } else if (soc_is_ar934x()) { - ath79_ip2_handler = ar934x_ip2_handler; + ath79_ip2_handler = ath79_default_ip2_handler; ath79_ip3_handler = ar934x_ip3_handler; + } else if (soc_is_qca955x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ath79_default_ip3_handler; } else { BUG(); } @@ -271,4 +365,6 @@ void __init arch_init_irq(void) if (soc_is_ar934x()) ar934x_ip2_irq_init(); + else if (soc_is_qca955x()) + qca955x_irq_init(); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 7b00e12..8782d8b 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -300,6 +300,7 @@ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) @@ -398,6 +399,37 @@ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ AR934X_PCIE_WMAC_INT_PCIE_RC3) +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + #define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_AR71XX 0x00a0 #define REV_ID_MAJOR_AR913X 0x00b0 diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 23e2bba..5c9ca76 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -10,7 +10,7 @@ #define __ASM_MACH_ATH79_IRQ_H #define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 48 +#define NR_IRQS 51 #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) @@ -26,6 +26,10 @@ #define ATH79_IP2_IRQ_COUNT 2 #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) +#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT) +#define ATH79_IP3_IRQ_COUNT 3 +#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) + #include_next #endif /* __ASM_MACH_ATH79_IRQ_H */ -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:32 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:40:19 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58595 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827513Ab3BOOicgQuUB (ORCPT ); Fri, 15 Feb 2013 15:38:32 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GkwtkL3vTB7U; Fri, 15 Feb 2013 15:38:21 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 5414C2802DD; Fri, 15 Feb 2013 15:38:21 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 05/11] MIPS: ath79: add GPIO setup code for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:19 +0100 Message-Id: <1360939105-23591-6-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35758 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1631 Lines: 48 The existing code can handle the GPIO controller of the QCA955x SoCs. Add a minimal glue code to make it working. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/gpio.c | 4 +++- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c index b7ed207..8d025b0 100644 --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c @@ -194,12 +194,14 @@ void __init ath79_gpio_init(void) ath79_gpio_count = AR933X_GPIO_COUNT; else if (soc_is_ar934x()) ath79_gpio_count = AR934X_GPIO_COUNT; + else if (soc_is_qca955x()) + ath79_gpio_count = QCA955X_GPIO_COUNT; else BUG(); ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); ath79_gpio_chip.ngpio = ath79_gpio_count; - if (soc_is_ar934x()) { + if (soc_is_ar934x() || soc_is_qca955x()) { ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 8782d8b..4868ed5 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -510,6 +510,7 @@ #define AR913X_GPIO_COUNT 22 #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 +#define QCA955X_GPIO_COUNT 24 /* * SRIF block -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:33 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:40:39 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58599 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827517Ab3BOOidZWqGA (ORCPT ); Fri, 15 Feb 2013 15:38:33 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FDE-hEGORjyq; Fri, 15 Feb 2013 15:38:22 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id EAF7228039B; Fri, 15 Feb 2013 15:38:21 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 06/11] MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set,clear} Date: Fri, 15 Feb 2013 15:38:20 +0100 Message-Id: <1360939105-23591-7-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35759 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1656 Lines: 50 The ath79_device_reset_* are causing BUG when those are used on the QCA955x SoCs. The patch adds the required code to avoid that. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/common.c | 4 ++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index 5a4adfc..eb3966c 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -72,6 +72,8 @@ void ath79_device_reset_set(u32 mask) reg = AR933X_RESET_REG_RESET_MODULE; else if (soc_is_ar934x()) reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; else BUG(); @@ -98,6 +100,8 @@ void ath79_device_reset_clear(u32 mask) reg = AR933X_RESET_REG_RESET_MODULE; else if (soc_is_ar934x()) reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 4868ed5..bf50ddf 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -299,6 +299,7 @@ #define AR934X_RESET_REG_BOOTSTRAP 0xb0 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac +#define QCA955X_RESET_REG_RESET_MODULE 0x1c #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:33 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:40:58 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58604 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827605Ab3BOOidvKbu0 (ORCPT ); Fri, 15 Feb 2013 15:38:33 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VjPz2X_HzF1p; Fri, 15 Feb 2013 15:38:23 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id B8B1128039B; Fri, 15 Feb 2013 15:38:22 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 07/11] MIPS: ath79: register UART for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:21 +0100 Message-Id: <1360939105-23591-8-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35760 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 964 Lines: 30 Similarly to the preceding SoCs, the QCA955X SoCs also have a built-in NS16650 compatible UART. Register the platform device for that to make it usable. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/dev-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c index 9be1465..a3a2741 100644 --- a/arch/mips/ath79/dev-common.c +++ b/arch/mips/ath79/dev-common.c @@ -90,7 +90,8 @@ void __init ath79_register_uart(void) if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x() || - soc_is_ar934x()) { + soc_is_ar934x() || + soc_is_qca955x()) { ath79_uart_data[0].uartclk = clk_get_rate(clk); platform_device_register(&ath79_uart_device); } else if (soc_is_ar933x()) { -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:34 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:41:19 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58608 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827626Ab3BOOieRuRyk (ORCPT ); Fri, 15 Feb 2013 15:38:34 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id M0ZzVByXgMtM; Fri, 15 Feb 2013 15:38:23 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 449DF2803BD; Fri, 15 Feb 2013 15:38:23 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 08/11] MIPS: ath79: add WMAC registration code for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:22 +0100 Message-Id: <1360939105-23591-9-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35761 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2492 Lines: 81 The SoC has a built-in wireless MAC. Register a platform device for that to make it usable with the ath9k driver. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/Kconfig | 2 +- arch/mips/ath79/dev-wmac.c | 20 ++++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index cffdc8e..77926e3 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -108,7 +108,7 @@ config ATH79_DEV_USB def_bool n config ATH79_DEV_WMAC - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) def_bool n endif diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index 4f6c4e3..3e00c09 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void) ath79_wmac_data.is_clk_25mhz = true; } +static void qca955x_wmac_setup(void) +{ + u32 t; + + ath79_wmac_device.name = "qca955x_wmac"; + + ath79_wmac_resources[0].start = QCA955X_WMAC_BASE; + ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1; + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); + + t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); + if (t & QCA955X_BOOTSTRAP_REF_CLK_40) + ath79_wmac_data.is_clk_25mhz = false; + else + ath79_wmac_data.is_clk_25mhz = true; +} + void __init ath79_register_wmac(u8 *cal_data) { if (soc_is_ar913x()) @@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_data) ar933x_wmac_setup(); else if (soc_is_ar934x()) ar934x_wmac_setup(); + else if (soc_is_qca955x()) + qca955x_wmac_setup(); else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index bf50ddf..4728212 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -94,6 +94,9 @@ #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) #define AR934X_SRIF_SIZE 0x1000 +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 + /* * DDR_CTRL block */ -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:34 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:41:38 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58612 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827636Ab3BOOieq7ndo (ORCPT ); Fri, 15 Feb 2013 15:38:34 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 53_5SFQutvdd; Fri, 15 Feb 2013 15:38:24 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id B22A32803BD; Fri, 15 Feb 2013 15:38:23 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 09/11] MIPS: ath79: add PCI controller registration code for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:23 +0100 Message-Id: <1360939105-23591-10-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35762 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3591 Lines: 114 Add SoC specific PCI IRQ map, and register platform devices for the two built-in PCIe RCs. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/Kconfig | 2 ++ arch/mips/ath79/pci.c | 36 ++++++++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 +++++++++ 3 files changed, 51 insertions(+) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 77926e3..76a001e 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -90,6 +90,8 @@ config SOC_AR934X config SOC_QCA955X select USB_ARCH_HAS_EHCI + select HW_HAS_PCI + select PCI_AR724X if PCI def_bool n config PCI_AR724X diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index 4350c25..730c0b0 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { } }; +static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { + { + .bus = 0, + .slot = 0, + .pin = 1, + .irq = ATH79_PCI_IRQ(0), + }, + { + .bus = 1, + .slot = 0, + .pin = 1, + .irq = ATH79_PCI_IRQ(1), + }, +}; + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) { int irq = -1; @@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) soc_is_ar9344()) { ath79_pci_irq_map = ar724x_pci_irq_map; ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); + } else if (soc_is_qca955x()) { + ath79_pci_irq_map = qca955x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); } else { pr_crit("pci %s: invalid irq map\n", pci_name((struct pci_dev *) dev)); @@ -225,6 +243,24 @@ int __init ath79_register_pci(void) AR724X_PCI_MEM_SIZE, 0, ATH79_IP2_IRQ(0)); + } else if (soc_is_qca9558()) { + pdev = ath79_register_pci_ar724x(0, + QCA955X_PCI_CFG_BASE0, + QCA955X_PCI_CTRL_BASE0, + QCA955X_PCI_CRP_BASE0, + QCA955X_PCI_MEM_BASE0, + QCA955X_PCI_MEM_SIZE, + 0, + ATH79_IP2_IRQ(0)); + + pdev = ath79_register_pci_ar724x(1, + QCA955X_PCI_CFG_BASE1, + QCA955X_PCI_CTRL_BASE1, + QCA955X_PCI_CRP_BASE1, + QCA955X_PCI_MEM_BASE1, + QCA955X_PCI_MEM_SIZE, + 1, + ATH79_IP3_IRQ(2)); } else { /* No PCI support */ return -ENODEV; diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 4728212..b7fa9d1 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -94,6 +94,19 @@ #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) #define AR934X_SRIF_SIZE 0x1000 +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define QCA955X_WMAC_SIZE 0x20000 -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:41:56 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58619 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827645Ab3BOOifKRlsZ (ORCPT ); Fri, 15 Feb 2013 15:38:35 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7FZt2INfF2Tu; Fri, 15 Feb 2013 15:38:24 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 244B3280329; Fri, 15 Feb 2013 15:38:24 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 10/11] MIPS: ath79: add USB controller registration code for the QCA955X SoCs Date: Fri, 15 Feb 2013 15:38:24 +0100 Message-Id: <1360939105-23591-11-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35763 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1895 Lines: 62 Register platfom devices for the built-in USB controllers of the SoCs. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/dev-usb.c | 15 +++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +++ 2 files changed, 18 insertions(+) diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c index 02124d0..8227265 100644 --- a/arch/mips/ath79/dev-usb.c +++ b/arch/mips/ath79/dev-usb.c @@ -208,6 +208,19 @@ static void __init ar934x_usb_setup(void) &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); } +static void __init qca955x_usb_setup(void) +{ + ath79_usb_register("ehci-platform", 0, + QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, + ATH79_IP3_IRQ(0), + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + + ath79_usb_register("ehci-platform", 1, + QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE, + ATH79_IP3_IRQ(1), + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); +} + void __init ath79_register_usb(void) { if (soc_is_ar71xx()) @@ -222,6 +235,8 @@ void __init ath79_register_usb(void) ar933x_usb_setup(); else if (soc_is_ar934x()) ar934x_usb_setup(); + else if (soc_is_qca955x()) + qca955x_usb_setup(); else BUG(); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index b7fa9d1..4de1831 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -109,6 +109,9 @@ #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 /* * DDR_CTRL block -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 15:38:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 15:42:16 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:58632 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827646Ab3BOOifjH0py (ORCPT ); Fri, 15 Feb 2013 15:38:35 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xt-y3m-zNdaP; Fri, 15 Feb 2013 15:38:24 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 93292280213; Fri, 15 Feb 2013 15:38:24 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH 11/11] MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board Date: Fri, 15 Feb 2013 15:38:25 +0100 Message-Id: <1360939105-23591-12-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> X-archive-position: 35764 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7061 Lines: 238 Also enable the board in the default configuration. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- arch/mips/ath79/Kconfig | 12 +++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/mach-ap136.c | 156 +++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + arch/mips/configs/ath79_defconfig | 1 + 5 files changed, 171 insertions(+) create mode 100644 arch/mips/ath79/mach-ap136.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 76a001e..3995e31 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -14,6 +14,18 @@ config ATH79_MACH_AP121 Say 'Y' here if you want your kernel to support the Atheros AP121 reference board. +config ATH79_MACH_AP136 + bool "Atheros AP136 reference board" + select SOC_QCA955X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help + Say 'Y' here if you want your kernel to support the + Atheros AP136 reference board. + config ATH79_MACH_AP81 bool "Atheros AP81 reference board" select SOC_AR913X diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 2b54d98..5c9ff69 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o # Machines # obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o +obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o diff --git a/arch/mips/ath79/mach-ap136.c b/arch/mips/ath79/mach-ap136.c new file mode 100644 index 0000000..479dd4b --- /dev/null +++ b/arch/mips/ath79/mach-ap136.c @@ -0,0 +1,156 @@ +/* + * Qualcomm Atheros AP136 reference board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +#include "machtypes.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "pci.h" + +#define AP136_GPIO_LED_STATUS_RED 14 +#define AP136_GPIO_LED_STATUS_GREEN 19 +#define AP136_GPIO_LED_USB 4 +#define AP136_GPIO_LED_WLAN_2G 13 +#define AP136_GPIO_LED_WLAN_5G 12 +#define AP136_GPIO_LED_WPS_RED 15 +#define AP136_GPIO_LED_WPS_GREEN 20 + +#define AP136_GPIO_BTN_WPS 16 +#define AP136_GPIO_BTN_RFKILL 21 + +#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) + +#define AP136_WMAC_CALDATA_OFFSET 0x1000 +#define AP136_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led ap136_leds_gpio[] __initdata = { + { + .name = "qca:green:status", + .gpio = AP136_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { + .name = "qca:red:status", + .gpio = AP136_GPIO_LED_STATUS_RED, + .active_low = 1, + }, + { + .name = "qca:green:wps", + .gpio = AP136_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, + { + .name = "qca:red:wps", + .gpio = AP136_GPIO_LED_WPS_RED, + .active_low = 1, + }, + { + .name = "qca:red:wlan-2g", + .gpio = AP136_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "qca:red:usb", + .gpio = AP136_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap136_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP136_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP136_GPIO_BTN_RFKILL, + .active_low = 1, + }, +}; + +static struct spi_board_info ap136_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "mx25l6405d", + } +}; + +static struct ath79_spi_platform_data ap136_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +#ifdef CONFIG_PCI +static struct ath9k_platform_data ap136_ath9k_data; + +static int ap136_pci_plat_dev_init(struct pci_dev *dev) +{ + if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) + dev->dev.platform_data = &ap136_ath9k_data; + + return 0; +} + +static void __init ap136_pci_init(u8 *eeprom) +{ + memcpy(ap136_ath9k_data.eeprom_data, eeprom, + sizeof(ap136_ath9k_data.eeprom_data)); + + ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); + ath79_register_pci(); +} +#else +static inline void ap136_pci_init(void) {} +#endif /* CONFIG_PCI */ + +static void __init ap136_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), + ap136_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap136_gpio_keys), + ap136_gpio_keys); + ath79_register_spi(&ap136_spi_data, ap136_spi_info, + ARRAY_SIZE(ap136_spi_info)); + ath79_register_usb(); + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); + ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", + "Atheros AP136-010 reference board", + ap136_setup); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index af92e5c..2625405 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -17,6 +17,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ ATH79_MACH_AP81, /* Atheros AP81 reference board */ ATH79_MACH_DB120, /* Atheros DB120 reference board */ ATH79_MACH_PB44, /* Atheros PB44 reference board */ diff --git a/arch/mips/configs/ath79_defconfig b/arch/mips/configs/ath79_defconfig index ea87d43..e3a3836 100644 --- a/arch/mips/configs/ath79_defconfig +++ b/arch/mips/configs/ath79_defconfig @@ -1,5 +1,6 @@ CONFIG_ATH79=y CONFIG_ATH79_MACH_AP121=y +CONFIG_ATH79_MACH_AP136=y CONFIG_ATH79_MACH_AP81=y CONFIG_ATH79_MACH_DB120=y CONFIG_ATH79_MACH_PB44=y -- 1.7.10 From blogic@openwrt.org Fri Feb 15 17:03:59 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 17:04:00 +0100 (CET) Received: from nbd.name ([46.4.11.11]:60549 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827499Ab3BOQD71dq0H (ORCPT ); Fri, 15 Feb 2013 17:03:59 +0100 Message-ID: <511E5BB8.8060800@openwrt.org> Date: Fri, 15 Feb 2013 17:00:56 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: Re: [PATCH 02/11] MIPS: ath79: add SoC detection code for the QCA955X SoCs References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> <1360939105-23591-3-git-send-email-juhosg@openwrt.org> In-Reply-To: <1360939105-23591-3-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35765 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 439 Lines: 18 > > - sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); > + if (soc_is_qca955x()) > + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", > + chip, rev); > + else > + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); > pr_info("SoC: %s\n", ath79_sys_type); > } > Hi, maybe a soc_is_qca() could be used here, otherwise you will need to patch this line again for the next SoC and so on .... John From blogic@openwrt.org Fri Feb 15 17:04:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 17:04:43 +0100 (CET) Received: from nbd.name ([46.4.11.11]:60569 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827652Ab3BOQEbTMftK (ORCPT ); Fri, 15 Feb 2013 17:04:31 +0100 Message-ID: <511E5BD9.1040407@openwrt.org> Date: Fri, 15 Feb 2013 17:01:29 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: Re: [PATCH 04/11] MIPS: ath79: add IRQ handling code for the QCA955X SoCs References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> <1360939105-23591-5-git-send-email-juhosg@openwrt.org> In-Reply-To: <1360939105-23591-5-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35766 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 750 Lines: 30 > > if (soc_is_ar71xx() || soc_is_ar913x()) > ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; > - else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) > + else if (soc_is_ar724x() || > + soc_is_ar933x() || > + soc_is_ar934x() || > + soc_is_qca955x()) > ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; Hi, the list is getting long. not a blocker but might be worth thinking of a different way to solve the different revisions of the irq core > + if (status& QCA955X_EXT_INT_USB1) { > + /* TODO: flush DDR? */ > + generic_handle_irq(ATH79_IP3_IRQ(0)); > + } > + > + if (status& QCA955X_EXT_INT_USB2) { > + /* TODO: flsuh DDR? */ > + generic_handle_irq(ATH79_IP3_IRQ(1)); > + } flsuh typo John From blogic@openwrt.org Fri Feb 15 17:04:47 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 17:05:16 +0100 (CET) Received: from nbd.name ([46.4.11.11]:60627 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827646Ab3BOQErJTscW (ORCPT ); Fri, 15 Feb 2013 17:04:47 +0100 Message-ID: <511E5BE9.7010400@openwrt.org> Date: Fri, 15 Feb 2013 17:01:45 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: Re: [PATCH 08/11] MIPS: ath79: add WMAC registration code for the QCA955X SoCs References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> <1360939105-23591-9-git-send-email-juhosg@openwrt.org> In-Reply-To: <1360939105-23591-9-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35767 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 196 Lines: 10 On 15/02/13 15:38, Gabor Juhos wrote: > + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); > + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); Hi, second line should read .stop ? John From blogic@openwrt.org Fri Feb 15 17:05:03 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 17:05:38 +0100 (CET) Received: from nbd.name ([46.4.11.11]:60639 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827650Ab3BOQFDIPeUd (ORCPT ); Fri, 15 Feb 2013 17:05:03 +0100 Message-ID: <511E5BF9.9070208@openwrt.org> Date: Fri, 15 Feb 2013 17:02:01 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: Re: [PATCH 11/11] MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> <1360939105-23591-12-git-send-email-juhosg@openwrt.org> In-Reply-To: <1360939105-23591-12-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35768 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 218 Lines: 9 On 15/02/13 15:38, Gabor Juhos wrote: > + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ Hi, just because i am curious ... why the AP136_010 the rest of the code uses AP136 with no suffix John From sanjayl@kymasys.com Fri Feb 15 17:10:54 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 17:10:54 +0100 (CET) Received: from kymasys.com ([64.62.140.43]:48070 "HELO kymasys.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S6827651Ab3BOQKyLupgC convert rfc822-to-8bit (ORCPT ); Fri, 15 Feb 2013 17:10:54 +0100 Received: from ::ffff:173.33.185.184 ([173.33.185.184]) by kymasys.com for ; Fri, 15 Feb 2013 08:10:45 -0800 Subject: Re: [PATCH v2 11/18] KVM/MIPS32: Routines to handle specific traps/exceptions while executing the guest. Mime-Version: 1.0 (Apple Message framework v1283) Content-Type: text/plain; charset=us-ascii From: Sanjay Lal In-Reply-To: <20130206132018.GC7837@redhat.com> Date: Fri, 15 Feb 2013 11:10:46 -0500 Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Content-Transfer-Encoding: 8BIT Message-Id: References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-12-git-send-email-sanjayl@kymasys.com> <20130206132018.GC7837@redhat.com> To: Gleb Natapov X-Mailer: Apple Mail (2.1283) X-archive-position: 35769 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sanjayl@kymasys.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 870 Lines: 21 On Feb 6, 2013, at 8:20 AM, Gleb Natapov wrote: > On Wed, Nov 21, 2012 at 06:34:09PM -0800, Sanjay Lal wrote: >> +static gpa_t kvm_trap_emul_gva_to_gpa_cb(gva_t gva) >> +{ >> + gpa_t gpa; >> + uint32_t kseg = KSEGX(gva); >> + >> + if ((kseg == CKSEG0) || (kseg == CKSEG1)) > You seems to be using KVM_GUEST_KSEGX variants on gva in all other > places. Why not here? This function is invoked to handle 2 scenarios: (1) Parse the boot code config tables setup by QEMU's Malta emulation. The pointers in the tables are actual KSEG0 addresses (unmapped, cached) and not Guest KSEG0 addresses. (2) Handle I/O accesses by the guest. On MIPS platforms, I/O device registers are mapped into the KSEG1 address space (unmapped, uncached). Again like (1) these are actual KSEG1 addresses, which cause an exception and are passed onto QEMU for I/O emulation. Regards Sanjay From juhosg@openwrt.org Fri Feb 15 17:42:28 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 17:42:29 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:53697 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827496Ab3BOQm2lKtRt (ORCPT ); Fri, 15 Feb 2013 17:42:28 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id As9vFoI_TWBu; Fri, 15 Feb 2013 17:42:17 +0100 (CET) Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 4B0DE2801AE; Fri, 15 Feb 2013 17:42:17 +0100 (CET) Message-ID: <511E656C.5080501@openwrt.org> Date: Fri, 15 Feb 2013 17:42:20 +0100 From: Gabor Juhos MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: Re: [PATCH 02/11] MIPS: ath79: add SoC detection code for the QCA955X SoCs References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> <1360939105-23591-3-git-send-email-juhosg@openwrt.org> <511E5BB8.8060800@openwrt.org> In-Reply-To: <511E5BB8.8060800@openwrt.org> X-Enigmail-Version: 1.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 35770 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 786 Lines: 24 2013.02.15. 17:00 keltezéssel, John Crispin írta: > >> >> - sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); >> + if (soc_is_qca955x()) >> + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", >> + chip, rev); >> + else >> + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); >> pr_info("SoC: %s\n", ath79_sys_type); >> } >> > Hi, > > maybe a soc_is_qca() could be used here, otherwise you will need to patch this > line again for the next SoC and so on .... Hm, if I would add a soc_is_qca() macro, I would have to patch that macro for the next SoCs instead of this line. Maybe it would be better to add the AR/QCA prefix to each chip name, and use 'Qualcomm Atheros' unconditionally in the sprintf call? -Gabor From juhosg@openwrt.org Fri Feb 15 18:14:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 18:14:06 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:59787 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827496Ab3BOROFqa3Mv (ORCPT ); Fri, 15 Feb 2013 18:14:05 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7ye8o7HZGIAh for ; Fri, 15 Feb 2013 18:13:54 +0100 (CET) Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 8B8142801AE for ; Fri, 15 Feb 2013 18:13:54 +0100 (CET) Message-ID: <511E6CD6.8050503@openwrt.org> Date: Fri, 15 Feb 2013 18:13:58 +0100 From: Gabor Juhos MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH 08/11] MIPS: ath79: add WMAC registration code for the QCA955X SoCs References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> <1360939105-23591-9-git-send-email-juhosg@openwrt.org> <511E5BE9.7010400@openwrt.org> In-Reply-To: <511E5BE9.7010400@openwrt.org> X-Enigmail-Version: 1.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 35771 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 411 Lines: 12 2013.02.15. 17:01 keltezéssel, John Crispin írta: > On 15/02/13 15:38, Gabor Juhos wrote: >> + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); >> + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); > Hi, > > second line should read .stop ? Yes. Although it does not cause problems because only the .start field is used by ath9k, but it must be fixed of course. Will do it in the next version. -Gabor From juhosg@openwrt.org Fri Feb 15 18:26:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 18:26:53 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:33561 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827653Ab3BOR0wSFpIy (ORCPT ); Fri, 15 Feb 2013 18:26:52 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0crYfCOyq23N; Fri, 15 Feb 2013 18:26:41 +0100 (CET) Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 289482801AE; Fri, 15 Feb 2013 18:26:41 +0100 (CET) Message-ID: <511E6FD4.6060802@openwrt.org> Date: Fri, 15 Feb 2013 18:26:44 +0100 From: Gabor Juhos MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: Re: [PATCH 04/11] MIPS: ath79: add IRQ handling code for the QCA955X SoCs References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> <1360939105-23591-5-git-send-email-juhosg@openwrt.org> <511E5BD9.1040407@openwrt.org> In-Reply-To: <511E5BD9.1040407@openwrt.org> X-Enigmail-Version: 1.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 35772 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1389 Lines: 43 2013.02.15. 17:01 keltezéssel, John Crispin írta: > >> >> if (soc_is_ar71xx() || soc_is_ar913x()) >> ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; >> - else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) >> + else if (soc_is_ar724x() || >> + soc_is_ar933x() || >> + soc_is_ar934x() || >> + soc_is_qca955x()) >> ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; > Hi, > > the list is getting long. not a blocker but might be worth thinking of a > different way to solve the different revisions of the irq core This code runs only once, so it is not worth the effort IMHO. If I would introduce a table to store the revision of the IRQ core, I would have to put a value into that for each different SoC. That means 15 entries at the moment. Alternatively I can introduce a global variable to store the revision, and intialize that variable from the SoC detection code. However I would have to set that variable individually for each SoC and that means 15 lines of code. >> + if (status& QCA955X_EXT_INT_USB1) { >> + /* TODO: flush DDR? */ >> + generic_handle_irq(ATH79_IP3_IRQ(0)); >> + } >> + >> + if (status& QCA955X_EXT_INT_USB2) { >> + /* TODO: flsuh DDR? */ >> + generic_handle_irq(ATH79_IP3_IRQ(1)); >> + } > > flsuh typo Yep, will fix it. Thanks, Gabor From juhosg@openwrt.org Fri Feb 15 18:34:08 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 18:34:12 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:34974 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827496Ab3BOReIEGQkW (ORCPT ); Fri, 15 Feb 2013 18:34:08 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FNsfY4pkyuxG for ; Fri, 15 Feb 2013 18:33:57 +0100 (CET) Received: from [192.168.254.50] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 112A22801AE for ; Fri, 15 Feb 2013 18:33:56 +0100 (CET) Message-ID: <511E7188.6000208@openwrt.org> Date: Fri, 15 Feb 2013 18:34:00 +0100 From: Gabor Juhos MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH 11/11] MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board References: <1360939105-23591-1-git-send-email-juhosg@openwrt.org> <1360939105-23591-12-git-send-email-juhosg@openwrt.org> <511E5BF9.9070208@openwrt.org> In-Reply-To: <511E5BF9.9070208@openwrt.org> X-Enigmail-Version: 1.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-archive-position: 35773 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 702 Lines: 18 2013.02.15. 17:02 keltezéssel, John Crispin írta: > On 15/02/13 15:38, Gabor Juhos wrote: >> + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ > > Hi, > > just because i am curious ... why the AP136_010 the rest of the code uses AP136 > with no suffix The rest of the code can be used as-is on the AP136-020 board as well. AFAIK, the main difference between the two versions is that the ethernet switch is connected differently to the SoC. Although we don't have ethernet support yet, but once that is added the setup code for the two boards will be different. Although it would be possible to remove the '010' part for now, but then it should be added later again. -Gabor From sanjayl@kymasys.com Fri Feb 15 19:19:36 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 19:19:37 +0100 (CET) Received: from kymasys.com ([64.62.140.43]:53172 "HELO kymasys.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S6827653Ab3BOSTgeqCMI convert rfc822-to-8bit (ORCPT ); Fri, 15 Feb 2013 19:19:36 +0100 Received: from ::ffff:173.33.185.184 ([173.33.185.184]) by kymasys.com for ; Fri, 15 Feb 2013 10:19:27 -0800 Subject: Re: [PATCH v2 07/18] KVM/MIPS32: MMU/TLB operations for the Guest. Mime-Version: 1.0 (Apple Message framework v1283) Content-Type: text/plain; charset=windows-1255 From: Sanjay Lal In-Reply-To: <20130206120820.GN23213@redhat.com> Date: Fri, 15 Feb 2013 13:19:29 -0500 Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Content-Transfer-Encoding: 8BIT Message-Id: <69F3ED2A-A9B3-4046-9B40-98125ED5A8FB@kymasys.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-8-git-send-email-sanjayl@kymasys.com> <20130206120820.GN23213@redhat.com> To: Gleb Natapov X-Mailer: Apple Mail (2.1283) X-archive-position: 35774 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sanjayl@kymasys.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1545 Lines: 42 On Feb 6, 2013, at 7:08 AM, Gleb Natapov wrote: >> >> +static void kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) >> +{ >> + pfn_t pfn; >> + >> + if (kvm->arch.guest_pmap[gfn] != KVM_INVALID_PAGE) >> + return; >> + >> + pfn =kvm_mips_gfn_to_pfn(kvm, gfn); > This call should be in srcu read section since it access memory slots which > are srcu protected. You should test with RCU debug enabled. kvm_mips_gfn_to_pfn just maps to gfn_to_pfn. I don't see an instance where gfn_to_pfn is in a scru read section? > >> >> + >> +uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu) >> +{ >> + uint32_t inst; >> + struct mips_coproc *cop0 __unused = vcpu->arch.cop0; >> + int index; >> + ulong paddr, flags; >> + >> + if (KVM_GUEST_KSEGX((ulong) opc) < KVM_GUEST_KSEG0 || >> + KVM_GUEST_KSEGX((ulong) opc) == KVM_GUEST_KSEG23) { >> + local_irq_save(flags); >> + index = kvm_mips_host_tlb_lookup(vcpu, (ulong) opc); >> + if (index >= 0) { >> + inst = *(opc); > Here and in some more places below you access __user memory. Shouldn't you > use get_user() to access it? What prevents the kernel crash by access fault here > if userspace remaps the memory to be non-readable? Hmm, may be it uses > guest translation here so it cannot happen, but still, sparse will not > be happy and kvm_mips_translate_guest_kseg0_to_hpa() case below uses > host translation anyway. > Actually, I don't need the __user declaration in most cases, since KVM/MIPS handles mapping the page (if needed) and does not rely on the usual kernel mechanisms. From sanjayl@kymasys.com Fri Feb 15 19:22:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 19:22:23 +0100 (CET) Received: from kymasys.com ([64.62.140.43]:38526 "HELO kymasys.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S6827653Ab3BOSWX0CHZe (ORCPT ); Fri, 15 Feb 2013 19:22:23 +0100 Received: from ::ffff:173.33.185.184 ([173.33.185.184]) by kymasys.com for ; Fri, 15 Feb 2013 10:22:13 -0800 Subject: Re: [PATCH v2 09/18] KVM/MIPS32: COP0 accesses profiling. Mime-Version: 1.0 (Apple Message framework v1283) Content-Type: text/plain; charset=us-ascii From: Sanjay Lal In-Reply-To: <20130206131715.GB7837@redhat.com> Date: Fri, 15 Feb 2013 13:22:15 -0500 Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Content-Transfer-Encoding: 7bit Message-Id: <88677E83-88FD-4AD2-88BD-09FF6BA68F63@kymasys.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-10-git-send-email-sanjayl@kymasys.com> <20130206131715.GB7837@redhat.com> To: Gleb Natapov X-Mailer: Apple Mail (2.1283) X-archive-position: 35775 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sanjayl@kymasys.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 831 Lines: 32 On Feb 6, 2013, at 8:17 AM, Gleb Natapov wrote: > On Wed, Nov 21, 2012 at 06:34:07PM -0800, Sanjay Lal wrote: >> >> +int kvm_mips_dump_stats(struct kvm_vcpu *vcpu) >> +{ >> + int i, j __unused; >> +#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS >> + printk("\nKVM VCPU[%d] COP0 Access Profile:\n", vcpu->vcpu_id); >> + for (i = 0; i < N_MIPS_COPROC_REGS; i++) { >> + for (j = 0; j < N_MIPS_COPROC_SEL; j++) { >> + if (vcpu->arch.cop0->stat[i][j]) >> + printk("%s[%d]: %lu\n", kvm_cop0_str[i], j, >> + vcpu->arch.cop0->stat[i][j]); >> + } >> + } >> +#endif >> + >> + return 0; >> +} > You need to use ftrace event for that. Much more flexible with perf > integration and no need to recompile to enabled/disable. > > -- > Gleb. Agreed, I'll start using trace for keeping track of COP0 accesses. Regards Sanjay From gleb@redhat.com Fri Feb 15 19:42:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 19:42:05 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:37251 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827660Ab3BOSmEq0bf8 (ORCPT ); Fri, 15 Feb 2013 19:42:04 +0100 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r1FIg1eN029458 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 15 Feb 2013 13:42:01 -0500 Received: from dhcp-1-237.tlv.redhat.com (dhcp-4-26.tlv.redhat.com [10.35.4.26]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id r1FIfx3A024722; Fri, 15 Feb 2013 13:42:00 -0500 Received: by dhcp-1-237.tlv.redhat.com (Postfix, from userid 13519) id 58B8D18D479; Fri, 15 Feb 2013 20:41:59 +0200 (IST) Date: Fri, 15 Feb 2013 20:41:59 +0200 From: Gleb Natapov To: Sanjay Lal Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH v2 07/18] KVM/MIPS32: MMU/TLB operations for the Guest. Message-ID: <20130215184159.GA16755@redhat.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-8-git-send-email-sanjayl@kymasys.com> <20130206120820.GN23213@redhat.com> <69F3ED2A-A9B3-4046-9B40-98125ED5A8FB@kymasys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <69F3ED2A-A9B3-4046-9B40-98125ED5A8FB@kymasys.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-archive-position: 35776 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gleb@redhat.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2434 Lines: 57 On Fri, Feb 15, 2013 at 01:19:29PM -0500, Sanjay Lal wrote: > > On Feb 6, 2013, at 7:08 AM, Gleb Natapov wrote: > > >> > >> +static void kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) > >> +{ > >> + pfn_t pfn; > >> + > >> + if (kvm->arch.guest_pmap[gfn] != KVM_INVALID_PAGE) > >> + return; > >> + > >> + pfn =kvm_mips_gfn_to_pfn(kvm, gfn); > > This call should be in srcu read section since it access memory slots which > > are srcu protected. You should test with RCU debug enabled. > > kvm_mips_gfn_to_pfn just maps to gfn_to_pfn. I don't see an instance where gfn_to_pfn is in a scru read section? > Where are you looking? On x86 if vcpu is not in a guest mode it is in srcu read section. The lock is taken immediately after exit and released before entry. This is because x86 access memory slots a lot. Other arches, that do not access memory slots as much, take the lock around each individual access. As far as I see this is the only place in MIPS kvm where this is needed. > > > >> > >> + > >> +uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu) > >> +{ > >> + uint32_t inst; > >> + struct mips_coproc *cop0 __unused = vcpu->arch.cop0; > >> + int index; > >> + ulong paddr, flags; > >> + > >> + if (KVM_GUEST_KSEGX((ulong) opc) < KVM_GUEST_KSEG0 || > >> + KVM_GUEST_KSEGX((ulong) opc) == KVM_GUEST_KSEG23) { > >> + local_irq_save(flags); > >> + index = kvm_mips_host_tlb_lookup(vcpu, (ulong) opc); > >> + if (index >= 0) { > >> + inst = *(opc); > > Here and in some more places below you access __user memory. Shouldn't you > > use get_user() to access it? What prevents the kernel crash by access fault here > > if userspace remaps the memory to be non-readable? Hmm, may be it uses > > guest translation here so it cannot happen, but still, sparse will not > > be happy and kvm_mips_translate_guest_kseg0_to_hpa() case below uses > > host translation anyway. > > > Actually, I don't need the __user declaration in most cases, since KVM/MIPS handles mapping the page (if needed) and does not rely on the usual kernel mechanisms. Yes I see that you check/populate tlb for non KVM_GUEST_KSEG0 access, for kvm_mips_translate_guest_kseg0_to_hpa() you do not, but now I notice that you are not using the address directly but uses CKSEG0ADDR() on it, which, as far as I can tell, gives you kernel mapping for the page, correct? Why this is better than using get_user()? To save tlb entries? -- Gleb. From juhosg@openwrt.org Fri Feb 15 20:52:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 20:52:07 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:55081 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827653Ab3BOTwGhmL1H (ORCPT ); Fri, 15 Feb 2013 20:52:06 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ah7X7Zp8aUbG; Fri, 15 Feb 2013 20:51:55 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 52F682801AE; Fri, 15 Feb 2013 20:51:54 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos Subject: [PATCH] MIPS: ath79: fix WMAC IRQ resource assignment Date: Fri, 15 Feb 2013 20:51:57 +0100 Message-Id: <1360957917-19196-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35777 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1001 Lines: 32 The '.start' field of the IRQ resource assigned twice in ar934x_wmac_setup(). The second assignment must set the '.end' field. Fix it. Signed-off-by: Gabor Juhos --- Note: This is a fix for the existing code. The modified version of the QCA955X specific patch will come later. -Gabor --- arch/mips/ath79/dev-wmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index 4f6c4e3..d71d745 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -107,7 +107,7 @@ static void ar934x_wmac_setup(void) ath79_wmac_resources[0].start = AR934X_WMAC_BASE; ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); - ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); if (t & AR934X_BOOTSTRAP_REF_CLK_40) -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 20:54:07 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 20:54:08 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:55371 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827653Ab3BOTyHwjMhE (ORCPT ); Fri, 15 Feb 2013 20:54:07 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3W8qwxor1pwT; Fri, 15 Feb 2013 20:53:57 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 6832A2801AE; Fri, 15 Feb 2013 20:53:55 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH v2 04/11] MIPS: ath79: add IRQ handling code for the QCA955X SoCs Date: Fri, 15 Feb 2013 20:53:47 +0100 Message-Id: <1360958027-19399-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35778 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7227 Lines: 248 The IRQ routing in the QCA955x SoCs is slightly different from the routing implemented in the already supported SoCs. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- v2: fix typos --- arch/mips/ath79/irq.c | 110 ++++++++++++++++++++++-- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++++++ arch/mips/include/asm/mach-ath79/irq.h | 6 +- 3 files changed, 140 insertions(+), 8 deletions(-) diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index df88d49..9c0e176 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -103,7 +103,10 @@ static void __init ath79_misc_irq_init(void) if (soc_is_ar71xx() || soc_is_ar913x()) ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; - else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) + else if (soc_is_ar724x() || + soc_is_ar933x() || + soc_is_ar934x() || + soc_is_qca955x()) ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; else BUG(); @@ -150,6 +153,88 @@ static void ar934x_ip2_irq_init(void) irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); } +static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) +{ + u32 status; + + disable_irq_nosync(irq); + + status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); + status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; + + if (status == 0) { + spurious_interrupt(); + goto enable; + } + + if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP2_IRQ(0)); + } + + if (status & QCA955X_EXT_INT_WMAC_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP2_IRQ(1)); + } + +enable: + enable_irq(irq); +} + +static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc) +{ + u32 status; + + disable_irq_nosync(irq); + + status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); + status &= QCA955X_EXT_INT_PCIE_RC2_ALL | + QCA955X_EXT_INT_USB1 | + QCA955X_EXT_INT_USB2; + + if (status == 0) { + spurious_interrupt(); + goto enable; + } + + if (status & QCA955X_EXT_INT_USB1) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(0)); + } + + if (status & QCA955X_EXT_INT_USB2) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(1)); + } + + if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(2)); + } + +enable: + enable_irq(irq); +} + +static void qca955x_irq_init(void) +{ + int i; + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &dummy_irq_chip, + handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); + + for (i = ATH79_IP3_IRQ_BASE; + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &dummy_irq_chip, + handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); +} + asmlinkage void plat_irq_dispatch(void) { unsigned long pending; @@ -185,6 +270,17 @@ asmlinkage void plat_irq_dispatch(void) * Issue a flush in the handlers to ensure that the driver sees * the update. */ + +static void ath79_default_ip2_handler(void) +{ + do_IRQ(ATH79_CPU_IRQ(2)); +} + +static void ath79_default_ip3_handler(void) +{ + do_IRQ(ATH79_CPU_IRQ(3)); +} + static void ar71xx_ip2_handler(void) { ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); @@ -209,11 +305,6 @@ static void ar933x_ip2_handler(void) do_IRQ(ATH79_CPU_IRQ(2)); } -static void ar934x_ip2_handler(void) -{ - do_IRQ(ATH79_CPU_IRQ(2)); -} - static void ar71xx_ip3_handler(void) { ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); @@ -259,8 +350,11 @@ void __init arch_init_irq(void) ath79_ip2_handler = ar933x_ip2_handler; ath79_ip3_handler = ar933x_ip3_handler; } else if (soc_is_ar934x()) { - ath79_ip2_handler = ar934x_ip2_handler; + ath79_ip2_handler = ath79_default_ip2_handler; ath79_ip3_handler = ar934x_ip3_handler; + } else if (soc_is_qca955x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ath79_default_ip3_handler; } else { BUG(); } @@ -271,4 +365,6 @@ void __init arch_init_irq(void) if (soc_is_ar934x()) ar934x_ip2_irq_init(); + else if (soc_is_qca955x()) + qca955x_irq_init(); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 7b00e12..8782d8b 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -300,6 +300,7 @@ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) @@ -398,6 +399,37 @@ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ AR934X_PCIE_WMAC_INT_PCIE_RC3) +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + #define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_AR71XX 0x00a0 #define REV_ID_MAJOR_AR913X 0x00b0 diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 23e2bba..5c9ca76 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -10,7 +10,7 @@ #define __ASM_MACH_ATH79_IRQ_H #define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 48 +#define NR_IRQS 51 #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) @@ -26,6 +26,10 @@ #define ATH79_IP2_IRQ_COUNT 2 #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) +#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT) +#define ATH79_IP3_IRQ_COUNT 3 +#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) + #include_next #endif /* __ASM_MACH_ATH79_IRQ_H */ -- 1.7.10 From juhosg@openwrt.org Fri Feb 15 20:54:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 20:54:46 +0100 (CET) Received: from arrakis.dune.hu ([78.24.191.176]:55425 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827653Ab3BOTyprJSjP (ORCPT ); Fri, 15 Feb 2013 20:54:45 +0100 Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3VcDa7HpeQ7A; Fri, 15 Feb 2013 20:54:34 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by arrakis.dune.hu (Postfix) with ESMTPSA id 586CF280213; Fri, 15 Feb 2013 20:54:32 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: John Crispin , linux-mips , Gabor Juhos , "Rodriguez, Luis" , "Giori, Kathy" , QCA Linux Team Subject: [PATCH v2 08/11] MIPS: ath79: add WMAC registration code for the QCA955X SoCs Date: Fri, 15 Feb 2013 20:54:33 +0100 Message-Id: <1360958073-19474-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.10 X-archive-position: 35779 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2526 Lines: 83 The SoC has a built-in wireless MAC. Register a platform device for that to make it usable with the ath9k driver. Cc: Rodriguez, Luis Cc: Giori, Kathy Cc: QCA Linux Team Signed-off-by: Gabor Juhos --- v2: fix IRQ resource assignment --- arch/mips/ath79/Kconfig | 2 +- arch/mips/ath79/dev-wmac.c | 20 ++++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index cffdc8e..77926e3 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -108,7 +108,7 @@ config ATH79_DEV_USB def_bool n config ATH79_DEV_WMAC - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) def_bool n endif diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index d71d745..da190b1 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void) ath79_wmac_data.is_clk_25mhz = true; } +static void qca955x_wmac_setup(void) +{ + u32 t; + + ath79_wmac_device.name = "qca955x_wmac"; + + ath79_wmac_resources[0].start = QCA955X_WMAC_BASE; + ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1; + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); + + t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); + if (t & QCA955X_BOOTSTRAP_REF_CLK_40) + ath79_wmac_data.is_clk_25mhz = false; + else + ath79_wmac_data.is_clk_25mhz = true; +} + void __init ath79_register_wmac(u8 *cal_data) { if (soc_is_ar913x()) @@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_data) ar933x_wmac_setup(); else if (soc_is_ar934x()) ar934x_wmac_setup(); + else if (soc_is_qca955x()) + qca955x_wmac_setup(); else BUG(); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index bf50ddf..4728212 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -94,6 +94,9 @@ #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) #define AR934X_SRIF_SIZE 0x1000 +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 + /* * DDR_CTRL block */ -- 1.7.10 From hauke@hauke-m.de Fri Feb 15 21:20:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Feb 2013 21:20:51 +0100 (CET) Received: from server19320154104.serverpool.info ([193.201.54.104]:52338 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827665Ab3BOUUuzJ54k (ORCPT ); Fri, 15 Feb 2013 21:20:50 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id A40228F60; Fri, 15 Feb 2013 21:20:49 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4QCMKBSUVLgW; Fri, 15 Feb 2013 21:20:41 +0100 (CET) Received: from [IPv6:2001:470:1f0b:447:6453:c44e:14a5:63c1] (unknown [IPv6:2001:470:1f0b:447:6453:c44e:14a5:63c1]) by hauke-m.de (Postfix) with ESMTPSA id 013BC85EA; Fri, 15 Feb 2013 21:20:40 +0100 (CET) Message-ID: <511E9896.9010502@hauke-m.de> Date: Fri, 15 Feb 2013 21:20:38 +0100 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: Hauke Mehrtens CC: john@phrozen.org, ralf@linux-mips.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org Subject: Re: [PATCH 2/2] ssb: add gpio_to_irq again References: <1355275031-19297-1-git-send-email-hauke@hauke-m.de> <1355275031-19297-2-git-send-email-hauke@hauke-m.de> In-Reply-To: <1355275031-19297-2-git-send-email-hauke@hauke-m.de> X-Enigmail-Version: 1.4.6 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35780 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 671 Lines: 17 On 12/12/2012 02:17 AM, Hauke Mehrtens wrote: > The old code had support for gpio_to_irq, but the new code did not > provide this function, but returned -ENXIO all the time. This patch > adds the missing function. > > arch/mips/bcm47xx/wgt634u.c calls gpio_to_irq() and got the correct irq > number with the old gpio handling code. With this patch the code in > wgt634u.c should work again. I do not have a wgt634u to test this. > > Signed-off-by: Hauke Mehrtens Please drop these two patches They will cause merge problems. After I talked to blogic and after that I send these patches to John Linville for inclusion into the wireless tree. Hauke From sanjayl@kymasys.com Sat Feb 16 16:57:32 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Feb 2013 16:57:34 +0100 (CET) Received: from kymasys.com ([64.62.140.43]:54783 "HELO kymasys.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S6825751Ab3BPP5cgpDRy convert rfc822-to-8bit (ORCPT ); Sat, 16 Feb 2013 16:57:32 +0100 Received: from ::ffff:173.33.185.184 ([173.33.185.184]) by kymasys.com for ; Sat, 16 Feb 2013 07:57:22 -0800 Subject: Re: [PATCH v2 07/18] KVM/MIPS32: MMU/TLB operations for the Guest. Mime-Version: 1.0 (Apple Message framework v1283) Content-Type: text/plain; charset=us-ascii From: Sanjay Lal In-Reply-To: <20130215184159.GA16755@redhat.com> Date: Sat, 16 Feb 2013 10:57:22 -0500 Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Content-Transfer-Encoding: 8BIT Message-Id: <15B0FF73-7030-4861-B7BD-834F12CEF5B1@kymasys.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-8-git-send-email-sanjayl@kymasys.com> <20130206120820.GN23213@redhat.com> <69F3ED2A-A9B3-4046-9B40-98125ED5A8FB@kymasys.com> <20130215184159.GA16755@redhat.com> To: Gleb Natapov X-Mailer: Apple Mail (2.1283) X-archive-position: 35781 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sanjayl@kymasys.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2769 Lines: 67 On Feb 15, 2013, at 1:41 PM, Gleb Natapov wrote: > On Fri, Feb 15, 2013 at 01:19:29PM -0500, Sanjay Lal wrote: >> >> On Feb 6, 2013, at 7:08 AM, Gleb Natapov wrote: >> >>>> >>>> +static void kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) >>>> +{ >>>> + pfn_t pfn; >>>> + >>>> + if (kvm->arch.guest_pmap[gfn] != KVM_INVALID_PAGE) >>>> + return; >>>> + >>>> + pfn =kvm_mips_gfn_to_pfn(kvm, gfn); >>> This call should be in srcu read section since it access memory slots which >>> are srcu protected. You should test with RCU debug enabled. >> >> kvm_mips_gfn_to_pfn just maps to gfn_to_pfn. I don't see an instance where gfn_to_pfn is in a scru read section? >> > Where are you looking? On x86 if vcpu is not in a guest mode it is in > srcu read section. The lock is taken immediately after exit and released > before entry. This is because x86 access memory slots a lot. Other > arches, that do not access memory slots as much, take the lock around > each individual access. As far as I see this is the only place in MIPS > kvm where this is needed. Ah I see what you mean. I'll wrap the access in a scru read section. > >>> >>>> >>>> + >>>> +uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu) >>>> +{ >>>> + uint32_t inst; >>>> + struct mips_coproc *cop0 __unused = vcpu->arch.cop0; >>>> + int index; >>>> + ulong paddr, flags; >>>> + >>>> + if (KVM_GUEST_KSEGX((ulong) opc) < KVM_GUEST_KSEG0 || >>>> + KVM_GUEST_KSEGX((ulong) opc) == KVM_GUEST_KSEG23) { >>>> + local_irq_save(flags); >>>> + index = kvm_mips_host_tlb_lookup(vcpu, (ulong) opc); >>>> + if (index >= 0) { >>>> + inst = *(opc); >>> Here and in some more places below you access __user memory. Shouldn't you >>> use get_user() to access it? What prevents the kernel crash by access fault here >>> if userspace remaps the memory to be non-readable? Hmm, may be it uses >>> guest translation here so it cannot happen, but still, sparse will not >>> be happy and kvm_mips_translate_guest_kseg0_to_hpa() case below uses >>> host translation anyway. >>> >> Actually, I don't need the __user declaration in most cases, since KVM/MIPS handles mapping the page (if needed) and does not rely on the usual kernel mechanisms. > Yes I see that you check/populate tlb for non KVM_GUEST_KSEG0 access, > for kvm_mips_translate_guest_kseg0_to_hpa() you do not, but now I notice > that you are not using the address directly but uses CKSEG0ADDR() on it, > which, as far as I can tell, gives you kernel mapping for the page, > correct? Why this is better than using get_user()? To save tlb entries? > Couple of reasons, KVM/MIPS uses its own TLB handlers while the guest is running, so get_user is not an option, and (2) it does save on TLBs when accessing the guest memory via KSEG0. From gleb@redhat.com Sat Feb 16 17:21:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Feb 2013 17:21:50 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:53623 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825751Ab3BPQVuCH5km (ORCPT ); Sat, 16 Feb 2013 17:21:50 +0100 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r1GGLkdP027271 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Sat, 16 Feb 2013 11:21:46 -0500 Received: from dhcp-1-237.tlv.redhat.com (dhcp-4-26.tlv.redhat.com [10.35.4.26]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id r1GGLjiB031581; Sat, 16 Feb 2013 11:21:46 -0500 Received: by dhcp-1-237.tlv.redhat.com (Postfix, from userid 13519) id 5ABA318D479; Sat, 16 Feb 2013 18:21:45 +0200 (IST) Date: Sat, 16 Feb 2013 18:21:45 +0200 From: Gleb Natapov To: Sanjay Lal Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH v2 07/18] KVM/MIPS32: MMU/TLB operations for the Guest. Message-ID: <20130216162145.GA15961@redhat.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-8-git-send-email-sanjayl@kymasys.com> <20130206120820.GN23213@redhat.com> <69F3ED2A-A9B3-4046-9B40-98125ED5A8FB@kymasys.com> <20130215184159.GA16755@redhat.com> <15B0FF73-7030-4861-B7BD-834F12CEF5B1@kymasys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <15B0FF73-7030-4861-B7BD-834F12CEF5B1@kymasys.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-archive-position: 35782 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gleb@redhat.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1407 Lines: 38 On Sat, Feb 16, 2013 at 10:57:22AM -0500, Sanjay Lal wrote: > > On Feb 15, 2013, at 1:41 PM, Gleb Natapov wrote: > > > On Fri, Feb 15, 2013 at 01:19:29PM -0500, Sanjay Lal wrote: > >> > >> On Feb 6, 2013, at 7:08 AM, Gleb Natapov wrote: > >> > >>>> > >>>> +static void kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) > >>>> +{ > >>>> + pfn_t pfn; > >>>> + > >>>> + if (kvm->arch.guest_pmap[gfn] != KVM_INVALID_PAGE) > >>>> + return; > >>>> + > >>>> + pfn =kvm_mips_gfn_to_pfn(kvm, gfn); > >>> This call should be in srcu read section since it access memory slots which > >>> are srcu protected. You should test with RCU debug enabled. > >> > >> kvm_mips_gfn_to_pfn just maps to gfn_to_pfn. I don't see an instance where gfn_to_pfn is in a scru read section? > >> > > Where are you looking? On x86 if vcpu is not in a guest mode it is in > > srcu read section. The lock is taken immediately after exit and released > > before entry. This is because x86 access memory slots a lot. Other > > arches, that do not access memory slots as much, take the lock around > > each individual access. As far as I see this is the only place in MIPS > > kvm where this is needed. > > Ah I see what you mean. I'll wrap the access in a scru read section. > Thanks. I think there is userspace triggerable panic() in kvm_mips_map_page(). See my original reply. Just making sure you haven't missed it :) -- Gleb. From lars@metafoo.de Sun Feb 17 13:26:47 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Feb 2013 13:27:35 +0100 (CET) Received: from smtp-out-015.synserver.de ([212.40.185.15]:1067 "EHLO smtp-out-012.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6817667Ab3BQM0rd7dSo (ORCPT ); Sun, 17 Feb 2013 13:26:47 +0100 Received: (qmail 16600 invoked by uid 0); 17 Feb 2013 12:26:43 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 16552 Received: from ppp-188-174-132-198.dynamic.mnet-online.de (HELO lars-laptop.fritz.box) [188.174.132.198] by 217.119.54.81 with SMTP; 17 Feb 2013 12:26:42 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: "Steven J. Hill" , Kristian Kielhofner , linux-mips@linux-mips.org, Lars-Peter Clausen Subject: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME Date: Sun, 17 Feb 2013 13:28:22 +0100 Message-Id: <1361104102-13294-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.7.2.5 X-archive-position: 35783 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1834 Lines: 62 Setting the LED_CORE_SUSPENDRESUME flag causes the LED driver core to call led_classdev_suspend/led_classdev_resume during suspend/resume. Since this is exactly what the driver's custom suspend/resume callbacks do we can replace them by setting the LED_CORE_SUSPENDRESUME flag. Signed-off-by: Lars-Peter Clausen --- arch/mips/mti-sead3/leds-sead3.c | 24 ++---------------------- 1 files changed, 2 insertions(+), 22 deletions(-) diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c index 322148c..0a168c9 100644 --- a/arch/mips/mti-sead3/leds-sead3.c +++ b/arch/mips/mti-sead3/leds-sead3.c @@ -34,33 +34,15 @@ static void sead3_fled_set(struct led_classdev *led_cdev, static struct led_classdev sead3_pled = { .name = "sead3::pled", .brightness_set = sead3_pled_set, + .flags = LED_CORE_SUSPENDRESUME, }; static struct led_classdev sead3_fled = { .name = "sead3::fled", .brightness_set = sead3_fled_set, + .flags = LED_CORE_SUSPENDRESUME, }; -#ifdef CONFIG_PM -static int sead3_led_suspend(struct platform_device *dev, - pm_message_t state) -{ - led_classdev_suspend(&sead3_pled); - led_classdev_suspend(&sead3_fled); - return 0; -} - -static int sead3_led_resume(struct platform_device *dev) -{ - led_classdev_resume(&sead3_pled); - led_classdev_resume(&sead3_fled); - return 0; -} -#else -#define sead3_led_suspend NULL -#define sead3_led_resume NULL -#endif - static int sead3_led_probe(struct platform_device *pdev) { int ret; @@ -86,8 +68,6 @@ static int sead3_led_remove(struct platform_device *pdev) static struct platform_driver sead3_led_driver = { .probe = sead3_led_probe, .remove = sead3_led_remove, - .suspend = sead3_led_suspend, - .resume = sead3_led_resume, .driver = { .name = DRVNAME, .owner = THIS_MODULE, -- 1.7.2.5 From gleb@redhat.com Mon Feb 18 10:44:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Feb 2013 10:44:58 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:65502 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816354Ab3BRJo4drKMo (ORCPT ); Mon, 18 Feb 2013 10:44:56 +0100 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r1I9iqE6021110 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 18 Feb 2013 04:44:52 -0500 Received: from dhcp-1-237.tlv.redhat.com (dhcp-4-26.tlv.redhat.com [10.35.4.26]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id r1I9ipTK005431; Mon, 18 Feb 2013 04:44:51 -0500 Received: by dhcp-1-237.tlv.redhat.com (Postfix, from userid 13519) id C2CE818D479; Mon, 18 Feb 2013 11:44:50 +0200 (IST) Date: Mon, 18 Feb 2013 11:44:50 +0200 From: Gleb Natapov To: Sanjay Lal Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH v2 11/18] KVM/MIPS32: Routines to handle specific traps/exceptions while executing the guest. Message-ID: <20130218094450.GA9817@redhat.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-12-git-send-email-sanjayl@kymasys.com> <20130206132018.GC7837@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-archive-position: 35784 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gleb@redhat.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1435 Lines: 32 On Fri, Feb 15, 2013 at 11:10:46AM -0500, Sanjay Lal wrote: > > On Feb 6, 2013, at 8:20 AM, Gleb Natapov wrote: > > > On Wed, Nov 21, 2012 at 06:34:09PM -0800, Sanjay Lal wrote: > >> +static gpa_t kvm_trap_emul_gva_to_gpa_cb(gva_t gva) > >> +{ > >> + gpa_t gpa; > >> + uint32_t kseg = KSEGX(gva); > >> + > >> + if ((kseg == CKSEG0) || (kseg == CKSEG1)) > > You seems to be using KVM_GUEST_KSEGX variants on gva in all other > > places. Why not here? > > This function is invoked to handle 2 scenarios: > (1) Parse the boot code config tables setup by QEMU's Malta emulation. The pointers in the tables are actual KSEG0 addresses (unmapped, cached) and not Guest KSEG0 addresses. > Where is it called for that purpose? The only place where gva_to_gpa callback is called is in kvm/kvm_mips_emul.c:kvm_mips_emulate_(store|load) > (2) Handle I/O accesses by the guest. On MIPS platforms, I/O device registers are mapped into the KSEG1 address space (unmapped, uncached). Again like (1) these are actual KSEG1 addresses, which cause an exception and are passed onto QEMU for I/O emulation. > So guest KSEG1 registers is mapped to 0xA0000000-0xBFFFFFFF ranges just like on a host? Can you give corresponding segment names to those ranges Guest User address space: 0x00000000 -> 0x40000000 (useg?) Guest Kernel Unmapped: 0x40000000 -> 0x60000000 (kseg0?) Guest Kernel Mapped: 0x60000000 -> 0x80000000 (?) -- Gleb. From aaro.koskinen@iki.fi Tue Feb 19 01:01:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Feb 2013 01:01:25 +0100 (CET) Received: from filtteri2.pp.htv.fi ([213.243.153.185]:47648 "EHLO filtteri2.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823899Ab3BSABXDreTr (ORCPT ); Tue, 19 Feb 2013 01:01:23 +0100 Received: from localhost (localhost [127.0.0.1]) by filtteri2.pp.htv.fi (Postfix) with ESMTP id 33A5819BA98; Tue, 19 Feb 2013 02:01:21 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp4.welho.com ([213.243.153.38]) by localhost (filtteri2.pp.htv.fi [213.243.153.185]) (amavisd-new, port 10024) with ESMTP id 5HG2tH16qkPZ; Tue, 19 Feb 2013 02:01:20 +0200 (EET) Received: from blackmetal.pp.htv.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp4.welho.com (Postfix) with ESMTP id 901185BC011; Tue, 19 Feb 2013 02:01:20 +0200 (EET) From: Aaro Koskinen To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Aaro Koskinen Subject: [PATCH] MIPS: loongson: fix random early boot hang Date: Tue, 19 Feb 2013 02:00:39 +0200 Message-Id: <1361232039-12555-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.7.10.4 X-archive-position: 35785 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3540 Lines: 76 Some Loongson boards (e.g. Lemote FuLoong mini-PC) use ISA/southbridge device (CS5536 general purpose timer) for the timer interrupt. It starts running early and is already enabled during the PCI configuration, during which there is a small window in pci_read_base() when the register access is temporarily disabled. If the timer interrupts at this point, the system will hang. Fix this by adding a fixup that keeps the register access always enabled. The hang the patch fixes usually looks like this: [ 0.844000] pci 0000:00:0e.0: [1022:2090] type 00 class 0x060100 [ 0.848000] pci 0000:00:0e.0: reg 10: [io 0xb410-0xb417] [ 0.852000] pci 0000:00:0e.0: reg 14: [io 0xb000-0xb0ff] [ 0.856000] pci 0000:00:0e.0: reg 18: [io 0xb380-0xb3bf] [ 28.140000] BUG: soft lockup - CPU#0 stuck for 23s! [swapper:1] [ 28.140000] Modules linked in: [ 28.140000] irq event stamp: 37965 [ 28.140000] hardirqs last enabled at (37964): [] restore_partial+0x6c/0x13c [ 28.140000] hardirqs last disabled at (37965): [] handle_int+0x144/0x15c [ 28.140000] softirqs last enabled at (24316): [] __do_softirq+0x1cc/0x258 [ 28.140000] softirqs last disabled at (24327): [] do_softirq+0xc8/0xd0 [ 28.140000] Cpu 0 [ 28.140000] $ 0 : 0000000000000000 00000000140044e1 980000009f090000 0000000000000001 [ 28.140000] $ 4 : 980000009f090000 0000000000000000 0000000000000100 03b7fff87fbde011 [ 28.140000] $ 8 : ffffffff812b1928 000000000001e000 043ffff87fbde011 fffffff87fbde011 [ 28.140000] $12 : 000000000000000e ffffffff807a0000 0000000000000698 0000000000000000 [ 28.140000] $16 : 0000000000000002 ffffffff81055e20 ffffffff80786810 0000000000000000 [ 28.140000] $20 : 000000000000000a ffffffff807bc244 ffffffff807e6350 ffffffff80770000 [ 28.140000] $24 : 0000000000000d80 00000000fffedbe0 [ 28.140000] $28 : 980000009f07c000 980000009f07fa10 ffffffff81050000 ffffffff802380f8 [ 28.140000] Hi : 0000000000d0fc00 [ 28.140000] Lo : 0000000000f82b40 [ 28.140000] epc : ffffffff8023810c __do_softirq+0xe4/0x258 [ 28.140000] Not tainted [ 28.140000] ra : ffffffff802380f8 __do_softirq+0xd0/0x258 [ 28.140000] Status: 140044e3 KX SX UX KERNEL EXL IE [ 28.140000] Cause : 10008400 [ 28.140000] PrId : 00006303 (ICT Loongson-2) Signed-off-by: Aaro Koskinen --- arch/mips/loongson/common/cs5536/cs5536_isa.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c index 4d9f65a..7b31ea7 100644 --- a/arch/mips/loongson/common/cs5536/cs5536_isa.c +++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c @@ -13,6 +13,7 @@ * option) any later version. */ +#include #include #include @@ -314,3 +315,16 @@ u32 pci_isa_read_reg(int reg) return conf_data; } + +/* + * The mfgpt timer interrupt is running early, so we must keep the south bridge + * mmio always enabled. Otherwise we may race with the PCI configuration which + * may temporarily disable it. When that happens and the timer interrupt fires, + * we are not able to clear it and the system will hang. + */ +static void cs5536_isa_mmio_always_on(struct pci_dev *dev) +{ + dev->mmio_always_on = 1; +} +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, + PCI_CLASS_BRIDGE_ISA, 8, cs5536_isa_mmio_always_on); -- 1.7.10.4 From sanjayl@kymasys.com Tue Feb 19 03:31:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Feb 2013 03:31:30 +0100 (CET) Received: from kymasys.com ([64.62.140.43]:60280 "HELO kymasys.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S6824790Ab3BSCb3kHiM6 convert rfc822-to-8bit (ORCPT ); Tue, 19 Feb 2013 03:31:29 +0100 Received: from ::ffff:75.40.23.192 ([75.40.23.192]) by kymasys.com for ; Mon, 18 Feb 2013 18:31:17 -0800 Subject: Re: [PATCH v2 11/18] KVM/MIPS32: Routines to handle specific traps/exceptions while executing the guest. Mime-Version: 1.0 (Apple Message framework v1283) Content-Type: text/plain; charset=us-ascii From: Sanjay Lal In-Reply-To: <20130218094450.GA9817@redhat.com> Date: Mon, 18 Feb 2013 18:31:17 -0800 Cc: kvm@vger.kernel.org, linux-mips@linux-mips.org Content-Transfer-Encoding: 8BIT Message-Id: <47FBD60F-AF5B-48C7-BCCF-C26AC581E540@kymasys.com> References: <1353551656-23579-1-git-send-email-sanjayl@kymasys.com> <1353551656-23579-12-git-send-email-sanjayl@kymasys.com> <20130206132018.GC7837@redhat.com> <20130218094450.GA9817@redhat.com> To: Gleb Natapov X-Mailer: Apple Mail (2.1283) X-archive-position: 35786 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sanjayl@kymasys.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1798 Lines: 42 On Feb 18, 2013, at 1:44 AM, Gleb Natapov wrote: > On Fri, Feb 15, 2013 at 11:10:46AM -0500, Sanjay Lal wrote: >> >> On Feb 6, 2013, at 8:20 AM, Gleb Natapov wrote: >> >>> On Wed, Nov 21, 2012 at 06:34:09PM -0800, Sanjay Lal wrote: >>>> +static gpa_t kvm_trap_emul_gva_to_gpa_cb(gva_t gva) >>>> +{ >>>> + gpa_t gpa; >>>> + uint32_t kseg = KSEGX(gva); >>>> + >>>> + if ((kseg == CKSEG0) || (kseg == CKSEG1)) >>> You seems to be using KVM_GUEST_KSEGX variants on gva in all other >>> places. Why not here? >> >> This function is invoked to handle 2 scenarios: >> (1) Parse the boot code config tables setup by QEMU's Malta emulation. The pointers in the tables are actual KSEG0 addresses (unmapped, cached) and not Guest KSEG0 addresses. >> > Where is it called for that purpose? The only place where gva_to_gpa > callback is called is in kvm/kvm_mips_emul.c:kvm_mips_emulate_(store|load) Load/stores from/to KSEG1 generate the Address Error Load/Store exceptions. The handler calls kvm_mips_emul.c:kvm_mips_emulate_(store|load) which then call the gva_to_gpa callback. > >> (2) Handle I/O accesses by the guest. On MIPS platforms, I/O device registers are mapped into the KSEG1 address space (unmapped, uncached). Again like (1) these are actual KSEG1 addresses, which cause an exception and are passed onto QEMU for I/O emulation. >> > So guest KSEG1 registers is mapped to 0xA0000000-0xBFFFFFFF ranges just > like on a host? Can you give corresponding segment names to those ranges > > Guest User address space: 0x00000000 -> 0x40000000 (useg?) > Guest Kernel Unmapped: 0x40000000 -> 0x60000000 (kseg0?) > Guest Kernel Mapped: 0x60000000 -> 0x80000000 (?) > Yes, now that you mention it :-). I'll add a corresponding Guest Kernel KSEG1 segment name. Regards Sanjay From lig.fnst@cn.fujitsu.com Tue Feb 19 09:12:58 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Feb 2013 09:13:00 +0100 (CET) Received: from cn.fujitsu.com ([222.73.24.84]:13878 "EHLO song.cn.fujitsu.com" rhost-flags-OK-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S6823059Ab3BSIM6c6wi9 (ORCPT ); Tue, 19 Feb 2013 09:12:58 +0100 X-IronPort-AV: E=Sophos;i="4.84,693,1355068800"; d="scan'208";a="6729000" Received: from unknown (HELO tang.cn.fujitsu.com) ([10.167.250.3]) by song.cn.fujitsu.com with ESMTP; 19 Feb 2013 16:10:29 +0800 Received: from fnstmail02.fnst.cn.fujitsu.com (tang.cn.fujitsu.com [127.0.0.1]) by tang.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id r1J8Cllm009740; Tue, 19 Feb 2013 16:12:47 +0800 Received: from liguang.fnst.cn.fujitsu.com ([10.167.225.128]) by fnstmail02.fnst.cn.fujitsu.com (Lotus Domino Release 8.5.3) with ESMTP id 2013021916120874-239743 ; Tue, 19 Feb 2013 16:12:08 +0800 From: liguang To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: liguang Subject: [PATCH] mips: remove unecessary __linux__ check Date: Tue, 19 Feb 2013 16:12:51 +0800 Message-Id: <1361261571-1556-1-git-send-email-lig.fnst@cn.fujitsu.com> X-Mailer: git-send-email 1.7.2.5 X-MIMETrack: Itemize by SMTP Server on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/02/19 16:12:08, Serialize by Router on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/02/19 16:12:09, Serialize complete at 2013/02/19 16:12:09 X-archive-position: 35787 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lig.fnst@cn.fujitsu.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 953 Lines: 34 sgidefs.h has strict check for __linux__, it seems too harsh, as far as I test, 2 cross compiler for mips will not define it automatically, and exit build process with error "#error Use a Linux compiler or give up". remove it will not hurt, I think. Signed-off-by: liguang --- arch/mips/include/uapi/asm/sgidefs.h | 8 -------- 1 files changed, 0 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/uapi/asm/sgidefs.h b/arch/mips/include/uapi/asm/sgidefs.h index 876442f..5be81f8 100644 --- a/arch/mips/include/uapi/asm/sgidefs.h +++ b/arch/mips/include/uapi/asm/sgidefs.h @@ -11,14 +11,6 @@ #define __ASM_SGIDEFS_H /* - * Using a Linux compiler for building Linux seems logic but not to - * everybody. - */ -#ifndef __linux__ -#error Use a Linux compiler or give up. -#endif - -/* * Definitions for the ISA levels * * With the introduction of MIPS32 / MIPS64 instruction sets definitions -- 1.7.2.5 From ralf@linux-mips.org Tue Feb 19 11:04:30 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Feb 2013 11:04:34 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:57258 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6823113Ab3BSKEabhhIE (ORCPT ); Tue, 19 Feb 2013 11:04:30 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r1JA4R91027943; Tue, 19 Feb 2013 11:04:28 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r1JA4P51027935; Tue, 19 Feb 2013 11:04:25 +0100 Date: Tue, 19 Feb 2013 11:04:25 +0100 From: Ralf Baechle To: liguang Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: remove unecessary __linux__ check Message-ID: <20130219100425.GB5256@linux-mips.org> References: <1361261571-1556-1-git-send-email-lig.fnst@cn.fujitsu.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1361261571-1556-1-git-send-email-lig.fnst@cn.fujitsu.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35788 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 578 Lines: 15 On Tue, Feb 19, 2013 at 04:12:51PM +0800, liguang wrote: > sgidefs.h has strict check for __linux__, > it seems too harsh, as far as I test, 2 cross > compiler for mips will not define it automatically, > and exit build process with error > "#error Use a Linux compiler or give up". > remove it will not hurt, I think. My mailbox used to get flooded by people who attempted to build a kernel using something like a mips-elf, mips-sde-elf or even stranger targets. There are further differences than just the definition of __linux__ so I eventually applied this check. Ralf From john@phrozen.org Tue Feb 19 21:50:09 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Feb 2013 21:50:11 +0100 (CET) Received: from nbd.name ([46.4.11.11]:41853 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825899Ab3BSUuJL9hd9 (ORCPT ); Tue, 19 Feb 2013 21:50:09 +0100 Message-ID: <5123E45B.8060203@phrozen.org> Date: Tue, 19 Feb 2013 21:45:15 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7 MIME-Version: 1.0 To: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= CC: ralf@linux-mips.org, "David S. Miller" , linux-mips@linux-mips.org, Network Development , Hauke Mehrtens Subject: Re: Upcoming cross-tree build breakage on merge window References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-archive-position: 35789 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 915 Lines: 28 On 19/02/13 20:44, RafaÅ‚ MiÅ‚ecki wrote: > 2013/1/23 RafaÅ‚ MiÅ‚ecki: >> I've noticed possible build breakage when two trees get merged: >> net-next and linux-john (MIPS). >> >> This is about two following commits: >> http://git.kernel.org/?p=linux/kernel/git/davem/net-next.git;a=commit;h=dd4544f05469aaaeee891d7dc54d66430344321e >> http://git.linux-mips.org/?p=john/linux-john.git;a=commit;h=a008ca117bc85a9d66c47cd5ab18a6c332411919 >> >> The first one adds "bgmac" driver which uses asm/mach-bcm47xx/nvram.h >> and nvram_getenv. The second one renames them. >> >> Can you handle this in some clever way during merge window, please? >> >> The fix is trivial: >> 1) Use >> 2) Use bcm47xx_nvram_getenv > > Just a reminder. > Hi, Ralf told me he will pull the fix into his upstream-sfr.git today so that the upcoming linux-next should not build break due to this patch John From yong.zhang0@gmail.com Wed Feb 20 07:17:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Feb 2013 07:17:57 +0100 (CET) Received: from mail-bk0-f46.google.com ([209.85.214.46]:61443 "EHLO mail-bk0-f46.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827454Ab3BTGRzIZPkH (ORCPT ); Wed, 20 Feb 2013 07:17:55 +0100 Received: by mail-bk0-f46.google.com with SMTP id j5so3481077bkw.19 for ; Tue, 19 Feb 2013 22:17:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=nbm0gZCeSkLhw8gAiYRbblFBhUEtHW9Z98h8f04L03o=; b=IaFwuz8CQc4jVyn/8HctSDBc4Wjr+uo36m6dQ8n1bnRv+haLIq2hf/7eaiOCk5QRWm e3y9CcP7VrHF7PnQDzdGkCWUE82wWeTKlVozEvmu8RqUks146+xsv99Tyxn1KwpnU8SQ TTFy9RcYe/1GU0CgWfpXZkgwc+e8vzqdTIpPqmBoVUMYZZ98IqGvJC1UdTFGMZd2zglQ jC6vqcM5lVjBG3hE1dIWHdTMy4QIf+reSF7dwu3f+VGHL0t6qBEp3zoqhtIAtUUg80dm iHOnWsEQMuxBpKmCgS/g081+Hjp+G3IkCa4xJQIZoK/IrnqshrAx07Dl8AJfzxx8pWPn iiuQ== X-Received: by 10.205.127.135 with SMTP id ha7mr7633253bkc.140.1361341069628; Tue, 19 Feb 2013 22:17:49 -0800 (PST) Received: from localhost ([61.148.56.138]) by mx.google.com with ESMTPS id go8sm22899083bkc.20.2013.02.19.22.17.44 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 19 Feb 2013 22:17:49 -0800 (PST) From: Yong Zhang To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Ralf Baechle , David Daney Subject: [PATCH] MIPS: fix access_ok() Date: Wed, 20 Feb 2013 14:17:36 +0800 Message-Id: <1361341056-15287-1-git-send-email-yong.zhang0@gmail.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35790 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang0@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1606 Lines: 48 From: Yong Zhang Current access_ok() will fail even if the address range is valid when it reaches to the end of TASK_SIZE. For exampe: addr = 0xfffffffff0; size = 16; the real address range it want to access is 0xfffffffff0~0xfffffffff; but addr + size = 0x10000000000 which we will not and can't access. In current realization of access_ok(), the high bit will be 1 thus access_ok() indicates the operation is not allowed. The bug is found in old kerenl(before vdso is realized) in following typical call trace: sys_mount() copy_mount_options() exact_copy_from_user() When the parameter 'from' for exact_copy_from_user() residents in the last page of the task's virtual address, such as stack. But it's still in current kernel. Signed-off-by: Yong Zhang Cc: Ralf Baechle Cc: David Daney --- arch/mips/include/asm/uaccess.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index 3b92efe..55d4214 100644 --- a/arch/mips/include/asm/uaccess.h +++ b/arch/mips/include/asm/uaccess.h @@ -114,8 +114,12 @@ extern u64 __ua_limit; unsigned long __ok; \ \ __chk_user_ptr(addr); \ - __ok = (signed long)(__mask & (__addr | (__addr + __size) | \ - __ua_size(__size))); \ + if (likely(size)) \ + __ok = (signed long)(__mask & (__addr | \ + (__addr + __size - 1) | \ + __ua_size(__size))); \ + else \ + __ok = 0; \ __ok == 0; \ }) -- 1.7.9.5 From Steven.Hill@imgtec.com Wed Feb 20 21:07:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Feb 2013 21:07:48 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:50515 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827511Ab3BTUHmsizz3 (ORCPT ); Wed, 20 Feb 2013 21:07:42 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1U8Fwy-0001Vi-TS; Wed, 20 Feb 2013 14:07:32 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org, mcdonald.shane@gmail.com Subject: [PATCH v5] MIPS: Add option to disable software I/O coherency. Date: Wed, 20 Feb 2013 14:07:20 -0600 Message-Id: <1361390840-31415-1-git-send-email-Steven.Hill@imgtec.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35792 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 7257 Lines: 241 From: "Steven J. Hill" Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill --- arch/mips/include/asm/dma-mapping.h | 3 + arch/mips/include/asm/mach-generic/dma-coherence.h | 2 +- arch/mips/mm/c-r4k.c | 33 ++++++--- arch/mips/mm/dma-default.c | 6 +- arch/mips/mti-malta/malta-setup.c | 71 ++++++++++++++++++++ arch/mips/mti-sead3/sead3-setup.c | 4 +- 6 files changed, 105 insertions(+), 14 deletions(-) diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 006b43e..206243d 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -5,6 +5,9 @@ #include #include +extern int coherentio; +extern int hw_coherentio; + #ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */ #include #endif diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177..ead4e7b 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -63,7 +63,7 @@ static inline int plat_device_is_coherent(struct device *dev) return 1; #endif #ifdef CONFIG_DMA_NONCOHERENT - return 0; + return coherentio; #endif } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 606e828..a363d6f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1379,19 +1379,34 @@ static void __cpuinit coherency_setup(void) } } -#if defined(CONFIG_DMA_NONCOHERENT) - -static int __cpuinitdata coherentio; +int coherentio = 0; /* no DMA cache coherency (may be set by user) */ +int hw_coherentio = 0; /* no HW DMA cache coherency (reflects real HW) */ static int __init setcoherentio(char *str) { - coherentio = 1; + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); return 0; } - early_param("coherentio", setcoherentio); -#endif + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 0; +} +early_param("nocoherentio", setnocoherentio); static void __cpuinit r4k_cache_error_setup(void) { @@ -1474,9 +1489,11 @@ void __cpuinit r4k_cache_init(void) build_clear_page(); build_copy_page(); -#if !defined(CONFIG_MIPS_CMP) + + /* We want to run CMP kernels on core(s) with and without coherent caches */ + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ local_r4k___flush_cache_all(NULL); -#endif + coherency_setup(); board_cache_error_setup = r4k_cache_error_setup; } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 3fab204..aad5f7e 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -115,7 +115,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, if (!plat_device_is_coherent(dev)) { dma_cache_wback_inv((unsigned long) ret, size); - ret = UNCAC_ADDR(ret); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } } @@ -143,7 +144,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) - addr = CAC_ADDR(addr); + if (!hw_coherentio) + addr = CAC_ADDR(addr); free_pages(addr, get_order(size)); } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index ed68073..4187102 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -104,6 +105,74 @@ static void __init fd_activate(void) } #endif +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(fw_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + hw_coherentio = supported; + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -205,6 +274,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index f012fd1..af6a22b 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -12,9 +12,7 @@ #include #include - -int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ -int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ +#include const char *get_system_type(void) { -- 1.7.9.5 From Steven.Hill@imgtec.com Wed Feb 20 21:22:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Feb 2013 21:22:19 +0100 (CET) Received: from multi.imgtec.com ([194.200.65.239]:38752 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827512Ab3BTUWQ3JwOr convert rfc822-to-8bit (ORCPT ); Wed, 20 Feb 2013 21:22:16 +0100 From: Steven Hill To: "linux-mips@linux-mips.org" CC: "ralf@linux-mips.org" , "mcdonald.shane@gmail.com" Subject: RE: [PATCH v5] MIPS: Add option to disable software I/O coherency. Thread-Topic: [PATCH v5] MIPS: Add option to disable software I/O coherency. Thread-Index: AQHOD6Xv5BmW7kWyKk6D5irwXl21yZiDMF4e Date: Wed, 20 Feb 2013 20:22:06 +0000 Message-ID: <0573B2AE5BBFFC408CC8740092293B5ACB389E@bamail02.ba.imgtec.org> References: <1361390840-31415-1-git-send-email-Steven.Hill@imgtec.com> In-Reply-To: <1361390840-31415-1-git-send-email-Steven.Hill@imgtec.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.64.117] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01181__2013_02_20_20_22_10 X-archive-position: 35793 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 123 Lines: 1 This new version of the patch fixes the error from the kbuild test robot from yesterday and also updates my email address. From Steven.Hill@imgtec.com Wed Feb 20 21:32:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Feb 2013 21:32:29 +0100 (CET) Received: from multi.imgtec.com ([194.200.65.239]:39852 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827512Ab3BTUc11wbT8 convert rfc822-to-8bit (ORCPT ); Wed, 20 Feb 2013 21:32:27 +0100 From: Steven Hill To: Lars-Peter Clausen , Ralf Baechle CC: Kristian Kielhofner , "linux-mips@linux-mips.org" Subject: RE: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME Thread-Topic: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME Thread-Index: AQHODQoO43iokqJrJECFfgqPXf48m5iDN/+c Date: Wed, 20 Feb 2013 20:31:57 +0000 Message-ID: <0573B2AE5BBFFC408CC8740092293B5ACB3CB7@bamail02.ba.imgtec.org> References: <1361104102-13294-1-git-send-email-lars@metafoo.de> In-Reply-To: <1361104102-13294-1-git-send-email-lars@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.64.117] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01181__2013_02_20_20_32_21 X-archive-position: 35794 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 646 Lines: 19 Hello. This patch does not apply cleanly because of space/tab differences. In both of the lines below with '.brightness_set' the character between 't' and '=' needs to be a tab, not a space. -Steve @@ -34,33 +34,15 @@ static void sead3_fled_set(struct led_classdev *led_cdev, static struct led_classdev sead3_pled = { .name = "sead3::pled", .brightness_set = sead3_pled_set, + .flags = LED_CORE_SUSPENDRESUME, }; static struct led_classdev sead3_fled = { .name = "sead3::fled", .brightness_set = sead3_fled_set, + .flags = LED_CORE_SUSPENDRESUME, }; From lars@metafoo.de Wed Feb 20 21:40:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Feb 2013 21:40:50 +0100 (CET) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:33996 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827522Ab3BTUklSYvd2 (ORCPT ); Wed, 20 Feb 2013 21:40:41 +0100 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 5BAA4571; Wed, 20 Feb 2013 21:40:10 +0100 (CET) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id C0kMHc9GtQVu; Wed, 20 Feb 2013 21:40:09 +0100 (CET) Received: from [192.168.178.21] (ppp-188-174-115-35.dynamic.mnet-online.de [188.174.115.35]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id C8038570; Wed, 20 Feb 2013 21:40:08 +0100 (CET) Message-ID: <51253531.90001@metafoo.de> Date: Wed, 20 Feb 2013 21:42:25 +0100 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20121215 Icedove/3.0.11 MIME-Version: 1.0 To: Steven Hill CC: Ralf Baechle , Kristian Kielhofner , "linux-mips@linux-mips.org" Subject: Re: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME References: <1361104102-13294-1-git-send-email-lars@metafoo.de> <0573B2AE5BBFFC408CC8740092293B5ACB3CB7@bamail02.ba.imgtec.org> In-Reply-To: <0573B2AE5BBFFC408CC8740092293B5ACB3CB7@bamail02.ba.imgtec.org> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35795 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 816 Lines: 31 On 02/20/2013 09:31 PM, Steven Hill wrote: > Hello. > > This patch does not apply cleanly because of space/tab differences. In both of the lines below with '.brightness_set' the character between 't' and '=' needs to be a tab, not a space. > > -Steve Hi, The patch depends on commit 70342287 ("MIPS: Whitespace cleanup."). - Lars > > > @@ -34,33 +34,15 @@ static void sead3_fled_set(struct led_classdev *led_cdev, > static struct led_classdev sead3_pled = { > .name = "sead3::pled", > .brightness_set = sead3_pled_set, > + .flags = LED_CORE_SUSPENDRESUME, > }; > > static struct led_classdev sead3_fled = { > .name = "sead3::fled", > .brightness_set = sead3_fled_set, > + .flags = LED_CORE_SUSPENDRESUME, > }; > From Steven.Hill@imgtec.com Wed Feb 20 21:45:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Feb 2013 21:45:56 +0100 (CET) Received: from multi.imgtec.com ([194.200.65.239]:39934 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827521Ab3BTUpzBa4qM convert rfc822-to-8bit (ORCPT ); Wed, 20 Feb 2013 21:45:55 +0100 From: Steven Hill To: Lars-Peter Clausen CC: Ralf Baechle , Kristian Kielhofner , "linux-mips@linux-mips.org" Subject: RE: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME Thread-Topic: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME Thread-Index: AQHODQoO43iokqJrJECFfgqPXf48m5iDN/+cgACJnYD//3odBQ== Date: Wed, 20 Feb 2013 20:44:23 +0000 Message-ID: <0573B2AE5BBFFC408CC8740092293B5ACB40F9@bamail02.ba.imgtec.org> References: <1361104102-13294-1-git-send-email-lars@metafoo.de> <0573B2AE5BBFFC408CC8740092293B5ACB3CB7@bamail02.ba.imgtec.org>,<51253531.90001@metafoo.de> In-Reply-To: <51253531.90001@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.64.117] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01181__2013_02_20_20_45_48 X-archive-position: 35796 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 134 Lines: 5 Lars, Please format patches for Malta and SEAD-3 to be against my 'linux-sjhill.git' repo and the 'mti-next' branch. Thanks. -Steve From lars@metafoo.de Wed Feb 20 22:00:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Feb 2013 22:00:54 +0100 (CET) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:36176 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827521Ab3BTVAws0cV1 (ORCPT ); Wed, 20 Feb 2013 22:00:52 +0100 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 0F87C5ED; Wed, 20 Feb 2013 22:00:22 +0100 (CET) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id Qi8F2albXE4k; Wed, 20 Feb 2013 22:00:21 +0100 (CET) Received: from [192.168.178.21] (ppp-188-174-115-35.dynamic.mnet-online.de [188.174.115.35]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 444BB5EC; Wed, 20 Feb 2013 22:00:20 +0100 (CET) Message-ID: <512539ED.8020308@metafoo.de> Date: Wed, 20 Feb 2013 22:02:37 +0100 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20121215 Icedove/3.0.11 MIME-Version: 1.0 To: Steven Hill CC: Ralf Baechle , Kristian Kielhofner , "linux-mips@linux-mips.org" Subject: Re: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME References: <1361104102-13294-1-git-send-email-lars@metafoo.de> <0573B2AE5BBFFC408CC8740092293B5ACB3CB7@bamail02.ba.imgtec.org>,<51253531.90001@metafoo.de> <0573B2AE5BBFFC408CC8740092293B5ACB40F9@bamail02.ba.imgtec.org> In-Reply-To: <0573B2AE5BBFFC408CC8740092293B5ACB40F9@bamail02.ba.imgtec.org> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 35797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 403 Lines: 14 On 02/20/2013 09:44 PM, Steven Hill wrote: > Lars, > > Please format patches for Malta and SEAD-3 to be against my 'linux-sjhill.git' repo and the 'mti-next' branch. Thanks. Hi, Can you fixup the patch manually in this case? It's probably faster for both of us than having me re-send the patch. Btw. I think it would be a good idea to add the information about your git repo to MAINTAINERS. - Lars From Steven.Hill@imgtec.com Wed Feb 20 22:08:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Feb 2013 22:08:28 +0100 (CET) Received: from multi.imgtec.com ([194.200.65.239]:44097 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827521Ab3BTVI1b08iC convert rfc822-to-8bit (ORCPT ); Wed, 20 Feb 2013 22:08:27 +0100 From: Steven Hill To: Lars-Peter Clausen CC: Ralf Baechle , Kristian Kielhofner , "linux-mips@linux-mips.org" Subject: RE: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME Thread-Topic: [PATCH] MIPS: sead3_led: Use LED_CORE_SUSPENDRESUME Thread-Index: AQHODQoO43iokqJrJECFfgqPXf48m5iDN/+cgACJnYD//3odBYAAi4iA//97OSw= Date: Wed, 20 Feb 2013 21:07:33 +0000 Message-ID: <0573B2AE5BBFFC408CC8740092293B5ACB411F@bamail02.ba.imgtec.org> References: <1361104102-13294-1-git-send-email-lars@metafoo.de> <0573B2AE5BBFFC408CC8740092293B5ACB3CB7@bamail02.ba.imgtec.org>,<51253531.90001@metafoo.de> <0573B2AE5BBFFC408CC8740092293B5ACB40F9@bamail02.ba.imgtec.org>,<512539ED.8020308@metafoo.de> In-Reply-To: <512539ED.8020308@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.64.117] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01181__2013_02_20_21_08_20 X-archive-position: 35798 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 28 Lines: 1 Sure, I'll take care of it. From Steven.Hill@imgtec.com Thu Feb 21 02:12:33 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 21 Feb 2013 02:12:36 +0100 (CET) Received: from home.bethel-hill.org ([63.228.164.32]:50917 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827529Ab3BUBMdqexdp (ORCPT ); Thu, 21 Feb 2013 02:12:33 +0100 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1U8Khy-0001fs-IQ; Wed, 20 Feb 2013 19:12:22 -0600 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: Lars-Peter Clausen , ralf@linux-mips.org, "Steven J. Hill" Subject: [PATCH] MIPS: sead3: Use generic suspend/resume for LEDs. Date: Wed, 20 Feb 2013 19:12:17 -0600 Message-Id: <1361409137-2123-1-git-send-email-Steven.Hill@imgtec.com> X-Mailer: git-send-email 1.7.9.5 X-archive-position: 35799 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1932 Lines: 65 From: Lars-Peter Clausen Setting the LED_CORE_SUSPENDRESUME flag causes the LED driver core to call led_classdev_suspend/led_classdev_resume during suspend/resume. Since this is exactly what the driver's custom suspend/resume callbacks do we can replace them by setting the LED_CORE_SUSPENDRESUME flag. Signed-off-by: Lars-Peter Clausen Signed-off-by: Steven J. Hill --- arch/mips/mti-sead3/leds-sead3.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c index a95ac59..47e3c0d 100644 --- a/arch/mips/mti-sead3/leds-sead3.c +++ b/arch/mips/mti-sead3/leds-sead3.c @@ -34,33 +34,15 @@ static void sead3_fled_set(struct led_classdev *led_cdev, static struct led_classdev sead3_pled = { .name = "sead3::pled", .brightness_set = sead3_pled_set, + .flags = LED_CORE_SUSPENDRESUME, }; static struct led_classdev sead3_fled = { .name = "sead3::fled", .brightness_set = sead3_fled_set, + .flags = LED_CORE_SUSPENDRESUME, }; -#ifdef CONFIG_PM -static int sead3_led_suspend(struct platform_device *dev, - pm_message_t state) -{ - led_classdev_suspend(&sead3_pled); - led_classdev_suspend(&sead3_fled); - return 0; -} - -static int sead3_led_resume(struct platform_device *dev) -{ - led_classdev_resume(&sead3_pled); - led_classdev_resume(&sead3_fled); - return 0; -} -#else -#define sead3_led_suspend NULL -#define sead3_led_resume NULL -#endif - static int sead3_led_probe(struct platform_device *pdev) { int ret; @@ -86,8 +68,6 @@ static int sead3_led_remove(struct platform_device *pdev) static struct platform_driver sead3_led_driver = { .probe = sead3_led_probe, .remove = sead3_led_remove, - .suspend = sead3_led_suspend, - .resume = sead3_led_resume, .driver = { .name = DRVNAME, .owner = THIS_MODULE, -- 1.7.9.5 From mcdonald.shane@gmail.com Thu Feb 21 06:23:08 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 21 Feb 2013 06:23:10 +0100 (CET) Received: from mail-we0-f179.google.com ([74.125.82.179]:39320 "EHLO mail-we0-f179.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816831Ab3BUFXIOEZ5h (ORCPT ); Thu, 21 Feb 2013 06:23:08 +0100 Received: by mail-we0-f179.google.com with SMTP id p43so5361027wea.38 for ; Wed, 20 Feb 2013 21:23:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:in-reply-to:references:date:message-id :subject:from:to:cc:content-type; bh=feU0tKYn0ilCIPev+kYVBdy3LJ/Nf7wnSohoLvJBObo=; b=uAIDCnHbV1WIQz90Cj63Ma5Ii0pIst4vcnbWKioAugdpz3wExLokibwu0Y2QJcq78w hr5fjTLI+azFF2RLoitL57fP4iwH/YUeLrUfIrai6QMEsBm6ircPL4YscS/PA1+AB3oG nfiEIIIw7uJcxd2HiatnS+qeLbqMpse41EvLrJ0yFvinkrnNcVw1DEARYoQroW/3Rp+V 0h73REiFLVAT7nwfsif0TkFsnpbK/+4SMLXNhQXfvFJGlp0gTaa47O1lv5uwjOOyZFZU yJ3w5VZ4RtGiTVmnVIEG7Wnx4XElg7HZfbnelLZwYcta7VNx8Qv627EB4X7khPVrNFLu IMFg== MIME-Version: 1.0 X-Received: by 10.180.75.110 with SMTP id b14mr39048095wiw.21.1361424182792; Wed, 20 Feb 2013 21:23:02 -0800 (PST) Received: by 10.194.58.84 with HTTP; Wed, 20 Feb 2013 21:23:02 -0800 (PST) In-Reply-To: <1361390840-31415-1-git-send-email-Steven.Hill@imgtec.com> References: <1361390840-31415-1-git-send-email-Steven.Hill@imgtec.com> Date: Wed, 20 Feb 2013 23:23:02 -0600 Message-ID: Subject: Re: [PATCH v5] MIPS: Add option to disable software I/O coherency. From: Shane McDonald To: "Steven J. Hill" Cc: linux-mips , Ralf Baechle Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35800 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 9472 Lines: 252 I tried applying this patch to the linux-mips.org 3.8-rc7 tree, and it failed to apply on the sead3-setup.c file. I ignored that, and applied the rest of the patch. This patch tested successfully on my RM7035C-based system that has CONFIG_DMA_NONCOHERENT set. My system works fine with this patch applied. Feel free to add my: Tested-by: Shane McDonald On Wed, Feb 20, 2013 at 2:07 PM, Steven J. Hill wrote: > From: "Steven J. Hill" > > Some MIPS controllers have hardware I/O coherency. This patch > detects those and turns off software coherency. A new kernel > command line option also allows the user to manually turn > software coherency on or off. > > Signed-off-by: Steven J. Hill > --- > arch/mips/include/asm/dma-mapping.h | 3 + > arch/mips/include/asm/mach-generic/dma-coherence.h | 2 +- > arch/mips/mm/c-r4k.c | 33 ++++++--- > arch/mips/mm/dma-default.c | 6 +- > arch/mips/mti-malta/malta-setup.c | 71 ++++++++++++++++++++ > arch/mips/mti-sead3/sead3-setup.c | 4 +- > 6 files changed, 105 insertions(+), 14 deletions(-) > > diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h > index 006b43e..206243d 100644 > --- a/arch/mips/include/asm/dma-mapping.h > +++ b/arch/mips/include/asm/dma-mapping.h > @@ -5,6 +5,9 @@ > #include > #include > > +extern int coherentio; > +extern int hw_coherentio; > + > #ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */ > #include > #endif > diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h > index 9c95177..ead4e7b 100644 > --- a/arch/mips/include/asm/mach-generic/dma-coherence.h > +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h > @@ -63,7 +63,7 @@ static inline int plat_device_is_coherent(struct device *dev) > return 1; > #endif > #ifdef CONFIG_DMA_NONCOHERENT > - return 0; > + return coherentio; > #endif > } > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > index 606e828..a363d6f 100644 > --- a/arch/mips/mm/c-r4k.c > +++ b/arch/mips/mm/c-r4k.c > @@ -1379,19 +1379,34 @@ static void __cpuinit coherency_setup(void) > } > } > > -#if defined(CONFIG_DMA_NONCOHERENT) > - > -static int __cpuinitdata coherentio; > +int coherentio = 0; /* no DMA cache coherency (may be set by user) */ > +int hw_coherentio = 0; /* no HW DMA cache coherency (reflects real HW) */ > > static int __init setcoherentio(char *str) > { > - coherentio = 1; > + if (coherentio == 0) > + pr_info("Command line enabling coherentio" > + " (this will break...)!!\n"); > > + coherentio = 1; > + pr_info("Hardware DMA cache coherency (command line)\n"); > return 0; > } > - > early_param("coherentio", setcoherentio); > -#endif > + > +static int __init setnocoherentio(char *str) > +{ > + if (coherentio < 0) > + pr_info("Command line checking done before" > + " plat_setup_iocoherency!!\n"); > + if (coherentio == 1) > + pr_info("Command line disabling coherentio\n"); > + > + coherentio = 0; > + pr_info("Software DMA cache coherency (command line)\n"); > + return 0; > +} > +early_param("nocoherentio", setnocoherentio); > > static void __cpuinit r4k_cache_error_setup(void) > { > @@ -1474,9 +1489,11 @@ void __cpuinit r4k_cache_init(void) > > build_clear_page(); > build_copy_page(); > -#if !defined(CONFIG_MIPS_CMP) > + > + /* We want to run CMP kernels on core(s) with and without coherent caches */ > + /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */ > local_r4k___flush_cache_all(NULL); > -#endif > + > coherency_setup(); > board_cache_error_setup = r4k_cache_error_setup; > } > diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c > index 3fab204..aad5f7e 100644 > --- a/arch/mips/mm/dma-default.c > +++ b/arch/mips/mm/dma-default.c > @@ -115,7 +115,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, > > if (!plat_device_is_coherent(dev)) { > dma_cache_wback_inv((unsigned long) ret, size); > - ret = UNCAC_ADDR(ret); > + if (!hw_coherentio) > + ret = UNCAC_ADDR(ret); > } > } > > @@ -143,7 +144,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, > plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); > > if (!plat_device_is_coherent(dev)) > - addr = CAC_ADDR(addr); > + if (!hw_coherentio) > + addr = CAC_ADDR(addr); > > free_pages(addr, get_order(size)); > } > diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c > index ed68073..4187102 100644 > --- a/arch/mips/mti-malta/malta-setup.c > +++ b/arch/mips/mti-malta/malta-setup.c > @@ -31,6 +31,7 @@ > #include > #include > #include > +#include > #ifdef CONFIG_VT > #include > #endif > @@ -104,6 +105,74 @@ static void __init fd_activate(void) > } > #endif > > +static int __init > +plat_enable_iocoherency(void) > +{ > + int supported = 0; > + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { > + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { > + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; > + pr_info("Enabled Bonito CPU coherency\n"); > + supported = 1; > + } > + if (strstr(fw_getcmdline(), "iobcuncached")) { > + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; > + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & > + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | > + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); > + pr_info("Disabled Bonito IOBC coherency\n"); > + } else { > + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; > + BONITO_PCIMEMBASECFG |= > + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | > + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); > + pr_info("Enabled Bonito IOBC coherency\n"); > + } > + } else if (gcmp_niocu() != 0) { > + /* Nothing special needs to be done to enable coherency */ > + pr_info("CMP IOCU detected\n"); > + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { > + pr_crit("IOCU OPERATION DISABLED BY SWITCH" > + " - DEFAULTING TO SW IO COHERENCY\n"); > + return 0; > + } > + supported = 1; > + } > + hw_coherentio = supported; > + return supported; > +} > + > +static void __init > +plat_setup_iocoherency(void) > +{ > +#ifdef CONFIG_DMA_NONCOHERENT > + /* > + * Kernel has been configured with software coherency > + * but we might choose to turn it off > + */ > + if (plat_enable_iocoherency()) { > + if (coherentio == 0) > + pr_info("Hardware DMA cache coherency supported" > + " but disabled from command line\n"); > + else { > + coherentio = 1; > + printk(KERN_INFO "Hardware DMA cache coherency\n"); > + } > + } else { > + if (coherentio == 1) > + pr_info("Hardware DMA cache coherency not supported" > + " but enabled from command line\n"); > + else { > + coherentio = 0; > + pr_info("Software DMA cache coherency\n"); > + } > + } > +#else > + if (!plat_enable_iocoherency()) > + panic("Hardware DMA cache coherency not supported"); > +#endif > +} > + > #ifdef CONFIG_BLK_DEV_IDE > static void __init pci_clock_check(void) > { > @@ -205,6 +274,8 @@ void __init plat_mem_setup(void) > if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) > bonito_quirks_setup(); > > + plat_setup_iocoherency(); > + > #ifdef CONFIG_BLK_DEV_IDE > pci_clock_check(); > #endif > diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c > index f012fd1..af6a22b 100644 > --- a/arch/mips/mti-sead3/sead3-setup.c > +++ b/arch/mips/mti-sead3/sead3-setup.c > @@ -12,9 +12,7 @@ > > #include > #include > - > -int coherentio; /* 0 => no DMA cache coherency (may be set by user) */ > -int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */ > +#include > > const char *get_system_type(void) > { > -- > 1.7.9.5 > From yuasa@linux-mips.org Thu Feb 21 07:39:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 21 Feb 2013 07:39:16 +0100 (CET) Received: from mo10.iij4u.or.jp ([210.138.174.78]:58980 "EHLO mo.iij4u.or.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827530Ab3BUGjOTVvWf (ORCPT ); Thu, 21 Feb 2013 07:39:14 +0100 Received: by mo.iij4u.or.jp (mo10) id r1L6d9hw021022; Thu, 21 Feb 2013 15:39:09 +0900 Received: from delta (sannin29190.nirai.ne.jp [203.160.29.190]) by mbox.iij4u.or.jp (mbox10) id r1L6d713000384 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 21 Feb 2013 15:39:09 +0900 Date: Thu, 21 Feb 2013 15:38:19 +0900 From: Yoichi Yuasa To: ralf@linux-mips.org Cc: yuasa@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH] MIPS: VR4133: add LL/SC support Message-Id: <20130221153819.b3e9b650d87ffea492679a86@linux-mips.org> X-Mailer: Sylpheed 3.2.0beta5 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 35801 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1220 Lines: 41 Signed-off-by: Yoichi Yuasa --- arch/mips/kernel/cpu-probe.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9f31334..44c5aad 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -547,6 +547,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->tlbsize = 48; break; case PRID_IMP_VR41XX: + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS; + c->tlbsize = 32; switch (c->processor_id & 0xf0) { case PRID_REV_VR4111: c->cputype = CPU_VR4111; @@ -571,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "NEC VR4131"; } else { c->cputype = CPU_VR4133; + c->options |= MIPS_CPU_LLSC; __cpu_name[cpu] = "NEC VR4133"; } break; @@ -580,9 +584,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "NEC Vr41xx"; break; } - c->isa_level = MIPS_CPU_ISA_III; - c->options = R4K_OPTS; - c->tlbsize = 32; break; case PRID_IMP_R4300: c->cputype = CPU_R4300; -- 1.7.9.5 From ralf@linux-mips.org Thu Feb 21 14:30:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 21 Feb 2013 14:30:54 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36240 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6827538Ab3BUNawlF9CW (ORCPT ); Thu, 21 Feb 2013 14:30:52 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r1LDUopH011512; Thu, 21 Feb 2013 14:30:50 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r1LDUmjV011502; Thu, 21 Feb 2013 14:30:48 +0100 Date: Thu, 21 Feb 2013 14:30:48 +0100 From: Ralf Baechle To: Steven Hill Cc: "linux-mips@linux-mips.org" , "mcdonald.shane@gmail.com" Subject: Re: [PATCH v5] MIPS: Add option to disable software I/O coherency. Message-ID: <20130221133048.GA6065@linux-mips.org> References: <1361390840-31415-1-git-send-email-Steven.Hill@imgtec.com> <0573B2AE5BBFFC408CC8740092293B5ACB389E@bamail02.ba.imgtec.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0573B2AE5BBFFC408CC8740092293B5ACB389E@bamail02.ba.imgtec.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35802 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 269 Lines: 7 On Wed, Feb 20, 2013 at 08:22:06PM +0000, Steven Hill wrote: > This new version of the patch fixes the error from the kbuild test robot from yesterday and also updates my email address. Maybe we should update the addresses of everybody in a single big patch? Ralf From hpa@linux.intel.com Fri Feb 22 01:36:46 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 01:36:49 +0100 (CET) Received: from terminus.zytor.com ([198.137.202.10]:60854 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827568Ab3BVAgqTpCzx (ORCPT ); Fri, 22 Feb 2013 01:36:46 +0100 Received: from terminus.zytor.com (localhost [127.0.0.1]) by terminus.zytor.com (8.14.5/8.14.5) with ESMTP id r1M0Y71W008312 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 21 Feb 2013 16:34:12 -0800 Received: (from hpa@localhost) by terminus.zytor.com (8.14.5/8.14.5/Submit) id r1M0Y6O8008311; Thu, 21 Feb 2013 16:34:06 -0800 Date: Thu, 21 Feb 2013 16:34:06 -0800 Message-Id: <201302220034.r1M0Y6O8008311@terminus.zytor.com> X-Authentication-Warning: terminus.zytor.com: hpa set sender to hpa@zytor.com using -f From: "H. Peter Anvin" To: Linus Torvalds Subject: [GIT PULL] x86/mm changes for v3.9-rc1 Cc: "David S. Miller" , "H. Peter Anvin" , "Rafael J. Wysocki" , , Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , "Eric W. Biederman" , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , "H. Peter Anvin" , "H. Peter Anvin" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Konrad Rzeszutek Wilk , Kyungmin Park , Lee Schermerhorn , Len Brown , Linus Torvalds , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , "Rafael J. Wysocki" , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , Ville =?ISO-8859-1?Q?=20Syrj=C3=A4l=C3=A4?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , avi@redhat.com, gleb@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, shuahkhan@gmail.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.2.7 (terminus.zytor.com [127.0.0.1]); Thu, 21 Feb 2013 16:34:13 -0800 (PST) X-archive-position: 35803 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 12675 Lines: 260 Hi Linus, This is a huge set of several partly interrelated (and concurrently developed) changes, which is why the branch history is messier than one would like. The *really* big items are two humonguous patchsets mostly developed by Yinghai Lu at my request, which completely revamps the way we create initial page tables. In particular, rather than estimating how much memory we will need for page tables and then build them into that memory -- a calculation that has shown to be incredibly fragile -- we now build them (on 64 bits) with the aid of a "pseudo-linear mode" -- a #PF handler which creates temporary page tables on demand. This has several advantages: 1. It makes it much easier to support things that need access to data very early (a followon patchset uses this to load microcode way early in the kernel startup). 2. It allows the kernel and all the kernel data objects to be invoked from above the 4 GB limit. This allows kdump to work on very large systems. 3. It greatly reduces the difference between Xen and native (Xen's equivalent of the #PF handler are the temporary page tables created by the domain builder), eliminating a bunch of fragile hooks. The patch series also gets us a bit closer to W^X. Additional work in this pull is the 64-bit get_user() work which you were also involved with, and a bunch of cleanups/speedups to __phys_addr()/__pa(). ---------------------------------------------------------------- The following changes since commit 5dcd14ecd41ea2b3ae3295a9b30d98769d52165f: x86, boot: Sanitize boot_params if not zeroed on creation (2013-01-29 01:22:17 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-mm-for-linus for you to fetch changes up to 0da3e7f526fde7a6522a3038b7ce609fc50f6707: Merge branch 'x86/mm2' into x86/mm (2013-02-15 09:25:08 -0800) ---------------------------------------------------------------- Alexander Duyck (9): x86: Move some contents of page_64_types.h into pgtable_64.h and page_64.h x86: Improve __phys_addr performance by making use of carry flags and inlining x86: Make it so that __pa_symbol can only process kernel symbols on x86_64 x86: Drop 4 unnecessary calls to __pa_symbol x86: Use __pa_symbol instead of __pa on C visible symbols x86/ftrace: Use __pa_symbol instead of __pa on C visible symbols x86/acpi: Use __pa_symbol instead of __pa on C visible symbols x86/lguest: Use __pa_symbol instead of __pa on C visible symbols x86: Fix warning about cast from pointer to integer of different size Borislav Petkov (1): x86/numa: Use __pa_nodebug() instead Dave Hansen (6): x86, mm: Make DEBUG_VIRTUAL work earlier in boot x86, mm: Pagetable level size/shift/mask helpers x86, mm: Use new pagetable helpers in try_preserve_large_page() x86, mm: Create slow_virt_to_phys() x86, kvm: Fix kvm's use of __pa() on percpu areas x86-32, mm: Rip out x86_32 NUMA remapping code H. Peter Anvin (13): Merge branch 'x86/mm' of ssh://ra.kernel.org/.../tip/tip into x86/mm Merge tag 'v3.8-rc5' into x86/mm Merge remote-tracking branch 'origin/x86/boot' into x86/mm2 x86, 64bit: Use a #PF handler to materialize early mappings on demand x86-32, mm: Remove reference to resume_map_numa_kva() x86-32, mm: Remove reference to alloc_remap() Merge remote-tracking branch 'origin/x86/mm' into x86/mm2 x86, mm: Use a bitfield to mask nuisance get_user() warnings x86: Be consistent with data size in getuser.S x86, mm: Redesign get_user with a __builtin_choose_expr hack x86, doc: Clarify the use of asm("%edx") in uaccess.h x86, mm: Move reserving low memory later in initialization Merge branch 'x86/mm2' into x86/mm Ingo Molnar (1): x86/mm: Don't flush the TLB on #WP pmd fixups Jacob Shin (3): x86, mm: if kernel .text .data .bss are not marked as E820_RAM, complain and fix x86, mm: Fixup code testing if a pfn is direct mapped x86, mm: Only direct map addresses that are marked as E820_RAM Shuah Khan (1): x86/kvm: Fix compile warning in kvm_register_steal_time() Stefano Stabellini (1): x86, mm: Add pointer about Xen mmu requirement for alloc_low_pages Ville Syrjälä (1): x86-32: Add support for 64bit get_user() Yinghai Lu (74): x86, mm: Add global page_size_mask and probe one time only x86, mm: Split out split_mem_range from init_memory_mapping x86, mm: Move down find_early_table_space() x86, mm: Move init_memory_mapping calling out of setup.c x86, mm: Revert back good_end setting for 64bit x86, mm: Change find_early_table_space() paramters x86, mm: Find early page table buffer together x86, mm: Separate out calculate_table_space_size() x86, mm: Set memblock initial limit to 1M x86, mm: use pfn_range_is_mapped() with CPA x86, mm: use pfn_range_is_mapped() with gart x86, mm: use pfn_range_is_mapped() with reserve_initrd x86, mm: relocate initrd under all mem for 64bit x86, mm: Align start address to correct big page size x86, mm: Use big page size for small memory range x86, mm: Don't clear page table if range is ram x86, mm: Break down init_all_memory_mapping x86, mm: setup page table in top-down x86, mm: Remove early_memremap workaround for page table accessing on 64bit x86, mm: Remove parameter in alloc_low_page for 64bit x86, mm: Merge alloc_low_page between 64bit and 32bit x86, mm: Move min_pfn_mapped back to mm/init.c x86, mm, Xen: Remove mapping_pagetable_reserve() x86, mm: Add alloc_low_pages(num) x86, mm: only call early_ioremap_page_table_range_init() once x86, mm: Move back pgt_buf_* to mm/init.c x86, mm: Move init_gbpages() out of setup.c x86, mm: change low/hignmem_pfn_init to static on 32bit x86, mm: Move function declaration into mm_internal.h x86, mm: Add check before clear pte above max_low_pfn on 32bit x86, mm: use round_up/down in split_mem_range() x86, mm: use PFN_DOWN in split_mem_range() x86, mm: use pfn instead of pos in split_mem_range x86, mm: use limit_pfn for end pfn x86, mm: Unifying after_bootmem for 32bit and 64bit x86, mm: Move after_bootmem to mm_internel.h x86, mm: Use clamp_t() in init_range_memory_mapping x86, mm: kill numa_free_all_bootmem() x86, mm: kill numa_64.h sparc, mm: Remove calling of free_all_bootmem_node() mm: Kill NO_BOOTMEM version free_all_bootmem_node() x86, mm: Let "memmap=" take more entries one time x86, mm: Fix page table early allocation offset checking x86: Factor out e820_add_kernel_range() x86, 64bit, mm: Make pgd next calculation consistent with pud/pmd x86, realmode: Set real_mode permissions early x86, 64bit, mm: Add generic kernel/ident mapping helper x86, 64bit: Copy struct boot_params early x86, 64bit, realmode: Use init_level4_pgt to set trampoline_pgd directly x86, realmode: Separate real_mode reserve and setup x86, 64bit: #PF handler set page to cover only 2M per #PF x86, 64bit: Don't set max_pfn_mapped wrong value early on native path x86: Merge early_reserve_initrd for 32bit and 64bit x86: Add get_ramdisk_image/size() x86, boot: Add get_cmd_line_ptr() x86, boot: Move checking of cmd_line_ptr out of common path x86, boot: Pass cmd_line_ptr with unsigned long instead x86, boot: Move verify_cpu.S and no_longmode down x86, boot: Move lldt/ltr out of 64bit code section x86, kexec: Remove 1024G limitation for kexec buffer on 64bit x86, kexec: Set ident mapping for kernel that is above max_pfn x86, kexec: Replace ident_mapping_init and init_level4_page x86, kexec, 64bit: Only set ident mapping for ram. x86, boot: Support loading bzImage, boot_params and ramdisk above 4G x86, boot: Update comments about entries for 64bit image x86, boot: Not need to check setup_header version for setup_data memblock: Add memblock_mem_size() x86, kdump: Remove crashkernel range find limit for 64bit x86: Add Crash kernel low reservation x86: Merge early kernel reserve for 32bit and 64bit x86, 64bit, mm: Mark data/bss/brk to nx x86, 64bit, mm: hibernate use generic mapping_init mm: Add alloc_bootmem_low_pages_nopanic() x86: Don't panic if can not alloc buffer for swiotlb Documentation/kernel-parameters.txt | 3 + Documentation/x86/boot.txt | 38 +++ arch/mips/cavium-octeon/dma-octeon.c | 3 +- arch/sparc/mm/init_64.c | 24 +- arch/x86/Kconfig | 4 - arch/x86/boot/boot.h | 18 +- arch/x86/boot/cmdline.c | 12 +- arch/x86/boot/compressed/cmdline.c | 12 +- arch/x86/boot/compressed/head_64.S | 48 ++-- arch/x86/boot/header.S | 10 +- arch/x86/include/asm/init.h | 28 +- arch/x86/include/asm/kexec.h | 6 +- arch/x86/include/asm/mmzone_32.h | 6 - arch/x86/include/asm/numa.h | 2 - arch/x86/include/asm/numa_64.h | 6 - arch/x86/include/asm/page.h | 7 +- arch/x86/include/asm/page_32.h | 1 + arch/x86/include/asm/page_64.h | 36 +++ arch/x86/include/asm/page_64_types.h | 22 -- arch/x86/include/asm/page_types.h | 2 + arch/x86/include/asm/pgtable.h | 16 ++ arch/x86/include/asm/pgtable_64.h | 5 + arch/x86/include/asm/pgtable_64_types.h | 4 + arch/x86/include/asm/pgtable_types.h | 4 +- arch/x86/include/asm/processor.h | 1 + arch/x86/include/asm/realmode.h | 3 +- arch/x86/include/asm/uaccess.h | 55 ++-- arch/x86/include/asm/x86_init.h | 12 - arch/x86/kernel/acpi/boot.c | 1 - arch/x86/kernel/acpi/sleep.c | 2 +- arch/x86/kernel/amd_gart_64.c | 5 +- arch/x86/kernel/apic/apic_numachip.c | 1 + arch/x86/kernel/cpu/amd.c | 9 +- arch/x86/kernel/cpu/intel.c | 3 +- arch/x86/kernel/e820.c | 16 +- arch/x86/kernel/ftrace.c | 4 +- arch/x86/kernel/head32.c | 20 -- arch/x86/kernel/head64.c | 131 ++++++--- arch/x86/kernel/head_64.S | 210 +++++++++------ arch/x86/kernel/i386_ksyms_32.c | 1 + arch/x86/kernel/kvm.c | 11 +- arch/x86/kernel/kvmclock.c | 4 +- arch/x86/kernel/machine_kexec_64.c | 171 ++++-------- arch/x86/kernel/setup.c | 260 +++++++++++------- arch/x86/kernel/traps.c | 9 + arch/x86/kernel/x8664_ksyms_64.c | 3 + arch/x86/kernel/x86_init.c | 4 - arch/x86/lguest/boot.c | 3 +- arch/x86/lib/getuser.S | 43 ++- arch/x86/mm/init.c | 459 +++++++++++++++++++++----------- arch/x86/mm/init_32.c | 106 +++++--- arch/x86/mm/init_64.c | 255 ++++++++++-------- arch/x86/mm/mm_internal.h | 19 ++ arch/x86/mm/numa.c | 32 +-- arch/x86/mm/numa_32.c | 161 ----------- arch/x86/mm/numa_64.c | 13 - arch/x86/mm/numa_internal.h | 6 - arch/x86/mm/pageattr.c | 66 +++-- arch/x86/mm/pat.c | 4 +- arch/x86/mm/pgtable.c | 7 +- arch/x86/mm/physaddr.c | 60 +++-- arch/x86/platform/efi/efi.c | 11 +- arch/x86/power/hibernate_32.c | 2 - arch/x86/power/hibernate_64.c | 66 ++--- arch/x86/realmode/init.c | 49 ++-- arch/x86/xen/mmu.c | 28 -- drivers/xen/swiotlb-xen.c | 4 +- include/linux/bootmem.h | 5 + include/linux/kexec.h | 3 + include/linux/memblock.h | 1 + include/linux/mm.h | 1 - include/linux/swiotlb.h | 2 +- kernel/kexec.c | 34 ++- lib/swiotlb.c | 47 ++-- mm/bootmem.c | 8 + mm/memblock.c | 17 ++ mm/nobootmem.c | 23 +- 77 files changed, 1541 insertions(+), 1247 deletions(-) [Skipping the full diff due to size] From Steven.Hill@imgtec.com Fri Feb 22 05:52:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 05:52:15 +0100 (CET) Received: from multi.imgtec.com ([194.200.65.239]:2846 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816288Ab3BVEwO335tN convert rfc822-to-8bit (ORCPT ); Fri, 22 Feb 2013 05:52:14 +0100 From: Steven Hill To: Ralf Baechle CC: "linux-mips@linux-mips.org" , "mcdonald.shane@gmail.com" Subject: RE: [PATCH v5] MIPS: Add option to disable software I/O coherency. Thread-Topic: [PATCH v5] MIPS: Add option to disable software I/O coherency. Thread-Index: AQHOD6Xv5BmW7kWyKk6D5irwXl21yZiDMF4egAGlwwCAAHXsVA== Date: Fri, 22 Feb 2013 04:50:44 +0000 Message-ID: <0573B2AE5BBFFC408CC8740092293B5ACB49E3@bamail02.ba.imgtec.org> References: <1361390840-31415-1-git-send-email-Steven.Hill@imgtec.com> <0573B2AE5BBFFC408CC8740092293B5ACB389E@bamail02.ba.imgtec.org>,<20130221133048.GA6065@linux-mips.org> In-Reply-To: <20130221133048.GA6065@linux-mips.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.64.117] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01181__2013_02_22_04_52_08 X-archive-position: 35804 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 247 Lines: 5 > Maybe we should update the addresses of everybody in a single big patch? > For the patches still not in your 3.9 tree, I have already updated the email addresses in my 'mti-next' tree. The patches slated for 3.9 can be left as they are. -Steve From aaro.koskinen@iki.fi Thu Feb 21 16:46:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 12:28:55 +0100 (CET) Received: from filtteri6.pp.htv.fi ([213.243.153.189]:51457 "EHLO filtteri6.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827542Ab3BUPqQTy8pj (ORCPT ); Thu, 21 Feb 2013 16:46:16 +0100 Received: from localhost (localhost [127.0.0.1]) by filtteri6.pp.htv.fi (Postfix) with ESMTP id 9518A56F5F6; Thu, 21 Feb 2013 17:46:15 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp4.welho.com ([213.243.153.38]) by localhost (filtteri6.pp.htv.fi [213.243.153.189]) (amavisd-new, port 10024) with ESMTP id poeBTS-V-lWL; Thu, 21 Feb 2013 17:46:14 +0200 (EET) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp4.welho.com (Postfix) with SMTP id 759C65BC010; Thu, 21 Feb 2013 17:46:13 +0200 (EET) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Thu, 21 Feb 2013 17:46:12 +0200 Date: Thu, 21 Feb 2013 17:46:12 +0200 From: Aaro Koskinen To: "Patrik, Kluba" Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: bug: keep_bootcon and early printk together can lead to (invisible) kernel panic Message-ID: <20130221154612.GA11617@blackmetal.musicnaut.iki.fi> References: <20130221153717.31400a88.pkluba@dension.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130221153717.31400a88.pkluba@dension.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 35805 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 873 Lines: 18 On Thu, Feb 21, 2013 at 03:37:17PM +0100, Patrik, Kluba wrote: > I had a silent lockup on one of our embedded system under development. > It was not easy to track it down, so here's what I discovered, in case > somebody runs into similar trouble. > Using 'keep_bootcon' command line parameter, and enabling early printk > can lead to a kernel panic. At least on MIPS, it does. The problem is > that in arch/mips/kernel/early_printk.c everything is declared as > __init and __initdata, so they are being freed, when the kernel > frees .init.* sections. If 'keep_bootcon' is given, the early console > does not get unregistered, and the entry in the console_drivers list > can point (will, believe me) to garbage data. It's up to you to imagine > the effects... I also ran into this recently, this should fix it: http://marc.info/?l=linux-kernel&m=136062078931024&w=2 A. From torvalds@linux-foundation.org Fri Feb 22 17:22:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 17:22:43 +0100 (CET) Received: from mail-vb0-f45.google.com ([209.85.212.45]:38578 "EHLO mail-vb0-f45.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827568Ab3BVQWlyj6mg (ORCPT ); Fri, 22 Feb 2013 17:22:41 +0100 Received: by mail-vb0-f45.google.com with SMTP id p1so503309vbi.4 for ; Fri, 22 Feb 2013 08:22:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=1/z2HptjR302a24hbbwFqasOppfSVXf9++eQRkTCQfg=; b=VbcTdscRO9XJN17mD+K8OqTtO2yVQqfFd5nOrFjVjk3nInRZmQyqmTCbIIXCN4Is0E IDz4nCF4IzcYIErIlNgIRLaqg0js/lw9L1ATQZm8g+jeLE5GH2x9QHrgxFTLWV8Qev6V Tx3vxudvwdz/ggsrqkGLvrknejVhIIR5RyhRWMdAAAiImEBspdDqko3EYLP/4SdmRBAr 9ipR5Z03g62NMAubLBz0sQGfQlonZt6O6JOYYXRoqF4U8dBYHu7nVyrszNsv8WfzRD1+ hesGos+W54+1//rJd2uS//6yNyndHplo/c3qNiDku8mDskOU43/nz1prNSEn/GVVgBRy 3w1Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux-foundation.org; s=google; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=1/z2HptjR302a24hbbwFqasOppfSVXf9++eQRkTCQfg=; b=ZHHGAMIgdbc7cqAoTBRpCP0MBYTYP4K+2SiGCeMGuyz0aco812PBFwC71UMfU8V038 u7m4sC9TR0D9ciBvfNnaaSn+XxVDQHF8HHCIvZlLIo0zry+YVEAQ6Q0n7aFGyTffYjSJ YsT9Z5IIaPSnTGKJDZTgDB0qacX/fqfieVP3g= MIME-Version: 1.0 X-Received: by 10.52.179.3 with SMTP id dc3mr2901372vdc.74.1361550150480; Fri, 22 Feb 2013 08:22:30 -0800 (PST) Received: by 10.220.145.131 with HTTP; Fri, 22 Feb 2013 08:22:30 -0800 (PST) In-Reply-To: <201302220034.r1M0Y6O8008311@terminus.zytor.com> References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> Date: Fri, 22 Feb 2013 08:22:30 -0800 X-Google-Sender-Auth: nbH_-pnQ2K1dUI4spHtJjNaHXAE Message-ID: Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 From: Linus Torvalds To: "H. Peter Anvin" Cc: "David S. Miller" , "H. Peter Anvin" , "Rafael J. Wysocki" , stable , Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , "Eric W. Biederman" , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Konrad Rzeszutek Wilk , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , Avi Kivity , linux-mips , "linux-pm@vger.kernel.org" , "Michael S. Tsirkin" , sparclinux@vger.kernel.org, virtualization , "Xen-devel@lists.xensource.com" Content-Type: text/plain; charset=UTF-8 X-archive-position: 35806 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: torvalds@linux-foundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1860 Lines: 53 On Thu, Feb 21, 2013 at 4:34 PM, H. Peter Anvin wrote: > > This is a huge set of several partly interrelated (and concurrently > developed) changes, which is why the branch history is messier than > one would like. > > The *really* big items are two humonguous patchsets mostly developed > by Yinghai Lu at my request, which completely revamps the way we > create initial page tables. Ugh. So I've tried to walk through this, and it's painful. If this results in problems, we're going to be *so* screwed. Is it bisectable? I also don't understand how "early_idt_handler" could *possibly* work. In particular, it seems to rely on the trap number being set up in the stack frame: cmpl $14,72(%rsp) # Page fault? but that's not even *true*. Why? Because we export both the early_idt_handlers[] array (that sets up the trap number and makes the stack frame be reliable) and the single early_idt_handler function (that relies on the trap number and the reliable stack frame), AND AFAIK WE USE THE LATTER! See x86_64_start_kernel(): for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) { #ifdef CONFIG_EARLY_PRINTK set_intr_gate(i, &early_idt_handlers[i]); #else set_intr_gate(i, early_idt_handler); #endif } so unless you have CONFIG_EARLY_PRINTK, the interrupt gate will point to that raw early_idt_handler function that doesn't *work* on its own, afaik. Btw, it's not just the page fault index testing that is wrong. The whole cmpl $__KERNEL_CS,96(%rsp) jne 11f also relies on the stack frame being set up the same way for all exceptions - which again is only true if we ran through the early_idt_handlers[] prologue that added the extra stack entry. How does this even work for me? I don't have EARLY_PRINTK enabled. What am I missing? Linus From konrad.wilk@oracle.com Fri Feb 22 17:57:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 17:57:46 +0100 (CET) Received: from aserp1040.oracle.com ([141.146.126.69]:36373 "EHLO aserp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827565Ab3BVQ5phCrFS (ORCPT ); Fri, 22 Feb 2013 17:57:45 +0100 Received: from ucsinet21.oracle.com (ucsinet21.oracle.com [156.151.31.93]) by aserp1040.oracle.com (Sentrion-MTA-4.3.1/Sentrion-MTA-4.3.1) with ESMTP id r1MGteJ5029018 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 22 Feb 2013 16:55:41 GMT Received: from acsmt357.oracle.com (acsmt357.oracle.com [141.146.40.157]) by ucsinet21.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id r1MGtb0U026898 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 22 Feb 2013 16:55:38 GMT Received: from abhmt115.oracle.com (abhmt115.oracle.com [141.146.116.67]) by acsmt357.oracle.com (8.12.11.20060308/8.12.11) with ESMTP id r1MGtaWE031325; Fri, 22 Feb 2013 10:55:36 -0600 Received: from phenom.dumpdata.com (/50.195.21.189) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 22 Feb 2013 08:55:35 -0800 Received: by phenom.dumpdata.com (Postfix, from userid 1000) id 2B90E1C3935; Fri, 22 Feb 2013 11:55:31 -0500 (EST) Date: Fri, 22 Feb 2013 11:55:31 -0500 From: Konrad Rzeszutek Wilk To: "H. Peter Anvin" Cc: Linus Torvalds , "David S. Miller" , "H. Peter Anvin" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 Message-ID: <20130222165531.GA29308@phenom.dumpdata.com> References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201302220034.r1M0Y6O8008311@terminus.zytor.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Source-IP: ucsinet21.oracle.com [156.151.31.93] X-archive-position: 35807 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: konrad.wilk@oracle.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3499 Lines: 76 On Thu, Feb 21, 2013 at 04:34:06PM -0800, H. Peter Anvin wrote: > Hi Linus, > > This is a huge set of several partly interrelated (and concurrently > developed) changes, which is why the branch history is messier than > one would like. > > The *really* big items are two humonguous patchsets mostly developed > by Yinghai Lu at my request, which completely revamps the way we > create initial page tables. In particular, rather than estimating how > much memory we will need for page tables and then build them into that > memory -- a calculation that has shown to be incredibly fragile -- we > now build them (on 64 bits) with the aid of a "pseudo-linear mode" -- > a #PF handler which creates temporary page tables on demand. > > This has several advantages: > > 1. It makes it much easier to support things that need access to > data very early (a followon patchset uses this to load microcode > way early in the kernel startup). > > 2. It allows the kernel and all the kernel data objects to be invoked > from above the 4 GB limit. This allows kdump to work on very large > systems. > > 3. It greatly reduces the difference between Xen and native (Xen's > equivalent of the #PF handler are the temporary page tables created > by the domain builder), eliminating a bunch of fragile hooks. > > The patch series also gets us a bit closer to W^X. > > Additional work in this pull is the 64-bit get_user() work which you > were also involved with, and a bunch of cleanups/speedups to > __phys_addr()/__pa(). Looking at figuring out which of the patches in the branch did this, but with this merge I am getting a crash with a very simple PV guest (booted with one 1G): Call Trace: [] xen_get_user_pgd+0x5a <-- [] xen_get_user_pgd+0x5a [] xen_write_cr3+0x77 [] init_mem_mapping+0x1f9 [] setup_arch+0x742 [] printk+0x48 [] start_kernel+0x90 [] __add_preferred_console.clone.1+0x9b [] x86_64_start_reservations+0x2a [] xen_start_kernel+0x564 And the hypervisor says: (XEN) d7:v0: unhandled page fault (ec=0000) (XEN) Pagetable walk from ffffea000005b2d0: (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff (XEN) domain_crash_sync called from entry.S (XEN) Domain 7 (vcpu#0) crashed on cpu#3: (XEN) ----[ Xen-4.2.0 x86_64 debug=n Not tainted ]---- (XEN) CPU: 3 (XEN) RIP: e033:[] (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest (XEN) rax: ffffea0000000000 rbx: 0000000001a0c000 rcx: 0000000080000000 (XEN) rdx: 000000000005b2a0 rsi: 0000000001a0c000 rdi: 0000000000000000 (XEN) rbp: ffffffff81a01dd8 rsp: ffffffff81a01d90 r8: 0000000000000000 (XEN) r9: 0000000010000001 r10: 0000000000000000 r11: 0000000000000000 (XEN) r12: 0000000000000000 r13: 0000001000000000 r14: 0000000000000000 (XEN) r15: 0000000000100000 cr0: 000000008005003b cr4: 00000000000406f0 (XEN) cr3: 0000000411165000 cr2: ffffea000005b2d0 (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 (XEN) Guest stack trace from rsp=ffffffff81a01d90: (XEN) 0000000080000000 0000000000000000 0000000000000000 ffffffff8103feba (XEN) 000000010000e030 0000000000010006 ffffffff81a01dd8 000000000000e02b What is bizzare is that I do recall testing this (and Stefano also did it). So I am not sure what has altered. From hpa@zytor.com Fri Feb 22 18:17:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 18:17:32 +0100 (CET) Received: from terminus.zytor.com ([198.137.202.10]:41010 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827565Ab3BVRRbG8ejl (ORCPT ); Fri, 22 Feb 2013 18:17:31 +0100 Received: from tazenda.hos.anvin.org ([IPv6:2601:9:3340:26:e269:95ff:fe35:9f3c]) (authenticated bits=0) by mail.zytor.com (8.14.5/8.14.5) with ESMTP id r1MHD24g006576 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO); Fri, 22 Feb 2013 09:13:03 -0800 Message-ID: <5127A719.3060702@zytor.com> Date: Fri, 22 Feb 2013 09:12:57 -0800 From: "H. Peter Anvin" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130110 Thunderbird/17.0.2 MIME-Version: 1.0 To: Konrad Rzeszutek Wilk CC: "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> In-Reply-To: <20130222165531.GA29308@phenom.dumpdata.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35808 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 362 Lines: 14 On 02/22/2013 08:55 AM, Konrad Rzeszutek Wilk wrote: > > What is bizzare is that I do recall testing this (and Stefano also did it). > So I am not sure what has altered. > Yes, there was a very specific reason why I wanted you guys to test it... -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. From konrad.wilk@oracle.com Fri Feb 22 18:25:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 18:25:44 +0100 (CET) Received: from aserp1040.oracle.com ([141.146.126.69]:18134 "EHLO aserp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827568Ab3BVRZloH00L (ORCPT ); Fri, 22 Feb 2013 18:25:41 +0100 Received: from ucsinet21.oracle.com (ucsinet21.oracle.com [156.151.31.93]) by aserp1040.oracle.com (Sentrion-MTA-4.3.1/Sentrion-MTA-4.3.1) with ESMTP id r1MHOD8J031407 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 22 Feb 2013 17:24:14 GMT Received: from acsmt357.oracle.com (acsmt357.oracle.com [141.146.40.157]) by ucsinet21.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id r1MHO9mE000990 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 22 Feb 2013 17:24:10 GMT Received: from abhmt114.oracle.com (abhmt114.oracle.com [141.146.116.66]) by acsmt357.oracle.com (8.12.11.20060308/8.12.11) with ESMTP id r1MHO8CM022422; Fri, 22 Feb 2013 11:24:08 -0600 Received: from phenom.dumpdata.com (/50.195.21.189) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 22 Feb 2013 09:24:08 -0800 Received: by phenom.dumpdata.com (Postfix, from userid 1000) id E7D701C3935; Fri, 22 Feb 2013 12:24:03 -0500 (EST) Date: Fri, 22 Feb 2013 12:24:03 -0500 From: Konrad Rzeszutek Wilk To: "H. Peter Anvin" , yinghai@kernel.org Cc: Linus Torvalds , "David S. Miller" , "H. Peter Anvin" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 Message-ID: <20130222172403.GA17056@phenom.dumpdata.com> References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130222165531.GA29308@phenom.dumpdata.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Source-IP: ucsinet21.oracle.com [156.151.31.93] X-archive-position: 35809 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: konrad.wilk@oracle.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 20808 Lines: 396 On Fri, Feb 22, 2013 at 11:55:31AM -0500, Konrad Rzeszutek Wilk wrote: > On Thu, Feb 21, 2013 at 04:34:06PM -0800, H. Peter Anvin wrote: > > Hi Linus, > > > > This is a huge set of several partly interrelated (and concurrently > > developed) changes, which is why the branch history is messier than > > one would like. > > > > The *really* big items are two humonguous patchsets mostly developed > > by Yinghai Lu at my request, which completely revamps the way we > > create initial page tables. In particular, rather than estimating how > > much memory we will need for page tables and then build them into that > > memory -- a calculation that has shown to be incredibly fragile -- we > > now build them (on 64 bits) with the aid of a "pseudo-linear mode" -- > > a #PF handler which creates temporary page tables on demand. > > > > This has several advantages: > > > > 1. It makes it much easier to support things that need access to > > data very early (a followon patchset uses this to load microcode > > way early in the kernel startup). > > > > 2. It allows the kernel and all the kernel data objects to be invoked > > from above the 4 GB limit. This allows kdump to work on very large > > systems. > > > > 3. It greatly reduces the difference between Xen and native (Xen's > > equivalent of the #PF handler are the temporary page tables created > > by the domain builder), eliminating a bunch of fragile hooks. > > > > The patch series also gets us a bit closer to W^X. > > > > Additional work in this pull is the 64-bit get_user() work which you > > were also involved with, and a bunch of cleanups/speedups to > > __phys_addr()/__pa(). > > Looking at figuring out which of the patches in the branch did this, but > with this merge I am getting a crash with a very simple PV guest (booted with > one 1G): > > Call Trace: > [] xen_get_user_pgd+0x5a <-- > [] xen_get_user_pgd+0x5a > [] xen_write_cr3+0x77 > [] init_mem_mapping+0x1f9 > [] setup_arch+0x742 > [] printk+0x48 > [] start_kernel+0x90 > [] __add_preferred_console.clone.1+0x9b > [] x86_64_start_reservations+0x2a > [] xen_start_kernel+0x564 > > And the hypervisor says: > (XEN) d7:v0: unhandled page fault (ec=0000) > (XEN) Pagetable walk from ffffea000005b2d0: > (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff > (XEN) domain_crash_sync called from entry.S > (XEN) Domain 7 (vcpu#0) crashed on cpu#3: > (XEN) ----[ Xen-4.2.0 x86_64 debug=n Not tainted ]---- > (XEN) CPU: 3 > (XEN) RIP: e033:[] > (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest > (XEN) rax: ffffea0000000000 rbx: 0000000001a0c000 rcx: 0000000080000000 > (XEN) rdx: 000000000005b2a0 rsi: 0000000001a0c000 rdi: 0000000000000000 > (XEN) rbp: ffffffff81a01dd8 rsp: ffffffff81a01d90 r8: 0000000000000000 > (XEN) r9: 0000000010000001 r10: 0000000000000000 r11: 0000000000000000 > (XEN) r12: 0000000000000000 r13: 0000001000000000 r14: 0000000000000000 > (XEN) r15: 0000000000100000 cr0: 000000008005003b cr4: 00000000000406f0 > (XEN) cr3: 0000000411165000 cr2: ffffea000005b2d0 > (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 > (XEN) Guest stack trace from rsp=ffffffff81a01d90: > (XEN) 0000000080000000 0000000000000000 0000000000000000 ffffffff8103feba > (XEN) 000000010000e030 0000000000010006 ffffffff81a01dd8 000000000000e02b Here is a better serial log of the crash (just booting a normal Xen 4.1 + initial kernel with 8GB): PXELINUX 3.82 2009-06-09 Copyright (C) 1994-2009 H. Peter Anvin et al boot: Loading xen.gz... ok Loading vmlinuz... ok Loading initramfs.cpio.gz... ok __ __ _ _ _ ____ \ \/ /___ _ __ | || | / | | ___| _ __ _ __ ___ \ // _ \ '_(_)_(_)____/ | .__/|_| \___| |_| (XEN) Xen version 4.1.5-pre (konrad@dumpdata.com) (gcc version 4.4.4 20100503 (Red Hat 4.4.4-2) (GCC) ) Fri Feb 22 11:37:00 EST 2013 (XEN) Latest ChangeSet: Fri Feb 15 15:31:55 2013 +0100 23459:9f12bdd6b7f0 (XEN) Console output is synchronous. (XEN) Bootloader: unknown (XEN) Command line: cpuinfo conring_size=1048576 sync_console cpufreq=verbose com1=115200,8n1 console=com1,vga loglvl=all guest_loglvl=all (XEN) Video information: (XEN) VGA is text mode 80x25, font 8x16 (XEN) VBE/DDC methods: none; EDID transfer time: 0 seconds (XEN) EDID info not retrieved because no DDC retrieval method detected (XEN) Disc information: (XEN) Found 1 MBR signatures (XEN) Found 1 EDD information structures (XEN) Xen-e820 RAM map: (XEN) 0000000000000000 - 000000000009ec00 (usable) (XEN) 000000000009ec00 - 00000000000a0000 (reserved) (XEN) 00000000000e0000 - 0000000000100000 (reserved) (XEN) 0000000000100000 - 0000000020000000 (usable) (XEN) 0000000020000000 - 0000000020200000 (reserved) (XEN) 0000000020200000 - 0000000040000000 (usable) (XEN) 0000000040000000 - 0000000040200000 (reserved) (XEN) 0000000040200000 - 00000000bad80000 (usable) (XEN) 00000000bad80000 - 00000000badc9000 (ACPI NVS) (XEN) 00000000badc9000 - 00000000badd1000 (ACPI data) (XEN) 00000000badd1000 - 00000000badf4000 (reserved) (XEN) 00000000badf4000 - 00000000badf6000 (usable) (XEN) 00000000badf6000 - 00000000bae06000 (reserved) (XEN) 00000000bae06000 - 00000000bae14000 (ACPI NVS) (XEN) 00000000bae14000 - 00000000bae3c000 (reserved) (XEN) 00000000bae3c000 - 00000000bae7f000 (ACPI NVS) (XEN) 00000000bae7f000 - 00000000bb000000 (usable) (XEN) 00000000bb800000 - 00000000bfa00000 (reserved) (XEN) 00000000fed1c000 - 00000000fed40000 (reserved) (XEN) 00000000ff000000 - 0000000100000000 (reserved) (XEN) 0000000100000000 - 000000023fe00000 (usable) (XEN) ACPI: RSDP 000F0450, 0024 (r2 ALASKA) (XEN) ACPI: XSDT BADC9068, 0054 (r1 ALASKA A M I 1072009 AMI 10013) (XEN) PROC 1 MSFT 3000001) (XEN) ACPI: MCFG BADD0580, 003C (r1 ALASKA A M I 1072009 MSFT 97) (XEN) ACPI: HPET BADD05C0, 0038 (r1 ALASKA A M I 1072009 AMI. 4) (XEN) ACPI: ASF! BADD05F8, 00A0 (r32 INTEL HCG 1 TFSM F4240) (XEN) System RAM: 8104MB (8299140kB) (XEN) No NUMA configuration found (XEN) Faking a node at 0000000000000000-000000023fe00000 (XEN) Domain heap initialised (XEN) found SMP MP-table at 000fcde0 (XEN) DMI 2.7 present. (XEN) Using APIC driver default (XEN) ACPI: PM-Timer IO Port: 0x408 (XEN) ACPI: ACPI SLEEP INFO: pm1x_cnt[404,0], pm1x_evt[400,0] (XEN) ACPI: 32/64X FACS address mismatch in FADT - bae0bf80/0000000000000000, using 32 (XEN) ACPI: wakeup_vec[bae0bf8c], vec_size[20] (XEN) ACPI: Local APIC address 0xfee00000 (XEN) ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled) (XEN) Processor #0 6:10 APIC version 21 (XEN) ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled) (XEN) Processor #2 6:10 APIC version 21 (XEN) ACPI: LAPIC (acpi_id[0x03] lapic_id[0x01] enabled) (XEN) Processor #1 6:10 APIC version 21 (XEN) ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] enabled) (XEN) Processor #3 6:10 APIC version 21 (XEN) ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) (XEN) ACPI: IOAPIC (id[0x00] address[0xfec00000] gsi_base[0]) (XEN) IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23 (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) (XEN) ACPI: IRQ0 used by override. (XEN) ACPI: IRQ2 used by override. (XEN) ACPI: IRQ9 used by override. (XEN) Enabling APIC mode: Flat. Using 1 I/O APICs (XEN) ACPI: HPET id: 0x8086a701 base: 0xfed00000 (XEN) PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 255 (XEN) PCI: Not using MMCONFIG. (XEN) Table is not found! (XEN) Using ACPI (MADT) for SMP configuration information (XEN) IRQ limits: 24 GSI, 760 MSI/MSI-X (XEN) Using scheduler: SMP Credit Scheduler (credit) (XEN) Initializing CPU#0 (XEN) Detected 3093.067 MHz processor. (XEN) Initing memory sharing. (XEN) CPU: Physical Processor ID: 0 (XEN) CPU: Processor Core ID: 0 (XEN) CPU: L1 I cache: 32K, L1 D cache: 32K (XEN) CPU: L2 cache: 256K (XEN) CPU: L3 cache: 3072K (XEN) mce_intel.c:1162: MCA Capability: BCAST 1 SER 0 CMCI 1 firstbank 0 extended MCE MSR 0 (XEN) CPU0: Thermal monitoring enabled (TM1) (XEN) Intel machine check reporting enabled (XEN) I/O virtualisation disabled (XEN) CPU0: Intel(R) Core(TM) i3-2100 CPU @ 3.10GHz stepping 07 (XEN) Enabled directed EOI with ioapic_ack_old on! (XEN) ENABLING IO-APIC IRQs (XEN) -> Using old ACK method (XEN) ..TIMER: vector=0xF0 apic1=0 pin1=2 apic2=-1 pin2=-1 (XEN) TSC deadline timer enabled (XEN) Platform timer is 14.318MHz HPET (XEN) Allocated console ring of 1048576 KiB. (XEN) VMX: Supported advanced features: (isation (XEN) - APIC TPR shadow (XEN) - Extended Page Tables (EPT) (XEN) - Virtual-Processor Identifiers (VPID) (XEN) - Virtual NMI (XEN) - MSR direct-access bitmap (XEN) - Unrestricted Guest (XEN) HVM: ASIDs enabled. (XEN) HVM: VMX enabled (XEN) HVM: Hardware Assisted Paging (HAP) detected (XEN) HVM: HAP page sizes: 4kB, 2MB (XEN) Booting processor 1/1 eip 7c000 (XEN) Initializing CPU#1 (XEN) CPU: Physical Processor ID: 0 (XEN) CPU: Processor Core ID: 0 (XEN) CPU: L1 I cache: 32K, L1 D (XEN) Initializing CPU#2 (XEN) CPU: Physical Processor ID: 0 (XEN) CPU: Processor Core ID: 1 (XEN) CPU: L1 I cache: 32K, L1 D cache: 32K (XEN) CPU: L2 cache: 256K (XEN) CPU: L3 cache: 3072K (XEN) CPU2: Thermal monitoring enabled (TM1) (XEN) CPU2: Intel(R) Core(TM) i3-2100 CPU @ 3.10GHz stepping 07 (XEN) Booting processor 3/3 eip 7c000 (XEN) Initializing CPU#3 (XEN) CPU: Physical Processor ID: 0 (XEN) CPU: Processor Core ID: 1 (XEN) CPU: L1 I cache: 32K, L1 D100 CPU @ 3.10GHz stepping 07 (XEN) Brought up 4 CPUs (XEN) ACPI sleep modes: S3 (XEN) mcheck_poll: Machine check polling timer started. (XEN) *** LOADING DOMAIN 0 *** (XEN) elf_parse_binary: phdr: paddr=0x1000000 memsz=0x9e0000 (XEN) elf_parse_binary: phdr: paddr=0x1a00000 memsz=0xa60f0 (XEN): paddr=0x1abc000 memsz=0x61b000 (XEN) elf_parse_binary: memory: 0x1000000 -> 0x20d7000 (XEN) elf_xen_parse_note: GUEST_OS = "linux" (XEN) elf_xen_parse_note: GUEST_VERSION = "2.6" (XEN) elf_xen_parse_note: XEN_VERSION = "xen-3.0" (XEN) elf_xen_parse_note: VIRT_BASE = 0xffffffff80000000 (XEN) elf_xen_parse_note: ENTRY = 0xffffffff81abc1e0 (XEN) elf_xen_parse_note: HYPERCALL_PAGE = 0xffffffff81001000 (XEN) elf_xen_parse_note: FEATURES = "!writable_page_tables|pae_pgdir_above_4gb" (XEN) elf_xen_parse_note: PAE_MODE = "yes" (XEN) elf_xen_parse_note: LOADER = "generic" (XEN) elf_xen_parse_note: unknown xen elf note (0xd) (XEN) elf_xen_parse_note: SUSPEND_CANCEL = 0x1 (XEN) elf_xen_parse_note: HV_START_LOW = 0xffff800000000000 (XEN) elf_xen_parse_note: PADDR_OFFSET = 0x0 (XEN) elf_xen_addr_calc_check: addresses: (XEN) virt_base = 0xffffffff80000000 (XEN) elf_paddr_offset = 0x0 (XEN) virt_offset = 0xffffffff80000000 (XEN) virt_kstart = 0xffffffff81000000 (XEN) virt_kend = 0xffffffff820d7000 (XEN) virt_entry = 0xffffffff81abc1e0 (XEN) p2m_base = 0xffffffffffffffff (XEN) Xen kernel: 64-bit, lsb, compat32 (XEN) Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x20d7000 (XEN) PHYSICAL MEMORY ARRANGEMENT: (XEN) Dom0 alloc.: 0000000220000000->0000000224000000 (1661249 pages to be allocated) (XEN) Init. ramdisk: 000000022cbdc000->000000023fe00000 (XEN) VIRTUAL MEMORY ARRANGEMENT: (XEN) Loaded kernel: ffffffff81000000->ffffffff820d7000 (XEN) Init. ramdisk: ffffffff820d7000->ffffffff952fb000 (XEN) Phys-Mach map: ffffffff952fb000->ffffffff96060b28 (XEN) Start info: ffffffff96061000->ffffffff960614b4 (XEN) Page tables: ffffffff96062000->ffffffff96117000 (XEN) Boot stack: ffffffff96117000->ffffffff96118000 (XEN) TOTAL: ffffffff80000000->ffffffff96400000 (XEN) ENTRY ADDRESS: ffffffff81abc1e0 (XEN) Dom0 has maximum 4 VCPUs (XEN) elf_load_binary: phdr 0 at 0xffffffff81000000 -> 0xffffffff819e0000 (XEN) elf_load_binary: phdr 1 at 0xffffffff81a00000 -> 0xffffffff81aa60f0 (XEN) elf_load_binary: phdr 2 at 0xffffffff81aa7000 -> 0xffffffff81abbbc0 (XEN) elf_load_binary: phdr 3 at 0xffffffff81abc000 -> 0xffffffff81baf000 (XEN) Scrubbing Free RAM: .done. (XEN) Xen trace buffers: disabled (XEN) Std. Loglevel: All (XEN) Guest Loglevel: All (XEN) ***************************intended to aid debugging of Xen by ensuring (XEN) ******* that all output is synchronously delivered on the serial line. (XEN) ******* However it can introduce SIGNIFICANT latencies and affect (XEN) ******* timekeeping. It is NOT recommended for production use! (XEN) ********************************************** (XEN) 3... 2... 1... (XEN) Xen is relinquishing VGA console. (XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen) (XEN) Freed 224kB init memory. mapping kernel into physical memory about to get started... [ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Linux version 3.8.0upstream-06471-g2ef14f4-dirty (konrad@build.dumpdata.com) (gcc version 4.4.4 20100503 (Red Hat 4.4.4-2) (GCC) ) #1 SMP Fri Feb 22 11:36:48 EST 2013 [ 0.000000] Command line: initcall_debug debug console=hvc0 loglevel=10 xen-pciback.hide=(01:00.0) earlyprintk=xen [ 0.000000] Freeing 9e-100 pfn range: 98 pages freed [ 0.000000] 1-1 mapping on 9e->100 [ 0.000000] Freeing 20000-20200 pfn range: 512 pages freed [ 0.000000] 1-1 mapping on 20000->20200 [ 0.000000] Freeing 40000-40200 pfn range: 512 pages freed [ 0.000000] 1-1 mapping on 40000->40200 [ 0.000000] Freeing bad80-badf4 pfn range: 116 pages freed [ 0.000000] 1-1 mapping on bad80->badf4 [ 0.000000] Freeing badf6-bae7f pfn range: 137 pages freed [ 0.000000] 1-1 mapping on badf6->bae7f [ 0.000000] Freeing bb000-100000 pfn range: 282624 pages freed [ 0.000000] 1-1 mapping on bb000->100000 [ 0.000000] Released 283999 pages of unused memory [ 0.000000] Set 283999 page(s) to 1-1 mapping [ 0.000000] Populating 1acb65-1f20c4 pfn range: 283999 pages added [ 0.000000] e820: BIOS-provided physical RAM map: [ 0.000000] Xen: [mem 0x0000000000000000-0x000000000009dfff] usable [ 0.000000] Xen: [mem 0x000000000009ec00-0x00000000000fffff] reserved [ 0.000000] Xen: [mem 0x0000000000100000-0x000000001fffffff] usable [ 0.000000] Xen: [mem 0x0000000020000000-0x00000000201fffff] reserved [ 0.000000] Xen: [mem 0x0000000020200000-0x000000003fffffff] usable [ 0.000000] Xen: [mem 0x0000000040000000-0x00000000401fffff] reserved [ 0.000000] Xen: [mem 0x0000000040200000-0x00000000bad7ffff] usable [ 0.000000] Xen: [mem 0x00000000bad80000-0x00000000badc8fff] ACPI NVS [ 0.000000] Xen: [mem 0x00000000badc9000-0x00000000badd0fff] ACPI data [ 0.000000] Xen: [mem 0x00000000badd1000-0x00000000badf3fff] reserved [ 0.000000] Xen: [mem 0x00000000badf4000-0x00000000badf5fff] usable [ 0.000000] Xen: [mem 0x00000000badf6000-0x00000000bae05fff] reserved [ 0.000000] Xen: [mem 0x00000000bae06000-0x00000000bae13fff] ACPI NVS [ 0.000000] Xen: [mem 0x00000000bae14000-0x00000000bae3bfff] reserved [ 0.000000] Xen: [mem 0x00000000bae3c000-0x00000000bae7efff] ACPI NVS [ 0.000000] Xen: [mem 0x00000000bae7f000-0x00000000baffffff] usable [ 0.000000] Xen: [mem 0x00000000bb800000-0x00000000bf9fffff] reserved [ 0.000000] Xen: [mem 0x00000000fec00000-0x00000000fec00fff] reserved [ 0.000000] Xen: [mem 0x00000000fed1c000-0x00000000fed3ffff] reserved [ 0.000000] Xen: [mem 0x00000000fee00000-0x00000000fee00fff] reserved [ 0.000000] Xen: [mem 0x00000000ff000000-0x00000000ffffffff] reserved [ 0.000000] Xen: [mem 0x0000000100000000-0x000000023fdfffff] usable [ 0.000000] bootconsole [xenboot0] enabled [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] SMBIOS 2.7 present. [ 0.000000] DMI: MSI MS-7680/H61M-P23 (MS-7680), BIOS V17.0 03/14/2011 [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.000000] No AGP bridge found [ 0.000000] e820: last_pfn = 0x23fe00 max_arch_pfn = 0x400000000 [ 0.000000] e820: lacanning 1 areas for low memory corruption [ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 [ 0.000000] reserving inaccessible SNB gfx pages [ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] [ 0.000000] [mem 0x00000000-0x000fffff] page 4k [ 0.000000] init_memory_mapping: [mem 0x1f2000000-0x1f20c3fff] [ 0.000000] [mem 0x1f2000000-0x1f20c3fff] page 4k [ 0.000000] BRK [0x01cd2000, 0x01cd2fff] PGTABLE [ 0.000000] BRK [0x01cd3000, 0x01cd3fff] PGTABLE [ 0.000000] init_memory_mapping: [mem 0x1f0000000-0x1f1ffffff] [ 0.000000] [mem 0x1f0000000-0x1f1ffffff] page 4k [ 0.000000] BRK [0x01cd4000, 0x01cd4fff] PGTABLE [ 0.000000] BRK [0x01cd5000, 0x01cd5fff] PGTABLE [ 0.000000] BRK [0x01cd6000, 0x01cd6fff] PGTABLE [ 0.000000] init_memory_mapping: [mem 0x180000000-0x1efffffff] [ 0.000000] [mem 0x180000000-0x1efffffff] page 4k [ 0.000000] init_memory_mapping: [mem 0x00100000-0x1fffffff] [ 0.000000] [mem 0x00100000-0x1fffffff] page 4k [ 0.000000] init_memory_mapping: [mem 0x20200000-0x3fffffff] [ 0.000000] [mem 0x20200000-0x3fffffff] page 4k [ 0.000000] init_memory_mapping: [mem 0x40200000-0xbad7ffff] [ 0.000000] [mem 0x40200000-0xbad7ffff] page 4k [ 0.000000] init_memory_mapping: [mem 0xbadf4000-0xbadf5fff] [ 0.000000] [mem 0xbadf4000-0xbadf5fff] page 4k [ 0.000000] init_memory_mapping: [mem 0xbae7f000-0xbaffffff] [ 0.000000] [mem 0xbae7f000-0xbaffffff] page 4k [ 0.000000] init_memory_mapping: [mem 0x100000000-0x17fffffff] [ 0.000000] [mem 0x100000000-0x17fffffff] page 4k [ 0.000000] init_memory_mapping: [mem 0x1f20c4000-0x23fdfffff] [ 0.000000] [mem 0x1f20c4000-0x23fdfffff] page 4k (XEN) d0:v0: unhandled page fault (ec=0000) (XEN) Pagetable walk from ffffea000005b2d0: (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff (XEN) domain_crash_sync called from entry.S (XEN) Domain 0 (vcpu#0) crashed on cpu#0: (XEN) ----[ Xen-4.1.5-pre x86_64 debug=y Tainted: C ]---- (XEN) CPU: 0 (XEN) RIP: e033:[] (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest (XEN) rax: ffffea0000000000 rbx: 0000000001a0c000 rcx: 0000000080000000 (XEN) rdx: 000000000005b2a0 rsi: 0000000001a0c000 rdi: 0000000000000000 (XEN) rbp: ffffffff81a01dd8 rsp: ffffffff81a01d90 r8: 0000000000000000 (XEN) r9: 0000000010000001 r10: 0000000000000005 r11: 0000000000100000 (XEN) r12: 0000000000000000 r13: 0000020000000000 r14: 0000000000000000 (XEN) r15: 0000000000100000 cr0: 000000008005003b cr4: 00000000000026f0 (XEN) cr3: 0000000221a0c000 cr2: ffffea000005b2d0 (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 (XEN) Guest stack trace from rsp=ffffffff81a01d90: (XEN) 0000000080000000 0000000000100000 0000000000000000 ffffffff8103feba (XEN) 000000010000e030 0000000000010006 ffffffff81a01dd8 000000000000e02b (XEN) 0000000000000000 ffffffff81a01e08 ffffffff81042d27 000000023fe00000 (XEN) 00000001f20c4000 0000020000000000 00000001acac7000 ffffffff81a01e48 (XEN) ffffffff81ad2d21 0000000000000000 0000000000000028 0000000040004000 (XEN) 0000000000000000 0000000000000000 0000000000000000 ffffffff81a01ed8 (XEN) ffffffff81ac293f ffffffff81b46900 0000000000000000 0000000000000000 (XEN) 0000000000000000 ffffffff81a01f00 ffffffff8165fbd1 ffffffff00000010 (XEN) ffffffff81a01ee8 ffffffff81a01ea8 0000000000000000 ffffffff81a01ec8 (XEN) ffffffffffffffff ffffffff81b46900 0000000000000000 0000000000000000 (XEN) 0000000000000000 ffffffff81a01f28 ffffffff81abcd62 ffffffff96062000 (XEN) ffffffff81cc6000 ffffffff81ccd000 ffffffff81b4f2e0 0000000000000000 (XEN) 0000000000000000 0000000000000000 0000000000000000 ffffffff81a01f38 (XEN) ffffffff81abc5f7 ffffffff81a01ff8 ffffffff81abf0c7 0300000100000032 (XEN) 0000000000000005 0000000000000000 0000000000000000 0000000000000000 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 (XEN) 0000000000000000 819822831fc9cbf5 000206a700100800 0000000000000001 (XEN) 0000000000000000 0000000000000000 0f00000060c0c748 ccccccccccccc305 (XEN) Domain 0 crashed: rebooting machine in 5 seconds. (XEN) Resetting with ACPI MEMORY or I/O RESET_REG. From hpa@zytor.com Fri Feb 22 18:32:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 18:32:42 +0100 (CET) Received: from terminus.zytor.com ([198.137.202.10]:41201 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827568Ab3BVRckxQ1E- (ORCPT ); Fri, 22 Feb 2013 18:32:40 +0100 Received: from tazenda.hos.anvin.org ([IPv6:2601:9:3340:26:e269:95ff:fe35:9f3c]) (authenticated bits=0) by mail.zytor.com (8.14.5/8.14.5) with ESMTP id r1MHUDNJ011902 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO); Fri, 22 Feb 2013 09:30:13 -0800 Message-ID: <5127AB1F.1030407@zytor.com> Date: Fri, 22 Feb 2013 09:30:07 -0800 From: "H. Peter Anvin" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130110 Thunderbird/17.0.2 MIME-Version: 1.0 To: Konrad Rzeszutek Wilk CC: "H. Peter Anvin" , yinghai@kernel.org, Linus Torvalds , "David S. Miller" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= , Yasuaki Ishimatsu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <20130222172403.GA17056@phenom.dumpdata.com> In-Reply-To: <20130222172403.GA17056@phenom.dumpdata.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35810 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 474 Lines: 16 On 02/22/2013 09:24 AM, Konrad Rzeszutek Wilk wrote: > > Here is a better serial log of the crash (just booting a normal Xen 4.1 + initial > kernel with 8GB): > Configuration, please, especially: is early_printk compiled in? Also, since this is Xen-related we really need your help on this. A lot of this is not going to be meaningful to non-Xen people. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. From hpa@zytor.com Fri Feb 22 18:35:37 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 18:35:38 +0100 (CET) Received: from terminus.zytor.com ([198.137.202.10]:41284 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827586Ab3BVRfhef9Oy (ORCPT ); Fri, 22 Feb 2013 18:35:37 +0100 Received: from tazenda.hos.anvin.org ([IPv6:2601:9:3340:26:e269:95ff:fe35:9f3c]) (authenticated bits=0) by mail.zytor.com (8.14.5/8.14.5) with ESMTP id r1MHVWRV012019 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO); Fri, 22 Feb 2013 09:31:32 -0800 Message-ID: <5127AB6F.3060806@zytor.com> Date: Fri, 22 Feb 2013 09:31:27 -0800 From: "H. Peter Anvin" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130110 Thunderbird/17.0.2 MIME-Version: 1.0 To: Linus Torvalds CC: "H. Peter Anvin" , "David S. Miller" , "Rafael J. Wysocki" , stable , Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , "Eric W. Biederman" , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Konrad Rzeszutek Wilk , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , Avi Kivity , linux-mips , "linux-pm@vger.kernel.org" , "Michael S. Tsirkin" , sparclinux@vger.kernel.org, virtualization , "Xen-devel@lists.xensource.com" Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35811 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2709 Lines: 72 On 02/22/2013 08:22 AM, Linus Torvalds wrote: > > Ugh. So I've tried to walk through this, and it's painful. If this > results in problems, we're going to be *so* screwed. Is it bisectable? > I can't tell you for sure that it is bisectable at every point. There are definite bisection points in there, though, as this is several pieces of work from two kernel cycles that were independently tested. > I also don't understand how "early_idt_handler" could *possibly* work. > In particular, it seems to rely on the trap number being set up in the > stack frame: > > cmpl $14,72(%rsp) # Page fault? > > but that's not even *true*. Why? Because we export both the > early_idt_handlers[] array (that sets up the trap number and makes the > stack frame be reliable) and the single early_idt_handler function > (that relies on the trap number and the reliable stack frame), AND > AFAIK WE USE THE LATTER! > > See x86_64_start_kernel(): > > for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) { > #ifdef CONFIG_EARLY_PRINTK > set_intr_gate(i, &early_idt_handlers[i]); > #else > set_intr_gate(i, early_idt_handler); > #endif > } > > so unless you have CONFIG_EARLY_PRINTK, the interrupt gate will point > to that raw early_idt_handler function that doesn't *work* on its own, > afaik. > This is a (pre-existing!) bug that absolutely needs to be fixed, which ought to break other things too (early use of *msr_safe for example, or anything else that relies on an early exception entry, which there aren't a lot of so far). The fix is simple and obvious. But you're right... what the heck is going on here? My own testing would probably not have caught this, as I consider EARLY_PRINTK a must have, but Ingo's test machines definitely would have. > Btw, it's not just the page fault index testing that is wrong. The whole > > cmpl $__KERNEL_CS,96(%rsp) > jne 11f > > also relies on the stack frame being set up the same way for all > exceptions - which again is only true if we ran through the > early_idt_handlers[] prologue that added the extra stack entry. > > How does this even work for me? I don't have EARLY_PRINTK enabled. > > What am I missing? I just ran a simulation without EARLY_PRINTK, presumably based on the memory layout, we can apparently go through the entire bootup sequence without actually ever taking an early trap. It is a bug, though, and it is a bug even without this patchset. I will submit a fix. However, the Xen "we tested this, this worked, now it doesn't" worries me a lot. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. From hpa@zytor.com Fri Feb 22 18:36:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 18:36:52 +0100 (CET) Received: from terminus.zytor.com ([198.137.202.10]:41315 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827576Ab3BVRgvE1y8r (ORCPT ); Fri, 22 Feb 2013 18:36:51 +0100 Received: from tazenda.hos.anvin.org ([IPv6:2601:9:3340:26:e269:95ff:fe35:9f3c]) (authenticated bits=0) by mail.zytor.com (8.14.5/8.14.5) with ESMTP id r1MHXdwS012535 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO); Fri, 22 Feb 2013 09:33:39 -0800 Message-ID: <5127ABEE.8080303@zytor.com> Date: Fri, 22 Feb 2013 09:33:34 -0800 From: "H. Peter Anvin" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130110 Thunderbird/17.0.2 MIME-Version: 1.0 To: Dave Hansen CC: Konrad Rzeszutek Wilk , "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <5127AB34.8090406@linux.vnet.ibm.com> In-Reply-To: <5127AB34.8090406@linux.vnet.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 35812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1229 Lines: 39 On 02/22/2013 09:30 AM, Dave Hansen wrote: > > Do you have CONFIG_DEBUG_VIRTUAL on? > > You're probably hitting the new BUG_ON() in __phys_addr(). It's > intended to detect places where someone is doing a __pa()/__phys_addr() > on an address that's outside the kernel's identity mapping. > > There are a lot of __pa() calls around there, but from the looks of it, > it's this code: > > static pgd_t *xen_get_user_pgd(pgd_t *pgd) > { > ... > if (offset < pgd_index(USER_LIMIT)) { > struct page *page = virt_to_page(pgd_page); > > I'm a bit fuzzy on exactly what the code is trying to do here. It could > mean either that the identity mapping isn't set up enough yet, or that > __pa() is getting called on a bogus address. > > I'm especially fuzzy on why we'd be calling anything that's looking at > userspace pagetables (xen_get_user_pgd() ??) this early in boot. > Ah yes, of course. This is unrelated to the early page table setups, which is why it didn't trip in Konrad's earlier testing. This debugging bits has already found real bugs in the kernel, and this might be another. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. From konrad.wilk@oracle.com Fri Feb 22 18:39:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 18:39:30 +0100 (CET) Received: from userp1040.oracle.com ([156.151.31.81]:45986 "EHLO userp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827576Ab3BVRj3D0LW0 (ORCPT ); Fri, 22 Feb 2013 18:39:29 +0100 Received: from ucsinet21.oracle.com (ucsinet21.oracle.com [156.151.31.93]) by userp1040.oracle.com (Sentrion-MTA-4.3.1/Sentrion-MTA-4.3.1) with ESMTP id r1MHcEIr014128 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 22 Feb 2013 17:38:15 GMT Received: from acsmt356.oracle.com (acsmt356.oracle.com [141.146.40.156]) by ucsinet21.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id r1MHcCoQ001862 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 22 Feb 2013 17:38:12 GMT Received: from abhmt109.oracle.com (abhmt109.oracle.com [141.146.116.61]) by acsmt356.oracle.com (8.12.11.20060308/8.12.11) with ESMTP id r1MHcAQ8005390; Fri, 22 Feb 2013 11:38:10 -0600 Received: from phenom.dumpdata.com (/50.195.21.189) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 22 Feb 2013 09:38:10 -0800 Received: by phenom.dumpdata.com (Postfix, from userid 1000) id B5AA41C3935; Fri, 22 Feb 2013 12:38:05 -0500 (EST) Date: Fri, 22 Feb 2013 12:38:05 -0500 From: Konrad Rzeszutek Wilk To: "H. Peter Anvin" Cc: "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 Message-ID: <20130222173805.GC7768@phenom.dumpdata.com> References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <5127A719.3060702@zytor.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5127A719.3060702@zytor.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Source-IP: ucsinet21.oracle.com [156.151.31.93] X-archive-position: 35813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: konrad.wilk@oracle.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1042 Lines: 24 On Fri, Feb 22, 2013 at 09:12:57AM -0800, H. Peter Anvin wrote: > On 02/22/2013 08:55 AM, Konrad Rzeszutek Wilk wrote: > > > >What is bizzare is that I do recall testing this (and Stefano also did it). > >So I am not sure what has altered. > > > > Yes, there was a very specific reason why I wanted you guys to test it... Exactly. And I re-ran the same test, but with a new kernel. This is what git reflog tells me: 473cd24 HEAD@{75}: checkout: moving from 08f321ed97353cf3b3fafa6b1c1971d6a8970830 to linux-next 08f321e HEAD@{76}: checkout: moving from linux-next to yinghai/for-x86-mm eb827a7 HEAD@{77}: checkout: moving from 1b66ccf15ff4bd0200567e8d70446a8763f96ee7 to linux-next [konrad@build linux]$ git show 08f321e commit 08f321ed97353cf3b3fafa6b1c1971d6a8970830 Author: Yinghai Lu Date: Thu Nov 8 00:00:19 2012 -0800 mm: Kill NO_BOOTMEM version free_all_bootmem_node() And I recall Stefano later on testing (I was in a conference and did not have the opportunity to test it). Not sure what he ran with. From dave@linux.vnet.ibm.com Fri Feb 22 18:46:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 18:46:16 +0100 (CET) Received: from e39.co.us.ibm.com ([32.97.110.160]:58315 "EHLO e39.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827576Ab3BVRqOyOac1 (ORCPT ); Fri, 22 Feb 2013 18:46:14 +0100 Received: from /spool/local by e39.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 22 Feb 2013 10:46:07 -0700 Received: from d03dlp02.boulder.ibm.com (9.17.202.178) by e39.co.us.ibm.com (192.168.1.139) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 22 Feb 2013 10:46:05 -0700 Received: from d03relay04.boulder.ibm.com (d03relay04.boulder.ibm.com [9.17.195.106]) by d03dlp02.boulder.ibm.com (Postfix) with ESMTP id D82123E40040; Fri, 22 Feb 2013 10:45:55 -0700 (MST) Received: from d03av03.boulder.ibm.com (d03av03.boulder.ibm.com [9.17.195.169]) by d03relay04.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r1MHiVjW154482; Fri, 22 Feb 2013 10:46:04 -0700 Received: from d03av03.boulder.ibm.com (loopback [127.0.0.1]) by d03av03.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r1MHdDhE032706; Fri, 22 Feb 2013 10:39:27 -0700 Received: from kernel.stglabs.ibm.com (kernel.stglabs.ibm.com [9.114.214.19]) by d03av03.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r1MHd9qx031972; Fri, 22 Feb 2013 10:39:09 -0700 Received: from [9.65.132.22] (sig-9-65-132-22.mts.ibm.com [9.65.132.22]) by kernel.stglabs.ibm.com (Postfix) with SMTP id 712E924028D; Fri, 22 Feb 2013 09:30:30 -0800 (PST) Message-ID: <5127AB34.8090406@linux.vnet.ibm.com> Date: Fri, 22 Feb 2013 09:30:28 -0800 From: Dave Hansen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Konrad Rzeszutek Wilk CC: "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "H. Peter Anvin" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> In-Reply-To: <20130222165531.GA29308@phenom.dumpdata.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13022217-3620-0000-0000-0000015836C2 X-archive-position: 35814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dave@linux.vnet.ibm.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3098 Lines: 74 On 02/22/2013 08:55 AM, Konrad Rzeszutek Wilk wrote: > On Thu, Feb 21, 2013 at 04:34:06PM -0800, H. Peter Anvin wrote: >> Hi Linus, >> >> This is a huge set of several partly interrelated (and concurrently >> developed) changes, which is why the branch history is messier than >> one would like. >> >> The *really* big items are two humonguous patchsets mostly developed >> by Yinghai Lu at my request, which completely revamps the way we >> create initial page tables. In particular, rather than estimating how >> much memory we will need for page tables and then build them into that >> memory -- a calculation that has shown to be incredibly fragile -- we >> now build them (on 64 bits) with the aid of a "pseudo-linear mode" -- >> a #PF handler which creates temporary page tables on demand. >> >> This has several advantages: >> >> 1. It makes it much easier to support things that need access to >> data very early (a followon patchset uses this to load microcode >> way early in the kernel startup). >> >> 2. It allows the kernel and all the kernel data objects to be invoked >> from above the 4 GB limit. This allows kdump to work on very large >> systems. >> >> 3. It greatly reduces the difference between Xen and native (Xen's >> equivalent of the #PF handler are the temporary page tables created >> by the domain builder), eliminating a bunch of fragile hooks. >> >> The patch series also gets us a bit closer to W^X. >> >> Additional work in this pull is the 64-bit get_user() work which you >> were also involved with, and a bunch of cleanups/speedups to >> __phys_addr()/__pa(). > > Looking at figuring out which of the patches in the branch did this, but > with this merge I am getting a crash with a very simple PV guest (booted with > one 1G): > > Call Trace: > [] xen_get_user_pgd+0x5a <-- > [] xen_get_user_pgd+0x5a > [] xen_write_cr3+0x77 > [] init_mem_mapping+0x1f9 > [] setup_arch+0x742 > [] printk+0x48 > [] start_kernel+0x90 > [] __add_preferred_console.clone.1+0x9b > [] x86_64_start_reservations+0x2a > [] xen_start_kernel+0x564 Do you have CONFIG_DEBUG_VIRTUAL on? You're probably hitting the new BUG_ON() in __phys_addr(). It's intended to detect places where someone is doing a __pa()/__phys_addr() on an address that's outside the kernel's identity mapping. There are a lot of __pa() calls around there, but from the looks of it, it's this code: static pgd_t *xen_get_user_pgd(pgd_t *pgd) { ... if (offset < pgd_index(USER_LIMIT)) { struct page *page = virt_to_page(pgd_page); I'm a bit fuzzy on exactly what the code is trying to do here. It could mean either that the identity mapping isn't set up enough yet, or that __pa() is getting called on a bogus address. I'm especially fuzzy on why we'd be calling anything that's looking at userspace pagetables (xen_get_user_pgd() ??) this early in boot. From yinghai@kernel.org Fri Feb 22 18:53:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 18:53:14 +0100 (CET) Received: from mail-ie0-f170.google.com ([209.85.223.170]:59893 "EHLO mail-ie0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827576Ab3BVRxLW4tKS (ORCPT ); Fri, 22 Feb 2013 18:53:11 +0100 Received: by mail-ie0-f170.google.com with SMTP id c11so1037348ieb.1 for ; Fri, 22 Feb 2013 09:53:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=8f6j8iLpIG3zT5eiJK3fuUFAYJwHJmuVHYnSTwjeQQg=; b=h/+y2on2H2jja84COrXlpe7//ClYZnHRwVcOQPwLlhyd+Qw+VERTlRDdfhZh364rXp iRApKmE6KvByx2FRi0RS2xTp0vpJjdiJDlz7jDfa1o+oI23tyztHwKJ4srUopaHEr8kT iGNlM2TaxqTC8X2Q3uZnretwPB9RBCo2K/vDeCqHC+U7/9keE0lhQLlc0KRzijnGKJRm JB+n59lXonYrYIEDBiJ3OZE9e66KEm+GjMiunSXQevX1m/Pq6p6OXgL6TcKTyrWBlMFo lpx6Gj/OOfNMdHAjBnZ0sqlGmplhZDdEzwpxNJt4e6bgrzoxtnPxwKpuRG+94UjOFRHF QB7A== MIME-Version: 1.0 X-Received: by 10.50.197.131 with SMTP id iu3mr15326530igc.109.1361555584360; Fri, 22 Feb 2013 09:53:04 -0800 (PST) Received: by 10.64.33.203 with HTTP; Fri, 22 Feb 2013 09:53:04 -0800 (PST) In-Reply-To: <20130222172403.GA17056@phenom.dumpdata.com> References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <20130222172403.GA17056@phenom.dumpdata.com> Date: Fri, 22 Feb 2013 09:53:04 -0800 X-Google-Sender-Auth: id8MzEWj1Jum5e4cIb5THdgo6aw Message-ID: Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 From: Yinghai Lu To: Konrad Rzeszutek Wilk Cc: "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "H. Peter Anvin" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= , Yasuaki Ishimatsu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yinghai@kernel.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 21630 Lines: 404 On Fri, Feb 22, 2013 at 9:24 AM, Konrad Rzeszutek Wilk wrote: > On Fri, Feb 22, 2013 at 11:55:31AM -0500, Konrad Rzeszutek Wilk wrote: >> On Thu, Feb 21, 2013 at 04:34:06PM -0800, H. Peter Anvin wrote: >> > Hi Linus, >> > >> > This is a huge set of several partly interrelated (and concurrently >> > developed) changes, which is why the branch history is messier than >> > one would like. >> > >> > The *really* big items are two humonguous patchsets mostly developed >> > by Yinghai Lu at my request, which completely revamps the way we >> > create initial page tables. In particular, rather than estimating how >> > much memory we will need for page tables and then build them into that >> > memory -- a calculation that has shown to be incredibly fragile -- we >> > now build them (on 64 bits) with the aid of a "pseudo-linear mode" -- >> > a #PF handler which creates temporary page tables on demand. >> > >> > This has several advantages: >> > >> > 1. It makes it much easier to support things that need access to >> > data very early (a followon patchset uses this to load microcode >> > way early in the kernel startup). >> > >> > 2. It allows the kernel and all the kernel data objects to be invoked >> > from above the 4 GB limit. This allows kdump to work on very large >> > systems. >> > >> > 3. It greatly reduces the difference between Xen and native (Xen's >> > equivalent of the #PF handler are the temporary page tables created >> > by the domain builder), eliminating a bunch of fragile hooks. >> > >> > The patch series also gets us a bit closer to W^X. >> > >> > Additional work in this pull is the 64-bit get_user() work which you >> > were also involved with, and a bunch of cleanups/speedups to >> > __phys_addr()/__pa(). >> >> Looking at figuring out which of the patches in the branch did this, but >> with this merge I am getting a crash with a very simple PV guest (booted with >> one 1G): >> >> Call Trace: >> [] xen_get_user_pgd+0x5a <-- >> [] xen_get_user_pgd+0x5a >> [] xen_write_cr3+0x77 >> [] init_mem_mapping+0x1f9 >> [] setup_arch+0x742 >> [] printk+0x48 >> [] start_kernel+0x90 >> [] __add_preferred_console.clone.1+0x9b >> [] x86_64_start_reservations+0x2a >> [] xen_start_kernel+0x564 >> >> And the hypervisor says: >> (XEN) d7:v0: unhandled page fault (ec=0000) >> (XEN) Pagetable walk from ffffea000005b2d0: >> (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff >> (XEN) domain_crash_sync called from entry.S >> (XEN) Domain 7 (vcpu#0) crashed on cpu#3: >> (XEN) ----[ Xen-4.2.0 x86_64 debug=n Not tainted ]---- >> (XEN) CPU: 3 >> (XEN) RIP: e033:[] >> (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest >> (XEN) rax: ffffea0000000000 rbx: 0000000001a0c000 rcx: 0000000080000000 >> (XEN) rdx: 000000000005b2a0 rsi: 0000000001a0c000 rdi: 0000000000000000 >> (XEN) rbp: ffffffff81a01dd8 rsp: ffffffff81a01d90 r8: 0000000000000000 >> (XEN) r9: 0000000010000001 r10: 0000000000000000 r11: 0000000000000000 >> (XEN) r12: 0000000000000000 r13: 0000001000000000 r14: 0000000000000000 >> (XEN) r15: 0000000000100000 cr0: 000000008005003b cr4: 00000000000406f0 >> (XEN) cr3: 0000000411165000 cr2: ffffea000005b2d0 >> (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 >> (XEN) Guest stack trace from rsp=ffffffff81a01d90: >> (XEN) 0000000080000000 0000000000000000 0000000000000000 ffffffff8103feba >> (XEN) 000000010000e030 0000000000010006 ffffffff81a01dd8 000000000000e02b > > Here is a better serial log of the crash (just booting a normal Xen 4.1 + initial > kernel with 8GB): > > PXELINUX 3.82 2009-06-09 Copyright (C) 1994-2009 H. Peter Anvin et al > boot: > Loading xen.gz... ok > Loading vmlinuz... ok > Loading initramfs.cpio.gz... ok > __ __ _ _ _ ____ > \ \/ /___ _ __ | || | / | | ___| _ __ _ __ ___ > \ // _ \ '_(_)_(_)____/ | .__/|_| \___| > |_| > (XEN) Xen version 4.1.5-pre (konrad@dumpdata.com) (gcc version 4.4.4 20100503 (Red Hat 4.4.4-2) (GCC) ) Fri Feb 22 11:37:00 EST 2013 > (XEN) Latest ChangeSet: Fri Feb 15 15:31:55 2013 +0100 23459:9f12bdd6b7f0 > (XEN) Console output is synchronous. > (XEN) Bootloader: unknown > (XEN) Command line: cpuinfo conring_size=1048576 sync_console cpufreq=verbose com1=115200,8n1 console=com1,vga loglvl=all guest_loglvl=all > (XEN) Video information: > (XEN) VGA is text mode 80x25, font 8x16 > (XEN) VBE/DDC methods: none; EDID transfer time: 0 seconds > (XEN) EDID info not retrieved because no DDC retrieval method detected > (XEN) Disc information: > (XEN) Found 1 MBR signatures > (XEN) Found 1 EDD information structures > (XEN) Xen-e820 RAM map: > (XEN) 0000000000000000 - 000000000009ec00 (usable) > (XEN) 000000000009ec00 - 00000000000a0000 (reserved) > (XEN) 00000000000e0000 - 0000000000100000 (reserved) > (XEN) 0000000000100000 - 0000000020000000 (usable) > (XEN) 0000000020000000 - 0000000020200000 (reserved) > (XEN) 0000000020200000 - 0000000040000000 (usable) > (XEN) 0000000040000000 - 0000000040200000 (reserved) > (XEN) 0000000040200000 - 00000000bad80000 (usable) > (XEN) 00000000bad80000 - 00000000badc9000 (ACPI NVS) > (XEN) 00000000badc9000 - 00000000badd1000 (ACPI data) > (XEN) 00000000badd1000 - 00000000badf4000 (reserved) > (XEN) 00000000badf4000 - 00000000badf6000 (usable) > (XEN) 00000000badf6000 - 00000000bae06000 (reserved) > (XEN) 00000000bae06000 - 00000000bae14000 (ACPI NVS) > (XEN) 00000000bae14000 - 00000000bae3c000 (reserved) > (XEN) 00000000bae3c000 - 00000000bae7f000 (ACPI NVS) > (XEN) 00000000bae7f000 - 00000000bb000000 (usable) > (XEN) 00000000bb800000 - 00000000bfa00000 (reserved) > (XEN) 00000000fed1c000 - 00000000fed40000 (reserved) > (XEN) 00000000ff000000 - 0000000100000000 (reserved) > (XEN) 0000000100000000 - 000000023fe00000 (usable) > (XEN) ACPI: RSDP 000F0450, 0024 (r2 ALASKA) > (XEN) ACPI: XSDT BADC9068, 0054 (r1 ALASKA A M I 1072009 AMI 10013) > (XEN) PROC 1 MSFT 3000001) > (XEN) ACPI: MCFG BADD0580, 003C (r1 ALASKA A M I 1072009 MSFT 97) > (XEN) ACPI: HPET BADD05C0, 0038 (r1 ALASKA A M I 1072009 AMI. 4) > (XEN) ACPI: ASF! BADD05F8, 00A0 (r32 INTEL HCG 1 TFSM F4240) > (XEN) System RAM: 8104MB (8299140kB) > (XEN) No NUMA configuration found > (XEN) Faking a node at 0000000000000000-000000023fe00000 > (XEN) Domain heap initialised > (XEN) found SMP MP-table at 000fcde0 > (XEN) DMI 2.7 present. > (XEN) Using APIC driver default > (XEN) ACPI: PM-Timer IO Port: 0x408 > (XEN) ACPI: ACPI SLEEP INFO: pm1x_cnt[404,0], pm1x_evt[400,0] > (XEN) ACPI: 32/64X FACS address mismatch in FADT - bae0bf80/0000000000000000, using 32 > (XEN) ACPI: wakeup_vec[bae0bf8c], vec_size[20] > (XEN) ACPI: Local APIC address 0xfee00000 > (XEN) ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled) > (XEN) Processor #0 6:10 APIC version 21 > (XEN) ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled) > (XEN) Processor #2 6:10 APIC version 21 > (XEN) ACPI: LAPIC (acpi_id[0x03] lapic_id[0x01] enabled) > (XEN) Processor #1 6:10 APIC version 21 > (XEN) ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] enabled) > (XEN) Processor #3 6:10 APIC version 21 > (XEN) ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) > (XEN) ACPI: IOAPIC (id[0x00] address[0xfec00000] gsi_base[0]) > (XEN) IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23 > (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) > (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) > (XEN) ACPI: IRQ0 used by override. > (XEN) ACPI: IRQ2 used by override. > (XEN) ACPI: IRQ9 used by override. > (XEN) Enabling APIC mode: Flat. Using 1 I/O APICs > (XEN) ACPI: HPET id: 0x8086a701 base: 0xfed00000 > (XEN) PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 255 > (XEN) PCI: Not using MMCONFIG. > (XEN) Table is not found! > (XEN) Using ACPI (MADT) for SMP configuration information > (XEN) IRQ limits: 24 GSI, 760 MSI/MSI-X > (XEN) Using scheduler: SMP Credit Scheduler (credit) > (XEN) Initializing CPU#0 > (XEN) Detected 3093.067 MHz processor. > (XEN) Initing memory sharing. > (XEN) CPU: Physical Processor ID: 0 > (XEN) CPU: Processor Core ID: 0 > (XEN) CPU: L1 I cache: 32K, L1 D cache: 32K > (XEN) CPU: L2 cache: 256K > (XEN) CPU: L3 cache: 3072K > (XEN) mce_intel.c:1162: MCA Capability: BCAST 1 SER 0 CMCI 1 firstbank 0 extended MCE MSR 0 > (XEN) CPU0: Thermal monitoring enabled (TM1) > (XEN) Intel machine check reporting enabled > (XEN) I/O virtualisation disabled > (XEN) CPU0: Intel(R) Core(TM) i3-2100 CPU @ 3.10GHz stepping 07 > (XEN) Enabled directed EOI with ioapic_ack_old on! > (XEN) ENABLING IO-APIC IRQs > (XEN) -> Using old ACK method > (XEN) ..TIMER: vector=0xF0 apic1=0 pin1=2 apic2=-1 pin2=-1 > (XEN) TSC deadline timer enabled > (XEN) Platform timer is 14.318MHz HPET > (XEN) Allocated console ring of 1048576 KiB. > (XEN) VMX: Supported advanced features: > (isation > (XEN) - APIC TPR shadow > (XEN) - Extended Page Tables (EPT) > (XEN) - Virtual-Processor Identifiers (VPID) > (XEN) - Virtual NMI > (XEN) - MSR direct-access bitmap > (XEN) - Unrestricted Guest > (XEN) HVM: ASIDs enabled. > (XEN) HVM: VMX enabled > (XEN) HVM: Hardware Assisted Paging (HAP) detected > (XEN) HVM: HAP page sizes: 4kB, 2MB > (XEN) Booting processor 1/1 eip 7c000 > (XEN) Initializing CPU#1 > (XEN) CPU: Physical Processor ID: 0 > (XEN) CPU: Processor Core ID: 0 > (XEN) CPU: L1 I cache: 32K, L1 D > (XEN) Initializing CPU#2 > (XEN) CPU: Physical Processor ID: 0 > (XEN) CPU: Processor Core ID: 1 > (XEN) CPU: L1 I cache: 32K, L1 D cache: 32K > (XEN) CPU: L2 cache: 256K > (XEN) CPU: L3 cache: 3072K > (XEN) CPU2: Thermal monitoring enabled (TM1) > (XEN) CPU2: Intel(R) Core(TM) i3-2100 CPU @ 3.10GHz stepping 07 > (XEN) Booting processor 3/3 eip 7c000 > (XEN) Initializing CPU#3 > (XEN) CPU: Physical Processor ID: 0 > (XEN) CPU: Processor Core ID: 1 > (XEN) CPU: L1 I cache: 32K, L1 D100 CPU @ 3.10GHz stepping 07 > (XEN) Brought up 4 CPUs > (XEN) ACPI sleep modes: S3 > (XEN) mcheck_poll: Machine check polling timer started. > (XEN) *** LOADING DOMAIN 0 *** > (XEN) elf_parse_binary: phdr: paddr=0x1000000 memsz=0x9e0000 > (XEN) elf_parse_binary: phdr: paddr=0x1a00000 memsz=0xa60f0 > (XEN): paddr=0x1abc000 memsz=0x61b000 > (XEN) elf_parse_binary: memory: 0x1000000 -> 0x20d7000 > (XEN) elf_xen_parse_note: GUEST_OS = "linux" > (XEN) elf_xen_parse_note: GUEST_VERSION = "2.6" > (XEN) elf_xen_parse_note: XEN_VERSION = "xen-3.0" > (XEN) elf_xen_parse_note: VIRT_BASE = 0xffffffff80000000 > (XEN) elf_xen_parse_note: ENTRY = 0xffffffff81abc1e0 > (XEN) elf_xen_parse_note: HYPERCALL_PAGE = 0xffffffff81001000 > (XEN) elf_xen_parse_note: FEATURES = "!writable_page_tables|pae_pgdir_above_4gb" > (XEN) elf_xen_parse_note: PAE_MODE = "yes" > (XEN) elf_xen_parse_note: LOADER = "generic" > (XEN) elf_xen_parse_note: unknown xen elf note (0xd) > (XEN) elf_xen_parse_note: SUSPEND_CANCEL = 0x1 > (XEN) elf_xen_parse_note: HV_START_LOW = 0xffff800000000000 > (XEN) elf_xen_parse_note: PADDR_OFFSET = 0x0 > (XEN) elf_xen_addr_calc_check: addresses: > (XEN) virt_base = 0xffffffff80000000 > (XEN) elf_paddr_offset = 0x0 > (XEN) virt_offset = 0xffffffff80000000 > (XEN) virt_kstart = 0xffffffff81000000 > (XEN) virt_kend = 0xffffffff820d7000 > (XEN) virt_entry = 0xffffffff81abc1e0 > (XEN) p2m_base = 0xffffffffffffffff > (XEN) Xen kernel: 64-bit, lsb, compat32 > (XEN) Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x20d7000 > (XEN) PHYSICAL MEMORY ARRANGEMENT: > (XEN) Dom0 alloc.: 0000000220000000->0000000224000000 (1661249 pages to be allocated) > (XEN) Init. ramdisk: 000000022cbdc000->000000023fe00000 > (XEN) VIRTUAL MEMORY ARRANGEMENT: > (XEN) Loaded kernel: ffffffff81000000->ffffffff820d7000 > (XEN) Init. ramdisk: ffffffff820d7000->ffffffff952fb000 > (XEN) Phys-Mach map: ffffffff952fb000->ffffffff96060b28 > (XEN) Start info: ffffffff96061000->ffffffff960614b4 > (XEN) Page tables: ffffffff96062000->ffffffff96117000 > (XEN) Boot stack: ffffffff96117000->ffffffff96118000 > (XEN) TOTAL: ffffffff80000000->ffffffff96400000 > (XEN) ENTRY ADDRESS: ffffffff81abc1e0 > (XEN) Dom0 has maximum 4 VCPUs > (XEN) elf_load_binary: phdr 0 at 0xffffffff81000000 -> 0xffffffff819e0000 > (XEN) elf_load_binary: phdr 1 at 0xffffffff81a00000 -> 0xffffffff81aa60f0 > (XEN) elf_load_binary: phdr 2 at 0xffffffff81aa7000 -> 0xffffffff81abbbc0 > (XEN) elf_load_binary: phdr 3 at 0xffffffff81abc000 -> 0xffffffff81baf000 > (XEN) Scrubbing Free RAM: .done. > (XEN) Xen trace buffers: disabled > (XEN) Std. Loglevel: All > (XEN) Guest Loglevel: All > (XEN) ***************************intended to aid debugging of Xen by ensuring > (XEN) ******* that all output is synchronously delivered on the serial line. > (XEN) ******* However it can introduce SIGNIFICANT latencies and affect > (XEN) ******* timekeeping. It is NOT recommended for production use! > (XEN) ********************************************** > (XEN) 3... 2... 1... > (XEN) Xen is relinquishing VGA console. > (XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen) > (XEN) Freed 224kB init memory. > mapping kernel into physical memory > about to get started... > [ 0.000000] Initializing cgroup subsys cpuset > [ 0.000000] Initializing cgroup subsys cpu > [ 0.000000] Linux version 3.8.0upstream-06471-g2ef14f4-dirty (konrad@build.dumpdata.com) (gcc version 4.4.4 20100503 (Red Hat 4.4.4-2) (GCC) ) #1 SMP Fri Feb 22 11:36:48 EST 2013 > [ 0.000000] Command line: initcall_debug debug console=hvc0 loglevel=10 xen-pciback.hide=(01:00.0) earlyprintk=xen > [ 0.000000] Freeing 9e-100 pfn range: 98 pages freed > [ 0.000000] 1-1 mapping on 9e->100 > [ 0.000000] Freeing 20000-20200 pfn range: 512 pages freed > [ 0.000000] 1-1 mapping on 20000->20200 > [ 0.000000] Freeing 40000-40200 pfn range: 512 pages freed > [ 0.000000] 1-1 mapping on 40000->40200 > [ 0.000000] Freeing bad80-badf4 pfn range: 116 pages freed > [ 0.000000] 1-1 mapping on bad80->badf4 > [ 0.000000] Freeing badf6-bae7f pfn range: 137 pages freed > [ 0.000000] 1-1 mapping on badf6->bae7f > [ 0.000000] Freeing bb000-100000 pfn range: 282624 pages freed > [ 0.000000] 1-1 mapping on bb000->100000 > [ 0.000000] Released 283999 pages of unused memory > [ 0.000000] Set 283999 page(s) to 1-1 mapping > [ 0.000000] Populating 1acb65-1f20c4 pfn range: 283999 pages added > [ 0.000000] e820: BIOS-provided physical RAM map: > [ 0.000000] Xen: [mem 0x0000000000000000-0x000000000009dfff] usable > [ 0.000000] Xen: [mem 0x000000000009ec00-0x00000000000fffff] reserved > [ 0.000000] Xen: [mem 0x0000000000100000-0x000000001fffffff] usable > [ 0.000000] Xen: [mem 0x0000000020000000-0x00000000201fffff] reserved > [ 0.000000] Xen: [mem 0x0000000020200000-0x000000003fffffff] usable > [ 0.000000] Xen: [mem 0x0000000040000000-0x00000000401fffff] reserved > [ 0.000000] Xen: [mem 0x0000000040200000-0x00000000bad7ffff] usable > [ 0.000000] Xen: [mem 0x00000000bad80000-0x00000000badc8fff] ACPI NVS > [ 0.000000] Xen: [mem 0x00000000badc9000-0x00000000badd0fff] ACPI data > [ 0.000000] Xen: [mem 0x00000000badd1000-0x00000000badf3fff] reserved > [ 0.000000] Xen: [mem 0x00000000badf4000-0x00000000badf5fff] usable > [ 0.000000] Xen: [mem 0x00000000badf6000-0x00000000bae05fff] reserved > [ 0.000000] Xen: [mem 0x00000000bae06000-0x00000000bae13fff] ACPI NVS > [ 0.000000] Xen: [mem 0x00000000bae14000-0x00000000bae3bfff] reserved > [ 0.000000] Xen: [mem 0x00000000bae3c000-0x00000000bae7efff] ACPI NVS > [ 0.000000] Xen: [mem 0x00000000bae7f000-0x00000000baffffff] usable > [ 0.000000] Xen: [mem 0x00000000bb800000-0x00000000bf9fffff] reserved > [ 0.000000] Xen: [mem 0x00000000fec00000-0x00000000fec00fff] reserved > [ 0.000000] Xen: [mem 0x00000000fed1c000-0x00000000fed3ffff] reserved > [ 0.000000] Xen: [mem 0x00000000fee00000-0x00000000fee00fff] reserved > [ 0.000000] Xen: [mem 0x00000000ff000000-0x00000000ffffffff] reserved > [ 0.000000] Xen: [mem 0x0000000100000000-0x000000023fdfffff] usable > [ 0.000000] bootconsole [xenboot0] enabled > [ 0.000000] NX (Execute Disable) protection: active > [ 0.000000] SMBIOS 2.7 present. > [ 0.000000] DMI: MSI MS-7680/H61M-P23 (MS-7680), BIOS V17.0 03/14/2011 > [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved > [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable > [ 0.000000] No AGP bridge found > [ 0.000000] e820: last_pfn = 0x23fe00 max_arch_pfn = 0x400000000 > [ 0.000000] e820: lacanning 1 areas for low memory corruption > [ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 > [ 0.000000] reserving inaccessible SNB gfx pages > [ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] > [ 0.000000] [mem 0x00000000-0x000fffff] page 4k > [ 0.000000] init_memory_mapping: [mem 0x1f2000000-0x1f20c3fff] > [ 0.000000] [mem 0x1f2000000-0x1f20c3fff] page 4k > [ 0.000000] BRK [0x01cd2000, 0x01cd2fff] PGTABLE > [ 0.000000] BRK [0x01cd3000, 0x01cd3fff] PGTABLE > [ 0.000000] init_memory_mapping: [mem 0x1f0000000-0x1f1ffffff] > [ 0.000000] [mem 0x1f0000000-0x1f1ffffff] page 4k > [ 0.000000] BRK [0x01cd4000, 0x01cd4fff] PGTABLE > [ 0.000000] BRK [0x01cd5000, 0x01cd5fff] PGTABLE > [ 0.000000] BRK [0x01cd6000, 0x01cd6fff] PGTABLE > [ 0.000000] init_memory_mapping: [mem 0x180000000-0x1efffffff] > [ 0.000000] [mem 0x180000000-0x1efffffff] page 4k > [ 0.000000] init_memory_mapping: [mem 0x00100000-0x1fffffff] > [ 0.000000] [mem 0x00100000-0x1fffffff] page 4k > [ 0.000000] init_memory_mapping: [mem 0x20200000-0x3fffffff] > [ 0.000000] [mem 0x20200000-0x3fffffff] page 4k > [ 0.000000] init_memory_mapping: [mem 0x40200000-0xbad7ffff] > [ 0.000000] [mem 0x40200000-0xbad7ffff] page 4k > [ 0.000000] init_memory_mapping: [mem 0xbadf4000-0xbadf5fff] > [ 0.000000] [mem 0xbadf4000-0xbadf5fff] page 4k > [ 0.000000] init_memory_mapping: [mem 0xbae7f000-0xbaffffff] > [ 0.000000] [mem 0xbae7f000-0xbaffffff] page 4k > [ 0.000000] init_memory_mapping: [mem 0x100000000-0x17fffffff] > [ 0.000000] [mem 0x100000000-0x17fffffff] page 4k > [ 0.000000] init_memory_mapping: [mem 0x1f20c4000-0x23fdfffff] > [ 0.000000] [mem 0x1f20c4000-0x23fdfffff] page 4k so init_memory_mapping are all done. > (XEN) d0:v0: unhandled page fault (ec=0000) > (XEN) Pagetable walk from ffffea000005b2d0: > (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff > (XEN) domain_crash_sync called from entry.S > (XEN) Domain 0 (vcpu#0) crashed on cpu#0: > (XEN) ----[ Xen-4.1.5-pre x86_64 debug=y Tainted: C ]---- > (XEN) CPU: 0 > (XEN) RIP: e033:[] > (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest > (XEN) rax: ffffea0000000000 rbx: 0000000001a0c000 rcx: 0000000080000000 > (XEN) rdx: 000000000005b2a0 rsi: 0000000001a0c000 rdi: 0000000000000000 > (XEN) rbp: ffffffff81a01dd8 rsp: ffffffff81a01d90 r8: 0000000000000000 > (XEN) r9: 0000000010000001 r10: 0000000000000005 r11: 0000000000100000 > (XEN) r12: 0000000000000000 r13: 0000020000000000 r14: 0000000000000000 > (XEN) r15: 0000000000100000 cr0: 000000008005003b cr4: 00000000000026f0 > (XEN) cr3: 0000000221a0c000 cr2: ffffea000005b2d0 > (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 > (XEN) Guest stack trace from rsp=ffffffff81a01d90: > (XEN) 0000000080000000 0000000000100000 0000000000000000 ffffffff8103feba > (XEN) 000000010000e030 0000000000010006 ffffffff81a01dd8 000000000000e02b > (XEN) 0000000000000000 ffffffff81a01e08 ffffffff81042d27 000000023fe00000 > (XEN) 00000001f20c4000 0000020000000000 00000001acac7000 ffffffff81a01e48 > (XEN) ffffffff81ad2d21 0000000000000000 0000000000000028 0000000040004000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 ffffffff81a01ed8 > (XEN) ffffffff81ac293f ffffffff81b46900 0000000000000000 0000000000000000 > (XEN) 0000000000000000 ffffffff81a01f00 ffffffff8165fbd1 ffffffff00000010 > (XEN) ffffffff81a01ee8 ffffffff81a01ea8 0000000000000000 ffffffff81a01ec8 > (XEN) ffffffffffffffff ffffffff81b46900 0000000000000000 0000000000000000 > (XEN) 0000000000000000 ffffffff81a01f28 ffffffff81abcd62 ffffffff96062000 > (XEN) ffffffff81cc6000 ffffffff81ccd000 ffffffff81b4f2e0 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 ffffffff81a01f38 > (XEN) ffffffff81abc5f7 ffffffff81a01ff8 ffffffff81abf0c7 0300000100000032 > (XEN) 0000000000000005 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 819822831fc9cbf5 000206a700100800 0000000000000001 > (XEN) 0000000000000000 0000000000000000 0f00000060c0c748 ccccccccccccc305 > (XEN) Domain 0 crashed: rebooting machine in 5 seconds. > (XEN) Resetting with ACPI MEMORY or I/O RESET_REG. can we get kernel trace instead? > From stefano.stabellini@eu.citrix.com Fri Feb 22 19:06:17 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 19:06:27 +0100 (CET) Received: from smtp02.citrix.com ([66.165.176.63]:26808 "EHLO SMTP02.CITRIX.COM" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827576Ab3BVSGRnJ7vf (ORCPT ); Fri, 22 Feb 2013 19:06:17 +0100 X-IronPort-AV: E=Sophos;i="4.84,717,1355097600"; d="scan'208";a="8631647" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP/TLS/AES128-SHA; 22 Feb 2013 18:06:10 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.318.1; Fri, 22 Feb 2013 13:06:09 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1U8x0b-0006RG-4R; Fri, 22 Feb 2013 18:06:09 +0000 Date: Fri, 22 Feb 2013 18:06:04 +0000 From: Stefano Stabellini X-X-Sender: sstabellini@kaball.uk.xensource.com To: Konrad Rzeszutek Wilk CC: "H. Peter Anvin" , "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "Rafael J. Wysocki" , "stable@vger.kernel.org" , Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?UTF-8?Q?Ville_Syrj=C3=A4l=C3=A4?= , Yasuaki Ishimatsu , Yinghai Lu , Zachary Amsden , "avi@redhat.com" , "linux-mips@linux-mips.org" , "linux-pm@vger.kernel.org" , "mst@redhat.com" , "sparclinux@vger.kernel.org" , "virtualization@lists.linux-foundation.org" , "xen-devel@lists.xensource.com" Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 In-Reply-To: <20130222173805.GC7768@phenom.dumpdata.com> Message-ID: References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <5127A719.3060702@zytor.com> <20130222173805.GC7768@phenom.dumpdata.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-archive-position: 35816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stefano.stabellini@eu.citrix.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1272 Lines: 29 On Fri, 22 Feb 2013, Konrad Rzeszutek Wilk wrote: > On Fri, Feb 22, 2013 at 09:12:57AM -0800, H. Peter Anvin wrote: > > On 02/22/2013 08:55 AM, Konrad Rzeszutek Wilk wrote: > > > > > >What is bizzare is that I do recall testing this (and Stefano also did it). > > >So I am not sure what has altered. > > > > > > > Yes, there was a very specific reason why I wanted you guys to test it... > > Exactly. And I re-ran the same test, but with a new kernel. This is what > git reflog tells me: > > 473cd24 HEAD@{75}: checkout: moving from 08f321ed97353cf3b3fafa6b1c1971d6a8970830 to linux-next > 08f321e HEAD@{76}: checkout: moving from linux-next to yinghai/for-x86-mm > eb827a7 HEAD@{77}: checkout: moving from 1b66ccf15ff4bd0200567e8d70446a8763f96ee7 to linux-next > [konrad@build linux]$ git show 08f321e > commit 08f321ed97353cf3b3fafa6b1c1971d6a8970830 > Author: Yinghai Lu > Date: Thu Nov 8 00:00:19 2012 -0800 > > mm: Kill NO_BOOTMEM version free_all_bootmem_node() > > And I recall Stefano later on testing (I was in a conference and did not have > the opportunity to test it). Not sure what he ran with. > FYI the last patch series I tested was Yinghai's "x86, boot, 64bit: Add support for loading ramdisk and bzImage above 4G" v7u1. From yinghai@kernel.org Fri Feb 22 19:08:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 19:08:31 +0100 (CET) Received: from mail-ia0-f170.google.com ([209.85.210.170]:43707 "EHLO mail-ia0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827576Ab3BVSI3SXD9t (ORCPT ); Fri, 22 Feb 2013 19:08:29 +0100 Received: by mail-ia0-f170.google.com with SMTP id k20so796953iak.29 for ; Fri, 22 Feb 2013 10:08:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=yHadZE0k7RbMizTRu9CY5ebriUWS+mgnLnMobvPY34Y=; b=iHTqeVkY2skJySmHE1c6XP+510F6hYrMFWoB/3/jwOLpNDxK6yaz6hzaHtllfs65KU 8+/k8OiKf/KZuPjBhxRtLmiLKFSvZEw9SuBbld9A9hriPmt/eGHnyl8UgOAw3fwFJTag ztzAFOYLRT4hvaHVEfdfU3+k6LL70Eh7M5gZaiAhuMTgIYxe8AhW7WC+16pzCYzfT46t EIs/DDhjnokSIKbZ1c+r3V+TOfpo6ml8Uc6y80I6MYiPwzUXEGkP0xcRfzetB/ji9xBO ZFYDQqDYMisftU/usGmZenD6waO/zW1KykhNoqIoPQrs6/oE5c3eZjsG+Tsb+FXEfcv5 VEdw== MIME-Version: 1.0 X-Received: by 10.50.186.165 with SMTP id fl5mr27295igc.81.1361556502652; Fri, 22 Feb 2013 10:08:22 -0800 (PST) Received: by 10.64.33.203 with HTTP; Fri, 22 Feb 2013 10:08:22 -0800 (PST) In-Reply-To: <20130222173805.GC7768@phenom.dumpdata.com> References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <5127A719.3060702@zytor.com> <20130222173805.GC7768@phenom.dumpdata.com> Date: Fri, 22 Feb 2013 10:08:22 -0800 X-Google-Sender-Auth: dLxEIz2E_oiR6OplMiNFNvUZ4uo Message-ID: Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 From: Yinghai Lu To: Konrad Rzeszutek Wilk Cc: "H. Peter Anvin" , "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= , Yasuaki Ishimatsu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35817 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yinghai@kernel.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1582 Lines: 38 On Fri, Feb 22, 2013 at 9:38 AM, Konrad Rzeszutek Wilk wrote: > On Fri, Feb 22, 2013 at 09:12:57AM -0800, H. Peter Anvin wrote: >> On 02/22/2013 08:55 AM, Konrad Rzeszutek Wilk wrote: >> > >> >What is bizzare is that I do recall testing this (and Stefano also did it). >> >So I am not sure what has altered. >> > >> >> Yes, there was a very specific reason why I wanted you guys to test it... > > Exactly. And I re-ran the same test, but with a new kernel. This is what > git reflog tells me: > > 473cd24 HEAD@{75}: checkout: moving from 08f321ed97353cf3b3fafa6b1c1971d6a8970830 to linux-next > 08f321e HEAD@{76}: checkout: moving from linux-next to yinghai/for-x86-mm > eb827a7 HEAD@{77}: checkout: moving from 1b66ccf15ff4bd0200567e8d70446a8763f96ee7 to linux-next > [konrad@build linux]$ git show 08f321e > commit 08f321ed97353cf3b3fafa6b1c1971d6a8970830 > Author: Yinghai Lu > Date: Thu Nov 8 00:00:19 2012 -0800 > > mm: Kill NO_BOOTMEM version free_all_bootmem_node() > > And I recall Stefano later on testing (I was in a conference and did not have > the opportunity to test it). Not sure what he ran with. the commit in tip and linus tree have different hash... commit 600cc5b7f6371706679490d7ee108015ae57ac2f Author: Yinghai Lu Date: Fri Nov 16 19:39:22 2012 -0800 mm: Kill NO_BOOTMEM version free_all_bootmem_node() Now NO_BOOTMEM version free_all_bootmem_node() does not really do free_bootmem at all, and it only call register_page_bootmem_info_node for online nodes instead. From yinghai@kernel.org Fri Feb 22 19:23:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 19:23:08 +0100 (CET) Received: from mail-ie0-f177.google.com ([209.85.223.177]:63870 "EHLO mail-ie0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827599Ab3BVSXF3XtDa (ORCPT ); Fri, 22 Feb 2013 19:23:05 +0100 Received: by mail-ie0-f177.google.com with SMTP id 16so1071265iea.22 for ; Fri, 22 Feb 2013 10:22:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=eawHSTBHCwjL2bRkJUFYFi1yDzmmlhlZR4+sK0dg5So=; b=GlP0/wJrAcIExv+bUMErz+l/wB39q9/qwScD0qOtLtJ7+l37Y2jM1eeMcyfdxPygnA /HBRB2eKwVJXggk5wPs4wugdvciOfBAbf75fZuMDTurbFDfZSjbQPzW4i27yGUqqAYDB yTQONC5plr4vYPhVf+qLfNasfcijDYp7kjGyD1+eitwxU44t523zjfVzNTHuTX7DM2ye B/fMPSBAnoYhnj0ImcC0YUr0aKl/vNNuslANNiD1SLKizl3T7a1RZ/V2vRhGHZykbZ+X oRmjF4xyCzU1Tk9oqVfzK4NnlvFAnhGDyvMLW8+BJnGOA9/53IrHAK/MySSNnQm5Sim+ 6KYA== MIME-Version: 1.0 X-Received: by 10.50.186.165 with SMTP id fl5mr46888igc.81.1361557379147; Fri, 22 Feb 2013 10:22:59 -0800 (PST) Received: by 10.64.33.203 with HTTP; Fri, 22 Feb 2013 10:22:59 -0800 (PST) In-Reply-To: References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <5127A719.3060702@zytor.com> <20130222173805.GC7768@phenom.dumpdata.com> Date: Fri, 22 Feb 2013 10:22:59 -0800 X-Google-Sender-Auth: OfM_9rT84W15D603mqOA0AtPjYI Message-ID: Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 From: Yinghai Lu To: Stefano Stabellini Cc: Konrad Rzeszutek Wilk , "H. Peter Anvin" , "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "Rafael J. Wysocki" , "stable@vger.kernel.org" , Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Steven Rostedt , Thomas Gleixner , =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= , Yasuaki Ishimatsu , Zachary Amsden , "avi@redhat.com" , "linux-mips@linux-mips.org" , "linux-pm@vger.kernel.org" , "mst@redhat.com" , "sparclinux@vger.kernel.org" , "virtualization@lists.linux-foundation.org" , "xen-devel@lists.xensource.com" Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 35818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yinghai@kernel.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1785 Lines: 49 On Fri, Feb 22, 2013 at 10:06 AM, Stefano Stabellini wrote: > On Fri, 22 Feb 2013, Konrad Rzeszutek Wilk wrote: >> On Fri, Feb 22, 2013 at 09:12:57AM -0800, H. Peter Anvin wrote: >> > On 02/22/2013 08:55 AM, Konrad Rzeszutek Wilk wrote: >> > > >> > >What is bizzare is that I do recall testing this (and Stefano also did it). >> > >So I am not sure what has altered. >> > > >> > >> > Yes, there was a very specific reason why I wanted you guys to test it... >> >> Exactly. And I re-ran the same test, but with a new kernel. This is what >> git reflog tells me: >> >> 473cd24 HEAD@{75}: checkout: moving from 08f321ed97353cf3b3fafa6b1c1971d6a8970830 to linux-next >> 08f321e HEAD@{76}: checkout: moving from linux-next to yinghai/for-x86-mm >> eb827a7 HEAD@{77}: checkout: moving from 1b66ccf15ff4bd0200567e8d70446a8763f96ee7 to linux-next >> [konrad@build linux]$ git show 08f321e >> commit 08f321ed97353cf3b3fafa6b1c1971d6a8970830 >> Author: Yinghai Lu >> Date: Thu Nov 8 00:00:19 2012 -0800 >> >> mm: Kill NO_BOOTMEM version free_all_bootmem_node() >> >> And I recall Stefano later on testing (I was in a conference and did not have >> the opportunity to test it). Not sure what he ran with. >> > > FYI the last patch series I tested was Yinghai's "x86, boot, 64bit: Add > support for loading ramdisk and bzImage above 4G" v7u1. the one in tip and linus's tree is --- -v7u2: update changelog and comments, and clear more fields for sentinel. Update swiotlb autoswitch off patch. Fix crash with xen PV guest with 2G. --- and it fixes xen crash that you reported with v7u1, and you tested that add-on patch fix_xen_2g.patch with v7u1. and I fold the addon patch into offending patch in v7u2. Thanks Yinghai From konrad.wilk@oracle.com Fri Feb 22 19:24:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 19:24:50 +0100 (CET) Received: from aserp1040.oracle.com ([141.146.126.69]:51989 "EHLO aserp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827583Ab3BVSYoouziF (ORCPT ); Fri, 22 Feb 2013 19:24:44 +0100 Received: from ucsinet21.oracle.com (ucsinet21.oracle.com [156.151.31.93]) by aserp1040.oracle.com (Sentrion-MTA-4.3.1/Sentrion-MTA-4.3.1) with ESMTP id r1MINTKq002870 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 22 Feb 2013 18:23:30 GMT Received: from acsmt357.oracle.com (acsmt357.oracle.com [141.146.40.157]) by ucsinet21.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id r1MINRdU002118 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 22 Feb 2013 18:23:28 GMT Received: from abhmt107.oracle.com (abhmt107.oracle.com [141.146.116.59]) by acsmt357.oracle.com (8.12.11.20060308/8.12.11) with ESMTP id r1MINRNv001337; Fri, 22 Feb 2013 12:23:27 -0600 Received: from phenom.dumpdata.com (/50.195.21.189) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 22 Feb 2013 10:23:26 -0800 Received: by phenom.dumpdata.com (Postfix, from userid 1000) id 099CB1C3935; Fri, 22 Feb 2013 13:23:22 -0500 (EST) Date: Fri, 22 Feb 2013 13:23:21 -0500 From: Konrad Rzeszutek Wilk To: Yinghai Lu Cc: "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "H. Peter Anvin" , "Rafael J. Wysocki" , stable@vger.kernel.org, Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie Lokier , Jarkko Sakkinen , Jeremy Fitzhardinge , Joe Millenbach , Joerg Roedel , Johannes Weiner , Josh Triplett , Kyungmin Park , Lee Schermerhorn , Len Brown , Linux Kernel Mailing List , Marcelo Tosatti , Marek Szyprowski , Matt Fleming , Mel Gorman , Paul Turner , Pavel Machek , Pekka Enberg , Peter Zijlstra , Ralf Baechle , Rik van Riel , Rob Landley , Russell King , Rusty Russell , Shuah Khan , Shuah Khan , Stefano Stabellini , Steven Rostedt , Thomas Gleixner , Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Yasuaki Ishimatsu , Zachary Amsden , avi@redhat.com, linux-mips@linux-mips.org, linux-pm@vger.kernel.org, mst@redhat.com, sparclinux@vger.kernel.org, virtualization@lists.linux-foundation.org, xen-devel@lists.xensource.com Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 Message-ID: <20130222182321.GA11311@phenom.dumpdata.com> References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <20130222172403.GA17056@phenom.dumpdata.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Source-IP: ucsinet21.oracle.com [156.151.31.93] X-archive-position: 35819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: konrad.wilk@oracle.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 5800 Lines: 99 > > [ 0.000000] DMI: MSI MS-7680/H61M-P23 (MS-7680), BIOS V17.0 03/14/2011 > > [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved > > [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable > > [ 0.000000] No AGP bridge found > > [ 0.000000] e820: last_pfn = 0x23fe00 max_arch_pfn = 0x400000000 > > [ 0.000000] e820: lacanning 1 areas for low memory corruption > > [ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 > > [ 0.000000] reserving inaccessible SNB gfx pages > > [ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] > > [ 0.000000] [mem 0x00000000-0x000fffff] page 4k > > [ 0.000000] init_memory_mapping: [mem 0x1f2000000-0x1f20c3fff] > > [ 0.000000] [mem 0x1f2000000-0x1f20c3fff] page 4k > > [ 0.000000] BRK [0x01cd2000, 0x01cd2fff] PGTABLE > > [ 0.000000] BRK [0x01cd3000, 0x01cd3fff] PGTABLE > > [ 0.000000] init_memory_mapping: [mem 0x1f0000000-0x1f1ffffff] > > [ 0.000000] [mem 0x1f0000000-0x1f1ffffff] page 4k > > [ 0.000000] BRK [0x01cd4000, 0x01cd4fff] PGTABLE > > [ 0.000000] BRK [0x01cd5000, 0x01cd5fff] PGTABLE > > [ 0.000000] BRK [0x01cd6000, 0x01cd6fff] PGTABLE > > [ 0.000000] init_memory_mapping: [mem 0x180000000-0x1efffffff] > > [ 0.000000] [mem 0x180000000-0x1efffffff] page 4k > > [ 0.000000] init_memory_mapping: [mem 0x00100000-0x1fffffff] > > [ 0.000000] [mem 0x00100000-0x1fffffff] page 4k > > [ 0.000000] init_memory_mapping: [mem 0x20200000-0x3fffffff] > > [ 0.000000] [mem 0x20200000-0x3fffffff] page 4k > > [ 0.000000] init_memory_mapping: [mem 0x40200000-0xbad7ffff] > > [ 0.000000] [mem 0x40200000-0xbad7ffff] page 4k > > [ 0.000000] init_memory_mapping: [mem 0xbadf4000-0xbadf5fff] > > [ 0.000000] [mem 0xbadf4000-0xbadf5fff] page 4k > > [ 0.000000] init_memory_mapping: [mem 0xbae7f000-0xbaffffff] > > [ 0.000000] [mem 0xbae7f000-0xbaffffff] page 4k > > [ 0.000000] init_memory_mapping: [mem 0x100000000-0x17fffffff] > > [ 0.000000] [mem 0x100000000-0x17fffffff] page 4k > > [ 0.000000] init_memory_mapping: [mem 0x1f20c4000-0x23fdfffff] > > [ 0.000000] [mem 0x1f20c4000-0x23fdfffff] page 4k > > so init_memory_mapping are all done. Not so. > > > (XEN) d0:v0: unhandled page fault (ec=0000) > > (XEN) Pagetable walk from ffffea000005b2d0: > > (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff > > (XEN) domain_crash_sync called from entry.S > > (XEN) Domain 0 (vcpu#0) crashed on cpu#0: > > (XEN) ----[ Xen-4.1.5-pre x86_64 debug=y Tainted: C ]---- > > (XEN) CPU: 0 > > (XEN) RIP: e033:[] > > (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest > > (XEN) rax: ffffea0000000000 rbx: 0000000001a0c000 rcx: 0000000080000000 > > (XEN) rdx: 000000000005b2a0 rsi: 0000000001a0c000 rdi: 0000000000000000 > > (XEN) rbp: ffffffff81a01dd8 rsp: ffffffff81a01d90 r8: 0000000000000000 > > (XEN) r9: 0000000010000001 r10: 0000000000000005 r11: 0000000000100000 > > (XEN) r12: 0000000000000000 r13: 0000020000000000 r14: 0000000000000000 > > (XEN) r15: 0000000000100000 cr0: 000000008005003b cr4: 00000000000026f0 > > (XEN) cr3: 0000000221a0c000 cr2: ffffea000005b2d0 > > (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 > > (XEN) Guest stack trace from rsp=ffffffff81a01d90: > > (XEN) 0000000080000000 0000000000100000 0000000000000000 ffffffff8103feba > > (XEN) 000000010000e030 0000000000010006 ffffffff81a01dd8 000000000000e02b > > (XEN) 0000000000000000 ffffffff81a01e08 ffffffff81042d27 000000023fe00000 > > (XEN) 00000001f20c4000 0000020000000000 00000001acac7000 ffffffff81a01e48 > > (XEN) ffffffff81ad2d21 0000000000000000 0000000000000028 0000000040004000 > > (XEN) 0000000000000000 0000000000000000 0000000000000000 ffffffff81a01ed8 > > (XEN) ffffffff81ac293f ffffffff81b46900 0000000000000000 0000000000000000 > > (XEN) 0000000000000000 ffffffff81a01f00 ffffffff8165fbd1 ffffffff00000010 > > (XEN) ffffffff81a01ee8 ffffffff81a01ea8 0000000000000000 ffffffff81a01ec8 > > (XEN) ffffffffffffffff ffffffff81b46900 0000000000000000 0000000000000000 > > (XEN) 0000000000000000 ffffffff81a01f28 ffffffff81abcd62 ffffffff96062000 > > (XEN) ffffffff81cc6000 ffffffff81ccd000 ffffffff81b4f2e0 0000000000000000 > > (XEN) 0000000000000000 0000000000000000 0000000000000000 ffffffff81a01f38 > > (XEN) ffffffff81abc5f7 ffffffff81a01ff8 ffffffff81abf0c7 0300000100000032 > > (XEN) 0000000000000005 0000000000000000 0000000000000000 0000000000000000 > > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > > (XEN) 0000000000000000 819822831fc9cbf5 000206a700100800 0000000000000001 > > (XEN) 0000000000000000 0000000000000000 0f00000060c0c748 ccccccccccccc305 > > (XEN) Domain 0 crashed: rebooting machine in 5 seconds. > > (XEN) Resetting with ACPI MEMORY or I/O RESET_REG. > > can we get kernel trace instead? If you look at the initial one I had posted: > >> Call Trace: > >> [] xen_get_user_pgd+0x5a <-- > >> [] xen_get_user_pgd+0x5a > >> [] xen_write_cr3+0x77 > >> [] init_mem_mapping+0x1f9 > >> [] setup_arch+0x742 > >> [] printk+0x48 > >> [] start_kernel+0x90 > >> [] __add_preferred_console.clone.1+0x9b > >> [] x86_64_start_reservations+0x2a > >> [] xen_start_kernel+0x564 The EIP matches with what this stack strace has. So we are still in init_mem_mapping. From andrew.cooper3@citrix.com Fri Feb 22 19:25:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 19:25:58 +0100 (CET) Received: from smtp02.citrix.com ([66.165.176.63]:8142 "EHLO SMTP02.CITRIX.COM" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827583Ab3BVSZ4KIv4D (ORCPT ); Fri, 22 Feb 2013 19:25:56 +0100 X-IronPort-AV: E=Sophos;i="4.84,717,1355097600"; d="scan'208";a="8635636" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP/TLS/AES128-SHA; 22 Feb 2013 18:25:48 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.318.1; Fri, 22 Feb 2013 13:25:48 -0500 Received: from andrewcoop.uk.xensource.com ([10.80.2.18]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1U8xJb-0006mv-CE; Fri, 22 Feb 2013 18:25:47 +0000 Message-ID: <5127B82A.3000506@citrix.com> Date: Fri, 22 Feb 2013 18:25:46 +0000 From: Andrew Cooper User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130119 Icedove/10.0.12 MIME-Version: 1.0 To: Yinghai Lu CC: Konrad Rzeszutek Wilk , "linux-mips@linux-mips.org" , Jeremy Fitzhardinge , Gleb Natapov , "H. J. Lu" , Frederic Weisbecker , Joe Millenbach , "virtualization@lists.linux-foundation.org" , Gokul Caushik , Ralf Baechle , Pavel Machek , "H. Peter Anvin" , "sparclinux@vger.kernel.org" , Christoph Lameter , Ingo Molnar , =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= , Marek Szyprowski , Andrea Arcangeli , Lee Schermerhorn , "xen-devel@lists.xensource.com" , Russell King , Len Brown , Joerg Roedel , "linux-pm@vger.kernel.org" , Hugh Dickins , Yasuaki Ishimatsu , Mel Gorman , Ingo Molnar , Borislav Petkov , Paul Turner , "avi@redhat.com" , Alexander Duyck , Fenghua Yu , Peter Zijlstra , Arnd Bergmann , Stefano Stabellini , Rusty Russell , Jamie Lokier , Josh Triplett , Steven Rostedt , "Rafael J. Wysocki" , Matt Fleming , Borislav Petkov , Andrzej Pietrasiewicz , Shuah Khan , Thomas Gleixner , Jarkko Sakkinen , Daniel J Blueman , Zachary Amsden , Marcelo Tosatti , Jacob Shin , Linux Kernel Mailing List , "stable@vger.kernel.org" , Dave Hansen , Pekka Enberg , Kyungmin Park , "mst@redhat.com" , Eric Biederman , Rob Landley , Johannes Weiner , Andrew Morton , "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , Shuah Khan Subject: Re: [Xen-devel] [GIT PULL] x86/mm changes for v3.9-rc1 References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <20130222172403.GA17056@phenom.dumpdata.com> In-Reply-To: X-Enigmail-Version: 1.4 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-archive-position: 35820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: andrew.cooper3@citrix.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 22584 Lines: 420 On 22/02/13 17:53, Yinghai Lu wrote: > On Fri, Feb 22, 2013 at 9:24 AM, Konrad Rzeszutek Wilk > wrote: >> On Fri, Feb 22, 2013 at 11:55:31AM -0500, Konrad Rzeszutek Wilk wrote: >>> On Thu, Feb 21, 2013 at 04:34:06PM -0800, H. Peter Anvin wrote: >>>> Hi Linus, >>>> >>>> This is a huge set of several partly interrelated (and concurrently >>>> developed) changes, which is why the branch history is messier than >>>> one would like. >>>> >>>> The *really* big items are two humonguous patchsets mostly developed >>>> by Yinghai Lu at my request, which completely revamps the way we >>>> create initial page tables. In particular, rather than estimating how >>>> much memory we will need for page tables and then build them into that >>>> memory -- a calculation that has shown to be incredibly fragile -- we >>>> now build them (on 64 bits) with the aid of a "pseudo-linear mode" -- >>>> a #PF handler which creates temporary page tables on demand. >>>> >>>> This has several advantages: >>>> >>>> 1. It makes it much easier to support things that need access to >>>> data very early (a followon patchset uses this to load microcode >>>> way early in the kernel startup). >>>> >>>> 2. It allows the kernel and all the kernel data objects to be invoked >>>> from above the 4 GB limit. This allows kdump to work on very large >>>> systems. >>>> >>>> 3. It greatly reduces the difference between Xen and native (Xen's >>>> equivalent of the #PF handler are the temporary page tables created >>>> by the domain builder), eliminating a bunch of fragile hooks. >>>> >>>> The patch series also gets us a bit closer to W^X. >>>> >>>> Additional work in this pull is the 64-bit get_user() work which you >>>> were also involved with, and a bunch of cleanups/speedups to >>>> __phys_addr()/__pa(). >>> Looking at figuring out which of the patches in the branch did this, but >>> with this merge I am getting a crash with a very simple PV guest (booted with >>> one 1G): >>> >>> Call Trace: >>> [] xen_get_user_pgd+0x5a <-- >>> [] xen_get_user_pgd+0x5a >>> [] xen_write_cr3+0x77 >>> [] init_mem_mapping+0x1f9 >>> [] setup_arch+0x742 >>> [] printk+0x48 >>> [] start_kernel+0x90 >>> [] __add_preferred_console.clone.1+0x9b >>> [] x86_64_start_reservations+0x2a >>> [] xen_start_kernel+0x564 >>> >>> And the hypervisor says: >>> (XEN) d7:v0: unhandled page fault (ec=0000) >>> (XEN) Pagetable walk from ffffea000005b2d0: >>> (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff >>> (XEN) domain_crash_sync called from entry.S >>> (XEN) Domain 7 (vcpu#0) crashed on cpu#3: >>> (XEN) ----[ Xen-4.2.0 x86_64 debug=n Not tainted ]---- >>> (XEN) CPU: 3 >>> (XEN) RIP: e033:[] >>> (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest >>> (XEN) rax: ffffea0000000000 rbx: 0000000001a0c000 rcx: 0000000080000000 >>> (XEN) rdx: 000000000005b2a0 rsi: 0000000001a0c000 rdi: 0000000000000000 >>> (XEN) rbp: ffffffff81a01dd8 rsp: ffffffff81a01d90 r8: 0000000000000000 >>> (XEN) r9: 0000000010000001 r10: 0000000000000000 r11: 0000000000000000 >>> (XEN) r12: 0000000000000000 r13: 0000001000000000 r14: 0000000000000000 >>> (XEN) r15: 0000000000100000 cr0: 000000008005003b cr4: 00000000000406f0 >>> (XEN) cr3: 0000000411165000 cr2: ffffea000005b2d0 >>> (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 >>> (XEN) Guest stack trace from rsp=ffffffff81a01d90: >>> (XEN) 0000000080000000 0000000000000000 0000000000000000 ffffffff8103feba >>> (XEN) 000000010000e030 0000000000010006 ffffffff81a01dd8 000000000000e02b >> Here is a better serial log of the crash (just booting a normal Xen 4.1 + initial >> kernel with 8GB): >> >> PXELINUX 3.82 2009-06-09 Copyright (C) 1994-2009 H. Peter Anvin et al >> boot: >> Loading xen.gz... ok >> Loading vmlinuz... ok >> Loading initramfs.cpio.gz... ok >> __ __ _ _ _ ____ >> \ \/ /___ _ __ | || | / | | ___| _ __ _ __ ___ >> \ // _ \ '_(_)_(_)____/ | .__/|_| \___| >> |_| >> (XEN) Xen version 4.1.5-pre (konrad@dumpdata.com) (gcc version 4.4.4 20100503 (Red Hat 4.4.4-2) (GCC) ) Fri Feb 22 11:37:00 EST 2013 >> (XEN) Latest ChangeSet: Fri Feb 15 15:31:55 2013 +0100 23459:9f12bdd6b7f0 >> (XEN) Console output is synchronous. >> (XEN) Bootloader: unknown >> (XEN) Command line: cpuinfo conring_size=1048576 sync_console cpufreq=verbose com1=115200,8n1 console=com1,vga loglvl=all guest_loglvl=all >> (XEN) Video information: >> (XEN) VGA is text mode 80x25, font 8x16 >> (XEN) VBE/DDC methods: none; EDID transfer time: 0 seconds >> (XEN) EDID info not retrieved because no DDC retrieval method detected >> (XEN) Disc information: >> (XEN) Found 1 MBR signatures >> (XEN) Found 1 EDD information structures >> (XEN) Xen-e820 RAM map: >> (XEN) 0000000000000000 - 000000000009ec00 (usable) >> (XEN) 000000000009ec00 - 00000000000a0000 (reserved) >> (XEN) 00000000000e0000 - 0000000000100000 (reserved) >> (XEN) 0000000000100000 - 0000000020000000 (usable) >> (XEN) 0000000020000000 - 0000000020200000 (reserved) >> (XEN) 0000000020200000 - 0000000040000000 (usable) >> (XEN) 0000000040000000 - 0000000040200000 (reserved) >> (XEN) 0000000040200000 - 00000000bad80000 (usable) >> (XEN) 00000000bad80000 - 00000000badc9000 (ACPI NVS) >> (XEN) 00000000badc9000 - 00000000badd1000 (ACPI data) >> (XEN) 00000000badd1000 - 00000000badf4000 (reserved) >> (XEN) 00000000badf4000 - 00000000badf6000 (usable) >> (XEN) 00000000badf6000 - 00000000bae06000 (reserved) >> (XEN) 00000000bae06000 - 00000000bae14000 (ACPI NVS) >> (XEN) 00000000bae14000 - 00000000bae3c000 (reserved) >> (XEN) 00000000bae3c000 - 00000000bae7f000 (ACPI NVS) >> (XEN) 00000000bae7f000 - 00000000bb000000 (usable) >> (XEN) 00000000bb800000 - 00000000bfa00000 (reserved) >> (XEN) 00000000fed1c000 - 00000000fed40000 (reserved) >> (XEN) 00000000ff000000 - 0000000100000000 (reserved) >> (XEN) 0000000100000000 - 000000023fe00000 (usable) >> (XEN) ACPI: RSDP 000F0450, 0024 (r2 ALASKA) >> (XEN) ACPI: XSDT BADC9068, 0054 (r1 ALASKA A M I 1072009 AMI 10013) >> (XEN) PROC 1 MSFT 3000001) >> (XEN) ACPI: MCFG BADD0580, 003C (r1 ALASKA A M I 1072009 MSFT 97) >> (XEN) ACPI: HPET BADD05C0, 0038 (r1 ALASKA A M I 1072009 AMI. 4) >> (XEN) ACPI: ASF! BADD05F8, 00A0 (r32 INTEL HCG 1 TFSM F4240) >> (XEN) System RAM: 8104MB (8299140kB) >> (XEN) No NUMA configuration found >> (XEN) Faking a node at 0000000000000000-000000023fe00000 >> (XEN) Domain heap initialised >> (XEN) found SMP MP-table at 000fcde0 >> (XEN) DMI 2.7 present. >> (XEN) Using APIC driver default >> (XEN) ACPI: PM-Timer IO Port: 0x408 >> (XEN) ACPI: ACPI SLEEP INFO: pm1x_cnt[404,0], pm1x_evt[400,0] >> (XEN) ACPI: 32/64X FACS address mismatch in FADT - bae0bf80/0000000000000000, using 32 >> (XEN) ACPI: wakeup_vec[bae0bf8c], vec_size[20] >> (XEN) ACPI: Local APIC address 0xfee00000 >> (XEN) ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled) >> (XEN) Processor #0 6:10 APIC version 21 >> (XEN) ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled) >> (XEN) Processor #2 6:10 APIC version 21 >> (XEN) ACPI: LAPIC (acpi_id[0x03] lapic_id[0x01] enabled) >> (XEN) Processor #1 6:10 APIC version 21 >> (XEN) ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] enabled) >> (XEN) Processor #3 6:10 APIC version 21 >> (XEN) ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) >> (XEN) ACPI: IOAPIC (id[0x00] address[0xfec00000] gsi_base[0]) >> (XEN) IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23 >> (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) >> (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) >> (XEN) ACPI: IRQ0 used by override. >> (XEN) ACPI: IRQ2 used by override. >> (XEN) ACPI: IRQ9 used by override. >> (XEN) Enabling APIC mode: Flat. Using 1 I/O APICs >> (XEN) ACPI: HPET id: 0x8086a701 base: 0xfed00000 >> (XEN) PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 255 >> (XEN) PCI: Not using MMCONFIG. >> (XEN) Table is not found! >> (XEN) Using ACPI (MADT) for SMP configuration information >> (XEN) IRQ limits: 24 GSI, 760 MSI/MSI-X >> (XEN) Using scheduler: SMP Credit Scheduler (credit) >> (XEN) Initializing CPU#0 >> (XEN) Detected 3093.067 MHz processor. >> (XEN) Initing memory sharing. >> (XEN) CPU: Physical Processor ID: 0 >> (XEN) CPU: Processor Core ID: 0 >> (XEN) CPU: L1 I cache: 32K, L1 D cache: 32K >> (XEN) CPU: L2 cache: 256K >> (XEN) CPU: L3 cache: 3072K >> (XEN) mce_intel.c:1162: MCA Capability: BCAST 1 SER 0 CMCI 1 firstbank 0 extended MCE MSR 0 >> (XEN) CPU0: Thermal monitoring enabled (TM1) >> (XEN) Intel machine check reporting enabled >> (XEN) I/O virtualisation disabled >> (XEN) CPU0: Intel(R) Core(TM) i3-2100 CPU @ 3.10GHz stepping 07 >> (XEN) Enabled directed EOI with ioapic_ack_old on! >> (XEN) ENABLING IO-APIC IRQs >> (XEN) -> Using old ACK method >> (XEN) ..TIMER: vector=0xF0 apic1=0 pin1=2 apic2=-1 pin2=-1 >> (XEN) TSC deadline timer enabled >> (XEN) Platform timer is 14.318MHz HPET >> (XEN) Allocated console ring of 1048576 KiB. >> (XEN) VMX: Supported advanced features: >> (isation >> (XEN) - APIC TPR shadow >> (XEN) - Extended Page Tables (EPT) >> (XEN) - Virtual-Processor Identifiers (VPID) >> (XEN) - Virtual NMI >> (XEN) - MSR direct-access bitmap >> (XEN) - Unrestricted Guest >> (XEN) HVM: ASIDs enabled. >> (XEN) HVM: VMX enabled >> (XEN) HVM: Hardware Assisted Paging (HAP) detected >> (XEN) HVM: HAP page sizes: 4kB, 2MB >> (XEN) Booting processor 1/1 eip 7c000 >> (XEN) Initializing CPU#1 >> (XEN) CPU: Physical Processor ID: 0 >> (XEN) CPU: Processor Core ID: 0 >> (XEN) CPU: L1 I cache: 32K, L1 D >> (XEN) Initializing CPU#2 >> (XEN) CPU: Physical Processor ID: 0 >> (XEN) CPU: Processor Core ID: 1 >> (XEN) CPU: L1 I cache: 32K, L1 D cache: 32K >> (XEN) CPU: L2 cache: 256K >> (XEN) CPU: L3 cache: 3072K >> (XEN) CPU2: Thermal monitoring enabled (TM1) >> (XEN) CPU2: Intel(R) Core(TM) i3-2100 CPU @ 3.10GHz stepping 07 >> (XEN) Booting processor 3/3 eip 7c000 >> (XEN) Initializing CPU#3 >> (XEN) CPU: Physical Processor ID: 0 >> (XEN) CPU: Processor Core ID: 1 >> (XEN) CPU: L1 I cache: 32K, L1 D100 CPU @ 3.10GHz stepping 07 >> (XEN) Brought up 4 CPUs >> (XEN) ACPI sleep modes: S3 >> (XEN) mcheck_poll: Machine check polling timer started. >> (XEN) *** LOADING DOMAIN 0 *** >> (XEN) elf_parse_binary: phdr: paddr=0x1000000 memsz=0x9e0000 >> (XEN) elf_parse_binary: phdr: paddr=0x1a00000 memsz=0xa60f0 >> (XEN): paddr=0x1abc000 memsz=0x61b000 >> (XEN) elf_parse_binary: memory: 0x1000000 -> 0x20d7000 >> (XEN) elf_xen_parse_note: GUEST_OS = "linux" >> (XEN) elf_xen_parse_note: GUEST_VERSION = "2.6" >> (XEN) elf_xen_parse_note: XEN_VERSION = "xen-3.0" >> (XEN) elf_xen_parse_note: VIRT_BASE = 0xffffffff80000000 >> (XEN) elf_xen_parse_note: ENTRY = 0xffffffff81abc1e0 >> (XEN) elf_xen_parse_note: HYPERCALL_PAGE = 0xffffffff81001000 >> (XEN) elf_xen_parse_note: FEATURES = "!writable_page_tables|pae_pgdir_above_4gb" >> (XEN) elf_xen_parse_note: PAE_MODE = "yes" >> (XEN) elf_xen_parse_note: LOADER = "generic" >> (XEN) elf_xen_parse_note: unknown xen elf note (0xd) >> (XEN) elf_xen_parse_note: SUSPEND_CANCEL = 0x1 >> (XEN) elf_xen_parse_note: HV_START_LOW = 0xffff800000000000 >> (XEN) elf_xen_parse_note: PADDR_OFFSET = 0x0 >> (XEN) elf_xen_addr_calc_check: addresses: >> (XEN) virt_base = 0xffffffff80000000 >> (XEN) elf_paddr_offset = 0x0 >> (XEN) virt_offset = 0xffffffff80000000 >> (XEN) virt_kstart = 0xffffffff81000000 >> (XEN) virt_kend = 0xffffffff820d7000 >> (XEN) virt_entry = 0xffffffff81abc1e0 >> (XEN) p2m_base = 0xffffffffffffffff >> (XEN) Xen kernel: 64-bit, lsb, compat32 >> (XEN) Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x20d7000 >> (XEN) PHYSICAL MEMORY ARRANGEMENT: >> (XEN) Dom0 alloc.: 0000000220000000->0000000224000000 (1661249 pages to be allocated) >> (XEN) Init. ramdisk: 000000022cbdc000->000000023fe00000 >> (XEN) VIRTUAL MEMORY ARRANGEMENT: >> (XEN) Loaded kernel: ffffffff81000000->ffffffff820d7000 >> (XEN) Init. ramdisk: ffffffff820d7000->ffffffff952fb000 >> (XEN) Phys-Mach map: ffffffff952fb000->ffffffff96060b28 >> (XEN) Start info: ffffffff96061000->ffffffff960614b4 >> (XEN) Page tables: ffffffff96062000->ffffffff96117000 >> (XEN) Boot stack: ffffffff96117000->ffffffff96118000 >> (XEN) TOTAL: ffffffff80000000->ffffffff96400000 >> (XEN) ENTRY ADDRESS: ffffffff81abc1e0 >> (XEN) Dom0 has maximum 4 VCPUs >> (XEN) elf_load_binary: phdr 0 at 0xffffffff81000000 -> 0xffffffff819e0000 >> (XEN) elf_load_binary: phdr 1 at 0xffffffff81a00000 -> 0xffffffff81aa60f0 >> (XEN) elf_load_binary: phdr 2 at 0xffffffff81aa7000 -> 0xffffffff81abbbc0 >> (XEN) elf_load_binary: phdr 3 at 0xffffffff81abc000 -> 0xffffffff81baf000 >> (XEN) Scrubbing Free RAM: .done. >> (XEN) Xen trace buffers: disabled >> (XEN) Std. Loglevel: All >> (XEN) Guest Loglevel: All >> (XEN) ***************************intended to aid debugging of Xen by ensuring >> (XEN) ******* that all output is synchronously delivered on the serial line. >> (XEN) ******* However it can introduce SIGNIFICANT latencies and affect >> (XEN) ******* timekeeping. It is NOT recommended for production use! >> (XEN) ********************************************** >> (XEN) 3... 2... 1... >> (XEN) Xen is relinquishing VGA console. >> (XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen) >> (XEN) Freed 224kB init memory. >> mapping kernel into physical memory >> about to get started... >> [ 0.000000] Initializing cgroup subsys cpuset >> [ 0.000000] Initializing cgroup subsys cpu >> [ 0.000000] Linux version 3.8.0upstream-06471-g2ef14f4-dirty (konrad@build.dumpdata.com) (gcc version 4.4.4 20100503 (Red Hat 4.4.4-2) (GCC) ) #1 SMP Fri Feb 22 11:36:48 EST 2013 >> [ 0.000000] Command line: initcall_debug debug console=hvc0 loglevel=10 xen-pciback.hide=(01:00.0) earlyprintk=xen >> [ 0.000000] Freeing 9e-100 pfn range: 98 pages freed >> [ 0.000000] 1-1 mapping on 9e->100 >> [ 0.000000] Freeing 20000-20200 pfn range: 512 pages freed >> [ 0.000000] 1-1 mapping on 20000->20200 >> [ 0.000000] Freeing 40000-40200 pfn range: 512 pages freed >> [ 0.000000] 1-1 mapping on 40000->40200 >> [ 0.000000] Freeing bad80-badf4 pfn range: 116 pages freed >> [ 0.000000] 1-1 mapping on bad80->badf4 >> [ 0.000000] Freeing badf6-bae7f pfn range: 137 pages freed >> [ 0.000000] 1-1 mapping on badf6->bae7f >> [ 0.000000] Freeing bb000-100000 pfn range: 282624 pages freed >> [ 0.000000] 1-1 mapping on bb000->100000 >> [ 0.000000] Released 283999 pages of unused memory >> [ 0.000000] Set 283999 page(s) to 1-1 mapping >> [ 0.000000] Populating 1acb65-1f20c4 pfn range: 283999 pages added >> [ 0.000000] e820: BIOS-provided physical RAM map: >> [ 0.000000] Xen: [mem 0x0000000000000000-0x000000000009dfff] usable >> [ 0.000000] Xen: [mem 0x000000000009ec00-0x00000000000fffff] reserved >> [ 0.000000] Xen: [mem 0x0000000000100000-0x000000001fffffff] usable >> [ 0.000000] Xen: [mem 0x0000000020000000-0x00000000201fffff] reserved >> [ 0.000000] Xen: [mem 0x0000000020200000-0x000000003fffffff] usable >> [ 0.000000] Xen: [mem 0x0000000040000000-0x00000000401fffff] reserved >> [ 0.000000] Xen: [mem 0x0000000040200000-0x00000000bad7ffff] usable >> [ 0.000000] Xen: [mem 0x00000000bad80000-0x00000000badc8fff] ACPI NVS >> [ 0.000000] Xen: [mem 0x00000000badc9000-0x00000000badd0fff] ACPI data >> [ 0.000000] Xen: [mem 0x00000000badd1000-0x00000000badf3fff] reserved >> [ 0.000000] Xen: [mem 0x00000000badf4000-0x00000000badf5fff] usable >> [ 0.000000] Xen: [mem 0x00000000badf6000-0x00000000bae05fff] reserved >> [ 0.000000] Xen: [mem 0x00000000bae06000-0x00000000bae13fff] ACPI NVS >> [ 0.000000] Xen: [mem 0x00000000bae14000-0x00000000bae3bfff] reserved >> [ 0.000000] Xen: [mem 0x00000000bae3c000-0x00000000bae7efff] ACPI NVS >> [ 0.000000] Xen: [mem 0x00000000bae7f000-0x00000000baffffff] usable >> [ 0.000000] Xen: [mem 0x00000000bb800000-0x00000000bf9fffff] reserved >> [ 0.000000] Xen: [mem 0x00000000fec00000-0x00000000fec00fff] reserved >> [ 0.000000] Xen: [mem 0x00000000fed1c000-0x00000000fed3ffff] reserved >> [ 0.000000] Xen: [mem 0x00000000fee00000-0x00000000fee00fff] reserved >> [ 0.000000] Xen: [mem 0x00000000ff000000-0x00000000ffffffff] reserved >> [ 0.000000] Xen: [mem 0x0000000100000000-0x000000023fdfffff] usable >> [ 0.000000] bootconsole [xenboot0] enabled >> [ 0.000000] NX (Execute Disable) protection: active >> [ 0.000000] SMBIOS 2.7 present. >> [ 0.000000] DMI: MSI MS-7680/H61M-P23 (MS-7680), BIOS V17.0 03/14/2011 >> [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved >> [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable >> [ 0.000000] No AGP bridge found >> [ 0.000000] e820: last_pfn = 0x23fe00 max_arch_pfn = 0x400000000 >> [ 0.000000] e820: lacanning 1 areas for low memory corruption >> [ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 >> [ 0.000000] reserving inaccessible SNB gfx pages >> [ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] >> [ 0.000000] [mem 0x00000000-0x000fffff] page 4k >> [ 0.000000] init_memory_mapping: [mem 0x1f2000000-0x1f20c3fff] >> [ 0.000000] [mem 0x1f2000000-0x1f20c3fff] page 4k >> [ 0.000000] BRK [0x01cd2000, 0x01cd2fff] PGTABLE >> [ 0.000000] BRK [0x01cd3000, 0x01cd3fff] PGTABLE >> [ 0.000000] init_memory_mapping: [mem 0x1f0000000-0x1f1ffffff] >> [ 0.000000] [mem 0x1f0000000-0x1f1ffffff] page 4k >> [ 0.000000] BRK [0x01cd4000, 0x01cd4fff] PGTABLE >> [ 0.000000] BRK [0x01cd5000, 0x01cd5fff] PGTABLE >> [ 0.000000] BRK [0x01cd6000, 0x01cd6fff] PGTABLE >> [ 0.000000] init_memory_mapping: [mem 0x180000000-0x1efffffff] >> [ 0.000000] [mem 0x180000000-0x1efffffff] page 4k >> [ 0.000000] init_memory_mapping: [mem 0x00100000-0x1fffffff] >> [ 0.000000] [mem 0x00100000-0x1fffffff] page 4k >> [ 0.000000] init_memory_mapping: [mem 0x20200000-0x3fffffff] >> [ 0.000000] [mem 0x20200000-0x3fffffff] page 4k >> [ 0.000000] init_memory_mapping: [mem 0x40200000-0xbad7ffff] >> [ 0.000000] [mem 0x40200000-0xbad7ffff] page 4k >> [ 0.000000] init_memory_mapping: [mem 0xbadf4000-0xbadf5fff] >> [ 0.000000] [mem 0xbadf4000-0xbadf5fff] page 4k >> [ 0.000000] init_memory_mapping: [mem 0xbae7f000-0xbaffffff] >> [ 0.000000] [mem 0xbae7f000-0xbaffffff] page 4k >> [ 0.000000] init_memory_mapping: [mem 0x100000000-0x17fffffff] >> [ 0.000000] [mem 0x100000000-0x17fffffff] page 4k >> [ 0.000000] init_memory_mapping: [mem 0x1f20c4000-0x23fdfffff] >> [ 0.000000] [mem 0x1f20c4000-0x23fdfffff] page 4k > so init_memory_mapping are all done. > >> (XEN) d0:v0: unhandled page fault (ec=0000) >> (XEN) Pagetable walk from ffffea000005b2d0: >> (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff >> (XEN) domain_crash_sync called from entry.S >> (XEN) Domain 0 (vcpu#0) crashed on cpu#0: >> (XEN) ----[ Xen-4.1.5-pre x86_64 debug=y Tainted: C ]---- >> (XEN) CPU: 0 >> (XEN) RIP: e033:[] >> (XEN) RFLAGS: 0000000000000206 EM: 1 CONTEXT: pv guest >> (XEN) rax: ffffea0000000000 rbx: 0000000001a0c000 rcx: 0000000080000000 >> (XEN) rdx: 000000000005b2a0 rsi: 0000000001a0c000 rdi: 0000000000000000 >> (XEN) rbp: ffffffff81a01dd8 rsp: ffffffff81a01d90 r8: 0000000000000000 >> (XEN) r9: 0000000010000001 r10: 0000000000000005 r11: 0000000000100000 >> (XEN) r12: 0000000000000000 r13: 0000020000000000 r14: 0000000000000000 >> (XEN) r15: 0000000000100000 cr0: 000000008005003b cr4: 00000000000026f0 >> (XEN) cr3: 0000000221a0c000 cr2: ffffea000005b2d0 >> (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 >> (XEN) Guest stack trace from rsp=ffffffff81a01d90: >> (XEN) 0000000080000000 0000000000100000 0000000000000000 ffffffff8103feba >> (XEN) 000000010000e030 0000000000010006 ffffffff81a01dd8 000000000000e02b >> (XEN) 0000000000000000 ffffffff81a01e08 ffffffff81042d27 000000023fe00000 >> (XEN) 00000001f20c4000 0000020000000000 00000001acac7000 ffffffff81a01e48 >> (XEN) ffffffff81ad2d21 0000000000000000 0000000000000028 0000000040004000 >> (XEN) 0000000000000000 0000000000000000 0000000000000000 ffffffff81a01ed8 >> (XEN) ffffffff81ac293f ffffffff81b46900 0000000000000000 0000000000000000 >> (XEN) 0000000000000000 ffffffff81a01f00 ffffffff8165fbd1 ffffffff00000010 >> (XEN) ffffffff81a01ee8 ffffffff81a01ea8 0000000000000000 ffffffff81a01ec8 >> (XEN) ffffffffffffffff ffffffff81b46900 0000000000000000 0000000000000000 >> (XEN) 0000000000000000 ffffffff81a01f28 ffffffff81abcd62 ffffffff96062000 >> (XEN) ffffffff81cc6000 ffffffff81ccd000 ffffffff81b4f2e0 0000000000000000 >> (XEN) 0000000000000000 0000000000000000 0000000000000000 ffffffff81a01f38 >> (XEN) ffffffff81abc5f7 ffffffff81a01ff8 ffffffff81abf0c7 0300000100000032 >> (XEN) 0000000000000005 0000000000000000 0000000000000000 0000000000000000 >> (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 >> (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 >> (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 >> (XEN) 0000000000000000 819822831fc9cbf5 000206a700100800 0000000000000001 >> (XEN) 0000000000000000 0000000000000000 0f00000060c0c748 ccccccccccccc305 >> (XEN) Domain 0 crashed: rebooting machine in 5 seconds. >> (XEN) Resetting with ACPI MEMORY or I/O RESET_REG. > can we get kernel trace instead? (XEN) d0:v0: unhandled page fault (ec=0000) (XEN) Pagetable walk from ffffea000005b2d0: (XEN) L4[0x1d4] = 0000000000000000 ffffffffffffffff (XEN) domain_crash_sync called from entry.S This means that Xen was unable to context switch back to dom0 The value in rax looks suspiciously related to the faulting address in cr2. Konrad: is the instruction at ffffffff8103feba possibly a rax-relative dereference? ~Andrew > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel From hpa@zytor.com Fri Feb 22 19:28:02 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Feb 2013 19:28:10 +0100 (CET) Received: from terminus.zytor.com ([198.137.202.10]:41873 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827583Ab3BVS2CSmMly (ORCPT ); Fri, 22 Feb 2013 19:28:02 +0100 Received: from [22.165.177.223] (me40536d0.tmodns.net [208.54.5.228]) (authenticated bits=0) by mail.zytor.com (8.14.5/8.14.5) with ESMTP id r1MIOx7d027151 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=NO); Fri, 22 Feb 2013 10:25:00 -0800 Message-Id: <201302221825.r1MIOx7d027151@mail.zytor.com> User-Agent: K-9 Mail for Android In-Reply-To: References: <201302220034.r1M0Y6O8008311@terminus.zytor.com> <20130222165531.GA29308@phenom.dumpdata.com> <5127A719.3060702@zytor.com> <20130222173805.GC7768@phenom.dumpdata.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [GIT PULL] x86/mm changes for v3.9-rc1 From: "H. Peter Anvin" Date: Fri, 22 Feb 2013 10:24:48 -0800 To: Yinghai Lu , Stefano Stabellini CC: Konrad Rzeszutek Wilk , "H. Peter Anvin" , Linus Torvalds , "David S. Miller" , "Rafael J. Wysocki" , "stable@vger.kernel.org" , Alexander Duyck , Andrea Arcangeli , Andrew Morton , Andrzej Pietrasiewicz , Arnd Bergmann , Borislav Petkov , Borislav Petkov , Christoph Lameter , Daniel J Blueman , Dave Hansen , Eric Biederman , Fenghua Yu , Frederic Weisbecker , Gleb Natapov , Gokul Caushik , "H. J. Lu" , Hugh Dickins , Ingo Molnar , Ingo Molnar , Jacob Shin , Jamie.Lokier@zytor.com X-archive-position: 35821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 3676 Lines: 70 ,Jarkko Sakkinen ,Jeremy Fitzhardinge ,Joe Millenbach ,Joerg Roedel ,Johannes Weiner ,Josh Triplett ,Kyungmin Park ,Lee Schermerhorn ,Len Brown ,Linux Kernel Mailing List ,Marcelo Tosatti ,Marek Szyprowski ,Matt Fleming ,Mel Gorman ,Paul Turner ,Pavel Machek ,Pekka Enberg ,Peter Zijlstra ,Ralf Baechle ,Rik van Riel ,Rob Landley ,Russell King ,Rusty Russell ,Shuah Khan ,Shuah Khan ,Steven Rostedt ,Thomas Gleixn! er ,=?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= ,Yasuaki Ishimatsu ,Zachary Amsden ,"avi@redhat.com" ,"linux-mips@linux-mips.org" ,"linux-pm@vger.kernel.org" ,"mst@redhat.com" ,"sparclinux@vger.kernel.org" ,"virtualization@lists.linux-foundation.org" ,"xen-devel@lists.xensource.com" Message-ID: <1b89b5cf-4ad4-4c25-ab76-a8ac6910c2ec@email.android.com> Again... you probably want to check into Dave's debug changes first. Makes more sense. Yinghai Lu wrote: >On Fri, Feb 22, 2013 at 10:06 AM, Stefano Stabellini > wrote: >> On Fri, 22 Feb 2013, Konrad Rzeszutek Wilk wrote: >>> On Fri, Feb 22, 2013 at 09:12:57AM -0800, H. Peter Anvin wrote: >>> > On 02/22/2013 08:55 AM, Konrad Rzeszutek Wilk wrote: >>> > > >>> > >What is bizzare is that I do recall testing this (and Stefano >also did it). >>> > >So I am not sure what has altered. >>> > > >>> > >>> > Yes, there was a very specific reason why I wanted you guys to >test it... >>> >>> Exactly. And I re-ran the same test, but with a new kernel. This is >what >>> git reflog tells me: >>> >>> 473cd24 HEAD@{75}: checkout: moving from >08f321ed97353cf3b3fafa6b1c1971d6a8970830 to linux-next >>> 08f321e HEAD@{76}: checkout: moving from linux-next to >yinghai/for-x86-mm >>> eb827a7 HEAD@{77}: checkout: moving from >1b66ccf15ff4bd0200567e8d70446a8763f96ee7 to linux-next >>> [konrad@build linux]$ git show 08f321e >>> commit 08f321ed97353cf3b3fafa6b1c1971d6a8970830 >>> Author: Yinghai Lu >>> Date: Thu Nov 8 00:00:19 2012 -0800 >>> >>> mm: Kill NO_BOOTMEM version free_all_bootmem_node() >>> >>> And I recall Stefano later on testing (I was in a conference and did >not have >>> the opportunity to test it). Not sure what he ran with. >>> >> >> FYI the last patch series I tested was Yinghai's "x86, boot, 64bit: >Add >> support for loading ramdisk and bzImage above 4G" v7u1. > > >the one in tip and linus's tree is >--- >-v7u2: update changelog and comments, and clear more fields for >sentinel. > Update swiotlb autoswitch off patch. > Fix crash with xen PV guest with 2G. >--- > >and it fixes xen crash that you reported with v7u1, and you tested >that add-on patch >fix_xen_2g.patch with v7u1. >and I fold the addon patch into offending patch in v7u2. > > >Thanks > >Yinghai -- Sent from my mobile phone. Please excuse brevity and lack of formatting. From alexander.shishkin@linux.intel.com Tue Feb 26 14:34:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 26 Feb 2013 14:34:19 +0100 (CET) Received: from mga02.intel.com ([134.134.136.20]:16201 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823015Ab3BZNeQYEsGi (ORCPT ); Tue, 26 Feb 2013 14:34:16 +0100 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 26 Feb 2013 05:34:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,740,1355126400"; d="scan'208";a="290665763" Received: from um.fi.intel.com (HELO localhost) ([10.237.72.68]) by orsmga002.jf.intel.com with ESMTP; 26 Feb 2013 05:34:03 -0800 From: Alexander Shishkin To: Svetoslav Neykov , Ralf Baechle , Greg Kroah-Hartman , Gabor Juhos , John Crispin , Alan Stern , "Luis R. Rodriguez" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, Svetoslav Neykov Subject: Re: [PATCH 0/5] Chipidea driver support for the AR933x platform In-Reply-To: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> User-Agent: Notmuch/0.12+187~ga2502b0 (http://notmuchmail.org) Emacs/23.4.1 (x86_64-pc-linux-gnu) Date: Tue, 26 Feb 2013 15:35:55 +0200 Message-ID: <87k3pvxkn8.fsf@ashishki-desk.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-archive-position: 35822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexander.shishkin@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 491 Lines: 15 Svetoslav Neykov writes: > Add support for the usb controller in AR933x platform. > The processor is big-endian so all multi-byte values of the usb > descriptors must be converted explicitly. Another difference is that > the controller supports both host and device modes but not OTG. > The patches are tested on WR703n router running OpenWRT trunk. Svetoslav, are you working on these or do you have time to address the issues raised in review? Thanks, -- Alex From svetoslav@neykov.name Tue Feb 26 15:39:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 26 Feb 2013 15:39:07 +0100 (CET) Received: from mail-ee0-f45.google.com ([74.125.83.45]:38138 "EHLO mail-ee0-f45.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820301Ab3BZOjEGzGsZ (ORCPT ); Tue, 26 Feb 2013 15:39:04 +0100 Received: by mail-ee0-f45.google.com with SMTP id b57so2344820eek.4 for ; Tue, 26 Feb 2013 06:38:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:references:in-reply-to:subject:date :message-id:mime-version:content-type:content-transfer-encoding :x-mailer:thread-index:content-language:x-gm-message-state; bh=MqkHjRT/6InU8FH1XU2wcv58o2lzObGTpx/2gFKCRbk=; b=TK9C292mf3UlSKv4NDct5dnkf2IIIQd0CFxlE9cjJ5LcNOTcGQsQQo8sgFVQ6VAHLN 2Uarc9LqhM7x+CtPdSpewJLPMydHHHktnvILhPCVQprS2kKfEj8QjAHWfpHoOIS5yvoy /ESBSTNIJWOw6L2t5IJ45DxtOM2re/w67n1l8kWt+Im3h186rgBfkqGXD/Rd2h6Tl64r W5VmZiT4ETD4+kAEs6kAO6aZSjM+om9vx/H7erqDMllqJm6rBoWgnKk0Tk9gp5/YsGJk qpFqKgSGC0TlApOpt116ImQRCIFhCDGzLfrVlpj7jBLRKaHucUiv2ohP/hMxo+BaJOAy 9fSw== X-Received: by 10.14.210.132 with SMTP id u4mr50314729eeo.19.1361889538276; Tue, 26 Feb 2013 06:38:58 -0800 (PST) Received: from hotrod ([77.70.100.51]) by mx.google.com with ESMTPS id l8sm1792933een.10.2013.02.26.06.38.56 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 26 Feb 2013 06:38:57 -0800 (PST) From: "Svetoslav Neykov" To: "'Alexander Shishkin'" , "'Ralf Baechle'" , "'Greg Kroah-Hartman'" , "'Gabor Juhos'" , "'John Crispin'" , "'Alan Stern'" , "'Luis R. Rodriguez'" Cc: , References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <87k3pvxkn8.fsf@ashishki-desk.ger.corp.intel.com> In-Reply-To: <87k3pvxkn8.fsf@ashishki-desk.ger.corp.intel.com> Subject: RE: [PATCH 0/5] Chipidea driver support for the AR933x platform Date: Tue, 26 Feb 2013 16:38:53 +0200 Message-ID: <078801ce142f$0108dea0$031a9be0$@neykov.name> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 14.0 thread-index: AQGDG6p+wHZ3zGBMHoZ7+PlD69kkYAF6L3a2mRZUdmA= Content-Language: bg X-Gm-Message-State: ALoCoQnhfKQxoZN9IBv/smSSd2KgKEttAp40pGoCp02y16tIHmcuJq4taHJebs2hw6cZbjw0w0cg X-archive-position: 35823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: svetoslav@neykov.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1135 Lines: 33 Hi Alex, I am working on the incorporating all received comments - thanks to all for taking their time to comment. Apologies for not replying to the received mails, didn't want to spam with OK replies to each separately. Regards, Svetoslav. -----Original Message----- From: Alexander Shishkin [mailto:alexander.shishkin@linux.intel.com] Sent: Tuesday, February 26, 2013 3:36 PM To: Svetoslav Neykov; Ralf Baechle; Greg Kroah-Hartman; Gabor Juhos; John Crispin; Alan Stern; Luis R. Rodriguez Cc: linux-mips@linux-mips.org; linux-usb@vger.kernel.org; Svetoslav Neykov Subject: Re: [PATCH 0/5] Chipidea driver support for the AR933x platform Svetoslav Neykov writes: > Add support for the usb controller in AR933x platform. > The processor is big-endian so all multi-byte values of the usb > descriptors must be converted explicitly. Another difference is that > the controller supports both host and device modes but not OTG. > The patches are tested on WR703n router running OpenWRT trunk. Svetoslav, are you working on these or do you have time to address the issues raised in review? Thanks, -- Alex From alexander.shishkin@linux.intel.com Tue Feb 26 15:46:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 26 Feb 2013 15:46:12 +0100 (CET) Received: from mga02.intel.com ([134.134.136.20]:13830 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6820301Ab3BZOqLDl0Oa (ORCPT ); Tue, 26 Feb 2013 15:46:11 +0100 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 26 Feb 2013 06:46:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,740,1355126400"; d="scan'208";a="267863854" Received: from um.fi.intel.com (HELO localhost) ([10.237.72.68]) by orsmga001.jf.intel.com with ESMTP; 26 Feb 2013 06:45:59 -0800 From: Alexander Shishkin To: Svetoslav Neykov , 'Ralf Baechle' , 'Greg Kroah-Hartman' , 'Gabor Juhos' , 'John Crispin' , 'Alan Stern' , "'Luis R. Rodriguez'" Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org Subject: RE: [PATCH 0/5] Chipidea driver support for the AR933x platform In-Reply-To: <078801ce142f$0108dea0$031a9be0$@neykov.name> References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <87k3pvxkn8.fsf@ashishki-desk.ger.corp.intel.com> <078801ce142f$0108dea0$031a9be0$@neykov.name> User-Agent: Notmuch/0.12+187~ga2502b0 (http://notmuchmail.org) Emacs/23.4.1 (x86_64-pc-linux-gnu) Date: Tue, 26 Feb 2013 16:47:50 +0200 Message-ID: <878v6bxhbd.fsf@ashishki-desk.ger.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-archive-position: 35824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexander.shishkin@linux.intel.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 447 Lines: 15 Svetoslav Neykov writes: > Hi Alex, > I am working on the incorporating all received comments - thanks to all for > taking their time to comment. > Apologies for not replying to the received mails, didn't want to spam with > OK replies to each separately. Great, thanks! Looks like this patchset will need some synchronization with Sacha's dr_mode/phy_mode patchset, but I presume you're aware of that. Regards, -- Alex From svetoslav@neykov.name Tue Feb 26 15:55:01 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 26 Feb 2013 15:55:05 +0100 (CET) Received: from mail-ee0-f54.google.com ([74.125.83.54]:41674 "EHLO mail-ee0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823907Ab3BZOzBNOskf (ORCPT ); Tue, 26 Feb 2013 15:55:01 +0100 Received: by mail-ee0-f54.google.com with SMTP id c41so2468669eek.41 for ; Tue, 26 Feb 2013 06:54:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:references:in-reply-to:subject:date :message-id:mime-version:content-type:content-transfer-encoding :x-mailer:thread-index:content-language:x-gm-message-state; bh=6RgI3oV8uf5xQUmef9sfEYVW8mL8EYzqqhk3KHimCtI=; b=ahedxSS7/OkMNnNiVZCBNl0OF25ie86Zxy0jeKASgwOHSO5OHgGIZgiLnUT7j32gcs bb6O/dPisjSS6mZ8La/34DWeZFFBEbD3jfdSai147v2zmwwBuAjclUECVvgXhrPLta72 D9GkSItUBMnRxDurkfSQA+XQxk+0Orr5IFg1jrFw3aB4UKlWZvp1DuWj1xCa5DdozHEA aHnuF7iWxhLOH2Yi8IxJYMhmjicMa4nDxwaOL5xEI+PF6LY4sjKdRRwUNWSFZXYNkqbj KfIGuD707L8odeIbhyTMfd8kaPJlGWeQ3WPpNDxgkz8rb+V7kF8ySJ5jXGbuTsmG1fKs mncg== X-Received: by 10.14.179.194 with SMTP id h42mr50197864eem.46.1361890495848; Tue, 26 Feb 2013 06:54:55 -0800 (PST) Received: from hotrod ([77.70.100.51]) by mx.google.com with ESMTPS id 3sm1876437eej.6.2013.02.26.06.54.53 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 26 Feb 2013 06:54:54 -0800 (PST) From: "Svetoslav Neykov" To: "'Alexander Shishkin'" , "'Ralf Baechle'" , "'Greg Kroah-Hartman'" , "'Gabor Juhos'" , "'John Crispin'" , "'Alan Stern'" , "'Luis R. Rodriguez'" Cc: , References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <87k3pvxkn8.fsf@ashishki-desk.ger.corp.intel.com> <078801ce142f$0108dea0$031a9be0$@neykov.name> <878v6bxhbd.fsf@ashishki-desk.ger.corp.intel.com> In-Reply-To: <878v6bxhbd.fsf@ashishki-desk.ger.corp.intel.com> Subject: RE: [PATCH 0/5] Chipidea driver support for the AR933x platform Date: Tue, 26 Feb 2013 16:54:50 +0200 Message-ID: <078901ce1431$3bcc4980$b364dc80$@neykov.name> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 14.0 thread-index: AQGDG6p+wHZ3zGBMHoZ7+PlD69kkYAF6L3a2AO2krxMBvH6/M5kBBuvw Content-Language: bg X-Gm-Message-State: ALoCoQkqG/eurzN4XAGLO0bnQux8s7ZQkvM7q1kjoYHuiZnVhdQKXWy/ikkMe1r6VbHsVdc9RuDH X-archive-position: 35825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: svetoslav@neykov.name Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 259 Lines: 10 >Great, thanks! >Looks like this patchset will need some synchronization with Sacha's >dr_mode/phy_mode patchset, but I presume you're aware of that. Yes, I will base the next patch on the existing changes, thanks for bringing that up. Regards, Svetoslav. From mkl@pengutronix.de Tue Feb 26 16:45:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 26 Feb 2013 16:45:43 +0100 (CET) Received: from metis.ext.pengutronix.de ([92.198.50.35]:50537 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6818018Ab3BZPpjMDQRx (ORCPT ); Tue, 26 Feb 2013 16:45:39 +0100 Received: from gallifrey.ext.pengutronix.de ([2001:6f8:1178:4:5054:ff:fe8d:eefb] helo=bjornoya.do.blackshift.org) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1UAMii-000707-Qy; Tue, 26 Feb 2013 16:45:32 +0100 Received: from [IPv6:2001:6f8:105b:1122:21d:e0ff:fe39:f61b] (hardanger.wlan.blackshift.org [IPv6:2001:6f8:105b:1122:21d:e0ff:fe39:f61b]) (using TLSv1 with cipher ECDHE-ECDSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: frogger) by bjornoya.do.blackshift.org (Postfix) with ESMTPSA id BCD3B5EA03; Tue, 26 Feb 2013 16:45:27 +0100 (CET) Message-ID: <512CD893.50904@pengutronix.de> Date: Tue, 26 Feb 2013 16:45:23 +0100 From: Marc Kleine-Budde Organization: Pengutronix e.K. User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130215 Thunderbird/17.0.3 MIME-Version: 1.0 To: Alexander Shishkin CC: Svetoslav Neykov , 'Ralf Baechle' , 'Greg Kroah-Hartman' , 'Gabor Juhos' , 'John Crispin' , 'Alan Stern' , "'Luis R. Rodriguez'" , linux-mips@linux-mips.org, linux-usb@vger.kernel.org Subject: Re: [PATCH 0/5] Chipidea driver support for the AR933x platform References: <1360791538-6332-1-git-send-email-svetoslav@neykov.name> <87k3pvxkn8.fsf@ashishki-desk.ger.corp.intel.com> <078801ce142f$0108dea0$031a9be0$@neykov.name> <878v6bxhbd.fsf@ashishki-desk.ger.corp.intel.com> In-Reply-To: <878v6bxhbd.fsf@ashishki-desk.ger.corp.intel.com> X-Enigmail-Version: 1.5 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="----enig2WVSVJIHALOVQLUUILEHP" X-SA-Exim-Connect-IP: 2001:6f8:1178:4:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: mkl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-mips@linux-mips.org X-archive-position: 35826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mkl@pengutronix.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 1607 Lines: 49 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) ------enig2WVSVJIHALOVQLUUILEHP Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On 02/26/2013 03:47 PM, Alexander Shishkin wrote: > Svetoslav Neykov writes: >=20 >> Hi Alex, >> I am working on the incorporating all received comments - thanks to al= l for >> taking their time to comment. >> Apologies for not replying to the received mails, didn't want to spam = with >> OK replies to each separately. >=20 > Great, thanks! > Looks like this patchset will need some synchronization with Sacha's > dr_mode/phy_mode patchset, but I presume you're aware of that. The current version of Sascha's patches is here: http://git.pengutronix.de/?p=3Dmgr/linux.git;a=3Dshortlog;h=3Drefs/heads/= chipidea-for-v3.10 Marc --=20 Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions | Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de | ------enig2WVSVJIHALOVQLUUILEHP Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iEYEARECAAYFAlEs2JYACgkQjTAFq1RaXHN2SwCdE8hBKqI+SZFviAk8J0e3QYrs 5IIAnAyW/+nkXufj/0xm3nITM5btme7L =tOL2 -----END PGP SIGNATURE----- ------enig2WVSVJIHALOVQLUUILEHP-- From ddaney.cavm@gmail.com Tue Feb 26 23:36:36 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 26 Feb 2013 23:36:37 +0100 (CET) Received: from mail-da0-f44.google.com ([209.85.210.44]:41825 "EHLO mail-da0-f44.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825727Ab3BZWggahll8 (ORCPT ); Tue, 26 Feb 2013 23:36:36 +0100 Received: by mail-da0-f44.google.com with SMTP id z20so2240457dae.31 for ; Tue, 26 Feb 2013 14:36:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=k/d2tkXDtEvmpQZNFOeShUva0bvPoxsqNVLILvLF01Q=; b=H3JI7dRttIZZvmTtnhlgcUTCTCf5qNP6gYHgDvLUsGBgV3QK9OsXOh1xD9Fjv2y3L6 g1c02bb1ZKWtSslAja14ySA61zRT932QUwSfE+Je50d34VwEt8FfrlqZ8M72/x0j3dwU 4LkD8BPVrrK4S0DW45xbn7A+xSIOGPcOON6Utf8y9FQrX9wQ/LoGIjhV1e2Hu5cBxqgr m6c+LV0GqTsGq6TPXiuNiMgAfloUHL0BJHTJyxUDkrz7Ef1L3x93jfOZZ17OH/QUU68b 9hUIMY+HB5wY0cbhFdRAXHDyAPnZmUc0BRujCeQYs4EcChmylAA6E7Y8rGH/ZsY+wZeN ShiQ== X-Received: by 10.68.31.73 with SMTP id y9mr26236508pbh.102.1361918189624; Tue, 26 Feb 2013 14:36:29 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id j7sm2840130pay.10.2013.02.26.14.36.28 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 26 Feb 2013 14:36:28 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r1QMZQbW019438; Tue, 26 Feb 2013 14:35:26 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r1QMZPFG019437; Tue, 26 Feb 2013 14:35:25 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Jim Quinlan , Subject: [PATCH] MIPS: Fix logic errors in bitops.c Date: Tue, 26 Feb 2013 14:35:23 -0800 Message-Id: <1361918123-19404-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-archive-position: 35828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2551 Lines: 95 From: David Daney commit 92d11594f6 (MIPS: Remove irqflags.h dependency from bitops.h) factored some of the bitops code out into a separate file (arch/mips/lib/bitops.c). Unfortunately the logic converting a bit mask into a boolean result was lost in some of the functions. We had: int res; unsigned long shifted_result_bit; . . . res = shifted_result_bit; return res; Which truncates off the high 32 bits (thus yielding an incorrect value) on 64-bit systems. The manifestation of this is that a non-SMP 64-bit kernel will not boot as the bitmap operations in bootmem.c are all screwed up. Signed-off-by: David Daney Cc: Jim Quinlan Cc: --- arch/mips/lib/bitops.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c index 239a9c9..f3f7756 100644 --- a/arch/mips/lib/bitops.c +++ b/arch/mips/lib/bitops.c @@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr, unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; - unsigned long res; + int res; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - res = (mask & *a); + res = (mask & *a) != 0; *a |= mask; raw_local_irq_restore(flags); return res; @@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr, unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; - unsigned long res; + int res; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - res = (mask & *a); + res = (mask & *a) != 0; *a |= mask; raw_local_irq_restore(flags); return res; @@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; - unsigned long res; + int res; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - res = (mask & *a); + res = (mask & *a) != 0; *a &= ~mask; raw_local_irq_restore(flags); return res; @@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr) unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; - unsigned long res; + int res; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - res = (mask & *a); + res = (mask & *a) != 0; *a ^= mask; raw_local_irq_restore(flags); return res; -- 1.7.11.7 From ddaney.cavm@gmail.com Wed Feb 27 00:23:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 27 Feb 2013 00:23:46 +0100 (CET) Received: from mail-da0-f50.google.com ([209.85.210.50]:43881 "EHLO mail-da0-f50.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825727Ab3BZXXnjPvYl (ORCPT ); Wed, 27 Feb 2013 00:23:43 +0100 Received: by mail-da0-f50.google.com with SMTP id h15so2064725dan.37 for ; Tue, 26 Feb 2013 15:23:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=HcSQJ/hVUgWLfJmNTO7bw32/1mMD8d+Tl3HN2TUTaGM=; b=K0TFPAPufG96xGweQn0eaWmdvcrA4vhhg/XG1hbVj/nM9jy8CbN2R5a//jUv4aAp9B NjT9e1h6eTfLxUCvOMitCan7gSizHNgbYIXTWfX/O57U6Mhj2SP5+GYnZak+XvTk2Jzi YI8dVnsstiMVa8nS8a3unqJQtzsWxbwNtZl189kUaOygvm27AzGcHuWcbHmh2oDw4bft Kt00F4zjej14ZJ7vKju3vKzqu2jchhLQvnUwz2L1C7loRvclizSOIoZu5GpVEvX4N8AN 5f2/nMjU+ji8PfFzUwn7krwDGCyeJW6FsezClBUUmihOKAJjKFBKxf8Qb0OECd1lNONd +nEQ== X-Received: by 10.66.217.164 with SMTP id oz4mr4281840pac.132.1361921017156; Tue, 26 Feb 2013 15:23:37 -0800 (PST) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPS id jp9sm2358209pbb.7.2013.02.26.15.23.35 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 26 Feb 2013 15:23:36 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r1QNMYQM019903; Tue, 26 Feb 2013 15:22:34 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r1QNMYf9019902; Tue, 26 Feb 2013 15:22:34 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Remove unneeded volatile from arch/mips/lib/bitops.c Date: Tue, 26 Feb 2013 15:22:33 -0800 Message-Id: <1361920953-19869-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-archive-position: 35829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: Content-Length: 2648 Lines: 82 From: David Daney The operations on the bitmap pointers are protected by "memory" clobbering raw_local_irq_{save,restore}(), so there is no need for volatile here. By removing the volatile we get better code generation out of the compiler. Signed-off-by: David Daney --- arch/mips/lib/bitops.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c index f3f7756..485846c 100644 --- a/arch/mips/lib/bitops.c +++ b/arch/mips/lib/bitops.c @@ -19,7 +19,7 @@ */ void __mips_set_bit(unsigned long nr, volatile unsigned long *addr) { - volatile unsigned long *a = addr; + unsigned long *a = (unsigned long *)addr; unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; @@ -41,7 +41,7 @@ EXPORT_SYMBOL(__mips_set_bit); */ void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr) { - volatile unsigned long *a = addr; + unsigned long *a = (unsigned long *)addr; unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; @@ -63,7 +63,7 @@ EXPORT_SYMBOL(__mips_clear_bit); */ void __mips_change_bit(unsigned long nr, volatile unsigned long *addr) { - volatile unsigned long *a = addr; + unsigned long *a = (unsigned long *)addr; unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; @@ -86,7 +86,7 @@ EXPORT_SYMBOL(__mips_change_bit); int __mips_test_and_set_bit(unsigned long nr, volatile unsigned long *addr) { - volatile unsigned long *a = addr; + unsigned long *a = (unsigned long *)addr; unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; @@ -112,7 +112,7 @@ EXPORT_SYMBOL(__mips_test_and_set_bit); int __mips_test_and_set_bit_lock(unsigned long nr, volatile unsigned long *addr) { - volatile unsigned long *a = addr; + unsigned long *a = (unsigned long *)addr; unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; @@ -137,7 +137,7 @@ EXPORT_SYMBOL(__mips_test_and_set_bit_lock); */ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) { - volatile unsigned long *a = addr; + unsigned long *a = (unsigned long *)addr; unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; @@ -162,7 +162,7 @@ EXPORT_SYMBOL(__mips_test_and_clear_bit); */ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr) { - volatile unsigned long *a = addr; + unsigned long *a = (unsigned long *)addr; unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; -- 1.7.11.7