From bigeasy@linutronix.de Mon Jul 1 09:49:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 09:49:23 +0200 (CEST) Received: from www.linutronix.de ([62.245.132.108]:54465 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823690Ab3GAHtLB0MOd (ORCPT ); Mon, 1 Jul 2013 09:49:11 +0200 Received: from localhost ([127.0.0.1] helo=[172.123.10.21]) by Galois.linutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1UtYqr-0000Vs-UZ; Mon, 01 Jul 2013 09:48:46 +0200 Message-ID: <51D1345B.8020509@linutronix.de> Date: Mon, 01 Jul 2013 09:48:43 +0200 From: Sebastian Andrzej Siewior User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130518 Icedove/17.0.5 MIME-Version: 1.0 To: Santosh Shilimkar CC: Jean-Christophe PLAGNIOL-VILLARD , Grant Likely , Rob Herring , Nicolas Pitre , linux-mips , Aurelien Jacquiot , Catalin Marinas , Will Deacon , Max Filippov , Paul Mackerras , Jonas Bonn , Russell King , linux-c6x-dev@linux-c6x.org, x86@kernel.org, arm@kernel.org, linux-xtensa@linux-xtensa.org, James Hogan , devicetree-discuss , Rob Herring , "linux-arm-kernel@lists.infradead.org" , Chris Zankel , Vineet Gupta , Linux Kernel Mailing List , Ralf Baechle , "linuxppc-dev@lists.ozlabs.org" Subject: Re: [PATCH] of: Specify initrd location using 64-bit References: <1371775956-16453-1-git-send-email-santosh.shilimkar@ti.com> <51C4171C.9050908@linutronix.de> <51C48B5A.2040404@ti.com> <51CCA67C.2010803@gmail.com> <20130628134931.GD21034@game.jcrosoft.org> <51CE1F92.3070802@ti.com> In-Reply-To: <51CE1F92.3070802@ti.com> X-Enigmail-Version: 1.5.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37234 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bigeasy@linutronix.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 06/29/2013 01:43 AM, Santosh Shilimkar wrote: > > Sebastian, > > Apart from waste of 32bit, what is the other concern you > have ? You pass a u64 as a physical address which is represented in other parts of the kernel (for a good reason) by phys_addr_t. > I really want to converge on this patch because it > has been a open ended discussion for quite some time. Does > that really break any thing on x86 or your concern is more > from semantics of the physical address. You want to have your code in so you can continue with your work, that is okay. The other two arguments why u64 here is a good thing was "due to what I said earlier" and "+1" and I don't have the time to look that up. There should be no problems on x86 if this goes in as it is now. But think about this: What happens if you boot your ARM device without PAE and your initrd is in the upper region? If you are lucky the kernel looks at a different place where it also has a read permission, notices nothing sane is there, writes a message and continues. And if it is not allowed to read? It is clearly the user's fault for booting a non-PAE kernel. > > Thanks for help. > > Regards, > Santosh Sebastian From geert.uytterhoeven@gmail.com Mon Jul 1 09:59:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 09:59:41 +0200 (CEST) Received: from mail-pa0-f44.google.com ([209.85.220.44]:65192 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817030Ab3GAH7jkJJLj (ORCPT ); Mon, 1 Jul 2013 09:59:39 +0200 Received: by mail-pa0-f44.google.com with SMTP id lj1so4739774pab.17 for ; Mon, 01 Jul 2013 00:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=TxVQjSA4mZhCU8JK1LHE+Te+AOwSOzpWCDKBZhjmwYI=; b=uECOImqeW79XintTUg9+fffZPYr3IAhw4ups8HtHv7iEBIraYJdvymrM1mDDpA4vh6 ZvuLBwIcI0IykFnx2SvGJHwSZUIgm/01UZfBTPtRxtxd8C+vh/C5EEN/rttlX08llyyi y6v2uONJg56zHJiKu823CyoAMkoIAwXEFiB9bKzMmIcURINIU0NnaIBPO/I1NtVu1Z48 DMlOBp71Yt/s+DPZMhlolidxTzl4pWHoC2oRe8H24o4w3n47xV5ie4YWHuLXpwqAfCDz /vT3cUYKbWIIgqYKzTcJGx5HX/CgI2uaP7iPrauoCWl0zgwkOHAqGcHZk5eV2nyQxCCS LqfQ== MIME-Version: 1.0 X-Received: by 10.66.163.7 with SMTP id ye7mr3990157pab.24.1372665573137; Mon, 01 Jul 2013 00:59:33 -0700 (PDT) Received: by 10.70.78.197 with HTTP; Mon, 1 Jul 2013 00:59:33 -0700 (PDT) In-Reply-To: <51D1345B.8020509@linutronix.de> References: <1371775956-16453-1-git-send-email-santosh.shilimkar@ti.com> <51C4171C.9050908@linutronix.de> <51C48B5A.2040404@ti.com> <51CCA67C.2010803@gmail.com> <20130628134931.GD21034@game.jcrosoft.org> <51CE1F92.3070802@ti.com> <51D1345B.8020509@linutronix.de> Date: Mon, 1 Jul 2013 09:59:33 +0200 X-Google-Sender-Auth: VcBufR2SziNNSg6ZpNaW158x-28 Message-ID: Subject: Re: [PATCH] of: Specify initrd location using 64-bit From: Geert Uytterhoeven To: Sebastian Andrzej Siewior Cc: Santosh Shilimkar , Nicolas Pitre , linux-mips , Aurelien Jacquiot , Catalin Marinas , Will Deacon , Max Filippov , Paul Mackerras , Jonas Bonn , Russell King , linux-c6x-dev@linux-c6x.org, "the arch/x86 maintainers" , "arm@kernel.org" , Rob Herring , Grant Likely , Jean-Christophe PLAGNIOL-VILLARD , linux-xtensa@linux-xtensa.org, James Hogan , devicetree-discuss , Rob Herring , "linux-arm-kernel@lists.infradead.org" , Chris Zankel , Vineet Gupta , Linux Kernel Mailing List , Ralf Baechle , "linuxppc-dev@lists.ozlabs.org" Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37235 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Mon, Jul 1, 2013 at 9:48 AM, Sebastian Andrzej Siewior wrote: > On 06/29/2013 01:43 AM, Santosh Shilimkar wrote: >> Apart from waste of 32bit, what is the other concern you >> have ? > > You pass a u64 as a physical address which is represented in other > parts of the kernel (for a good reason) by phys_addr_t. > >> I really want to converge on this patch because it >> has been a open ended discussion for quite some time. Does >> that really break any thing on x86 or your concern is more >> from semantics of the physical address. > You want to have your code in so you can continue with your work, that > is okay. The other two arguments why u64 here is a good thing was "due > to what I said earlier" and "+1" and I don't have the time to look > that up. > > There should be no problems on x86 if this goes in as it is now. > > But think about this: What happens if you boot your ARM device without > PAE and your initrd is in the upper region? If you are lucky the kernel > looks at a different place where it also has a read permission, notices > nothing sane is there, writes a message and continues. And if it is not > allowed to read? It is clearly the user's fault for booting a non-PAE > kernel. That's actual the original reason: DT has it as 64 bit, and passes it to a 32 bit kernel when running in 32 bit mode without PAE. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From bigeasy@linutronix.de Mon Jul 1 10:09:54 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 10:09:55 +0200 (CEST) Received: from www.linutronix.de ([62.245.132.108]:54602 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817030Ab3GAIJx4ulAh (ORCPT ); Mon, 1 Jul 2013 10:09:53 +0200 Received: from localhost ([127.0.0.1] helo=[172.123.10.21]) by Galois.linutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1UtZB3-0000gR-68; Mon, 01 Jul 2013 10:09:37 +0200 Message-ID: <51D1393E.6060001@linutronix.de> Date: Mon, 01 Jul 2013 10:09:34 +0200 From: Sebastian Andrzej Siewior User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130518 Icedove/17.0.5 MIME-Version: 1.0 To: Geert Uytterhoeven CC: Santosh Shilimkar , Nicolas Pitre , linux-mips , Aurelien Jacquiot , Catalin Marinas , Will Deacon , Max Filippov , Paul Mackerras , Jonas Bonn , Russell King , linux-c6x-dev@linux-c6x.org, the arch/x86 maintainers , "arm@kernel.org" , Rob Herring , Grant Likely , Jean-Christophe PLAGNIOL-VILLARD , linux-xtensa@linux-xtensa.org, James Hogan , devicetree-discuss , Rob Herring , "linux-arm-kernel@lists.infradead.org" , Chris Zankel , Vineet Gupta , Linux Kernel Mailing List , Ralf Baechle , "linuxppc-dev@lists.ozlabs.org" Subject: Re: [PATCH] of: Specify initrd location using 64-bit References: <1371775956-16453-1-git-send-email-santosh.shilimkar@ti.com> <51C4171C.9050908@linutronix.de> <51C48B5A.2040404@ti.com> <51CCA67C.2010803@gmail.com> <20130628134931.GD21034@game.jcrosoft.org> <51CE1F92.3070802@ti.com> <51D1345B.8020509@linutronix.de> In-Reply-To: X-Enigmail-Version: 1.5.1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37236 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bigeasy@linutronix.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 07/01/2013 09:59 AM, Geert Uytterhoeven wrote: > That's actual the original reason: DT has it as 64 bit, and passes it to a > 32 bit kernel when running in 32 bit mode without PAE. And I think the DT code should check if the u64 fits in phys_addr_t and if does not it should write an error message and act like no initrd was specified (instead of passing "something" to the architecture). > > Gr{oetje,eeting}s, > > Geert > Sebastian From rusty@ozlabs.org Mon Jul 1 10:53:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 10:53:08 +0200 (CEST) Received: from ozlabs.org ([203.10.76.45]:44589 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822972Ab3GAIxE70RXh (ORCPT ); Mon, 1 Jul 2013 10:53:04 +0200 Received: by ozlabs.org (Postfix, from userid 1011) id 2D1D42C0209; Mon, 1 Jul 2013 18:53:00 +1000 (EST) From: Rusty Russell To: Joe Perches , Andrew Morton Cc: Ralf Baechle , Veli-Pekka Peltola , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, Russell King , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra Subject: Re: [PATCH v2] mm: module_alloc: check if size is 0 In-Reply-To: <1372373188.2060.32.camel@joe-AO722> References: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com> <1331125768-25454-1-git-send-email-veli-pekka.peltola@bluegiga.com> <20130627093917.GQ7171@linux-mips.org> <20130627152335.c3a4c9f4c647cf4a2b263479@linux-foundation.org> <1372373188.2060.32.camel@joe-AO722> User-Agent: Notmuch/0.15.2+81~gd2c8818 (http://notmuchmail.org) Emacs/23.4.1 (i686-pc-linux-gnu) Date: Mon, 01 Jul 2013 12:48:28 +0930 Message-ID: <87sizzrmrf.fsf@rustcorp.com.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37237 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Joe Perches writes: > On Thu, 2013-06-27 at 15:23 -0700, Andrew Morton wrote: >> On Thu, 27 Jun 2013 11:39:17 +0200 Ralf Baechle wrote: > [] >> Veli-Pekka's original patch would be neater if we were to add a new >> >> void *__vmalloc_node_range_zero_size_ok() >> { >> if (size == 0) >> return NULL; > > I believe you mean > return ZERO_SIZE_PTR; Yes, this is the Right Fix. Thanks, Rusty. From Markos.Chandras@imgtec.com Mon Jul 1 12:38:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 12:38:42 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:28067 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822972Ab3GAKik4alwT (ORCPT ); Mon, 1 Jul 2013 12:38:40 +0200 From: Markos Chandras To: CC: Markos Chandras Subject: [PATCH] MIPS: boot: compressed: Remove -fstack-protector from CFLAGS Date: Mon, 1 Jul 2013 11:38:30 +0100 Message-ID: <1372675110-1301-1-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 1.8.2.1 MIME-Version: 1.0 Content-Type: text/plain X-SEF-Processed: 7_3_0_01192__2013_07_01_11_38_34 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37238 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips When building with -fstack-protector, gcc emits the __stack_chk_guard and __stack_chk_fail symbols to check for stack stability. These symbols are defined in vmlinux but the generated vmlinux.bin that is used to create the compressed vmlinuz image has no symbol table so the linker can't find these symbols during the final linking phase. As a result of which, we need either to redefine these symbols just for the compressed image or drop the -fstack-protector option when building the compressed image. This patch implements the latter of two options. Fixes the following linking problem: dbg.c:(.text+0x7c): undefined reference to `__stack_chk_guard' dbg.c:(.text+0x80): undefined reference to `__stack_chk_guard' dbg.c:(.text+0xd4): undefined reference to `__stack_chk_guard' dbg.c:(.text+0xec): undefined reference to `__stack_chk_fail' Signed-off-by: Markos Chandras --- This patch is for the upstream-sfr/mips-for-linux-next tree --- arch/mips/boot/compressed/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index bbaa1d4..bb1dbf4 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -18,6 +18,8 @@ BOOT_HEAP_SIZE := 0x400000 # Disable Function Tracer KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//") +KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS)) + KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \ -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" -- 1.8.2.1 From Markos.Chandras@imgtec.com Mon Jul 1 12:58:00 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 12:58:01 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:31255 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822972Ab3GAK6Ac6UCk (ORCPT ); Mon, 1 Jul 2013 12:58:00 +0200 From: Markos Chandras To: CC: Markos Chandras Subject: [PATCH] MIPS: bcm63xx: clk: Add dummy clk_set_rate() function Date: Mon, 1 Jul 2013 11:57:24 +0100 Message-ID: <1372676244-1399-1-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 1.8.2.1 MIME-Version: 1.0 Content-Type: text/plain X-SEF-Processed: 7_3_0_01192__2013_07_01_11_57_54 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37239 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Several drivers use the clk_set_rate() function that needs to be defined in the platform's clock code. The Broadcom BCM63xx platform hardcodes the clock rate so we create a new dummy clk_set_rate() function which just returns -EINVAL. Also fixes the following build problem on a randconfig: drivers/built-in.o: In function `nop_usb_xceiv_probe': phy-nop.c:(.text+0x3ec26c): undefined reference to `clk_set_rate' Signed-off-by: Markos Chandras Acked-by: Steven J. Hill --- This patch is for the upstream-sfr/mips-for-linux-next tree --- arch/mips/bcm63xx/clk.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index c726a97..70dcc52 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -318,6 +318,12 @@ unsigned long clk_get_rate(struct clk *clk) EXPORT_SYMBOL(clk_get_rate); +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + return -EINVAL; +} +EXPORT_SYMBOL_GPL(clk_set_rate); + struct clk *clk_get(struct device *dev, const char *id) { if (!strcmp(id, "enet0")) -- 1.8.2.1 From lars@metafoo.de Mon Jul 1 13:02:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 13:02:43 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:64269 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822972Ab3GALCkpiRyi (ORCPT ); Mon, 1 Jul 2013 13:02:40 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 9026FD92; Mon, 1 Jul 2013 13:02:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id MhryFjXFtgw4; Mon, 1 Jul 2013 13:02:33 +0200 (CEST) Received: from [192.168.178.21] (ppp-188-174-150-173.dynamic.mnet-online.de [188.174.150.173]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 90431D91; Mon, 1 Jul 2013 13:02:32 +0200 (CEST) Message-ID: <51D1629A.6040700@metafoo.de> Date: Mon, 01 Jul 2013 13:06:02 +0200 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130116 Icedove/10.0.12 MIME-Version: 1.0 To: Markos Chandras CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: bcm63xx: clk: Add dummy clk_set_rate() function References: <1372676244-1399-1-git-send-email-markos.chandras@imgtec.com> In-Reply-To: <1372676244-1399-1-git-send-email-markos.chandras@imgtec.com> X-Enigmail-Version: 1.4.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37240 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 07/01/2013 12:57 PM, Markos Chandras wrote: > Several drivers use the clk_set_rate() function that needs > to be defined in the platform's clock code. The Broadcom > BCM63xx platform hardcodes the clock rate so we create a new > dummy clk_set_rate() function which just returns -EINVAL. > > Also fixes the following build problem on a randconfig: > drivers/built-in.o: In function `nop_usb_xceiv_probe': > phy-nop.c:(.text+0x3ec26c): undefined reference to `clk_set_rate' > > Signed-off-by: Markos Chandras > Acked-by: Steven J. Hill To make the set complete clk_round_rate() should be added as well > --- > This patch is for the upstream-sfr/mips-for-linux-next tree > --- > arch/mips/bcm63xx/clk.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c > index c726a97..70dcc52 100644 > --- a/arch/mips/bcm63xx/clk.c > +++ b/arch/mips/bcm63xx/clk.c > @@ -318,6 +318,12 @@ unsigned long clk_get_rate(struct clk *clk) > > EXPORT_SYMBOL(clk_get_rate); > > +int clk_set_rate(struct clk *clk, unsigned long rate) > +{ > + return -EINVAL; > +} > +EXPORT_SYMBOL_GPL(clk_set_rate); > + > struct clk *clk_get(struct device *dev, const char *id) > { > if (!strcmp(id, "enet0")) From alexander.sverdlin@nsn.com Mon Jul 1 14:35:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 14:35:47 +0200 (CEST) Received: from demumfd001.nsn-inter.net ([93.183.12.32]:10263 "EHLO demumfd001.nsn-inter.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816668Ab3GAMfnX0Xgj (ORCPT ); Mon, 1 Jul 2013 14:35:43 +0200 Received: from demuprx017.emea.nsn-intra.net ([10.150.129.56]) by demumfd001.nsn-inter.net (8.12.11.20060308/8.12.11) with ESMTP id r61CZY3H002028 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 1 Jul 2013 14:35:35 +0200 Received: from [10.151.24.91] ([10.151.24.91]) by demuprx017.emea.nsn-intra.net (8.12.11.20060308/8.12.11) with ESMTP id r61CZY18022064; Mon, 1 Jul 2013 14:35:34 +0200 Message-ID: <51D17795.8090307@nsn.com> Date: Mon, 01 Jul 2013 14:35:33 +0200 From: Alexander Sverdlin User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 MIME-Version: 1.0 To: david.daney@cavium.com CC: linux-mips@linux-mips.org, Ralf Baechle Subject: Re: [PATCH] Octeon: fix broken plat_mem_setup() References: <5139FF2F.2000003@nsn.com> In-Reply-To: <5139FF2F.2000003@nsn.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-purgate-type: clean X-purgate-Ad: Categorized by eleven eXpurgate (R) http://www.eleven.de X-purgate: clean X-purgate: This mail is considered clean (visit http://www.eleven.de for further information) X-purgate-size: 8422 X-purgate-ID: 151667::1372682135-000017BA-6D30A31B/0-0/0-0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37241 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexander.sverdlin@nsn.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Hello David, Just a friendly reminder: you've said you have other version of the fix below. But today 3.10 is released and in fact we have now 3.8, 3.9, 3.10 -- all of them are broken for Octeon... On 03/08/2013 04:09 PM, ext Alexander Sverdlin wrote: > Octeon: fix broken plat_mem_setup() > > Upstream patch abe77f90dc9c65a7c9a4d61c2cbb8db4d5566e4f (MIPS: Octeon: Add kexec > and kdump support) seems to be untested and broken Linux 3.8 on Octeon -- in > comparison with 3.7 Linux crashes with > > [ 0.000000] BUG: Bad page state in process swapper pfn:00000 > [ 0.000000] page:8000000001016000 count:0 mapcount:1 mapping: (null) index:0x0 > [ 0.000000] page flags: 0x0() > [ 0.000000] Modules linked in: > [ 0.000000] Call Trace: > [ 0.000000] [] dump_stack+0x8/0x34 > [ 0.000000] [] bad_page+0xdc/0x170 > [ 0.000000] [] free_pages_prepare+0x188/0x190 > [ 0.000000] [] __free_pages_ok+0x20/0x110 > [ 0.000000] [] free_all_bootmem_core+0x274/0x2cc > [ 0.000000] [] free_all_bootmem+0x8c/0xa4 > [ 0.000000] [] mem_init+0x54/0x1c4 > [ 0.000000] [] start_kernel+0x1d4/0x4e8 > [ 0.000000] > [ 0.000000] Disabling lock debugging due to kernel taint > ... skipped some simillar output... > [ 0.000000] BUG: Bad page state in process swapper pfn:0003b > [ 0.000000] page:8000000001016ce8 count:0 mapcount:1 mapping: (null) index:0x0 > [ 0.000000] page flags: 0x0() > [ 0.000000] Modules linked in: > [ 0.000000] Call Trace: > [ 0.000000] [] dump_stack+0x8/0x34 > [ 0.000000] [] bad_page+0xdc/0x170 > [ 0.000000] [] free_pages_prepare+0x188/0x190 > [ 0.000000] [] __free_pages_ok+0x20/0x110 > [ 0.000000] [] free_all_bootmem_core+0x274/0x2cc > [ 0.000000] [] free_all_bootmem+0x8c/0xa4 > [ 0.000000] [] mem_init+0x54/0x1c4 > [ 0.000000] [] start_kernel+0x1d4/0x4e8 > [ 0.000000] > [ 0.000000] CPU 0 Unable to handle kernel paging request at virtual address 0000000000380000, epc == ffffffff8074b85c, ra == ffffffff80738778 > [ 0.000000] Oops[#1]: > [ 0.000000] Cpu 0 > [ 0.000000] $ 0 : 0000000000000000 00000000101000e0 0000000000000001 0000000000380038 > [ 0.000000] $ 4 : 0000000000000001 0000000000000006 0000000000380000 0000000000000040 > [ 0.000000] $ 8 : 0000000000380000 fffffffffffffbff 0000000000000040 ffffffff80f9dd00 > [ 0.000000] $12 : 6db6db6db6db6db7 0000000000000000 6db6db6db6db0000 ffffffff80700000 > [ 0.000000] $16 : 0000000000010000 ffffffffffffffff 0000000000071c00 0000000000010040 > [ 0.000000] $20 : ffffffff80753070 000000000000fe73 ffffffff80f9dd00 0000000000050000 > [ 0.000000] $24 : 0000000000000002 0000000000200200 > [ 0.000000] $28 : ffffffff806b4000 ffffffff806b7d60 fffffffffffffffc ffffffff80738778 > [ 0.000000] Hi : 0000000000000000 > [ 0.000000] Lo : 0000000000000370 > [ 0.000000] epc : ffffffff8074b85c __free_pages_bootmem+0xcc/0xe4 > [ 0.000000] Tainted: G B > [ 0.000000] ra : ffffffff80738778 free_all_bootmem_core+0x274/0x2cc > [ 0.000000] Status: 101000e2 KX SX UX KERNEL EXL > [ 0.000000] Cause : 40808008 > [ 0.000000] BadVA : 0000000000380000 > [ 0.000000] PrId : 000d9009 (Cavium Octeon II) > [ 0.000000] Modules linked in: > [ 0.000000] Process swapper (pid: 0, threadinfo=ffffffff806b4000, task=ffffffff806dcbf0, tls=0000000000000000) > [ 0.000000] *HwTLS: 000000ffec6c46c0 > [ 0.000000] Stack : 0000000000000000 ffffffff80753070 ffffffff80753060 ffffffff80750000 > ffffffff8074fab0 ffffffff80770000 ffffffff806d0000 ffffffffc0111bf0 > 0000000000000000 ffffffff8073885c ffffff8000000001 ffffffff806e0000 > ffffffff80fa0000 ffffffff8072fc8c ffffff8000000001 0000000000000084 > ffffffff80770000 ffffffff80750000 ffffffff8074fab0 ffffffff80770000 > ffffffff806d0000 ffffffff80724904 ffffffff8074fab0 0000000000000000 > ffffffffc00a56c8 800000000fd01030 800000000fda5688 0000000000000001 > ffffffff80541dc0 000000000000000b 000000000000000b ffffffffc00018b8 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > ... > [ 0.000000] Call Trace: > [ 0.000000] [] __free_pages_bootmem+0xcc/0xe4 > [ 0.000000] [] free_all_bootmem_core+0x274/0x2cc > [ 0.000000] [] free_all_bootmem+0x8c/0xa4 > [ 0.000000] [] mem_init+0x54/0x1c4 > [ 0.000000] [] start_kernel+0x1d4/0x4e8 > [ 0.000000] > [ 0.000000] > Code: fc6206b8 0808011c ad06001c cc7c0000 00491024 fcc20000 081d2def ac60ffe4 > [ 0.000000] ---[ end trace 139ce121c98e96c9 ]--- > [ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task! > > There are at least couple of issues in the patch: > 1. reason for add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM) instead of > add_memory_region(memory, size, BOOT_MEM_RAM) is unclear, especially because it > will discard corrections performed by two preceding calls to memory_exclude_page(). > 2. add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM) seems to be not related > to KEXEC functionality and has no visible reason in 3.8 kernel... Probably these are > some traces of the original 2010 patch for older kernels... In any case, this is the > reason for the crash. > > Signed-off-by: Alexander Sverdlin > Cc: David Daney > Cc: Ralf Baechle > --- > --- linux.orig/arch/mips/cavium-octeon/setup.c > +++ linux/arch/mips/cavium-octeon/setup.c > @@ -1092,8 +1092,6 @@ void __init plat_mem_setup(void) > uint64_t crashk_end; > #ifndef CONFIG_CRASH_DUMP > int64_t memory; > - uint64_t kernel_start; > - uint64_t kernel_size; > #endif > const struct cvmx_bootmem_named_block_desc *named_block; > > @@ -1217,7 +1215,7 @@ void __init plat_mem_setup(void) > * next to each other if they are received in > * incrementing order > */ > - if (memory < crashk_base && end > crashk_end) { > + if (memory < crashk_base && end > crashk_end) { > /* region is fully in */ > add_memory_region(memory, > crashk_base - memory, > @@ -1243,7 +1241,7 @@ void __init plat_mem_setup(void) > * Overlap with the beginning of the region, > * reserve the beginning. > */ > - mem_alloc_size -= crashk_end - memory; > + size -= crashk_end - memory; > memory = crashk_end; > } else if (memory < crashk_base && end > crashk_base && > end < crashk_end) > @@ -1251,24 +1249,16 @@ void __init plat_mem_setup(void) > * Overlap with the beginning of the region, > * chop of end. > */ > - mem_alloc_size -= end - crashk_base; > + size -= end - crashk_base; > #endif > - add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); > + if (size) > + add_memory_region(memory, size, BOOT_MEM_RAM); > total += mem_alloc_size; > - /* Recovering mem_alloc_size */ > - mem_alloc_size = 4 << 20; > } else { > break; > } > } > cvmx_bootmem_unlock(); > - /* Add the memory region for the kernel. */ > - kernel_start = (unsigned long) _text; > - kernel_size = ALIGN(_end - _text, 0x100000); > - > - /* Adjust for physical offset. */ > - kernel_start &= ~0xffffffff80000000ULL; > - add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); > #endif /* CONFIG_CRASH_DUMP */ > > mem_alloc_done: > > > > -- Best regards, Alexander Sverdlin. From Markos.Chandras@imgtec.com Mon Jul 1 15:06:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 15:06:16 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:43000 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816668Ab3GANGOmPtSQ (ORCPT ); Mon, 1 Jul 2013 15:06:14 +0200 Message-ID: <51D17EBE.7000902@imgtec.com> Date: Mon, 1 Jul 2013 14:06:06 +0100 From: Markos Chandras User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 To: Lars-Peter Clausen CC: Subject: Re: [PATCH] MIPS: bcm63xx: clk: Add dummy clk_set_rate() function References: <1372676244-1399-1-git-send-email-markos.chandras@imgtec.com> <51D1629A.6040700@metafoo.de> In-Reply-To: <51D1629A.6040700@metafoo.de> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.154.58] X-SEF-Processed: 7_3_0_01192__2013_07_01_14_06_08 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37242 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Markos.Chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 07/01/13 12:06, Lars-Peter Clausen wrote: > On 07/01/2013 12:57 PM, Markos Chandras wrote: >> Several drivers use the clk_set_rate() function that needs >> to be defined in the platform's clock code. The Broadcom >> BCM63xx platform hardcodes the clock rate so we create a new >> dummy clk_set_rate() function which just returns -EINVAL. >> >> Also fixes the following build problem on a randconfig: >> drivers/built-in.o: In function `nop_usb_xceiv_probe': >> phy-nop.c:(.text+0x3ec26c): undefined reference to `clk_set_rate' >> >> Signed-off-by: Markos Chandras >> Acked-by: Steven J. Hill > > To make the set complete clk_round_rate() should be added as well > >> --- >> This patch is for the upstream-sfr/mips-for-linux-next tree >> --- >> arch/mips/bcm63xx/clk.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c >> index c726a97..70dcc52 100644 >> --- a/arch/mips/bcm63xx/clk.c >> +++ b/arch/mips/bcm63xx/clk.c >> @@ -318,6 +318,12 @@ unsigned long clk_get_rate(struct clk *clk) >> >> EXPORT_SYMBOL(clk_get_rate); >> >> +int clk_set_rate(struct clk *clk, unsigned long rate) >> +{ >> + return -EINVAL; >> +} >> +EXPORT_SYMBOL_GPL(clk_set_rate); >> + >> struct clk *clk_get(struct device *dev, const char *id) >> { >> if (!strcmp(id, "enet0")) > Hi Lars, Thanks. I will submit a new patch From ralf@linux-mips.org Mon Jul 1 15:19:36 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 15:19:39 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:35325 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6826533Ab3GANTgppt4A (ORCPT ); Mon, 1 Jul 2013 15:19:36 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r61DJYtA029863; Mon, 1 Jul 2013 15:19:35 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r61DJYsY029860; Mon, 1 Jul 2013 15:19:34 +0200 Date: Mon, 1 Jul 2013 15:19:33 +0200 From: Ralf Baechle To: Markos Chandras Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: boot: compressed: Remove -fstack-protector from CFLAGS Message-ID: <20130701131933.GD27158@linux-mips.org> References: <1372675110-1301-1-git-send-email-markos.chandras@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1372675110-1301-1-git-send-email-markos.chandras@imgtec.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37243 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Mon, Jul 01, 2013 at 11:38:30AM +0100, Markos Chandras wrote: I've inserted this patch before the patch that actually adds the stack protector. Thanks, Ralf From thomas.petazzoni@free-electrons.com Mon Jul 1 15:42:44 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 15:42:51 +0200 (CEST) Received: from mail.free-electrons.com ([94.23.35.102]:60247 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6826533Ab3GANmofSQFL (ORCPT ); Mon, 1 Jul 2013 15:42:44 +0200 Received: by mail.free-electrons.com (Postfix, from userid 106) id F2A9C1C15; Mon, 1 Jul 2013 15:42:39 +0200 (CEST) Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id F36FA1C16; Mon, 1 Jul 2013 15:42:25 +0200 (CEST) From: Thomas Petazzoni To: Bjorn Helgaas , linux-pci@vger.kernel.org, Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement Cc: Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Subject: [PATCHv4 02/11] pci: use weak functions for MSI arch-specific functions Date: Mon, 1 Jul 2013 15:42:07 +0200 Message-Id: <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37244 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Until now, the MSI architecture-specific functions could be overloaded using a fairly complex set of #define and compile-time conditionals. In order to prepare for the introduction of the msi_chip infrastructure, it is desirable to switch all those functions to use the 'weak' mechanism. This commit converts all the architectures that were overidding those MSI functions to use the new strategy. Note that we keep a separate, non-weak, function default_teardown_msi_irqs() for the default behavior of the arch_teardown_msi_irqs(), as the default behavior is needed by the Xen x86 PCI code. Signed-off-by: Thomas Petazzoni Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: x86@kernel.org Cc: Russell King Cc: Tony Luck Cc: Fenghua Yu Cc: linux-ia64@vger.kernel.org Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: David S. Miller Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf --- arch/mips/include/asm/pci.h | 5 ----- arch/powerpc/include/asm/pci.h | 5 ----- arch/s390/include/asm/pci.h | 4 ---- arch/x86/include/asm/pci.h | 28 -------------------------- arch/x86/kernel/x86_init.c | 21 ++++++++++++++++++++ drivers/pci/msi.c | 45 +++++++++++++++++++----------------------- include/linux/msi.h | 7 ++++++- 7 files changed, 47 insertions(+), 68 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index b8e24fd..031f4c1 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -137,11 +137,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } -#ifdef CONFIG_CPU_CAVIUM_OCTEON -/* MSI arch hook for OCTEON */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#endif - extern char * (*pcibios_plat_setup)(char *str); #ifdef CONFIG_OF diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index 6653f27..95145a1 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h @@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus); /* Decide whether to display the domain number in /proc */ extern int pci_proc_domain(struct pci_bus *bus); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs -#define arch_msi_check_device arch_msi_check_device - struct vm_area_struct; /* Map a range of PCI memory or I/O space for a device into user space */ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index 6c18012..8641e8d 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h @@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *); int pci_domain_nr(struct pci_bus *); int pci_proc_domain(struct pci_bus *); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs - #define ZPCI_BUS_NR 0 /* default bus number */ #define ZPCI_DEVFN 0 /* default device number */ diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index d9e9e6c..8c61de0 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -100,29 +100,6 @@ static inline void early_quirks(void) { } extern void pci_iommu_alloc(void); #ifdef CONFIG_PCI_MSI -/* MSI arch specific hooks */ -static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) -{ - return x86_msi.setup_msi_irqs(dev, nvec, type); -} - -static inline void x86_teardown_msi_irqs(struct pci_dev *dev) -{ - x86_msi.teardown_msi_irqs(dev); -} - -static inline void x86_teardown_msi_irq(unsigned int irq) -{ - x86_msi.teardown_msi_irq(irq); -} -static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq) -{ - x86_msi.restore_msi_irqs(dev, irq); -} -#define arch_setup_msi_irqs x86_setup_msi_irqs -#define arch_teardown_msi_irqs x86_teardown_msi_irqs -#define arch_teardown_msi_irq x86_teardown_msi_irq -#define arch_restore_msi_irqs x86_restore_msi_irqs /* implemented in arch/x86/kernel/apic/io_apic. */ struct msi_desc; int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); @@ -130,11 +107,6 @@ void native_teardown_msi_irq(unsigned int irq); void native_restore_msi_irqs(struct pci_dev *dev, int irq); int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, unsigned int irq_base, unsigned int irq_offset); -/* default to the implementation in drivers/lib/msi.c */ -#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS -#define HAVE_DEFAULT_MSI_RESTORE_IRQS -void default_teardown_msi_irqs(struct pci_dev *dev); -void default_restore_msi_irqs(struct pci_dev *dev, int irq); #else #define native_setup_msi_irqs NULL #define native_teardown_msi_irq NULL diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 45a14db..a2b189c 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -116,6 +116,27 @@ struct x86_msi_ops x86_msi = { .setup_hpet_msi = default_setup_hpet_msi, }; +/* MSI arch specific hooks */ +int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +{ + return x86_msi.setup_msi_irqs(dev, nvec, type); +} + +void arch_teardown_msi_irqs(struct pci_dev *dev) +{ + x86_msi.teardown_msi_irqs(dev); +} + +void arch_teardown_msi_irq(unsigned int irq) +{ + x86_msi.teardown_msi_irq(irq); +} + +void arch_restore_msi_irqs(struct pci_dev *dev, int irq) +{ + x86_msi.restore_msi_irqs(dev, irq); +} + struct x86_io_apic_ops x86_io_apic_ops = { .init = native_io_apic_init_mappings, .read = native_io_apic_read, diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 2c10752..289fbfd 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -30,20 +30,21 @@ static int pci_msi_enable = 1; /* Arch hooks */ -#ifndef arch_msi_check_device -int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) +int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) { - return 0; + return -EINVAL; } -#endif -#ifndef arch_setup_msi_irqs -# define arch_setup_msi_irqs default_setup_msi_irqs -# define HAVE_DEFAULT_MSI_SETUP_IRQS -#endif +void __weak arch_teardown_msi_irq(unsigned int irq) +{ +} -#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS -int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) +{ + return 0; +} + +int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) { struct msi_desc *entry; int ret; @@ -65,14 +66,11 @@ int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) return 0; } -#endif -#ifndef arch_teardown_msi_irqs -# define arch_teardown_msi_irqs default_teardown_msi_irqs -# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS -#endif - -#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS +/* + * We have a default implementation available as a separate non-weak + * function, as it is used by the Xen x86 PCI code + */ void default_teardown_msi_irqs(struct pci_dev *dev) { struct msi_desc *entry; @@ -86,15 +84,13 @@ void default_teardown_msi_irqs(struct pci_dev *dev) arch_teardown_msi_irq(entry->irq + i); } } -#endif -#ifndef arch_restore_msi_irqs -# define arch_restore_msi_irqs default_restore_msi_irqs -# define HAVE_DEFAULT_MSI_RESTORE_IRQS -#endif +void __weak arch_teardown_msi_irqs(struct pci_dev *dev) +{ + return default_teardown_msi_irqs(dev); +} -#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS -void default_restore_msi_irqs(struct pci_dev *dev, int irq) +void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq) { struct msi_desc *entry; @@ -111,7 +107,6 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq) if (entry) write_msi_msg(irq, &entry->msg); } -#endif static void msi_set_enable(struct pci_dev *dev, int enable) { diff --git a/include/linux/msi.h b/include/linux/msi.h index 20c2d6d..c82ff8d 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -50,12 +50,17 @@ struct msi_desc { }; /* - * The arch hook for setup up msi irqs + * The arch hooks to setup up msi irqs. Those functions are + * implemented as weak symbols so that they /can/ be overriden by + * architecture specific code if needed. */ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); void arch_teardown_msi_irq(unsigned int irq); int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); void arch_teardown_msi_irqs(struct pci_dev *dev); int arch_msi_check_device(struct pci_dev* dev, int nvec, int type); +void arch_restore_msi_irqs(struct pci_dev *dev, int irq); + +void default_teardown_msi_irqs(struct pci_dev *dev); #endif /* LINUX_MSI_H */ -- 1.8.1.2 From thomas.petazzoni@free-electrons.com Mon Jul 1 15:43:13 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 15:43:24 +0200 (CEST) Received: from mail.free-electrons.com ([94.23.35.102]:60293 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825735Ab3GANmy2jP8X (ORCPT ); Mon, 1 Jul 2013 15:42:54 +0200 Received: by mail.free-electrons.com (Postfix, from userid 106) id 06349780; Mon, 1 Jul 2013 15:42:49 +0200 (CEST) Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 777531C1B; Mon, 1 Jul 2013 15:42:27 +0200 (CEST) From: Thomas Petazzoni To: Bjorn Helgaas , linux-pci@vger.kernel.org, Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement Cc: Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Subject: [PATCHv4 03/11] pci: remove ARCH_SUPPORTS_MSI kconfig option Date: Mon, 1 Jul 2013 15:42:08 +0200 Message-Id: <1372686136-1370-4-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37245 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Now that we have weak versions for each of the PCI MSI architecture functions, we can actually build the MSI support for all platforms, regardless of whether they provide or not architecture-specific versions of those functions. For this reason, the ARCH_SUPPORTS_MSI hidden kconfig boolean becomes useless, and this patch gets rid of it. Signed-off-by: Thomas Petazzoni Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: x86@kernel.org Cc: Russell King Cc: Tony Luck Cc: Fenghua Yu Cc: linux-ia64@vger.kernel.org Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: David S. Miller Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf --- arch/arm/Kconfig | 1 - arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 -- arch/powerpc/Kconfig | 1 - arch/s390/Kconfig | 1 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - drivers/pci/Kconfig | 4 ---- 9 files changed, 13 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8ab5962..3413679 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -435,7 +435,6 @@ config ARCH_NETX config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU - select ARCH_SUPPORTS_MSI select CPU_XSC3 select NEED_MACH_MEMORY_H select NEED_RET_TO_USER diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 1a2b774..943d425 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -9,7 +9,6 @@ config IA64 select PCI if (!IA64_HP_SIM) select ACPI if (!IA64_HP_SIM) select PM if (!IA64_HP_SIM) - select ARCH_SUPPORTS_MSI select HAVE_UNSTABLE_SCHED_CLOCK select HAVE_IDE select HAVE_OPROFILE diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7a58ab9..96c1225 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -763,7 +763,6 @@ config CAVIUM_OCTEON_REFERENCE_BOARD select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE select HW_HAS_PCI - select ARCH_SUPPORTS_MSI select ZONE_DMA32 select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI @@ -799,7 +798,6 @@ config NLM_XLR_BOARD select CEVT_R4K select CSRC_R4K select IRQ_CPU - select ARCH_SUPPORTS_MSI select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c33e3ad..f9d9d8e 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -734,7 +734,6 @@ config PCI default y if !40x && !CPM2 && !8xx && !PPC_83xx \ && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON default PCI_QSPAN if !4xx && !CPM2 && 8xx - select ARCH_SUPPORTS_MSI select GENERIC_PCI_IOMAP help Find out whether your system includes a PCI bus. PCI is the name of diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index da183c5..9a6225b 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -429,7 +429,6 @@ menuconfig PCI bool "PCI support" default n depends on 64BIT - select ARCH_SUPPORTS_MSI select PCI_MSI help Enable PCI support. diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 9ac9f16..822e1a1 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -52,7 +52,6 @@ config SPARC32 config SPARC64 def_bool 64BIT - select ARCH_SUPPORTS_MSI select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_GRAPH_FP_TEST diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index 3aa3766..d2d519c 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -379,7 +379,6 @@ config PCI select PCI_DOMAINS select GENERIC_PCI_IOMAP select TILE_GXIO_TRIO if TILEGX - select ARCH_SUPPORTS_MSI if TILEGX select PCI_MSI if TILEGX ---help--- Enable PCI root complex support, so PCIe endpoint devices can diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 685692c..4229ce0 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1999,7 +1999,6 @@ menu "Bus options (PCI etc.)" config PCI bool "PCI support" default y - select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC) ---help--- Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index ac45398..3d4c061 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -1,13 +1,9 @@ # # PCI configuration # -config ARCH_SUPPORTS_MSI - bool - config PCI_MSI bool "Message Signaled Interrupts (MSI and MSI-X)" depends on PCI - depends on ARCH_SUPPORTS_MSI help This allows device drivers to enable MSI (Message Signaled Interrupts). Message Signaled Interrupts enable a device to -- 1.8.1.2 From santosh.shilimkar@ti.com Mon Jul 1 15:59:17 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 15:59:22 +0200 (CEST) Received: from comal.ext.ti.com ([198.47.26.152]:54286 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825731Ab3GAN7Rd-0b- (ORCPT ); Mon, 1 Jul 2013 15:59:17 +0200 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r61Dwbm7028271; Mon, 1 Jul 2013 08:58:37 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r61DwbuI024380; Mon, 1 Jul 2013 08:58:37 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Mon, 1 Jul 2013 08:58:36 -0500 Received: from [158.218.103.117] (ula0393909.am.dhcp.ti.com [158.218.103.117]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r61DwZ1o017673; Mon, 1 Jul 2013 08:58:35 -0500 Message-ID: <51D18B0B.1060906@ti.com> Date: Mon, 1 Jul 2013 09:58:35 -0400 From: Santosh Shilimkar User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 CC: Geert Uytterhoeven , Sebastian Andrzej Siewior , Nicolas Pitre , linux-mips , Aurelien Jacquiot , Catalin Marinas , Will Deacon , Max Filippov , Paul Mackerras , Jonas Bonn , Russell King , , the arch/x86 maintainers , "arm@kernel.org" , Rob Herring , Grant Likely , Jean-Christophe PLAGNIOL-VILLARD , , James Hogan , devicetree-discuss , Rob Herring , "linux-arm-kernel@lists.infradead.org" , Chris Zankel , Vineet Gupta , Linux Kernel Mailing List , Ralf Baechle , "linuxppc-dev@lists.ozlabs.org" Subject: Re: [PATCH] of: Specify initrd location using 64-bit References: <1371775956-16453-1-git-send-email-santosh.shilimkar@ti.com> <51C4171C.9050908@linutronix.de> <51C48B5A.2040404@ti.com> <51CCA67C.2010803@gmail.com> <20130628134931.GD21034@game.jcrosoft.org> <51CE1F92.3070802@ti.com> <51D1345B.8020509@linutronix.de> In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit To: unlisted-recipients:; (no To-header on input) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37246 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: santosh.shilimkar@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Monday 01 July 2013 03:59 AM, Geert Uytterhoeven wrote: > On Mon, Jul 1, 2013 at 9:48 AM, Sebastian Andrzej Siewior > wrote: >> On 06/29/2013 01:43 AM, Santosh Shilimkar wrote: >>> Apart from waste of 32bit, what is the other concern you >>> have ? >> >> You pass a u64 as a physical address which is represented in other >> parts of the kernel (for a good reason) by phys_addr_t. >> >>> I really want to converge on this patch because it >>> has been a open ended discussion for quite some time. Does >>> that really break any thing on x86 or your concern is more >>> from semantics of the physical address. >> You want to have your code in so you can continue with your work, that >> is okay. The other two arguments why u64 here is a good thing was "due >> to what I said earlier" and "+1" and I don't have the time to look >> that up. >> >> There should be no problems on x86 if this goes in as it is now. >> >> But think about this: What happens if you boot your ARM device without >> PAE and your initrd is in the upper region? If you are lucky the kernel >> looks at a different place where it also has a read permission, notices >> nothing sane is there, writes a message and continues. And if it is not >> allowed to read? It is clearly the user's fault for booting a non-PAE >> kernel. > > That's actual the original reason: DT has it as 64 bit, and passes it to a > 32 bit kernel when running in 32 bit mode without PAE. > Thanks all for comments and useful discussion. I will resubmit the patch with update to fix the printk warnings reported by Vineet and James post the $subject change. Am assuming the patch will go via Grant Likely's tree. Regards, Santosh From santosh.shilimkar@ti.com Mon Jul 1 20:21:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 20:21:37 +0200 (CEST) Received: from bear.ext.ti.com ([192.94.94.41]:38364 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835054Ab3GASV3TcHus (ORCPT ); Mon, 1 Jul 2013 20:21:29 +0200 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r61IKeOS022182; Mon, 1 Jul 2013 13:20:40 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r61IKe0i016233; Mon, 1 Jul 2013 13:20:40 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Mon, 1 Jul 2013 13:20:39 -0500 Received: from ula0393909.am.dhcp.ti.com (ula0393909.am.dhcp.ti.com [158.218.103.117]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r61IKcs0010608; Mon, 1 Jul 2013 13:20:38 -0500 From: Santosh Shilimkar To: CC: Santosh Shilimkar , Rob Herring , Geert Uytterhoeven , Sebastian Andrzej Siewior , Jean-Christophe PLAGNIOL-VILLARD , Vineet Gupta , Russell King , Catalin Marinas , Will Deacon , Mark Salter , Aurelien Jacquiot , James Hogan , Michal Simek , Ralf Baechle , Jonas Bonn , Benjamin Herrenschmidt , Paul Mackerras , , , Chris Zankel , Max Filippov , , Nicolas Pitre , , , , , , Subject: [PATCH v2] of: Specify initrd location using 64-bit Date: Mon, 1 Jul 2013 14:20:35 -0400 Message-ID: <1372702835-5333-1-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37247 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: santosh.shilimkar@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On some PAE architectures, the entire range of physical memory could reside outside the 32-bit limit. These systems need the ability to specify the initrd location using 64-bit numbers. This patch globally modifies the early_init_dt_setup_initrd_arch() function to use 64-bit numbers instead of the current unsigned long. There has been quite a bit of debate about whether to use u64 or phys_addr_t. It was concluded to stick to u64 to be consistent with rest of the device tree code. As summarized by Geert, "The address to load the initrd is decided by the bootloader/user and set at that point later in time. The dtb should not be tied to the kernel you are booting" More details on the discussion can be found here: https://lkml.org/lkml/2013/6/20/690 https://lkml.org/lkml/2012/9/13/544 Cc: Grant Likely Cc: Rob Herring Cc: Geert Uytterhoeven Cc: Sebastian Andrzej Siewior Cc: Jean-Christophe PLAGNIOL-VILLARD Cc: Vineet Gupta Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Salter Cc: Aurelien Jacquiot Cc: James Hogan Cc: Michal Simek Cc: Ralf Baechle Cc: Jonas Bonn Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: x86@kernel.org Cc: arm@kernel.org Cc: Chris Zankel Cc: Max Filippov Cc: bigeasy@linutronix.de Cc: robherring2@gmail.com Cc: Nicolas Pitre Cc: linux-arm-kernel@lists.infradead.org Cc: linux-c6x-dev@linux-c6x.org Cc: linux-mips@linux-mips.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-xtensa@linux-xtensa.org Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Santosh Shilimkar --- arch/arc/mm/init.c | 5 ++--- arch/arm/mm/init.c | 2 +- arch/arm64/mm/init.c | 3 +-- arch/c6x/kernel/devicetree.c | 3 +-- arch/metag/mm/init.c | 5 ++--- arch/microblaze/kernel/prom.c | 3 +-- arch/mips/kernel/prom.c | 3 +-- arch/openrisc/kernel/prom.c | 3 +-- arch/powerpc/kernel/prom.c | 3 +-- arch/x86/kernel/devicetree.c | 3 +-- arch/xtensa/kernel/setup.c | 3 +-- drivers/of/fdt.c | 10 ++++++---- include/linux/of_fdt.h | 3 +-- 13 files changed, 20 insertions(+), 29 deletions(-) diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c index 4a17736..7991e08 100644 --- a/arch/arc/mm/init.c +++ b/arch/arc/mm/init.c @@ -157,9 +157,8 @@ void __init free_initrd_mem(unsigned long start, unsigned long end) #endif #ifdef CONFIG_OF_FLATTREE -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { - pr_err("%s(%lx, %lx)\n", __func__, start, end); + pr_err("%s(%llx, %llx)\n", __func__, start, end); } #endif /* CONFIG_OF_FLATTREE */ diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 9a5cdc0..afeaef7 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -76,7 +76,7 @@ static int __init parse_tag_initrd2(const struct tag *tag) __tagtable(ATAG_INITRD2, parse_tag_initrd2); #ifdef CONFIG_OF_FLATTREE -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { phys_initrd_start = start; phys_initrd_size = end - start; diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index f497ca7..7047708 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -44,8 +44,7 @@ static unsigned long phys_initrd_size __initdata = 0; phys_addr_t memstart_addr __read_mostly = 0; -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { phys_initrd_start = start; phys_initrd_size = end - start; diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c index bdb56f0..287d0e6 100644 --- a/arch/c6x/kernel/devicetree.c +++ b/arch/c6x/kernel/devicetree.c @@ -33,8 +33,7 @@ void __init early_init_devtree(void *params) #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c index d05b845..bdc4811 100644 --- a/arch/metag/mm/init.c +++ b/arch/metag/mm/init.c @@ -419,10 +419,9 @@ void free_initrd_mem(unsigned long start, unsigned long end) #endif #ifdef CONFIG_OF_FLATTREE -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { - pr_err("%s(%lx, %lx)\n", + pr_err("%s(%llx, %llx)\n", __func__, start, end); } #endif /* CONFIG_OF_FLATTREE */ diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c index 0a2c68f..62e2e8f 100644 --- a/arch/microblaze/kernel/prom.c +++ b/arch/microblaze/kernel/prom.c @@ -136,8 +136,7 @@ void __init early_init_devtree(void *params) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 5712bb5..32b8788 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -58,8 +58,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/openrisc/kernel/prom.c b/arch/openrisc/kernel/prom.c index 5869e3f..150215a 100644 --- a/arch/openrisc/kernel/prom.c +++ b/arch/openrisc/kernel/prom.c @@ -96,8 +96,7 @@ void __init early_init_devtree(void *params) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 8b6f7a9..2f3e252 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -550,8 +550,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index b158152..2fbad6b 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -52,8 +52,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) } #ifdef CONFIG_BLK_DEV_INITRD -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index 6dd25ec..d45e602 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c @@ -170,8 +170,7 @@ static int __init parse_tag_fdt(const bp_tag_t *tag) __tagtable(BP_TAG_FDT, parse_tag_fdt); -void __init early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end) +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) { initrd_start = (void *)__va(start); initrd_end = (void *)__va(end); diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 808be06..21123b8 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -550,7 +550,8 @@ int __init of_flat_dt_match(unsigned long node, const char *const *compat) */ void __init early_init_dt_check_for_initrd(unsigned long node) { - unsigned long start, end, len; + u64 start, end; + unsigned long len; __be32 *prop; pr_debug("Looking for initrd properties... "); @@ -558,15 +559,16 @@ void __init early_init_dt_check_for_initrd(unsigned long node) prop = of_get_flat_dt_prop(node, "linux,initrd-start", &len); if (!prop) return; - start = of_read_ulong(prop, len/4); + start = of_read_number(prop, len/4); prop = of_get_flat_dt_prop(node, "linux,initrd-end", &len); if (!prop) return; - end = of_read_ulong(prop, len/4); + end = of_read_number(prop, len/4); early_init_dt_setup_initrd_arch(start, end); - pr_debug("initrd_start=0x%lx initrd_end=0x%lx\n", start, end); + pr_debug("initrd_start=0x%llx initrd_end=0x%llx\n", + (unsigned long long)start, (unsigned long long)end); } #else inline void early_init_dt_check_for_initrd(unsigned long node) diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h index ed136ad..4a17939 100644 --- a/include/linux/of_fdt.h +++ b/include/linux/of_fdt.h @@ -106,8 +106,7 @@ extern u64 dt_mem_next_cell(int s, __be32 **cellp); * physical addresses. */ #ifdef CONFIG_BLK_DEV_INITRD -extern void early_init_dt_setup_initrd_arch(unsigned long start, - unsigned long end); +extern void early_init_dt_setup_initrd_arch(u64 start, u64 end); #endif /* Early flat tree scan hooks */ -- 1.7.9.5 From robherring2@gmail.com Mon Jul 1 23:34:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jul 2013 23:34:52 +0200 (CEST) Received: from mail-gh0-f172.google.com ([209.85.160.172]:34288 "EHLO mail-gh0-f172.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817545Ab3GAVek0ffo4 (ORCPT ); Mon, 1 Jul 2013 23:34:40 +0200 Received: by mail-gh0-f172.google.com with SMTP id r18so2202482ghr.31 for ; Mon, 01 Jul 2013 14:34:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=KeIuCLHaXMJpc288qPyYqtwLaIoETp8elhPYHHu79Eg=; b=pLGEtDiFMjMp7qWlabGWVPP3YLePIknoNmlKsG9hCEkaJnPnIXYqZBOCWViHLJ4jO2 oz+lHaff/MKbcrdM/q/pLV6c/rNzkhulAvAO5T331qSFw+xcYIDd/nCHxCaUt5HyHYYZ 0nwMA6/4cflVIys5htGGf5JVcsrxBgZgMBX/xEkbkhgk/YT71d/YfHRqy6xmR8kjmZ77 j12fEAbOf2n40zJs7Wq2rTFiALT4wT70nA6kjnCBSXUhVf0lEnrb0omQpggGtX+4sbLC 5aoPIJsDonkf68On7ONKCHd8aICvdqs0RmlwY0F2WaiTOo9QW951u2PmZxfUhWJfN+IS 3YBA== X-Received: by 10.236.70.9 with SMTP id o9mr13350041yhd.35.1372714473693; Mon, 01 Jul 2013 14:34:33 -0700 (PDT) Received: from [10.10.10.90] ([173.226.190.126]) by mx.google.com with ESMTPSA id s80sm35716355yhe.27.2013.07.01.14.34.31 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 01 Jul 2013 14:34:33 -0700 (PDT) Message-ID: <51D1F5E2.6070609@gmail.com> Date: Mon, 01 Jul 2013 16:34:26 -0500 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 MIME-Version: 1.0 To: Santosh Shilimkar CC: grant.likely@linaro.org, Rob Herring , Geert Uytterhoeven , Sebastian Andrzej Siewior , Jean-Christophe PLAGNIOL-VILLARD , Vineet Gupta , Russell King , Catalin Marinas , Will Deacon , Mark Salter , Aurelien Jacquiot , James Hogan , Michal Simek , Ralf Baechle , Jonas Bonn , Benjamin Herrenschmidt , Paul Mackerras , x86@kernel.org, arm@kernel.org, Chris Zankel , Max Filippov , Nicolas Pitre , linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org, devicetree-discuss@lists.ozlabs.org Subject: Re: [PATCH v2] of: Specify initrd location using 64-bit References: <1372702835-5333-1-git-send-email-santosh.shilimkar@ti.com> In-Reply-To: <1372702835-5333-1-git-send-email-santosh.shilimkar@ti.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37248 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robherring2@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 07/01/2013 01:20 PM, Santosh Shilimkar wrote: > On some PAE architectures, the entire range of physical memory could reside > outside the 32-bit limit. These systems need the ability to specify the > initrd location using 64-bit numbers. > > This patch globally modifies the early_init_dt_setup_initrd_arch() function to > use 64-bit numbers instead of the current unsigned long. > > There has been quite a bit of debate about whether to use u64 or phys_addr_t. > It was concluded to stick to u64 to be consistent with rest of the device > tree code. As summarized by Geert, "The address to load the initrd is decided > by the bootloader/user and set at that point later in time. The dtb should not > be tied to the kernel you are booting" That was quoting me. Otherwise: Acked-by: Rob Herring Unless Grant feels compelled to pick this up for 3.11, I think it has to wait for 3.12. Rob > > More details on the discussion can be found here: > https://lkml.org/lkml/2013/6/20/690 > https://lkml.org/lkml/2012/9/13/544 > > Cc: Grant Likely > Cc: Rob Herring > Cc: Geert Uytterhoeven > Cc: Sebastian Andrzej Siewior > Cc: Jean-Christophe PLAGNIOL-VILLARD > Cc: Vineet Gupta > Cc: Russell King > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Salter > Cc: Aurelien Jacquiot > Cc: James Hogan > Cc: Michal Simek > Cc: Ralf Baechle > Cc: Jonas Bonn > Cc: Benjamin Herrenschmidt > Cc: Paul Mackerras > Cc: x86@kernel.org > Cc: arm@kernel.org > Cc: Chris Zankel > Cc: Max Filippov > Cc: bigeasy@linutronix.de > Cc: robherring2@gmail.com > Cc: Nicolas Pitre > > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-c6x-dev@linux-c6x.org > Cc: linux-mips@linux-mips.org > Cc: linuxppc-dev@lists.ozlabs.org > Cc: linux-xtensa@linux-xtensa.org > Cc: devicetree-discuss@lists.ozlabs.org > > Signed-off-by: Santosh Shilimkar > --- > arch/arc/mm/init.c | 5 ++--- > arch/arm/mm/init.c | 2 +- > arch/arm64/mm/init.c | 3 +-- > arch/c6x/kernel/devicetree.c | 3 +-- > arch/metag/mm/init.c | 5 ++--- > arch/microblaze/kernel/prom.c | 3 +-- > arch/mips/kernel/prom.c | 3 +-- > arch/openrisc/kernel/prom.c | 3 +-- > arch/powerpc/kernel/prom.c | 3 +-- > arch/x86/kernel/devicetree.c | 3 +-- > arch/xtensa/kernel/setup.c | 3 +-- > drivers/of/fdt.c | 10 ++++++---- > include/linux/of_fdt.h | 3 +-- > 13 files changed, 20 insertions(+), 29 deletions(-) > > diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c > index 4a17736..7991e08 100644 > --- a/arch/arc/mm/init.c > +++ b/arch/arc/mm/init.c > @@ -157,9 +157,8 @@ void __init free_initrd_mem(unsigned long start, unsigned long end) > #endif > > #ifdef CONFIG_OF_FLATTREE > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > - pr_err("%s(%lx, %lx)\n", __func__, start, end); > + pr_err("%s(%llx, %llx)\n", __func__, start, end); > } > #endif /* CONFIG_OF_FLATTREE */ > diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c > index 9a5cdc0..afeaef7 100644 > --- a/arch/arm/mm/init.c > +++ b/arch/arm/mm/init.c > @@ -76,7 +76,7 @@ static int __init parse_tag_initrd2(const struct tag *tag) > __tagtable(ATAG_INITRD2, parse_tag_initrd2); > > #ifdef CONFIG_OF_FLATTREE > -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > phys_initrd_start = start; > phys_initrd_size = end - start; > diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c > index f497ca7..7047708 100644 > --- a/arch/arm64/mm/init.c > +++ b/arch/arm64/mm/init.c > @@ -44,8 +44,7 @@ static unsigned long phys_initrd_size __initdata = 0; > > phys_addr_t memstart_addr __read_mostly = 0; > > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > phys_initrd_start = start; > phys_initrd_size = end - start; > diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c > index bdb56f0..287d0e6 100644 > --- a/arch/c6x/kernel/devicetree.c > +++ b/arch/c6x/kernel/devicetree.c > @@ -33,8 +33,7 @@ void __init early_init_devtree(void *params) > > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c > index d05b845..bdc4811 100644 > --- a/arch/metag/mm/init.c > +++ b/arch/metag/mm/init.c > @@ -419,10 +419,9 @@ void free_initrd_mem(unsigned long start, unsigned long end) > #endif > > #ifdef CONFIG_OF_FLATTREE > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > - pr_err("%s(%lx, %lx)\n", > + pr_err("%s(%llx, %llx)\n", > __func__, start, end); > } > #endif /* CONFIG_OF_FLATTREE */ > diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c > index 0a2c68f..62e2e8f 100644 > --- a/arch/microblaze/kernel/prom.c > +++ b/arch/microblaze/kernel/prom.c > @@ -136,8 +136,7 @@ void __init early_init_devtree(void *params) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c > index 5712bb5..32b8788 100644 > --- a/arch/mips/kernel/prom.c > +++ b/arch/mips/kernel/prom.c > @@ -58,8 +58,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/openrisc/kernel/prom.c b/arch/openrisc/kernel/prom.c > index 5869e3f..150215a 100644 > --- a/arch/openrisc/kernel/prom.c > +++ b/arch/openrisc/kernel/prom.c > @@ -96,8 +96,7 @@ void __init early_init_devtree(void *params) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c > index 8b6f7a9..2f3e252 100644 > --- a/arch/powerpc/kernel/prom.c > +++ b/arch/powerpc/kernel/prom.c > @@ -550,8 +550,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c > index b158152..2fbad6b 100644 > --- a/arch/x86/kernel/devicetree.c > +++ b/arch/x86/kernel/devicetree.c > @@ -52,8 +52,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c > index 6dd25ec..d45e602 100644 > --- a/arch/xtensa/kernel/setup.c > +++ b/arch/xtensa/kernel/setup.c > @@ -170,8 +170,7 @@ static int __init parse_tag_fdt(const bp_tag_t *tag) > > __tagtable(BP_TAG_FDT, parse_tag_fdt); > > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (void *)__va(start); > initrd_end = (void *)__va(end); > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c > index 808be06..21123b8 100644 > --- a/drivers/of/fdt.c > +++ b/drivers/of/fdt.c > @@ -550,7 +550,8 @@ int __init of_flat_dt_match(unsigned long node, const char *const *compat) > */ > void __init early_init_dt_check_for_initrd(unsigned long node) > { > - unsigned long start, end, len; > + u64 start, end; > + unsigned long len; > __be32 *prop; > > pr_debug("Looking for initrd properties... "); > @@ -558,15 +559,16 @@ void __init early_init_dt_check_for_initrd(unsigned long node) > prop = of_get_flat_dt_prop(node, "linux,initrd-start", &len); > if (!prop) > return; > - start = of_read_ulong(prop, len/4); > + start = of_read_number(prop, len/4); > > prop = of_get_flat_dt_prop(node, "linux,initrd-end", &len); > if (!prop) > return; > - end = of_read_ulong(prop, len/4); > + end = of_read_number(prop, len/4); > > early_init_dt_setup_initrd_arch(start, end); > - pr_debug("initrd_start=0x%lx initrd_end=0x%lx\n", start, end); > + pr_debug("initrd_start=0x%llx initrd_end=0x%llx\n", > + (unsigned long long)start, (unsigned long long)end); > } > #else > inline void early_init_dt_check_for_initrd(unsigned long node) > diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h > index ed136ad..4a17939 100644 > --- a/include/linux/of_fdt.h > +++ b/include/linux/of_fdt.h > @@ -106,8 +106,7 @@ extern u64 dt_mem_next_cell(int s, __be32 **cellp); > * physical addresses. > */ > #ifdef CONFIG_BLK_DEV_INITRD > -extern void early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end); > +extern void early_init_dt_setup_initrd_arch(u64 start, u64 end); > #endif > > /* Early flat tree scan hooks */ > From michael@ellerman.id.au Tue Jul 2 02:53:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jul 2013 02:53:25 +0200 (CEST) Received: from ozlabs.org ([203.10.76.45]:56355 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835049Ab3GBAxX3BqbM (ORCPT ); Tue, 2 Jul 2013 02:53:23 +0200 Received: from [192.168.1.2] (124-171-102-126.dyn.iinet.net.au [124.171.102.126]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPSA id 641002C0079; Tue, 2 Jul 2013 10:53:17 +1000 (EST) Message-ID: <1372726396.17904.1.camel@concordia> Subject: Re: [PATCHv4 02/11] pci: use weak functions for MSI arch-specific functions From: Michael Ellerman To: Thomas Petazzoni Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Lior Amsalem , linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, Heiko Carstens , Thierry Reding , Paul Mackerras , "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, x86@kernel.org, Ingo Molnar , Ezequiel Garcia , Fenghua Yu , Chris Metcalf , linux-arm-kernel@lists.infradead.org, Tony Luck , Ralf Baechle , Maen Suleiman , Martin Schwidefsky , linux390@de.ibm.com, linuxppc-dev@lists.ozlabs.org, "David S. Miller" Date: Tue, 02 Jul 2013 10:53:16 +1000 In-Reply-To: <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.6.2-0ubuntu0.1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37249 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: michael@ellerman.id.au Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Mon, 2013-07-01 at 15:42 +0200, Thomas Petazzoni wrote: > Until now, the MSI architecture-specific functions could be overloaded > using a fairly complex set of #define and compile-time > conditionals. In order to prepare for the introduction of the msi_chip > infrastructure, it is desirable to switch all those functions to use > the 'weak' mechanism. This commit converts all the architectures that > were overidding those MSI functions to use the new strategy. The MSI code used to use weak functions, until we discovered they were being miscompiled on some toolchains (11df1f0). I assume these days we're confident they work correctly. cheers From Vineet.Gupta1@synopsys.com Tue Jul 2 06:18:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jul 2013 06:18:14 +0200 (CEST) Received: from alvesta.synopsys.com ([198.182.60.77]:65134 "EHLO alvesta.synopsys.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815756Ab3GBESFEpv2B convert rfc822-to-8bit (ORCPT ); Tue, 2 Jul 2013 06:18:05 +0200 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by alvesta.synopsys.com (Postfix) with ESMTP id D4B9E2CE07; Mon, 1 Jul 2013 21:17:56 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id ACB111599; Mon, 1 Jul 2013 21:17:56 -0700 (PDT) Received: from US01WXQAHTC1.internal.synopsys.com (us01wxqahtc1.internal.synopsys.com [10.12.238.230]) by mailhost.synopsys.com (Postfix) with ESMTP id 5D6E81594; Mon, 1 Jul 2013 21:17:51 -0700 (PDT) Received: from IN01WEHTCB.internal.synopsys.com (10.144.199.106) by US01WXQAHTC1.internal.synopsys.com (10.12.238.230) with Microsoft SMTP Server (TLS) id 14.2.298.4; Mon, 1 Jul 2013 21:17:49 -0700 Received: from IN01WEMBXA.internal.synopsys.com ([fe80::ed6f:22d3:d35:4833]) by IN01WEHTCB.internal.synopsys.com ([::1]) with mapi id 14.02.0298.004; Tue, 2 Jul 2013 09:47:46 +0530 From: Vineet Gupta To: Santosh Shilimkar CC: "grant.likely@linaro.org" , Rob Herring , Geert Uytterhoeven , Sebastian Andrzej Siewior , "Jean-Christophe PLAGNIOL-VILLARD" , Vineet Gupta , Russell King , Catalin Marinas , Will Deacon , Mark Salter , Aurelien Jacquiot , James Hogan , Michal Simek , Ralf Baechle , Jonas Bonn , Benjamin Herrenschmidt , Paul Mackerras , "x86@kernel.org" , "arm@kernel.org" , Chris Zankel , "Max Filippov" , "robherring2@gmail.com" , Nicolas Pitre , "linux-arm-kernel@lists.infradead.org" , "linux-c6x-dev@linux-c6x.org" , "linux-mips@linux-mips.org" , "linuxppc-dev@lists.ozlabs.org" , "linux-xtensa@linux-xtensa.org" , "devicetree-discuss@lists.ozlabs.org" Subject: Re: [PATCH v2] of: Specify initrd location using 64-bit Thread-Topic: [PATCH v2] of: Specify initrd location using 64-bit Thread-Index: AQHOdofpxQf8v8v2iESI1tlwA9f07A== Date: Tue, 2 Jul 2013 04:17:46 +0000 Message-ID: References: <1372702835-5333-1-git-send-email-santosh.shilimkar@ti.com> Accept-Language: en-US, en-IN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.15.84.232] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37250 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Vineet.Gupta1@synopsys.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 07/01/2013 11:52 PM, Santosh Shilimkar wrote: > On some PAE architectures, the entire range of physical memory could reside > outside the 32-bit limit. These systems need the ability to specify the > initrd location using 64-bit numbers. > > This patch globally modifies the early_init_dt_setup_initrd_arch() function to > use 64-bit numbers instead of the current unsigned long. > > There has been quite a bit of debate about whether to use u64 or phys_addr_t. > It was concluded to stick to u64 to be consistent with rest of the device > tree code. As summarized by Geert, "The address to load the initrd is decided > by the bootloader/user and set at that point later in time. The dtb should not > be tied to the kernel you are booting" > > More details on the discussion can be found here: > https://lkml.org/lkml/2013/6/20/690 > https://lkml.org/lkml/2012/9/13/544 > > Cc: Grant Likely > Cc: Rob Herring > Cc: Geert Uytterhoeven > Cc: Sebastian Andrzej Siewior > Cc: Jean-Christophe PLAGNIOL-VILLARD > Cc: Vineet Gupta > Cc: Russell King > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Salter > Cc: Aurelien Jacquiot > Cc: James Hogan > Cc: Michal Simek > Cc: Ralf Baechle > Cc: Jonas Bonn > Cc: Benjamin Herrenschmidt > Cc: Paul Mackerras > Cc: x86@kernel.org > Cc: arm@kernel.org > Cc: Chris Zankel > Cc: Max Filippov > Cc: bigeasy@linutronix.de > Cc: robherring2@gmail.com > Cc: Nicolas Pitre > > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-c6x-dev@linux-c6x.org > Cc: linux-mips@linux-mips.org > Cc: linuxppc-dev@lists.ozlabs.org > Cc: linux-xtensa@linux-xtensa.org > Cc: devicetree-discuss@lists.ozlabs.org > > Signed-off-by: Santosh Shilimkar > --- Acked-by: Vineet Gupta [For arch/arc bits] -Vineet From thomas.petazzoni@free-electrons.com Tue Jul 2 07:30:46 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jul 2013 07:30:49 +0200 (CEST) Received: from mail.free-electrons.com ([94.23.35.102]:35288 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817667Ab3GBFaq0N6y1 (ORCPT ); Tue, 2 Jul 2013 07:30:46 +0200 Received: by mail.free-electrons.com (Postfix, from userid 106) id C38DC753; Tue, 2 Jul 2013 07:30:41 +0200 (CEST) Received: from skate (AToulouse-651-1-103-169.w109-222.abo.wanadoo.fr [109.222.70.169]) by mail.free-electrons.com (Postfix) with ESMTPSA id 772AA753; Tue, 2 Jul 2013 07:30:40 +0200 (CEST) Date: Tue, 2 Jul 2013 07:30:37 +0200 From: Thomas Petazzoni To: Michael Ellerman Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Lior Amsalem , linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, Heiko Carstens , Thierry Reding , Paul Mackerras , "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, x86@kernel.org, Ingo Molnar , Ezequiel Garcia , Fenghua Yu , Chris Metcalf , linux-arm-kernel@lists.infradead.org, Tony Luck , Ralf Baechle , Maen Suleiman , Martin Schwidefsky , linux390@de.ibm.com, linuxppc-dev@lists.ozlabs.org, "David S. Miller" Subject: Re: [PATCHv4 02/11] pci: use weak functions for MSI arch-specific functions Message-ID: <20130702073037.55a53642@skate> In-Reply-To: <1372726396.17904.1.camel@concordia> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> <1372726396.17904.1.camel@concordia> Organization: Free Electrons X-Mailer: Claws Mail 3.9.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37251 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Dear Michael Ellerman, On Tue, 02 Jul 2013 10:53:16 +1000, Michael Ellerman wrote: > On Mon, 2013-07-01 at 15:42 +0200, Thomas Petazzoni wrote: > > Until now, the MSI architecture-specific functions could be overloaded > > using a fairly complex set of #define and compile-time > > conditionals. In order to prepare for the introduction of the msi_chip > > infrastructure, it is desirable to switch all those functions to use > > the 'weak' mechanism. This commit converts all the architectures that > > were overidding those MSI functions to use the new strategy. > > The MSI code used to use weak functions, until we discovered they were > being miscompiled on some toolchains (11df1f0). I assume these days > we're confident they work correctly. Hum, interesting. I see from your commit that gcc 4.3.2 was apparently affected, and gcc 4.3.x is not /that/ old. Bjorn, what's your point of view on this? Another option would be to have architecture register some msi_arch_ops structure, with a set of operations, which I believe is a pattern that is more widespread in the kernel than weak functions. Thoughts? Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com From michael@ellerman.id.au Tue Jul 2 08:52:28 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jul 2013 08:52:30 +0200 (CEST) Received: from ozlabs.org ([203.10.76.45]:59309 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817545Ab3GBGw2jfg0Q (ORCPT ); Tue, 2 Jul 2013 08:52:28 +0200 Received: from concordia (ibmaus65.lnk.telstra.net [165.228.126.9]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPSA id A542A2C009F; Tue, 2 Jul 2013 16:52:22 +1000 (EST) Date: Tue, 2 Jul 2013 16:52:20 +1000 From: Michael Ellerman To: Thomas Petazzoni Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Lior Amsalem , linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, Heiko Carstens , Thierry Reding , Paul Mackerras , "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, x86@kernel.org, Ingo Molnar , Ezequiel Garcia , Fenghua Yu , Chris Metcalf , linux-arm-kernel@lists.infradead.org, Tony Luck , Ralf Baechle , Maen Suleiman , Martin Schwidefsky , linux390@de.ibm.com, linuxppc-dev@lists.ozlabs.org, "David S. Miller" Subject: Re: [PATCHv4 02/11] pci: use weak functions for MSI arch-specific functions Message-ID: <20130702065220.GA20521@concordia> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> <1372726396.17904.1.camel@concordia> <20130702073037.55a53642@skate> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130702073037.55a53642@skate> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37252 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: michael@ellerman.id.au Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Tue, Jul 02, 2013 at 07:30:37AM +0200, Thomas Petazzoni wrote: > Dear Michael Ellerman, > > On Tue, 02 Jul 2013 10:53:16 +1000, Michael Ellerman wrote: > > On Mon, 2013-07-01 at 15:42 +0200, Thomas Petazzoni wrote: > > > Until now, the MSI architecture-specific functions could be overloaded > > > using a fairly complex set of #define and compile-time > > > conditionals. In order to prepare for the introduction of the msi_chip > > > infrastructure, it is desirable to switch all those functions to use > > > the 'weak' mechanism. This commit converts all the architectures that > > > were overidding those MSI functions to use the new strategy. > > > > The MSI code used to use weak functions, until we discovered they were > > being miscompiled on some toolchains (11df1f0). I assume these days > > we're confident they work correctly. > > Hum, interesting. I see from your commit that gcc 4.3.2 was apparently > affected, and gcc 4.3.x is not /that/ old. Bjorn, what's your point of > view on this? Stop press. I went back and found the old threads on this, it's been a while. It looks like it was only gcc 4.1.[01] that miscompiled. The reference to gcc 4.3.2 was WRT ellision of the unused code, which is a separate issue. The kernel blacklists gcc 4.1.[01] (see f9d1425), so weak should be safe to use. We merged the change to the PCI code anyway because we thought it was nicer and it also avoided any problems with weak. So pretend I never said anything :) cheers From Markos.Chandras@imgtec.com Tue Jul 2 12:29:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jul 2013 12:29:43 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:48023 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816209Ab3GBK3msxsRK (ORCPT ); Tue, 2 Jul 2013 12:29:42 +0200 From: Markos Chandras To: CC: Markos Chandras Subject: [PATCH v2] MIPS: bcm63xx: clk: Add dummy clk_{set,round}_rate() functions Date: Tue, 2 Jul 2013 11:13:44 +0100 Message-ID: <1372760024-26297-1-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 1.8.2.1 MIME-Version: 1.0 Content-Type: text/plain X-SEF-Processed: 7_3_0_01192__2013_07_02_11_29_08 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37253 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Several drivers use the clk_{set,round}_rate() functions that need to be defined in the platform's clock code. The Broadcom BCM63xx platform hardcodes the clock rate so we create new clk_{set,round}_rate() functions which just return 0 like those in include/linux/clk.h for the common clock framework do. Also fixes the following build problem on a randconfig: drivers/built-in.o: In function `nop_usb_xceiv_probe': phy-nop.c:(.text+0x3ec26c): undefined reference to `clk_set_rate' Signed-off-by: Markos Chandras Acked-by: Steven J. Hill --- Changes since v1: - Return 0 instead of -EINVAL for clk_set_rate to be compatible with the common clock framework interfaces - Add dummy clk_round_rate http://www.linux-mips.org/archives/linux-mips/2013-07/msg00006.html This patch is for the upstream-sfr/mips-for-linux-next tree --- arch/mips/bcm63xx/clk.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index fda2690..43da4ae 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -318,6 +318,18 @@ unsigned long clk_get_rate(struct clk *clk) EXPORT_SYMBOL(clk_get_rate); +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} +EXPORT_SYMBOL_GPL(clk_set_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} +EXPORT_SYMBOL_GPL(clk_round_rate); + struct clk *clk_get(struct device *dev, const char *id) { if (!strcmp(id, "enet0")) -- 1.8.2.1 From f.fainelli@gmail.com Tue Jul 2 12:46:49 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jul 2013 12:46:51 +0200 (CEST) Received: from mail-pa0-f43.google.com ([209.85.220.43]:50074 "EHLO mail-pa0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816209Ab3GBKqto8Trm (ORCPT ); Tue, 2 Jul 2013 12:46:49 +0200 Received: by mail-pa0-f43.google.com with SMTP id hz11so6103545pad.2 for ; Tue, 02 Jul 2013 03:46:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=m361KGpdZT5Z9vH/WsoGtXzVOuX87jx9Xhl1lBsygPc=; b=ZyFFx8NV+KiHo3VURO57s77uYgWN218hGYeb5pjceMsZGC2hyRTXZNtZtm5mby9aJC 8KDwm8R26MDR2WPi/Dmccg24J19PTRYrcjHeJxxNtAi0irvNZkNtg+JEWL91df1eUIFz IozNahqVuPwCPoaW2VAwJagHbz5K0BgK+uNWPJqBSFNsBeoOhtMmsv4J2ytwJvn5Rndt Qltpjc+hw1S6PvwbDXx8rHQzZj8nkVvxvAROicdqP+rPvCq3WkALeFESUwoWnH0e5VXU kV7dHS5RERK899MNrn9YNKiDfI+Iozfo+peUdBy5KdF7Lr5DN2N+nohvPkPmYUYJzAJq wfgA== X-Received: by 10.66.37.43 with SMTP id v11mr28448568paj.108.1372762003496; Tue, 02 Jul 2013 03:46:43 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.10.101 with HTTP; Tue, 2 Jul 2013 03:46:03 -0700 (PDT) In-Reply-To: <1372760024-26297-1-git-send-email-markos.chandras@imgtec.com> References: <1372760024-26297-1-git-send-email-markos.chandras@imgtec.com> From: Florian Fainelli Date: Tue, 2 Jul 2013 11:46:03 +0100 Message-ID: Subject: Re: [PATCH v2] MIPS: bcm63xx: clk: Add dummy clk_{set,round}_rate() functions To: Markos Chandras Cc: Linux-MIPS Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37254 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: f.fainelli@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips 2013/7/2 Markos Chandras : > Several drivers use the clk_{set,round}_rate() functions > that need to be defined in the platform's clock code. > The Broadcom BCM63xx platform hardcodes the clock rate so > we create new clk_{set,round}_rate() functions > which just return 0 like those in include/linux/clk.h > for the common clock framework do. > > Also fixes the following build problem on a randconfig: > drivers/built-in.o: In function `nop_usb_xceiv_probe': > phy-nop.c:(.text+0x3ec26c): undefined reference to `clk_set_rate' > > Signed-off-by: Markos Chandras > Acked-by: Steven J. Hill Acked-by: Florian Fainelli -- Florian From ralf@linux-mips.org Tue Jul 2 16:32:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jul 2013 16:32:06 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:39298 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6820610Ab3GBOcFXqWMe (ORCPT ); Tue, 2 Jul 2013 16:32:05 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r62EW3fj003130; Tue, 2 Jul 2013 16:32:03 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r62EW2RY003129; Tue, 2 Jul 2013 16:32:02 +0200 Date: Tue, 2 Jul 2013 16:32:02 +0200 From: Ralf Baechle To: Florian Fainelli Cc: Markos Chandras , Linux-MIPS Subject: Re: [PATCH v2] MIPS: bcm63xx: clk: Add dummy clk_{set,round}_rate() functions Message-ID: <20130702143202.GB2007@linux-mips.org> References: <1372760024-26297-1-git-send-email-markos.chandras@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37255 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Thanks folks, applied. Ralf From bhelgaas@google.com Tue Jul 2 19:15:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jul 2013 19:16:41 +0200 (CEST) Received: from mail-ob0-f174.google.com ([209.85.214.174]:64443 "EHLO mail-ob0-f174.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835080Ab3GBRPNYtjAy (ORCPT ); Tue, 2 Jul 2013 19:15:13 +0200 Received: by mail-ob0-f174.google.com with SMTP id wd20so5839953obb.19 for ; Tue, 02 Jul 2013 10:14:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=xF+DXO4KSbCkA4lU7sHkBVhSf2mVUPKtorHqZnZNSCg=; b=aX4REXTaYidDZyLoDI0LFita4FddxeIYey/UtGGZWqRcFQuMQvfow6fsCU6JkTWHRf Kpaa4O/SFWfLCitOSp42zB1KO2bvfmq7dwUuGHRbh8VBRplI80w3OG6J0K8Om4lpw+z9 frG/lbH2CSOwJ7p2Vtl541O6if2IyqObH5lU8AxDwdaMDkIC2wFKFJDtR9+FCoPTCBUK IHWGeHBayOP3fGtF82fUPj/oxno3Jeu7dWLAIlEiVYgME5yKpLmKeqDtwhhE+uUD1lyN XqhJFgClP0GaBLYeZj/InEetvV8UVrRRQqKN4QB5fVzFmyZOHmWjB7O1h8sS5e5uBB23 M13A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=xF+DXO4KSbCkA4lU7sHkBVhSf2mVUPKtorHqZnZNSCg=; b=YtxhY/ol1oYApRFAhA5ICTTj7eKGosu+rCPoGxKGnKiDuVjScRj/HxYpq8284ZuUdI fS7KJLIT/JiYo1lTcCQK3PIa+wgfCN6rfGQ4GxTRDlT9qUIyQj0BXhUH4CxM8W/UuoTH zEVMFsbycweEvgFkBaeOV0gTlB7707hR+U1dNyB5dOkP0rShH+8zzLC0y4tKKBm66wb+ RopaYgsmoG2Q8YILLQgTz68RBT62nCobbZ+em5S+4Dht3GUV8vFqPmmXIhMlLVz3/e/u 9Iu04nDAxEM5BXF9YOPSvL6UAahMGVFWBDG+wsyo26cEzUs7bS7tdZEYGI+FoFcMO8Ld dmbw== X-Received: by 10.182.81.202 with SMTP id c10mr13742446oby.27.1372785261566; Tue, 02 Jul 2013 10:14:21 -0700 (PDT) MIME-Version: 1.0 Received: by 10.182.75.99 with HTTP; Tue, 2 Jul 2013 10:14:01 -0700 (PDT) In-Reply-To: <20130702073037.55a53642@skate> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> <1372726396.17904.1.camel@concordia> <20130702073037.55a53642@skate> From: Bjorn Helgaas Date: Tue, 2 Jul 2013 11:14:01 -0600 Message-ID: Subject: Re: [PATCHv4 02/11] pci: use weak functions for MSI arch-specific functions To: Thomas Petazzoni Cc: Michael Ellerman , "linux-pci@vger.kernel.org" , Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Lior Amsalem , "linux-mips@linux-mips.org" , "linux-ia64@vger.kernel.org" , Heiko Carstens , Thierry Reding , Paul Mackerras , "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, "x86@kernel.org" , Ingo Molnar , Ezequiel Garcia , Fenghua Yu , Chris Metcalf , linux-arm , Tony Luck , Ralf Baechle , Maen Suleiman , Martin Schwidefsky , linux390@de.ibm.com, linuxppc-dev , "David S. Miller" Content-Type: text/plain; charset=ISO-8859-1 X-Gm-Message-State: ALoCoQnfwxGXIooLQAFj9ojZL367+2aoCnSsa/GjvHub0y9dUBr73NNCGR9OhMrFQaiXqQDaInBOcfIxqAkJaa/R1Rj5cRJIKbUh5EwzHyEg6oEZNsnIHvVOyVFr3WoCG7vIu9SNZ2dk4aDxAMqZ+9IgRbpCf3TjK9pOUsxpzM45JOVxEe2GuzHJNByVXJ60neAh/cifaUD4Vf7umAqAd9P9avSl8MFiNA== Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37256 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Mon, Jul 1, 2013 at 11:30 PM, Thomas Petazzoni wrote: > Dear Michael Ellerman, > > On Tue, 02 Jul 2013 10:53:16 +1000, Michael Ellerman wrote: >> On Mon, 2013-07-01 at 15:42 +0200, Thomas Petazzoni wrote: >> > Until now, the MSI architecture-specific functions could be overloaded >> > using a fairly complex set of #define and compile-time >> > conditionals. In order to prepare for the introduction of the msi_chip >> > infrastructure, it is desirable to switch all those functions to use >> > the 'weak' mechanism. This commit converts all the architectures that >> > were overidding those MSI functions to use the new strategy. >> >> The MSI code used to use weak functions, until we discovered they were >> being miscompiled on some toolchains (11df1f0). I assume these days >> we're confident they work correctly. > > Hum, interesting. I see from your commit that gcc 4.3.2 was apparently > affected, and gcc 4.3.x is not /that/ old. Bjorn, what's your point of > view on this? There *were* compilation issues with weak functions, but AFAIK they've been resolved and there's no reason to avoid them. Commit f9d142500 addressed this. Bjorn From markos.chandras@gmail.com Wed Jul 3 16:01:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jul 2013 16:01:55 +0200 (CEST) Received: from mail-wg0-f49.google.com ([74.125.82.49]:33061 "EHLO mail-wg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823015Ab3GCOBvMFA0f (ORCPT ); Wed, 3 Jul 2013 16:01:51 +0200 Received: by mail-wg0-f49.google.com with SMTP id a12so160758wgh.16 for ; Wed, 03 Jul 2013 07:01:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=p6tzu1pwq9Qyveu7YGkwgh2MqdEwEajk5JGXWgSUUL8=; b=y+Hi5iuD5kYMxDyidNFcicayKXhT6G9/dG0Jd5VkD9KsmQcLCfYnPhaJ+SIrIR8lvJ J62eEVVMyEMEMjQDQdjjz3IgzFtwJw5DwuPhvTyPr8KTBK6lxvAJbqksekNUmef6mamA Cdi5bP5R1XHaztQsfFwlI4EkcA9emns2AvxLbFkWGTS87KXswZ1evqUAolSdLuW+Zdsi 8dIIbhlp/nI7OElj9FGcxQAuxJga00N2dIuCJIUtdM2DWGlJezy8XuBo0h1bcHfVaR1S p4hJbtqXeiuHOfrCcZK4x/1YtDM2tdxBJfuYJhvjISoJ60OyAsOO8WgtqCYMCMZ/1Fnu g/qA== X-Received: by 10.180.36.12 with SMTP id m12mr710457wij.10.1372860105664; Wed, 03 Jul 2013 07:01:45 -0700 (PDT) MIME-Version: 1.0 Received: by 10.194.163.138 with HTTP; Wed, 3 Jul 2013 07:01:05 -0700 (PDT) In-Reply-To: <20130626145234.GB7171@linux-mips.org> References: <1371742590-10138-1-git-send-email-Steven.Hill@imgtec.com> <20130626145234.GB7171@linux-mips.org> From: Markos Chandras Date: Wed, 3 Jul 2013 15:01:05 +0100 Message-ID: Subject: Re: [PATCH v2] Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET" To: Ralf Baechle Cc: "Steven J. Hill" , linux-mips@linux-mips.org, Leonid Yegoshin , Florian Fainelli Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37260 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1633 Lines: 40 On 26 June 2013 15:52, Ralf Baechle wrote: > On Thu, Jun 20, 2013 at 10:36:30AM -0500, Steven J. Hill wrote: > >> From: Leonid Yegoshin >> >> This reverts commit 3f4579252aa166641861a64f1c2883365ca126c2. It is >> invalid because the macros CAC_ADDR and UNCAC_ADDR have a kernel >> virtual address as an argument and also returns a kernel virtual >> address. Using and physical address PHYS_OFFSET is blatantly wrong >> for a macro common to multiple platforms. > > While the patch itself is looking sane at a glance, I'm wondering if this > is fixing any actual bug or is just the result of a code review? > > Ralf > I am afraid this commit[1] broke the build in upstream-sfr/mips-for-linux-next with errors like this arch/mips/include/asm/mach-generic/spaces.h:29:0: warning: "UNCAC_BASE" redefined [enabled by default] In file included from arch/mips/include/asm/addrspace.h:13:0, from arch/mips/include/asm/barrier.h:11, from arch/mips/include/asm/bitops.h:18, from include/linux/bitops.h:22, from include/linux/kernel.h:10, from include/asm-generic/bug.h:13, from arch/mips/include/asm/bug.h:41, from include/linux/bug.h:4, from include/linux/page-flags.h:9, from kernel/bounds.c:9: arch/mips/include/asm/mach-ar7/spaces.h:20:0: note: this is the location of the previous definition [1]: http://git.linux-mips.org/?p=ralf/upstream-sfr.git;a=commit;h=ed3ce16c3d2ba7cac321d29ec0a7d21408ea8437 -- Regards, Markos Chandras From James.Hogan@imgtec.com Wed Jul 3 16:42:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jul 2013 16:42:17 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:35867 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823020Ab3GCOmLglNVF (ORCPT ); Wed, 3 Jul 2013 16:42:11 +0200 From: James Hogan To: CC: James Hogan , Ralf Baechle , Christoph Lameter , Tejun Heo , "Dave Jones" , David Howells , David Sharp , "Paul E. McKenney" , "Thomas Gleixner" , Subject: [PATCH] MIPS: use generic-y where possible Date: Wed, 3 Jul 2013 15:40:58 +0100 Message-ID: <1372862458-22693-1-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 Content-Type: text/plain X-SEF-Processed: 7_3_0_01192__2013_07_03_15_41_15 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37261 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: james.hogan@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 8056 Lines: 246 Use generic-y and remove headers in arch/mips/include/[uapi/]asm/Kbuild where the header just includes or is identical to the corresponding . We can't do the same for uapi/asm/kvm_para.h because it's presence is explicitly checked in include/uapi/linux/Kbuild to decide whether to add kvm_para.h to header-y. Signed-off-by: James Hogan Cc: Ralf Baechle Cc: Christoph Lameter Cc: Tejun Heo Cc: Dave Jones Cc: David Howells Cc: David Sharp Cc: "Paul E. McKenney" Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org --- arch/mips/include/asm/Kbuild | 13 +++++++++++++ arch/mips/include/asm/cputime.h | 6 ------ arch/mips/include/asm/current.h | 1 - arch/mips/include/asm/emergency-restart.h | 6 ------ arch/mips/include/asm/local64.h | 1 - arch/mips/include/asm/mutex.h | 9 --------- arch/mips/include/asm/parport.h | 1 - arch/mips/include/asm/percpu.h | 6 ------ arch/mips/include/asm/scatterlist.h | 6 ------ arch/mips/include/asm/sections.h | 6 ------ arch/mips/include/asm/segment.h | 6 ------ arch/mips/include/asm/serial.h | 1 - arch/mips/include/asm/ucontext.h | 1 - arch/mips/include/asm/xor.h | 1 - arch/mips/include/uapi/asm/Kbuild | 5 +++-- arch/mips/include/uapi/asm/auxvec.h | 4 ---- arch/mips/include/uapi/asm/ipcbuf.h | 1 - 17 files changed, 16 insertions(+), 58 deletions(-) delete mode 100644 arch/mips/include/asm/cputime.h delete mode 100644 arch/mips/include/asm/current.h delete mode 100644 arch/mips/include/asm/emergency-restart.h delete mode 100644 arch/mips/include/asm/local64.h delete mode 100644 arch/mips/include/asm/mutex.h delete mode 100644 arch/mips/include/asm/parport.h delete mode 100644 arch/mips/include/asm/percpu.h delete mode 100644 arch/mips/include/asm/scatterlist.h delete mode 100644 arch/mips/include/asm/sections.h delete mode 100644 arch/mips/include/asm/segment.h delete mode 100644 arch/mips/include/asm/serial.h delete mode 100644 arch/mips/include/asm/ucontext.h delete mode 100644 arch/mips/include/asm/xor.h delete mode 100644 arch/mips/include/uapi/asm/auxvec.h delete mode 100644 arch/mips/include/uapi/asm/ipcbuf.h diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 9b54b7a..454ddf9 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -1,2 +1,15 @@ # MIPS headers +generic-y += cputime.h +generic-y += current.h +generic-y += emergency-restart.h +generic-y += local64.h +generic-y += mutex.h +generic-y += parport.h +generic-y += percpu.h +generic-y += scatterlist.h +generic-y += sections.h +generic-y += segment.h +generic-y += serial.h generic-y += trace_clock.h +generic-y += ucontext.h +generic-y += xor.h diff --git a/arch/mips/include/asm/cputime.h b/arch/mips/include/asm/cputime.h deleted file mode 100644 index c00eacb..0000000 --- a/arch/mips/include/asm/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __MIPS_CPUTIME_H -#define __MIPS_CPUTIME_H - -#include - -#endif /* __MIPS_CPUTIME_H */ diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h deleted file mode 100644 index 4c51401..0000000 --- a/arch/mips/include/asm/current.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mips/include/asm/emergency-restart.h b/arch/mips/include/asm/emergency-restart.h deleted file mode 100644 index 108d8c4..0000000 --- a/arch/mips/include/asm/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/arch/mips/include/asm/local64.h b/arch/mips/include/asm/local64.h deleted file mode 100644 index 36c93b5..0000000 --- a/arch/mips/include/asm/local64.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mips/include/asm/mutex.h b/arch/mips/include/asm/mutex.h deleted file mode 100644 index 458c1f7..0000000 --- a/arch/mips/include/asm/mutex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Pull in the generic implementation for the mutex fastpath. - * - * TODO: implement optimized primitives instead, or leave the generic - * implementation in place, or pick the atomic_xchg() based generic - * implementation. (see asm-generic/mutex-xchg.h for details) - */ - -#include diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h deleted file mode 100644 index cf252af..0000000 --- a/arch/mips/include/asm/parport.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mips/include/asm/percpu.h b/arch/mips/include/asm/percpu.h deleted file mode 100644 index 844e763..0000000 --- a/arch/mips/include/asm/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_PERCPU_H -#define __ASM_PERCPU_H - -#include - -#endif /* __ASM_PERCPU_H */ diff --git a/arch/mips/include/asm/scatterlist.h b/arch/mips/include/asm/scatterlist.h deleted file mode 100644 index 7ee0e64..0000000 --- a/arch/mips/include/asm/scatterlist.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_SCATTERLIST_H -#define __ASM_SCATTERLIST_H - -#include - -#endif /* __ASM_SCATTERLIST_H */ diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h deleted file mode 100644 index b7e3726..0000000 --- a/arch/mips/include/asm/sections.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SECTIONS_H -#define _ASM_SECTIONS_H - -#include - -#endif /* _ASM_SECTIONS_H */ diff --git a/arch/mips/include/asm/segment.h b/arch/mips/include/asm/segment.h deleted file mode 100644 index 92ac001..0000000 --- a/arch/mips/include/asm/segment.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SEGMENT_H -#define _ASM_SEGMENT_H - -/* Only here because we have some old header files that expect it.. */ - -#endif /* _ASM_SEGMENT_H */ diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h deleted file mode 100644 index a0cb0ca..0000000 --- a/arch/mips/include/asm/serial.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h deleted file mode 100644 index 9bc07b9..0000000 --- a/arch/mips/include/asm/ucontext.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mips/include/asm/xor.h b/arch/mips/include/asm/xor.h deleted file mode 100644 index c82eb12..0000000 --- a/arch/mips/include/asm/xor.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild index 350cccc..be7196e 100644 --- a/arch/mips/include/uapi/asm/Kbuild +++ b/arch/mips/include/uapi/asm/Kbuild @@ -1,7 +1,9 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm -header-y += auxvec.h +generic-y += auxvec.h +generic-y += ipcbuf.h + header-y += bitsperlong.h header-y += break.h header-y += byteorder.h @@ -11,7 +13,6 @@ header-y += fcntl.h header-y += inst.h header-y += ioctl.h header-y += ioctls.h -header-y += ipcbuf.h header-y += kvm_para.h header-y += mman.h header-y += msgbuf.h diff --git a/arch/mips/include/uapi/asm/auxvec.h b/arch/mips/include/uapi/asm/auxvec.h deleted file mode 100644 index 7cf7f2d..0000000 --- a/arch/mips/include/uapi/asm/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _ASM_AUXVEC_H -#define _ASM_AUXVEC_H - -#endif /* _ASM_AUXVEC_H */ diff --git a/arch/mips/include/uapi/asm/ipcbuf.h b/arch/mips/include/uapi/asm/ipcbuf.h deleted file mode 100644 index 84c7e51..0000000 --- a/arch/mips/include/uapi/asm/ipcbuf.h +++ /dev/null @@ -1 +0,0 @@ -#include -- 1.8.1.2 From Steven.Hill@imgtec.com Wed Jul 3 17:56:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jul 2013 17:56:50 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:48294 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824768Ab3GCP4l1luN0 (ORCPT ); Wed, 3 Jul 2013 17:56:41 +0200 Message-ID: <51D449A8.6010207@imgtec.com> Date: Wed, 3 Jul 2013 10:56:24 -0500 From: "Steven J. Hill" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 MIME-Version: 1.0 To: Markos Chandras CC: Ralf Baechle , , "Leonid Yegoshin" , Florian Fainelli Subject: Re: [PATCH v2] Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET" References: <1371742590-10138-1-git-send-email-Steven.Hill@imgtec.com> <20130626145234.GB7171@linux-mips.org> In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.159.70] X-SEF-Processed: 7_3_0_01192__2013_07_03_16_56_35 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37262 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1081 Lines: 25 On 07/03/2013 09:01 AM, Markos Chandras wrote: > > I am afraid this commit[1] broke the build in > upstream-sfr/mips-for-linux-next with errors like this > > arch/mips/include/asm/mach-generic/spaces.h:29:0: warning: > "UNCAC_BASE" redefined [enabled by default] > In file included from arch/mips/include/asm/addrspace.h:13:0, > from arch/mips/include/asm/barrier.h:11, > from arch/mips/include/asm/bitops.h:18, > from include/linux/bitops.h:22, > from include/linux/kernel.h:10, > from include/asm-generic/bug.h:13, > from arch/mips/include/asm/bug.h:41, > from include/linux/bug.h:4, > from include/linux/page-flags.h:9, > from kernel/bounds.c:9: > arch/mips/include/asm/mach-ar7/spaces.h:20:0: note: this is the > location of the previous definition > > [1]: http://git.linux-mips.org/?p=ralf/upstream-sfr.git;a=commit;h=ed3ce16c3d2ba7cac321d29ec0a7d21408ea8437 > Let me rebase the patch and send another version. From Steven.Hill@imgtec.com Wed Jul 3 20:25:59 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jul 2013 20:26:00 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:37613 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827447Ab3GCSZ7E4n2w (ORCPT ); Wed, 3 Jul 2013 20:25:59 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1UuRkU-0006FW-TR; Wed, 03 Jul 2013 13:25:50 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH v3] MIPS: Fix multiple definitions of UNCAC_BASE. Date: Wed, 3 Jul 2013 13:25:46 -0500 Message-Id: <1372875946-17311-1-git-send-email-Steven.Hill@imgtec.com> X-Mailer: git-send-email 1.7.9.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37263 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1506 Lines: 46 From: "Steven J. Hill" Fix build error below: arch/mips/include/asm/mach-generic/spaces.h:29:0: warning: "UNCAC_BASE" redefined [enabled by default] In file included from arch/mips/include/asm/addrspace.h:13:0, from arch/mips/include/asm/barrier.h:11, from arch/mips/include/asm/bitops.h:18, from include/linux/bitops.h:22, from include/linux/kernel.h:10, from include/asm-generic/bug.h:13, from arch/mips/include/asm/bug.h:41, from include/linux/bug.h:4, from include/linux/page-flags.h:9, from kernel/bounds.c:9: arch/mips/include/asm/mach-ar7/spaces.h:20:0: note: this is the location of the previous definition Signed-off-by: Steven J. Hill --- Changes in v3: Fix up multiple definiition errors for 32-bit. arch/mips/include/asm/mach-generic/spaces.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index 5b2f2e6..9488fa5 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -25,8 +25,12 @@ #else #define CAC_BASE _AC(0x80000000, UL) #endif +#ifndef IO_BASE #define IO_BASE _AC(0xa0000000, UL) +#endif +#ifndef UNCAC_BASE #define UNCAC_BASE _AC(0xa0000000, UL) +#endif #ifndef MAP_BASE #ifdef CONFIG_KVM_GUEST -- 1.7.9.5 From Steven.Hill@imgtec.com Wed Jul 3 20:28:33 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jul 2013 20:28:35 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:37623 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816859Ab3GCS2dPYcB0 (ORCPT ); Wed, 3 Jul 2013 20:28:33 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1UuRn0-0006Fx-SN; Wed, 03 Jul 2013 13:28:26 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , ralf@linux-mips.org Subject: [PATCH] MIPS: Fix multiple definitions of UNCAC_BASE. Date: Wed, 3 Jul 2013 13:28:22 -0500 Message-Id: <1372876102-17372-1-git-send-email-Steven.Hill@imgtec.com> X-Mailer: git-send-email 1.7.9.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37264 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1444 Lines: 45 From: "Steven J. Hill" Fix build error below: arch/mips/include/asm/mach-generic/spaces.h:29:0: warning: "UNCAC_BASE" redefined [enabled by default] In file included from arch/mips/include/asm/addrspace.h:13:0, from arch/mips/include/asm/barrier.h:11, from arch/mips/include/asm/bitops.h:18, from include/linux/bitops.h:22, from include/linux/kernel.h:10, from include/asm-generic/bug.h:13, from arch/mips/include/asm/bug.h:41, from include/linux/bug.h:4, from include/linux/page-flags.h:9, from kernel/bounds.c:9: arch/mips/include/asm/mach-ar7/spaces.h:20:0: note: this is the location of the previous definition Signed-off-by: Steven J. Hill --- arch/mips/include/asm/mach-generic/spaces.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index 5b2f2e6..9488fa5 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -25,8 +25,12 @@ #else #define CAC_BASE _AC(0x80000000, UL) #endif +#ifndef IO_BASE #define IO_BASE _AC(0xa0000000, UL) +#endif +#ifndef UNCAC_BASE #define UNCAC_BASE _AC(0xa0000000, UL) +#endif #ifndef MAP_BASE #ifdef CONFIG_KVM_GUEST -- 1.7.9.5 From Markos.Chandras@imgtec.com Thu Jul 4 10:38:38 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jul 2013 10:38:40 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:10499 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819996Ab3GDIiiwgQKk (ORCPT ); Thu, 4 Jul 2013 10:38:38 +0200 From: Markos Chandras To: CC: Markos Chandras Subject: [PATCH] MIPS: loongson: Hide the pci code behind CONFIG_PCI Date: Thu, 4 Jul 2013 09:38:29 +0100 Message-ID: <1372927109-21498-1-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 1.8.2.1 MIME-Version: 1.0 Content-Type: text/plain X-SEF-Processed: 7_3_0_01192__2013_07_04_09_38_33 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37265 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1100 Lines: 37 The pci.c code depends on symbols which are only visible if CONFIG_PCI is selected. Also fixes the following problem on loongson allnoconfig: arch/mips/built-in.o: In function `pcibios_init': pci.c:(.init.text+0x528): undefined reference to `register_pci_controller' arch/mips/built-in.o:(.data+0xc): undefined reference to `loongson_pci_ops' Signed-off-by: Markos Chandras Acked-by: Steven J. Hill --- This patch is for the upstream-sfr/mips-for-linux-next tree --- arch/mips/loongson/common/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index 4c57b3e..9e4484c 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -3,8 +3,9 @@ # obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ - pci.o bonito-irq.o mem.o machtype.o platform.o + bonito-irq.o mem.o machtype.o platform.o obj-$(CONFIG_GPIOLIB) += gpio.o +obj-$(CONFIG_PCI) += pci.o # # Serial port support -- 1.8.2.1 From amurray@embedded-bits.co.uk Fri Jul 5 15:31:21 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Jul 2013 15:31:29 +0200 (CEST) Received: from mail-ee0-f42.google.com ([74.125.83.42]:62514 "EHLO mail-ee0-f42.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823068Ab3GENbVKnZfV (ORCPT ); Fri, 5 Jul 2013 15:31:21 +0200 Received: by mail-ee0-f42.google.com with SMTP id c4so1423917eek.1 for ; Fri, 05 Jul 2013 06:31:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=XRMiJh2xFMSpbXXpU2Zbo0K6YUCK/HQqDaW+W6rSG68=; b=E0G3OBRlbThvYJwj14HF6eLkYlF5DxuREqY7RQXG5iKl+CSCRVuu0lbGMkcpbHbeWN VvnVg0GtIc3kwkyahflkKbU1qdo5DXz+p7QofSad0icbUUhEo8qaAfPqV+DELqRIQeOJ RX5QqtHfCnBzm6Hi3m3+pKkCNikZEe3ZE8Z/e/VVD231X8/umZONlQewWXWgsLMIzYa5 FCqJPsLmhJQgq7hGF6q6M+31SxOExLplVj6A2dfGcv7ZBbkx4BD/AXGTMmnriNtiSUEQ JVv185KjvlpUg4+ytPiWo5w8VDt+20N0gahrI8a/+8i3Ob0yrgCP90lT/mofT0eDuETO cjaw== X-Received: by 10.14.99.71 with SMTP id w47mr12244844eef.140.1373031074454; Fri, 05 Jul 2013 06:31:14 -0700 (PDT) Received: from gmail.com (host-92-28-211-145.as13285.net. [92.28.211.145]) by mx.google.com with ESMTPSA id i2sm14044485eeu.4.2013.07.05.06.31.12 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 05 Jul 2013 06:31:13 -0700 (PDT) Date: Fri, 5 Jul 2013 14:29:44 +0100 From: Andrew Murray To: ralf@linux-mips.org Cc: Andrew.Murray@arm.com, monstr@monstr.eu, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, blogic@openwrt.org, ddaney@caviumnetworks.com, jason@lakedaemon.net Subject: Re: of_pci_range_parser patch series Message-ID: <20130705132944.GA6417@gmail.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQkaiNVABBtFgu2VrbXbl6IcqKSAu6+Sa0zjsKiFsIhT7Adf+BCCcUh/Crh8ZNYyrqLH/YOk Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37268 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: amurray@embedded-bits.co.uk Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 584 Lines: 25 > Andrew, > > I noticed that [1] is now in -next but not the MIPS patch [2], not the > MicroBlaze patch [3]. What is the reason for that? If it's only the > lack of an ack, here's mine for the MIPS version: There was no reason other that the missing acks. > > Acked-by: Ralf Baechle Thanks for this. Jason - is it possible/best to take this through your tree? Andrew Murray > > Thanks, > > Ralf > > [1] http://patchwork.linux-mips.org/patch/5218/ > [2] http://patchwork.linux-mips.org/patch/5217/ > [3] http://patchwork.linux-mips.org/patch/5216/ From jason@lakedaemon.net Fri Jul 5 19:19:57 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Jul 2013 19:19:58 +0200 (CEST) Received: from mho-03-ewr.mailhop.org ([204.13.248.66]:60453 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6827525Ab3GERT5V130c (ORCPT ); Fri, 5 Jul 2013 19:19:57 +0200 Received: from pool-72-84-113-162.nrflva.fios.verizon.net ([72.84.113.162] helo=titan) by mho-01-ewr.mailhop.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1Uv9fg-000Ixh-CS; Fri, 05 Jul 2013 17:19:48 +0000 Received: from titan.lakedaemon.net (localhost [127.0.0.1]) by titan (Postfix) with ESMTP id A0C4E45EC48; Fri, 5 Jul 2013 13:19:44 -0400 (EDT) X-Mail-Handler: Dyn Standard SMTP by Dyn X-Originating-IP: 72.84.113.162 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/sendlabs/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX18wXOkNyRVX73rTPGh4UJu5rEtNzt15vmc= Date: Fri, 5 Jul 2013 13:19:44 -0400 From: Jason Cooper To: Andrew Murray Cc: ralf@linux-mips.org, Andrew.Murray@arm.com, monstr@monstr.eu, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, blogic@openwrt.org, ddaney@caviumnetworks.com Subject: Re: of_pci_range_parser patch series Message-ID: <20130705171944.GI2569@titan.lakedaemon.net> References: <20130705132944.GA6417@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130705132944.GA6417@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37269 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jason@lakedaemon.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1022 Lines: 28 On Fri, Jul 05, 2013 at 02:29:44PM +0100, Andrew Murray wrote: > > Andrew, > > > > I noticed that [1] is now in -next but not the MIPS patch [2], not the > > MicroBlaze patch [3]. What is the reason for that? If it's only the > > lack of an ack, here's mine for the MIPS version: > > There was no reason other that the missing acks. This series got held up one release cycle for build failure on powerpc, so we trimmed it down to the essentials that we needed and could confirm didn't break anything. Hence dropping mips and microblaze portions. > > Acked-by: Ralf Baechle > > Thanks for this. > > Jason - is it possible/best to take this through your tree? All the other bits will be in v3.11-rc1. It'd probably be best to go ahead and take it through the linux-mips tree once -rc1 drops. We can take it if you'd like but there really isn't any need to do so. Same goes for the microblaze portion. Just rebase the patch onto -rc1 and send to the appropriate maintainers. hth, Jason. From bhelgaas@google.com Fri Jul 5 23:32:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Jul 2013 23:32:57 +0200 (CEST) Received: from mail-ob0-f182.google.com ([209.85.214.182]:45770 "EHLO mail-ob0-f182.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831921Ab3GEVcjtDZoe (ORCPT ); Fri, 5 Jul 2013 23:32:39 +0200 Received: by mail-ob0-f182.google.com with SMTP id va7so3386224obc.13 for ; Fri, 05 Jul 2013 14:32:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=JIRIoDekTtIYp7Ug4Lx8h8DbSPlsioRgMIIpKQTQWgA=; b=LqfYQj3khTVkRwqI0g8Xvyw1/aRGTl+3FHtZ+G5VgS5jBEG7L2yUc48ErLJgoPF07U qNukr1pc3hLIrs8zSz6viJVIYIO6nKVGXyyGHn3JzSHLlV61j9QgiYyVDk1AxDEGLJye cCgaTZXiEmKTkgpk3ysqbhO7oW04IX89WsBdFnV+UbO9GqN1W7iqQFrTVV8mE2thDUk+ cHNlFTGmbiocvIxbLjZG72U029FiW51Xer9QD03flSdiu5vjG15CRKt/vQIrm7svZd3X H6+ZPEgjpz347ObRyqp3XTyvzRKnyy3HwnPnQMdj3E6hqgMjkRUHIjqtBMABeEx28x8z A+GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=JIRIoDekTtIYp7Ug4Lx8h8DbSPlsioRgMIIpKQTQWgA=; b=ZwwaTepvyDJYexqhwYij27ODBKBSNI4uULhqY6aOBtX/8oBT6xPclzo7cxCi00GTly cEJsaz+ted2d29dC3hRSWh89aeoaZF+8EJ5QvjUxsgO5vWlmkQEGfO5dDHrNZqwkmtOA tap86WW3Av02zDNDJETrsqGRS2F8xGeXJ7Wx7CRaAClOByI4zezyAfNB1cJPJUOFwyrd ijYiJgP+ocV3YsVgayPX0RY4D5ZZHVI4esPsqLOnmQp+P7pWDSjwuHGJ85/xB9j6nyi8 G9kypus9hDKL0iuwtRWFyhhcoYiOTbE9cTPv80GRO9eEqQ8tGtCVUI962BvHdFKHNIgR AS7A== X-Received: by 10.182.213.10 with SMTP id no10mr12796718obc.76.1373059953193; Fri, 05 Jul 2013 14:32:33 -0700 (PDT) MIME-Version: 1.0 Received: by 10.182.75.99 with HTTP; Fri, 5 Jul 2013 14:32:13 -0700 (PDT) In-Reply-To: <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> From: Bjorn Helgaas Date: Fri, 5 Jul 2013 15:32:13 -0600 Message-ID: Subject: Re: [PATCHv4 02/11] pci: use weak functions for MSI arch-specific functions To: Thomas Petazzoni Cc: "linux-pci@vger.kernel.org" , Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Ezequiel Garcia , linux-arm , Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , "x86@kernel.org" , Tony Luck , Fenghua Yu , "linux-ia64@vger.kernel.org" , Ralf Baechle , "linux-mips@linux-mips.org" , "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Content-Type: text/plain; charset=ISO-8859-1 X-Gm-Message-State: ALoCoQkkHBcYglrOGfTyP8jZc2aTs1ODI2Wng2yRNS3bL0K0MT3CmpndNokmrzxupZZcZ1PpTXEhC8txWLV+rF94BFxtLvl1GO33UhxUTQv+/kyiqYCaPd397E1qaVpl+R0Qz05k14kdqOCznR9wTrPixDego99JfewYF25J0ZpPkFYc/EwDuujFoT0EoyM5HMkoQZs8MVEb3kB5GivUpF40QNC2RVh1Vw== Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37270 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 10137 Lines: 283 On Mon, Jul 1, 2013 at 7:42 AM, Thomas Petazzoni wrote: > Until now, the MSI architecture-specific functions could be overloaded > using a fairly complex set of #define and compile-time > conditionals. In order to prepare for the introduction of the msi_chip > infrastructure, it is desirable to switch all those functions to use > the 'weak' mechanism. This commit converts all the architectures that > were overidding those MSI functions to use the new strategy. > > Note that we keep a separate, non-weak, function > default_teardown_msi_irqs() for the default behavior of the > arch_teardown_msi_irqs(), as the default behavior is needed by the Xen > x86 PCI code. > > Signed-off-by: Thomas Petazzoni > Cc: Benjamin Herrenschmidt > Cc: Paul Mackerras > Cc: linuxppc-dev@lists.ozlabs.org > Cc: Martin Schwidefsky > Cc: Heiko Carstens > Cc: linux390@de.ibm.com > Cc: linux-s390@vger.kernel.org > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: H. Peter Anvin > Cc: x86@kernel.org > Cc: Russell King > Cc: Tony Luck > Cc: Fenghua Yu > Cc: linux-ia64@vger.kernel.org > Cc: Ralf Baechle > Cc: linux-mips@linux-mips.org > Cc: David S. Miller > Cc: sparclinux@vger.kernel.org > Cc: Chris Metcalf Acked-by: Bjorn Helgaas > --- > arch/mips/include/asm/pci.h | 5 ----- > arch/powerpc/include/asm/pci.h | 5 ----- > arch/s390/include/asm/pci.h | 4 ---- > arch/x86/include/asm/pci.h | 28 -------------------------- > arch/x86/kernel/x86_init.c | 21 ++++++++++++++++++++ > drivers/pci/msi.c | 45 +++++++++++++++++++----------------------- > include/linux/msi.h | 7 ++++++- > 7 files changed, 47 insertions(+), 68 deletions(-) > > diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h > index b8e24fd..031f4c1 100644 > --- a/arch/mips/include/asm/pci.h > +++ b/arch/mips/include/asm/pci.h > @@ -137,11 +137,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) > return channel ? 15 : 14; > } > > -#ifdef CONFIG_CPU_CAVIUM_OCTEON > -/* MSI arch hook for OCTEON */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#endif > - > extern char * (*pcibios_plat_setup)(char *str); > > #ifdef CONFIG_OF > diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h > index 6653f27..95145a1 100644 > --- a/arch/powerpc/include/asm/pci.h > +++ b/arch/powerpc/include/asm/pci.h > @@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus); > /* Decide whether to display the domain number in /proc */ > extern int pci_proc_domain(struct pci_bus *bus); > > -/* MSI arch hooks */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#define arch_teardown_msi_irqs arch_teardown_msi_irqs > -#define arch_msi_check_device arch_msi_check_device > - > struct vm_area_struct; > /* Map a range of PCI memory or I/O space for a device into user space */ > int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, > diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h > index 6c18012..8641e8d 100644 > --- a/arch/s390/include/asm/pci.h > +++ b/arch/s390/include/asm/pci.h > @@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *); > int pci_domain_nr(struct pci_bus *); > int pci_proc_domain(struct pci_bus *); > > -/* MSI arch hooks */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#define arch_teardown_msi_irqs arch_teardown_msi_irqs > - > #define ZPCI_BUS_NR 0 /* default bus number */ > #define ZPCI_DEVFN 0 /* default device number */ > > diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h > index d9e9e6c..8c61de0 100644 > --- a/arch/x86/include/asm/pci.h > +++ b/arch/x86/include/asm/pci.h > @@ -100,29 +100,6 @@ static inline void early_quirks(void) { } > extern void pci_iommu_alloc(void); > > #ifdef CONFIG_PCI_MSI > -/* MSI arch specific hooks */ > -static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > -{ > - return x86_msi.setup_msi_irqs(dev, nvec, type); > -} > - > -static inline void x86_teardown_msi_irqs(struct pci_dev *dev) > -{ > - x86_msi.teardown_msi_irqs(dev); > -} > - > -static inline void x86_teardown_msi_irq(unsigned int irq) > -{ > - x86_msi.teardown_msi_irq(irq); > -} > -static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq) > -{ > - x86_msi.restore_msi_irqs(dev, irq); > -} > -#define arch_setup_msi_irqs x86_setup_msi_irqs > -#define arch_teardown_msi_irqs x86_teardown_msi_irqs > -#define arch_teardown_msi_irq x86_teardown_msi_irq > -#define arch_restore_msi_irqs x86_restore_msi_irqs > /* implemented in arch/x86/kernel/apic/io_apic. */ > struct msi_desc; > int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); > @@ -130,11 +107,6 @@ void native_teardown_msi_irq(unsigned int irq); > void native_restore_msi_irqs(struct pci_dev *dev, int irq); > int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, > unsigned int irq_base, unsigned int irq_offset); > -/* default to the implementation in drivers/lib/msi.c */ > -#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS > -#define HAVE_DEFAULT_MSI_RESTORE_IRQS > -void default_teardown_msi_irqs(struct pci_dev *dev); > -void default_restore_msi_irqs(struct pci_dev *dev, int irq); > #else > #define native_setup_msi_irqs NULL > #define native_teardown_msi_irq NULL > diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c > index 45a14db..a2b189c 100644 > --- a/arch/x86/kernel/x86_init.c > +++ b/arch/x86/kernel/x86_init.c > @@ -116,6 +116,27 @@ struct x86_msi_ops x86_msi = { > .setup_hpet_msi = default_setup_hpet_msi, > }; > > +/* MSI arch specific hooks */ > +int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > +{ > + return x86_msi.setup_msi_irqs(dev, nvec, type); > +} > + > +void arch_teardown_msi_irqs(struct pci_dev *dev) > +{ > + x86_msi.teardown_msi_irqs(dev); > +} > + > +void arch_teardown_msi_irq(unsigned int irq) > +{ > + x86_msi.teardown_msi_irq(irq); > +} > + > +void arch_restore_msi_irqs(struct pci_dev *dev, int irq) > +{ > + x86_msi.restore_msi_irqs(dev, irq); > +} > + > struct x86_io_apic_ops x86_io_apic_ops = { > .init = native_io_apic_init_mappings, > .read = native_io_apic_read, > diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c > index 2c10752..289fbfd 100644 > --- a/drivers/pci/msi.c > +++ b/drivers/pci/msi.c > @@ -30,20 +30,21 @@ static int pci_msi_enable = 1; > > /* Arch hooks */ > > -#ifndef arch_msi_check_device > -int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) > +int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) > { > - return 0; > + return -EINVAL; > } > -#endif > > -#ifndef arch_setup_msi_irqs > -# define arch_setup_msi_irqs default_setup_msi_irqs > -# define HAVE_DEFAULT_MSI_SETUP_IRQS > -#endif > +void __weak arch_teardown_msi_irq(unsigned int irq) > +{ > +} > > -#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS > -int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > +int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) > +{ > + return 0; > +} > + > +int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > { > struct msi_desc *entry; > int ret; > @@ -65,14 +66,11 @@ int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > > return 0; > } > -#endif > > -#ifndef arch_teardown_msi_irqs > -# define arch_teardown_msi_irqs default_teardown_msi_irqs > -# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS > -#endif > - > -#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS > +/* > + * We have a default implementation available as a separate non-weak > + * function, as it is used by the Xen x86 PCI code > + */ > void default_teardown_msi_irqs(struct pci_dev *dev) > { > struct msi_desc *entry; > @@ -86,15 +84,13 @@ void default_teardown_msi_irqs(struct pci_dev *dev) > arch_teardown_msi_irq(entry->irq + i); > } > } > -#endif > > -#ifndef arch_restore_msi_irqs > -# define arch_restore_msi_irqs default_restore_msi_irqs > -# define HAVE_DEFAULT_MSI_RESTORE_IRQS > -#endif > +void __weak arch_teardown_msi_irqs(struct pci_dev *dev) > +{ > + return default_teardown_msi_irqs(dev); > +} > > -#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS > -void default_restore_msi_irqs(struct pci_dev *dev, int irq) > +void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq) > { > struct msi_desc *entry; > > @@ -111,7 +107,6 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq) > if (entry) > write_msi_msg(irq, &entry->msg); > } > -#endif > > static void msi_set_enable(struct pci_dev *dev, int enable) > { > diff --git a/include/linux/msi.h b/include/linux/msi.h > index 20c2d6d..c82ff8d 100644 > --- a/include/linux/msi.h > +++ b/include/linux/msi.h > @@ -50,12 +50,17 @@ struct msi_desc { > }; > > /* > - * The arch hook for setup up msi irqs > + * The arch hooks to setup up msi irqs. Those functions are > + * implemented as weak symbols so that they /can/ be overriden by > + * architecture specific code if needed. > */ > int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); > void arch_teardown_msi_irq(unsigned int irq); > int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); > void arch_teardown_msi_irqs(struct pci_dev *dev); > int arch_msi_check_device(struct pci_dev* dev, int nvec, int type); > +void arch_restore_msi_irqs(struct pci_dev *dev, int irq); > + > +void default_teardown_msi_irqs(struct pci_dev *dev); > > #endif /* LINUX_MSI_H */ > -- > 1.8.1.2 > From bhelgaas@google.com Fri Jul 5 23:34:37 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Jul 2013 23:34:52 +0200 (CEST) Received: from mail-ob0-f179.google.com ([209.85.214.179]:55907 "EHLO mail-ob0-f179.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831921Ab3GEVeg5FL4- (ORCPT ); Fri, 5 Jul 2013 23:34:36 +0200 Received: by mail-ob0-f179.google.com with SMTP id xk17so3320449obc.24 for ; Fri, 05 Jul 2013 14:34:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=z8ktEPWiS70Fe9fzHy32EAbCfrdP9R5wn7O1PbImyJA=; b=nX/u5jdTp5FF3R65A4s6veFDnlhzLwLk9sVdzabJ7E3rtFKGjTUsqBEyFZsnf+WkiB AXfDxq4pPAlCu2fdVFTr/psbU0SiFF6X0V+hvGBX4WwNs0yWJiJh4kd4zDtv0x1+Oci0 C6MXvGOSqrUBO64hfFoCSeARomHWOZKaATebd8y7KXazry3c0AMDqjV2sAJSReMe1sxT TpSOcvDMSo6wC/7tqzWi+5B0koG//3Cy9IJtRDuus6jS73rixVuE2Jpyuv0xWp6nT51f kZgzz75muSV8a+CvZ6GYOTO3ESKk6P9EWFcSGGAdHBTDGUkUApjS8xfCevGR1eQhSP8J QWWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=z8ktEPWiS70Fe9fzHy32EAbCfrdP9R5wn7O1PbImyJA=; b=loa+4s7YjTySEZ+8ri0891GHxY2e2xdnw85J1TQptF/VToNNTdnbaQJwH1ZTb+0Gbz PX+uOFEe0lBzw3+eC7kmarjhQHOcUaqXUvn1VaX5Nuc7faFr+VN5bZDUHbdetPy6xYqV lFnmVDBKlHGsP4Ag+83nC8y2HU3QZWlM+9YXAhjC9pMQHoxUnWa2UwTiOsfC4PJy2/+n zbtDPgcHi1KUVZKKFnhwXZ8EN9Vzg0pIbqFffbpN98qXyXDxTiE2t6teuWmZLYiuyKjO W0tz5I5d8QuPp1vUvNtMoWsWtGR3q0S8kJDSdSMIHiKJkSTH6GfLF+7bRZ5PSLIKdYC3 xakQ== X-Received: by 10.182.186.66 with SMTP id fi2mr13053453obc.98.1373060070614; Fri, 05 Jul 2013 14:34:30 -0700 (PDT) MIME-Version: 1.0 Received: by 10.182.75.99 with HTTP; Fri, 5 Jul 2013 14:34:10 -0700 (PDT) In-Reply-To: References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> From: Bjorn Helgaas Date: Fri, 5 Jul 2013 15:34:10 -0600 Message-ID: Subject: Re: [PATCHv4 02/11] pci: use weak functions for MSI arch-specific functions To: Thomas Petazzoni Cc: "linux-pci@vger.kernel.org" , Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Ezequiel Garcia , linux-arm , Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , "x86@kernel.org" , Tony Luck , Fenghua Yu , "linux-ia64@vger.kernel.org" , Ralf Baechle , "linux-mips@linux-mips.org" , "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Content-Type: text/plain; charset=ISO-8859-1 X-Gm-Message-State: ALoCoQnYSi5iSRNDygkfjwrv8fq9sc1mivkCQ+h0Fo95qknCcAJJx2CCfUFgja/PVbhREUzSSlsDVT4eDTYevXjDR7uPfjQzP7B5EPAztkoUx6UJa0CvROZ/1a7cDnOiKxVRomAGeMjrCdEZU6r8sZ8KeQpzl7eJ/SLh+og08iiha972BVIgsndrM+frN/iUPLl4aD8Yd4qumRDcQcPbBw6t3jonUFoEGQ== Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37271 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 220 Lines: 7 On Fri, Jul 5, 2013 at 3:32 PM, Bjorn Helgaas wrote: > Acked-by: Bjorn Helgaas But please update your subject line to use consistent capitalization, e.g., PCI: Use weak ... From thomas.petazzoni@free-electrons.com Fri Jul 5 23:40:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Jul 2013 23:41:03 +0200 (CEST) Received: from mail.free-electrons.com ([94.23.35.102]:33453 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831921Ab3GEVkm4MdQI (ORCPT ); Fri, 5 Jul 2013 23:40:42 +0200 Received: by mail.free-electrons.com (Postfix, from userid 106) id 81C89BAB; Fri, 5 Jul 2013 23:40:35 +0200 (CEST) Received: from skate (AToulouse-651-1-103-169.w109-222.abo.wanadoo.fr [109.222.70.169]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1B1B07B6; Fri, 5 Jul 2013 23:40:34 +0200 (CEST) Date: Fri, 5 Jul 2013 23:40:34 +0200 From: Thomas Petazzoni To: Bjorn Helgaas Cc: "linux-pci@vger.kernel.org" , Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Ezequiel Garcia , linux-arm , Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , "x86@kernel.org" , Tony Luck , Fenghua Yu , "linux-ia64@vger.kernel.org" , Ralf Baechle , "linux-mips@linux-mips.org" , "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Subject: Re: [PATCHv4 02/11] pci: use weak functions for MSI arch-specific functions Message-ID: <20130705234034.6c57cd43@skate> In-Reply-To: References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-3-git-send-email-thomas.petazzoni@free-electrons.com> Organization: Free Electrons X-Mailer: Claws Mail 3.9.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37272 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 641 Lines: 25 Dear Bjorn Helgaas, On Fri, 5 Jul 2013 15:34:10 -0600, Bjorn Helgaas wrote: > On Fri, Jul 5, 2013 at 3:32 PM, Bjorn Helgaas wrote: > > > Acked-by: Bjorn Helgaas > > But please update your subject line to use consistent capitalization, e.g., > > PCI: Use weak ... Sure, will do. Would it be possible to get Tested-by and/or Acked-by from the different architecture maintainers affected by PATCH 02/11 and PATCH 03/11 ? Thanks, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com From thomas.petazzoni@free-electrons.com Fri Jul 5 23:45:09 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Jul 2013 23:45:17 +0200 (CEST) Received: from mail.free-electrons.com ([94.23.35.102]:33662 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835018Ab3GEVpJRMC8M (ORCPT ); Fri, 5 Jul 2013 23:45:09 +0200 Received: by mail.free-electrons.com (Postfix, from userid 106) id 2E2397D2; Fri, 5 Jul 2013 23:45:02 +0200 (CEST) Received: from skate (AToulouse-651-1-103-169.w109-222.abo.wanadoo.fr [109.222.70.169]) by mail.free-electrons.com (Postfix) with ESMTPSA id 002037BF; Fri, 5 Jul 2013 23:45:00 +0200 (CEST) Date: Fri, 5 Jul 2013 23:45:01 +0200 From: Thomas Petazzoni To: Bjorn Helgaas Cc: "linux-pci@vger.kernel.org" , Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Ezequiel Garcia , linux-arm , Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , "x86@kernel.org" , Tony Luck , Fenghua Yu , "linux-ia64@vger.kernel.org" , Ralf Baechle , "linux-mips@linux-mips.org" , "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Subject: Re: [PATCHv4 03/11] pci: remove ARCH_SUPPORTS_MSI kconfig option Message-ID: <20130705234501.1341f52e@skate> In-Reply-To: References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-4-git-send-email-thomas.petazzoni@free-electrons.com> Organization: Free Electrons X-Mailer: Claws Mail 3.9.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37273 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 838 Lines: 25 Dear Bjorn Helgaas, On Fri, 5 Jul 2013 15:37:33 -0600, Bjorn Helgaas wrote: > Acked-by: Bjorn Helgaas > > Again, please update the subject line to "PCI: Remove ..." > > I doubt that you'll get explicit acks from all the arches you touched, > but I think it's reasonable to put at least patches 2 & 3 in -next > soon after v3.11-rc1, so we should have time to shake out issues. Sure. Which merge strategy do you suggest for this patch series, which touches a number of different areas, and has some build-time dependencies between the patches (if needed, I can detail those build time dependencies to help figuring out the best strategy). Thanks, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com From jason@lakedaemon.net Sat Jul 6 15:54:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Jul 2013 15:54:57 +0200 (CEST) Received: from mho-03-ewr.mailhop.org ([204.13.248.66]:23948 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6817419Ab3GFNyzD0xAE (ORCPT ); Sat, 6 Jul 2013 15:54:55 +0200 Received: from pool-72-84-113-162.nrflva.fios.verizon.net ([72.84.113.162] helo=titan) by mho-01-ewr.mailhop.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1UvSwk-000DfJ-US; Sat, 06 Jul 2013 13:54:42 +0000 Received: from titan.lakedaemon.net (localhost [127.0.0.1]) by titan (Postfix) with ESMTP id BA88945F529; Sat, 6 Jul 2013 09:54:33 -0400 (EDT) X-Mail-Handler: Dyn Standard SMTP by Dyn X-Originating-IP: 72.84.113.162 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/sendlabs/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX180+krwpg+c/bjrcZ7VudixnPD3IILOvY0= Date: Sat, 6 Jul 2013 09:54:33 -0400 From: Jason Cooper To: Thomas Petazzoni Cc: Bjorn Helgaas , Lior Amsalem , Andrew Lunn , "linux-ia64@vger.kernel.org" , "linux-mips@linux-mips.org" , "linux-pci@vger.kernel.org" , Heiko Carstens , Grant Likely , Thierry Reding , Paul Mackerras , "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, Russell King , "x86@kernel.org" , Ingo Molnar , Ezequiel Garcia , Benjamin Herrenschmidt , Fenghua Yu , Rob Herring , Chris Metcalf , Gregory Clement , Thomas Gleixner , linux-arm , Tony Luck , Ralf Baechle , Maen Suleiman , Martin Schwidefsky , linux390@de.ibm.com, linuxppc-dev , "David S. Miller" Subject: Re: [PATCHv4 03/11] pci: remove ARCH_SUPPORTS_MSI kconfig option Message-ID: <20130706135433.GL2569@titan.lakedaemon.net> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-4-git-send-email-thomas.petazzoni@free-electrons.com> <20130705234501.1341f52e@skate> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130705234501.1341f52e@skate> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37274 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jason@lakedaemon.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 960 Lines: 25 On Fri, Jul 05, 2013 at 11:45:01PM +0200, Thomas Petazzoni wrote: > Dear Bjorn Helgaas, > > On Fri, 5 Jul 2013 15:37:33 -0600, Bjorn Helgaas wrote: > > > Acked-by: Bjorn Helgaas > > > > Again, please update the subject line to "PCI: Remove ..." > > > > I doubt that you'll get explicit acks from all the arches you touched, > > but I think it's reasonable to put at least patches 2 & 3 in -next > > soon after v3.11-rc1, so we should have time to shake out issues. > > Sure. Which merge strategy do you suggest for this patch series, which > touches a number of different areas, and has some build-time > dependencies between the patches (if needed, I can detail those build > time dependencies to help figuring out the best strategy). If we end up handling this the same as the of/pci & mvebu-pcie series (whole series through mvebu -> arm-soc) I can have it up in -next within a few days of -rc1. Just let me know. hth, Jason. From bhelgaas@google.com Sat Jul 6 17:41:22 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Jul 2013 17:41:24 +0200 (CEST) Received: from mail-ob0-f182.google.com ([209.85.214.182]:39338 "EHLO mail-ob0-f182.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823081Ab3GFPlVzPhA9 (ORCPT ); Sat, 6 Jul 2013 17:41:21 +0200 Received: by mail-ob0-f182.google.com with SMTP id va7so4042116obc.27 for ; Sat, 06 Jul 2013 08:41:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=/uyHRuK5L8fmDukxCJcyPWToHS124B0Q3+hrMl4YGUM=; b=OnAPippALWPuszXthIIJTvFQMyvO9v4N81IgbLwCiEMR4xQdgi/qTaWzhUVS0e+eOT MsR/sUXwoe0f/a3K56nx4vVVBN1PwQgkEn/sLMe83zGjxSlO7wjJBPn9pcnDC282arY5 TA4r2zvnOJEp6IpalnJ5UGws8mOepVtTD6E7zq/DpphJdngpqXFNNLzVm/Bh1jCoVD2I YLpwQoj6zZn6XMIhIEwSWoSGpsN1rShQS9HeJrQil/GbJsZSF3E4Jt1ZURxOt7dMaLom m+kgW+IEbDThdyrgyf4MJCwqLtzD0FdphOyZ9NnEEbbgnFNtyybfqif6ByO7XeqNka7L 918g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=/uyHRuK5L8fmDukxCJcyPWToHS124B0Q3+hrMl4YGUM=; b=IyTdDTmzsynlzUQGl/KYEepumtspBE/vVM2CCxO6bYxceMaWjvY1vabHmQ0gpvfT8Y w/bHPaEr3M6/3eT1YiXau3+5vLR+HokKbQljNfHmetERsSSEPKTS1HM0gKvbJUqjuldb JPbR8xPsvAa5PDtH42tM11uHgl4Mmr8EhBW31RHiymLuUzuqshHIjIEZPib+vbjkyPrQ zkMr0J4imuWQ4PY7kEkA4PGN3GOPhoyWSung8qxwNjPgyDLqOW2ajyGhuuViM8y/5PJ0 zsKZKTRgt+SK/m6oqxDu8ciNch0TitXZUIr2vaGZNZaRHgaPHS880/NFVbU2cnNAX/Aw iK+Q== X-Received: by 10.182.87.170 with SMTP id az10mr15589798obb.10.1373125275397; Sat, 06 Jul 2013 08:41:15 -0700 (PDT) MIME-Version: 1.0 Received: by 10.182.75.99 with HTTP; Sat, 6 Jul 2013 08:40:55 -0700 (PDT) In-Reply-To: <20130706135433.GL2569@titan.lakedaemon.net> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-4-git-send-email-thomas.petazzoni@free-electrons.com> <20130705234501.1341f52e@skate> <20130706135433.GL2569@titan.lakedaemon.net> From: Bjorn Helgaas Date: Sat, 6 Jul 2013 09:40:55 -0600 Message-ID: Subject: Re: [PATCHv4 03/11] pci: remove ARCH_SUPPORTS_MSI kconfig option To: Jason Cooper Cc: Thomas Petazzoni , Lior Amsalem , Andrew Lunn , "linux-ia64@vger.kernel.org" , "linux-mips@linux-mips.org" , "linux-pci@vger.kernel.org" , Heiko Carstens , Grant Likely , Thierry Reding , Paul Mackerras , "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, Russell King , "x86@kernel.org" , Ingo Molnar , Ezequiel Garcia , Benjamin Herrenschmidt , Fenghua Yu , Rob Herring , Chris Metcalf , Gregory Clement , Thomas Gleixner , linux-arm , Tony Luck , Ralf Baechle , Maen Suleiman , Martin Schwidefsky , linux390@de.ibm.com, linuxppc-dev , "David S. Miller" Content-Type: text/plain; charset=ISO-8859-1 X-Gm-Message-State: ALoCoQl4saGmYFgdAlF7y6LJjtOVD9SexV2iUjGxDxJbZZhK8HrsFqV6eFAHl2WJre8aKz10358qKLz6WZo2eQlewxOsVz30dySb9Oy4b8ypl4PGnR2k+XewcwOVV6saqEFaHD1YkR+P5+5lr70ynjwgLm61Nzh1uhfnWrE7s6FFFRpO+EsU6dXL3TF2+BDx5YVUsRwHfCWZ7XCzTM0Hg8MiKwQQUcLCYg== Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37275 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1195 Lines: 26 On Sat, Jul 6, 2013 at 7:54 AM, Jason Cooper wrote: > On Fri, Jul 05, 2013 at 11:45:01PM +0200, Thomas Petazzoni wrote: >> Dear Bjorn Helgaas, >> >> On Fri, 5 Jul 2013 15:37:33 -0600, Bjorn Helgaas wrote: >> >> > Acked-by: Bjorn Helgaas >> > >> > Again, please update the subject line to "PCI: Remove ..." >> > >> > I doubt that you'll get explicit acks from all the arches you touched, >> > but I think it's reasonable to put at least patches 2 & 3 in -next >> > soon after v3.11-rc1, so we should have time to shake out issues. >> >> Sure. Which merge strategy do you suggest for this patch series, which >> touches a number of different areas, and has some build-time >> dependencies between the patches (if needed, I can detail those build >> time dependencies to help figuring out the best strategy). > > If we end up handling this the same as the of/pci & mvebu-pcie series > (whole series through mvebu -> arm-soc) I can have it up in -next within > a few days of -rc1. Just let me know. That sounds fine with me. I don't think it's worth trying to split out the drivers/pci stuff and trying to coordinate it going through different trees. From jason@lakedaemon.net Sat Jul 6 18:18:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Jul 2013 18:18:06 +0200 (CEST) Received: from mho-03-ewr.mailhop.org ([204.13.248.66]:43516 "EHLO mho-01-ewr.mailhop.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6817419Ab3GFQSE57O3Y (ORCPT ); Sat, 6 Jul 2013 18:18:04 +0200 Received: from pool-72-84-113-162.nrflva.fios.verizon.net ([72.84.113.162] helo=titan) by mho-01-ewr.mailhop.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1UvVBH-0008Cn-11; Sat, 06 Jul 2013 16:17:51 +0000 Received: from titan.lakedaemon.net (localhost [127.0.0.1]) by titan (Postfix) with ESMTP id 4F1B645F64F; Sat, 6 Jul 2013 12:17:43 -0400 (EDT) X-Mail-Handler: Dyn Standard SMTP by Dyn X-Originating-IP: 72.84.113.162 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/sendlabs/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX1+2OC/xE6UIElSscpZbWdcHGfw5Q4UAc70= Date: Sat, 6 Jul 2013 12:17:43 -0400 From: Jason Cooper To: Bjorn Helgaas Cc: Lior Amsalem , "linux-mips@linux-mips.org" , "linux-ia64@vger.kernel.org" , Andrew Lunn , "linux-pci@vger.kernel.org" , Heiko Carstens , Grant Likely , Thierry Reding , Paul Mackerras , "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, Russell King , "x86@kernel.org" , Ingo Molnar , Ezequiel Garcia , Benjamin Herrenschmidt , Fenghua Yu , Chris Metcalf , Rob Herring , Gregory Clement , Thomas Gleixner , linux-arm , Thomas Petazzoni , Tony Luck , Ralf Baechle , Maen Suleiman , Martin Schwidefsky , linux390@de.ibm.com, linuxppc-dev , "David S. Miller" Subject: Re: [PATCHv4 03/11] pci: remove ARCH_SUPPORTS_MSI kconfig option Message-ID: <20130706161743.GM2569@titan.lakedaemon.net> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-4-git-send-email-thomas.petazzoni@free-electrons.com> <20130705234501.1341f52e@skate> <20130706135433.GL2569@titan.lakedaemon.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37276 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jason@lakedaemon.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1421 Lines: 36 On Sat, Jul 06, 2013 at 09:40:55AM -0600, Bjorn Helgaas wrote: > On Sat, Jul 6, 2013 at 7:54 AM, Jason Cooper wrote: > > On Fri, Jul 05, 2013 at 11:45:01PM +0200, Thomas Petazzoni wrote: > >> Dear Bjorn Helgaas, > >> > >> On Fri, 5 Jul 2013 15:37:33 -0600, Bjorn Helgaas wrote: > >> > >> > Acked-by: Bjorn Helgaas > >> > > >> > Again, please update the subject line to "PCI: Remove ..." > >> > > >> > I doubt that you'll get explicit acks from all the arches you touched, > >> > but I think it's reasonable to put at least patches 2 & 3 in -next > >> > soon after v3.11-rc1, so we should have time to shake out issues. > >> > >> Sure. Which merge strategy do you suggest for this patch series, which > >> touches a number of different areas, and has some build-time > >> dependencies between the patches (if needed, I can detail those build > >> time dependencies to help figuring out the best strategy). > > > > If we end up handling this the same as the of/pci & mvebu-pcie series > > (whole series through mvebu -> arm-soc) I can have it up in -next within > > a few days of -rc1. Just let me know. > > That sounds fine with me. I don't think it's worth trying to split > out the drivers/pci stuff and trying to coordinate it going through > different trees. Ok, will do. Thomas, I assume there will be one more version to address Bjorn's last comments? thx, Jason. From thomas.petazzoni@free-electrons.com Sat Jul 6 18:33:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Jul 2013 18:33:53 +0200 (CEST) Received: from mail.free-electrons.com ([94.23.35.102]:35920 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823081Ab3GFQduherT8 (ORCPT ); Sat, 6 Jul 2013 18:33:50 +0200 Received: by mail.free-electrons.com (Postfix, from userid 106) id 150047D2; Sat, 6 Jul 2013 18:33:43 +0200 (CEST) Received: from skate (AToulouse-651-1-103-169.w109-222.abo.wanadoo.fr [109.222.70.169]) by mail.free-electrons.com (Postfix) with ESMTPSA id C0ED57A6; Sat, 6 Jul 2013 18:33:41 +0200 (CEST) Date: Sat, 6 Jul 2013 18:33:41 +0200 From: Thomas Petazzoni To: Jason Cooper Cc: Bjorn Helgaas , Lior Amsalem , "linux-mips@linux-mips.org" , "linux-ia64@vger.kernel.org" , Andrew Lunn , "linux-pci@vger.kernel.org" , Heiko Carstens , Grant Likely , Thierry Reding , Paul Mackerras , "H. Peter Anvin" , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, Russell King , "x86@kernel.org" , Ingo Molnar , Ezequiel Garcia , Benjamin Herrenschmidt , Fenghua Yu , Chris Metcalf , Rob Herring , Gregory Clement , Thomas Gleixner , linux-arm , Tony Luck , Ralf Baechle , Maen Suleiman , Martin Schwidefsky , linux390@de.ibm.com, linuxppc-dev , "David S. Miller" Subject: Re: [PATCHv4 03/11] pci: remove ARCH_SUPPORTS_MSI kconfig option Message-ID: <20130706183341.379d2fea@skate> In-Reply-To: <20130706161743.GM2569@titan.lakedaemon.net> References: <1372686136-1370-1-git-send-email-thomas.petazzoni@free-electrons.com> <1372686136-1370-4-git-send-email-thomas.petazzoni@free-electrons.com> <20130705234501.1341f52e@skate> <20130706135433.GL2569@titan.lakedaemon.net> <20130706161743.GM2569@titan.lakedaemon.net> Organization: Free Electrons X-Mailer: Claws Mail 3.9.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37277 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 910 Lines: 29 Dear Jason Cooper, On Sat, 6 Jul 2013 12:17:43 -0400, Jason Cooper wrote: > > > If we end up handling this the same as the of/pci & mvebu-pcie series > > > (whole series through mvebu -> arm-soc) I can have it up in -next within > > > a few days of -rc1. Just let me know. > > > > That sounds fine with me. I don't think it's worth trying to split > > out the drivers/pci stuff and trying to coordinate it going through > > different trees. > > Ok, will do. > > Thomas, I assume there will be one more version to address Bjorn's last > comments? Yes, indeed. I was waiting to see if Thierry Redding would give some additional feedback on Bjorn's comment, but if he doesn't, I'll resend an updated version, most likely next week. Thanks! Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com From Markos.Chandras@imgtec.com Tue Jul 9 10:21:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Jul 2013 10:21:56 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:33660 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835021Ab3GIIVzPPDe0 (ORCPT ); Tue, 9 Jul 2013 10:21:55 +0200 From: Markos Chandras To: CC: Markos Chandras Subject: [PATCH] MIPS: pnx833x: PNX8335_PCI_ETHERNET_INT depends on CONFIG_SOC_PNX8335 Date: Tue, 9 Jul 2013 09:21:35 +0100 Message-ID: <1373358095-14213-1-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 1.8.2.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.58] X-SEF-Processed: 7_3_0_01192__2013_07_09_09_21_49 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37279 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1069 Lines: 37 The PNX8335_PCI_ETHERNET_INT macro is defined in arch/mips/include/asm/mach-pnx833x/irq-mapping.h only if CONFIG_SOC_PNX8335 is selected. Fixes the following randconfig problem: arch/mips/pnx833x/common/platform.c:210:12: error: 'PNX8335_PIC_ETHERNET_INT' undeclared here (not in a function) Signed-off-by: Markos Chandras Acked-by: Steven J. Hill --- arch/mips/pnx833x/common/platform.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/pnx833x/common/platform.c b/arch/mips/pnx833x/common/platform.c index d22dc0d..2b7e837 100644 --- a/arch/mips/pnx833x/common/platform.c +++ b/arch/mips/pnx833x/common/platform.c @@ -206,11 +206,13 @@ static struct resource pnx833x_ethernet_resources[] = { .end = PNX8335_IP3902_PORTS_END, .flags = IORESOURCE_MEM, }, +#ifdef CONFIG_SOC_PNX8335 [1] = { .start = PNX8335_PIC_ETHERNET_INT, .end = PNX8335_PIC_ETHERNET_INT, .flags = IORESOURCE_IRQ, }, +#endif }; static struct platform_device pnx833x_ethernet_device = { -- 1.8.2.1 From mcdonald.shane@gmail.com Tue Jul 9 17:57:26 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Jul 2013 18:00:51 +0200 (CEST) Received: from mail-we0-f177.google.com ([74.125.82.177]:39639 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835062Ab3GIP50qCLe8 (ORCPT ); Tue, 9 Jul 2013 17:57:26 +0200 Received: by mail-we0-f177.google.com with SMTP id m19so4882509wev.36 for ; Tue, 09 Jul 2013 08:57:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=q0ZrjRVC7hPJCfYOMoGy8oJxB+9d3t5ADCJ5Kzc+j1k=; b=Kqjctxjfm7Cf/ykFmlalqpNPpbf/81OGydJzGhm+vMsWa9bY/cYKBoA/2ZG+cctxwF We17WLVag/uVTXPffNxZq7HBxEsNJvSj8okWdXb0fiCfeYfSUE6oN97KIPLiGWBZNUop RUs8yykS7stHsStPyRw2VcJWr25Zvuv5mF0+iKYigX7DdLTRggER40Tr0cHgFyC6atd2 ftJsmNqDWGoHHeCkxcwZm4juv6aU8hwDnzPBldHJhhlb2nzU3V37v9C6GRmESmtjtu2t E1BEjFWses0Ho8F67R0BGv6QwLHamlamSf3n5hIGv0s9gvVi4z8ID6/0TH7X43VYPkUg 28Ig== MIME-Version: 1.0 X-Received: by 10.194.119.228 with SMTP id kx4mr15311696wjb.33.1373385441392; Tue, 09 Jul 2013 08:57:21 -0700 (PDT) Received: by 10.194.1.131 with HTTP; Tue, 9 Jul 2013 08:57:21 -0700 (PDT) In-Reply-To: <20130627144707.GE10727@linux-mips.org> References: <20130627143439.GD10727@linux-mips.org> <20130627144707.GE10727@linux-mips.org> Date: Tue, 9 Jul 2013 09:57:21 -0600 Message-ID: Subject: Re: Pending PMC-Sierra MSP patches From: Shane McDonald To: Ralf Baechle Cc: "linux-mips@linux-mips.org" , Adam Kiepul , "Anoop P.A." Content-Type: multipart/alternative; boundary=089e012292e25fc4ed04e1163719 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37280 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2415 Lines: 62 --089e012292e25fc4ed04e1163719 Content-Type: text/plain; charset=ISO-8859-1 On Thursday, June 27, 2013, Ralf Baechle wrote: > Resendig with a few people who might be interested (or know somebody > who might be) added to cc. > > On Thu, Jun 27, 2013 at 04:34:39PM +0200, Ralf Baechle wrote: > > There is still a fair number of patches for the PMC-Sierra MSP series > > of platforms pending. Those patches being over two years old are > > fairly stale by now so I wonder if somebody with interest in the > > platform could review, respin and test the patches? > > > > The patches in question are can be found in patchwork at > > > > > http://patchwork.linux-mips.org/project/linux-mips/list/?submitter=413&archive=true > > Ralf > I've forwarded this email on to internal contacts at PMC-Sierra, but it appears there is little PMC activity on this platform. Feel free to drop the patches; if I find a need for them, I can respin and resubmit. Shane --089e012292e25fc4ed04e1163719 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

On Thursday, June 27, 2013, Ralf Baechle wrote:
Resendig with a few people who might be interested (or= know somebody
who might be) added to cc.

On Thu, Jun 27, 2013 at 04:34:39PM +0200, Ralf Baechle wrote:
> There is still a fair number of patches for the PMC-Sierra MSP series<= br> > of platforms pending. =A0Those patches being over two years old are > fairly stale by now so I wonder if somebody with interest in the
> platform could review, respin and test the patches?
>
> The patches in question are can be found in patchwork at
>
> =A0 =A0http://patchwork= .linux-mips.org/project/linux-mips/list/?submitter=3D413&archive=3Dtrue=

=A0 Ralf

I've forwarded this email on to intern= al contacts at PMC-Sierra, but it appears there is little PMC= =A0activity on this platform. Feel free to drop the patches; if I find a ne= ed for them, I can respin and resubmit.

Shane=A0
--089e012292e25fc4ed04e1163719-- From ralf@linux-mips.org Tue Jul 9 18:29:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Jul 2013 18:29:45 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:59526 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6835076Ab3GIQ3lYs80T (ORCPT ); Tue, 9 Jul 2013 18:29:41 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r69GTaYX026466; Tue, 9 Jul 2013 18:29:36 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r69GTZWI026465; Tue, 9 Jul 2013 18:29:35 +0200 Date: Tue, 9 Jul 2013 18:29:35 +0200 From: Ralf Baechle To: Shane McDonald Cc: "linux-mips@linux-mips.org" , Adam Kiepul , "Anoop P.A." Subject: Re: Pending PMC-Sierra MSP patches Message-ID: <20130709162935.GD24481@linux-mips.org> References: <20130627143439.GD10727@linux-mips.org> <20130627144707.GE10727@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37281 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1143 Lines: 31 On Tue, Jul 09, 2013 at 09:57:21AM -0600, Shane McDonald wrote: > On Thursday, June 27, 2013, Ralf Baechle wrote: > > > Resendig with a few people who might be interested (or know somebody > > who might be) added to cc. > > > > On Thu, Jun 27, 2013 at 04:34:39PM +0200, Ralf Baechle wrote: > > > There is still a fair number of patches for the PMC-Sierra MSP series > > > of platforms pending. Those patches being over two years old are > > > fairly stale by now so I wonder if somebody with interest in the > > > platform could review, respin and test the patches? > > > > > > The patches in question are can be found in patchwork at > > > > > > > > http://patchwork.linux-mips.org/project/linux-mips/list/?submitter=413&archive=true > > > > Ralf > > > > I've forwarded this email on to internal contacts at PMC-Sierra, but it > appears there is little PMC activity on this platform. Feel free to drop > the patches; if I find a need for them, I can respin and resubmit. Ok, I'm going to drop the patches then. The patches will remain accessible under http://patchwork.linux-mips.org/user/bundle/130/?state=*&archive=both Ralf From chenhuacai@gmail.com Thu Jul 11 11:32:03 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Jul 2013 11:32:16 +0200 (CEST) Received: from mail-bk0-f42.google.com ([209.85.214.42]:56660 "EHLO mail-bk0-f42.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816671Ab3GKJcDiPWO0 (ORCPT ); Thu, 11 Jul 2013 11:32:03 +0200 Received: by mail-bk0-f42.google.com with SMTP id jk13so3248911bkc.1 for ; Thu, 11 Jul 2013 02:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=B8+9cOeZ1wAZ5i59esQ3jDFF4jPQvUMXkv/lLEewQAc=; b=Kb2WLPZGFoYLBU/r7JyUiEZaeaxcECVreg7O7Ze3nrXSf8SEC0n3Q4ni+Q08UqOBqC SxP3iSvIhxcB95fPxqpMV5tgdQCU19s1OfelaDHEseksvTxSis8kisGNYbOqp5hdMiEc 4rYZE5FumLTKes0hBBiYLdMHVbJ5dUUtiSCiSGeQ4j90IoZ60UTe3Ua0SRfyCmj9McC2 6GAB6PwBH3tTJHJjETPdi1lbfSSb+GvRtmu9xZIUggqG9x6hJ/6H2eQSbkU8B7eSq70R oSihE+wI2Pahu+PmwLPz6UkQEmSE9d0XsYkDXGSsPHXTXnSMwETnXqxRUr6BtydXYLyd FUEQ== MIME-Version: 1.0 X-Received: by 10.205.9.129 with SMTP id ow1mr5437355bkb.43.1373535118076; Thu, 11 Jul 2013 02:31:58 -0700 (PDT) Received: by 10.204.73.1 with HTTP; Thu, 11 Jul 2013 02:31:58 -0700 (PDT) In-Reply-To: <20130628070829.GJ10727@linux-mips.org> References: <1366030028-5084-1-git-send-email-chenhc@lemote.com> <1366030028-5084-13-git-send-email-chenhc@lemote.com> <20130628070553.GI10727@linux-mips.org> <20130628070829.GJ10727@linux-mips.org> Date: Thu, 11 Jul 2013 17:31:58 +0800 X-Google-Sender-Auth: 7v7trgsqTHccDaak4it5ztL9IZU Message-ID: Subject: Re: [PATCH V10 12/13] MIPS: Loongson 3: Add CPU hotplug support From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Hongliang Tao , Hua Yan Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37282 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 615 Lines: 16 Normal labels and nops can be removed, but loongson3_play_dead() should be run at CKSEG0, I'm afraid that it will have a wrong behavior if I write it with C. On Fri, Jun 28, 2013 at 3:08 PM, Ralf Baechle wrote: > On Fri, Jun 28, 2013 at 09:05:53AM +0200, Ralf Baechle wrote: > >> > + "flush_loop: \n" /* flush L1 */ >> >> Please don't use normale in inline assembler. This might result in build >> errors. it's horrible to read but number local labels like: > > That was meant to read "Please don't use normal labels" in inline assembler. > > Ralf > From zhangfx@lemote.com Thu Jul 11 14:35:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Jul 2013 14:35:59 +0200 (CEST) Received: from mail.lemote.com ([222.92.8.138]:57606 "EHLO mail.lemote.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815760Ab3GKMfuC3EsA (ORCPT ); Thu, 11 Jul 2013 14:35:50 +0200 Received: from localhost (localhost [127.0.0.1]) by mail.lemote.com (Postfix) with ESMTP id 5F5FA230B6; Thu, 11 Jul 2013 20:35:38 +0800 (CST) X-Virus-Scanned: Debian amavisd-new at lemote.com Received: from mail.lemote.com ([127.0.0.1]) by localhost (mail.lemote.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ndwh-JjR2Pei; Thu, 11 Jul 2013 20:35:26 +0800 (CST) Received: from [192.168.0.228] (unknown [218.57.204.90]) (Authenticated sender: zhangfx@lemote.com) by mail.lemote.com (Postfix) with ESMTPSA id 9884A22F44; Thu, 11 Jul 2013 20:35:24 +0800 (CST) Message-ID: <51DEA687.6040208@lemote.com> Date: Thu, 11 Jul 2013 20:35:19 +0800 From: Fuxin Zhang User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 MIME-Version: 1.0 To: Huacai Chen CC: Ralf Baechle , John Crispin , linux-mips@linux-mips.org, Zhangjin Wu , Hongliang Tao , Hua Yan Subject: Re: [PATCH V10 12/13] MIPS: Loongson 3: Add CPU hotplug support References: <1366030028-5084-1-git-send-email-chenhc@lemote.com> <1366030028-5084-13-git-send-email-chenhc@lemote.com> <20130628070553.GI10727@linux-mips.org> <20130628070829.GJ10727@linux-mips.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37283 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 853 Lines: 24 于 2013/7/11 17:31, Huacai Chen 写道: > Normal labels and nops can be removed, but loongson3_play_dead() > should be run at CKSEG0, I'm afraid that it will have a wrong behavior > if I write it with C. I think just replacing flush_loop with number label like 1: will be ok. Don't think too much. > > On Fri, Jun 28, 2013 at 3:08 PM, Ralf Baechle wrote: >> On Fri, Jun 28, 2013 at 09:05:53AM +0200, Ralf Baechle wrote: >> >>>> + "flush_loop: \n" /* flush L1 */ >>> Please don't use normale in inline assembler. This might result in build >>> errors. it's horrible to read but number local labels like: >> That was meant to read "Please don't use normal labels" in inline assembler. >> >> Ralf >> -- 江苏中科梦兰电子科技有限公司 总经理 张福新 zhangfx@lemote.com From aaro.koskinen@iki.fi Thu Jul 11 21:36:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Jul 2013 21:36:44 +0200 (CEST) Received: from filtteri1.pp.htv.fi ([213.243.153.184]:36694 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835038Ab3GKTgkCnRmB (ORCPT ); Thu, 11 Jul 2013 21:36:40 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id 3F2BD21B877; Thu, 11 Jul 2013 22:36:38 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp6.welho.com ([213.243.153.40]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id kptgRwwqJk8u; Thu, 11 Jul 2013 22:36:33 +0300 (EEST) Received: from blackmetal.pp.htv.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp6.welho.com (Postfix) with ESMTP id 410895BC003; Thu, 11 Jul 2013 22:36:33 +0300 (EEST) From: Aaro Koskinen To: "Rafael J. Wysocki" , Viresh Kumar , Ralf Baechle , cpufreq@vger.kernel.org, Julia Lawall , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Aaro Koskinen , stable@vger.kernel.org Subject: [PATCH] MIPS: loongson2: cpufreq: fix broken cpufreq Date: Thu, 11 Jul 2013 22:34:41 +0300 Message-Id: <1373571281-4457-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.8.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37284 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1372 Lines: 46 Commit 42913c799 (MIPS: Loongson2: Use clk API instead of direct dereferences) broke the cpufreq functionality on Loongson2 boards: clk_set_rate() is called before the CPU frequency table is initialized, and therefore will always fail. Fix by moving the clk_set_rate() after the table initialization. Tested on Lemote FuLoong mini-PC. Signed-off-by: Aaro Koskinen Cc: stable@vger.kernel.org --- drivers/cpufreq/loongson2_cpufreq.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/loongson2_cpufreq.c b/drivers/cpufreq/loongson2_cpufreq.c index d539127..f92b02a 100644 --- a/drivers/cpufreq/loongson2_cpufreq.c +++ b/drivers/cpufreq/loongson2_cpufreq.c @@ -118,11 +118,6 @@ static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy) clk_put(cpuclk); return -EINVAL; } - ret = clk_set_rate(cpuclk, rate); - if (ret) { - clk_put(cpuclk); - return ret; - } /* clock table init */ for (i = 2; @@ -130,6 +125,12 @@ static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy) i++) loongson2_clockmod_table[i].frequency = (rate * i) / 8; + ret = clk_set_rate(cpuclk, rate); + if (ret) { + clk_put(cpuclk); + return ret; + } + policy->cur = loongson2_cpufreq_get(policy->cpu); cpufreq_frequency_table_get_attr(&loongson2_clockmod_table[0], -- 1.8.3.1 From paravoid@tty.gr Fri Jul 12 00:08:12 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Jul 2013 00:08:14 +0200 (CEST) Received: from scrooge.tty.gr ([62.217.125.135]:43270 "EHLO mail.tty.gr" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835038Ab3GKWIMeXiFH (ORCPT ); Fri, 12 Jul 2013 00:08:12 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=tty.gr; s=x; h=Message-Id:Date:Subject:Cc:To:From; bh=nuAbwwn3ILsUvVp3T/u3UQ7ahsbqvjmL0UDqkennPQM=; b=NWldSZTu7+g+SmnvxWuQYjqL7yMSeT7i2PWP9TdP+pPEftWCD9LYni3ezovxUxRvJvKt+DoU13ge2/1tLtWk9LaavE1YnWQQqnauRiSqTcoqYkCq/lhtqZH7qCvoFW5/; Received: from [2001:648:2001:f000:223:aeff:fe91:b5f4] (helo=serenity.void.home) by mail.tty.gr (envelope-from ) with esmtpsa (tls_cipher TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80 (Debian GNU/Linux)) id 1UxP21-000545-J0; Fri, 12 Jul 2013 01:08:09 +0300 Received: from paravoid by serenity.void.home with local (Exim 4.80) (envelope-from ) id 1UxP21-00061i-3g; Fri, 12 Jul 2013 01:08:09 +0300 From: Faidon Liambotis To: Ralf Baechle , linux-mips@linux-mips.org Cc: Aaro Koskinen Subject: [PATCH] MIPS: octeon: fix DT pruning bug with pip ports Date: Fri, 12 Jul 2013 01:08:09 +0300 Message-Id: <1373580489-23142-1-git-send-email-paravoid@debian.org> X-Mailer: git-send-email 1.7.10.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37285 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paravoid@debian.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1396 Lines: 36 During the pruning of the device tree octeon_fdt_pip_iface() is called for each PIP interface and every port up to the port count is removed from the device tree. However, the count was set to the return value of cvmx_helper_interface_enumerate() which doesn't actually return the count but just returns zero on success. This effectively removed *all* ports from the tree. Use cvmx_helper_ports_on_interface() instead to fix this. This successfully restores the 3 ports of my ERLite-3 and fixes the "kernel assigns random MAC addresses" issue. Signed-off-by: Faidon Liambotis --- arch/mips/cavium-octeon/octeon-platform.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 389512e..250eb20 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -334,9 +334,10 @@ static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) char name_buffer[20]; int iface; int p; - int count; + int count = 0; - count = cvmx_helper_interface_enumerate(idx); + if (cvmx_helper_interface_enumerate(idx) == 0) + count = cvmx_helper_ports_on_interface(idx); snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); -- 1.8.3.2 From viresh.linux@gmail.com Fri Jul 12 08:05:12 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Jul 2013 08:05:23 +0200 (CEST) Received: from mail-vc0-f174.google.com ([209.85.220.174]:51297 "EHLO mail-vc0-f174.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816288Ab3GLGFMFGx9b (ORCPT ); Fri, 12 Jul 2013 08:05:12 +0200 Received: by mail-vc0-f174.google.com with SMTP id kw10so7304214vcb.5 for ; Thu, 11 Jul 2013 23:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=ZWn18pqkOq4g5qF9/TC6EvJ/G6TRlxEWcGTkw/EB3Y0=; b=Cty3svmtcpUeO+KECMECX7Euql331grpSVu6wIxtW1oVBRfR9DedkbFRSbWd8R6Kn/ aDBmbmiVuJMNPFh73hSaBrlDaMq0mCULKrkYH8eK9LUaBnPFG/t2FFWTKG1EVJXtI9Xo tqCg5irjvnuk8g5vXzm1bgOOx/45SGcK3zCWCPczZi1xaCrQiUahv/CkD/3OXGqnJ2X2 vWihKLj1Z3q28dJQ4kTcMaFcJh/JTBWek2bwKhKkow1y9/uWXvL8/S+j/NfX9jSlmv92 tNuu8qVQ9OhAVFlaX6V1tdS8O6aOlfYMVGjn/b+M7h3D+2Pohik8EQEihO3vEC1wlwdN dDeQ== MIME-Version: 1.0 X-Received: by 10.58.46.48 with SMTP id s16mr23842879vem.52.1373609105388; Thu, 11 Jul 2013 23:05:05 -0700 (PDT) Received: by 10.52.231.4 with HTTP; Thu, 11 Jul 2013 23:05:05 -0700 (PDT) In-Reply-To: <1373571281-4457-1-git-send-email-aaro.koskinen@iki.fi> References: <1373571281-4457-1-git-send-email-aaro.koskinen@iki.fi> Date: Fri, 12 Jul 2013 11:35:05 +0530 X-Google-Sender-Auth: UXFwICWKPs-OPNYVJbIrfI0anDQ Message-ID: Subject: Re: [PATCH] MIPS: loongson2: cpufreq: fix broken cpufreq From: Viresh Kumar To: Aaro Koskinen Cc: "Rafael J. Wysocki" , Ralf Baechle , cpufreq@vger.kernel.org, Julia Lawall , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37286 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: viresh.kumar@linaro.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 674 Lines: 16 On Fri, Jul 12, 2013 at 1:04 AM, Aaro Koskinen wrote: > Commit 42913c799 (MIPS: Loongson2: Use clk API instead of direct > dereferences) broke the cpufreq functionality on Loongson2 boards: > clk_set_rate() is called before the CPU frequency table is initialized, > and therefore will always fail. > > Fix by moving the clk_set_rate() after the table initialization. > Tested on Lemote FuLoong mini-PC. > > Signed-off-by: Aaro Koskinen > Cc: stable@vger.kernel.org > --- > drivers/cpufreq/loongson2_cpufreq.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) Ackec-by: Viresh Kumar From James.Hogan@imgtec.com Fri Jul 12 13:27:01 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Jul 2013 13:27:03 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:30016 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822508Ab3GLL1BC4Crz (ORCPT ); Fri, 12 Jul 2013 13:27:01 +0200 Message-ID: <51DFE7D3.3090002@imgtec.com> Date: Fri, 12 Jul 2013 12:26:11 +0100 From: James Hogan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: linux-mips , Sanjay Lal , Ralf Baechle CC: David Daney , kvm Subject: [PATCH] MIPS: mark KVM_GUEST (T&E KVM) as BROKEN_ON_SMP X-Enigmail-Version: 1.5.1 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.154.65] X-SEF-Processed: 7_3_0_01192__2013_07_12_12_26_54 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37287 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: james.hogan@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1017 Lines: 34 Make KVM_GUEST depend on BROKEN_ON_SMP so that it cannot be enabled with SMP. SMP kernels use ll/sc instructions for an atomic section in the tlb fill handler, with a tlbp instruction contained in the middle. This cannot be emulated with trap & emulate KVM because the tlbp instruction traps and the eret to return to the guest code clears the LLbit which makes the sc instruction always fail. Signed-off-by: James Hogan Cc: Sanjay Lal Cc: Ralf Baechle Cc: David Daney Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7a58ab9..6a6a096 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1736,6 +1736,7 @@ endchoice config KVM_GUEST bool "KVM Guest Kernel" + depends on BROKEN_ON_SMP help Select this option if building a guest kernel for KVM (Trap & Emulate) mode -- 1.8.1.2 From aaro.koskinen@iki.fi Sun Jul 14 21:10:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Jul 2013 21:10:06 +0200 (CEST) Received: from filtteri5.pp.htv.fi ([213.243.153.188]:39407 "EHLO filtteri5.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816847Ab3GNTKEe5IqM (ORCPT ); Sun, 14 Jul 2013 21:10:04 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri5.pp.htv.fi (Postfix) with ESMTP id 58C135A7218; Sun, 14 Jul 2013 22:10:01 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp5.welho.com ([213.243.153.39]) by localhost (filtteri5.pp.htv.fi [213.243.153.188]) (amavisd-new, port 10024) with ESMTP id 9iUIh+dyHYAv; Sun, 14 Jul 2013 22:09:56 +0300 (EEST) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp5.welho.com (Postfix) with SMTP id 6534C5BC003; Sun, 14 Jul 2013 22:09:55 +0300 (EEST) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Sun, 14 Jul 2013 22:09:57 +0300 Date: Sun, 14 Jul 2013 22:09:57 +0300 From: Aaro Koskinen To: Faidon Liambotis Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: octeon: fix DT pruning bug with pip ports Message-ID: <20130714190957.GA3296@blackmetal.musicnaut.iki.fi> References: <1373580489-23142-1-git-send-email-paravoid@debian.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1373580489-23142-1-git-send-email-paravoid@debian.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37289 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1600 Lines: 45 On Fri, Jul 12, 2013 at 01:08:09AM +0300, Faidon Liambotis wrote: > During the pruning of the device tree octeon_fdt_pip_iface() is called > for each PIP interface and every port up to the port count is removed > from the device tree. However, the count was set to the return value of > cvmx_helper_interface_enumerate() which doesn't actually return the > count but just returns zero on success. This effectively removed *all* > ports from the tree. > > Use cvmx_helper_ports_on_interface() instead to fix this. This > successfully restores the 3 ports of my ERLite-3 and fixes the "kernel > assigns random MAC addresses" issue. > > Signed-off-by: Faidon Liambotis Tested-by: Aaro Koskinen Thanks, A. > --- > arch/mips/cavium-octeon/octeon-platform.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c > index 389512e..250eb20 100644 > --- a/arch/mips/cavium-octeon/octeon-platform.c > +++ b/arch/mips/cavium-octeon/octeon-platform.c > @@ -334,9 +334,10 @@ static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) > char name_buffer[20]; > int iface; > int p; > - int count; > + int count = 0; > > - count = cvmx_helper_interface_enumerate(idx); > + if (cvmx_helper_interface_enumerate(idx) == 0) > + count = cvmx_helper_ports_on_interface(idx); > > snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); > iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); > -- > 1.8.3.2 > > From aaro.koskinen@iki.fi Mon Jul 15 10:22:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Jul 2013 10:22:46 +0200 (CEST) Received: from filtteri1.pp.htv.fi ([213.243.153.184]:45163 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817088Ab3GOIWmsXEUJ (ORCPT ); Mon, 15 Jul 2013 10:22:42 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id A381A21B7BA; Mon, 15 Jul 2013 11:22:41 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp6.welho.com ([213.243.153.40]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id RIZ-4zG0+DSM; Mon, 15 Jul 2013 11:22:36 +0300 (EEST) Received: from blackmetal.pp.htv.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp6.welho.com (Postfix) with ESMTP id A98F15BC00B; Mon, 15 Jul 2013 11:22:36 +0300 (EEST) From: Aaro Koskinen To: Ralf Baechle , Jayachandran C , linux-mips@linux-mips.org Cc: Aaro Koskinen Subject: [PATCH] MIPS: tlbex: fix broken build in v3.11-rc1 Date: Mon, 15 Jul 2013 11:21:57 +0300 Message-Id: <1373876517-14646-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.8.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37291 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 848 Lines: 25 Commit 6ba045f9fbdafb48da42aa8576ea7a3980443136 (MIPS: Move generated code to .text for microMIPS) deleted tlbmiss_handler_setup_pgd_array, but some references were not converted. Fix that to enable building a MIPS kernel. Signed-off-by: Aaro Koskinen --- arch/mips/mm/tlbex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 9ab0f90..cc34521 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1466,7 +1466,7 @@ static void __cpuinit build_r4000_setup_pgd(void) { const int a0 = 4; const int a1 = 5; - u32 *p = tlbmiss_handler_setup_pgd_array; + u32 *p = tlbmiss_handler_setup_pgd; const int tlbmiss_handler_setup_pgd_size = tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; struct uasm_label *l = labels; -- 1.8.3.1 From jchandra@broadcom.com Mon Jul 15 11:54:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Jul 2013 11:54:26 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:1312 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822429Ab3GOJyXbTE1Z (ORCPT ); Mon, 15 Jul 2013 11:54:23 +0200 Received: from [10.9.208.57] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 15 Jul 2013 02:48:09 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.438.0; Mon, 15 Jul 2013 02:53:54 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.1.438.0; Mon, 15 Jul 2013 02:53:54 -0700 Received: from jayachandranc.netlogicmicro.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2B606F301B; Mon, 15 Jul 2013 02:52:56 -0700 (PDT) Date: Mon, 15 Jul 2013 15:25:02 +0530 From: "Jayachandran C." To: "Aaro Koskinen" cc: "Ralf Baechle" , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: tlbex: fix broken build in v3.11-rc1 Message-ID: <20130715095501.GE22314@jayachandranc.netlogicmicro.com> References: <1373876517-14646-1-git-send-email-aaro.koskinen@iki.fi> MIME-Version: 1.0 In-Reply-To: <1373876517-14646-1-git-send-email-aaro.koskinen@iki.fi> User-Agent: Mutt/1.5.21 (2010-09-15) X-WSS-ID: 7DFD1AD31R044338170-02-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37292 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1127 Lines: 31 On Mon, Jul 15, 2013 at 11:21:57AM +0300, Aaro Koskinen wrote: > Commit 6ba045f9fbdafb48da42aa8576ea7a3980443136 (MIPS: Move generated code > to .text for microMIPS) deleted tlbmiss_handler_setup_pgd_array, but some > references were not converted. Fix that to enable building a MIPS kernel. > > Signed-off-by: Aaro Koskinen > --- > arch/mips/mm/tlbex.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > index 9ab0f90..cc34521 100644 > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -1466,7 +1466,7 @@ static void __cpuinit build_r4000_setup_pgd(void) > { > const int a0 = 4; > const int a1 = 5; > - u32 *p = tlbmiss_handler_setup_pgd_array; > + u32 *p = tlbmiss_handler_setup_pgd; > const int tlbmiss_handler_setup_pgd_size = > tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; > struct uasm_label *l = labels; Acked-by: "Jayachandran C." Thanks, looks like I made a mistake splitting the patchset, this part went into the next patch which didn't make it to 3.11. JC. From thomas.petazzoni@free-electrons.com Mon Jul 15 13:52:58 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Jul 2013 13:53:01 +0200 (CEST) Received: from mail.free-electrons.com ([94.23.35.102]:37671 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823098Ab3GOLw6aibxm (ORCPT ); Mon, 15 Jul 2013 13:52:58 +0200 Received: by mail.free-electrons.com (Postfix, from userid 106) id 7A4077C9; Mon, 15 Jul 2013 13:52:52 +0200 (CEST) Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 774D67A0; Mon, 15 Jul 2013 13:52:51 +0200 (CEST) From: Thomas Petazzoni To: Bjorn Helgaas , linux-pci@vger.kernel.org, Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement Cc: Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Subject: [PATCHv5 02/11] PCI: use weak functions for MSI arch-specific functions Date: Mon, 15 Jul 2013 13:52:38 +0200 Message-Id: <1373889167-27878-3-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1373889167-27878-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1373889167-27878-1-git-send-email-thomas.petazzoni@free-electrons.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37293 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 9187 Lines: 278 Until now, the MSI architecture-specific functions could be overloaded using a fairly complex set of #define and compile-time conditionals. In order to prepare for the introduction of the msi_chip infrastructure, it is desirable to switch all those functions to use the 'weak' mechanism. This commit converts all the architectures that were overidding those MSI functions to use the new strategy. Note that we keep a separate, non-weak, function default_teardown_msi_irqs() for the default behavior of the arch_teardown_msi_irqs(), as the default behavior is needed by the Xen x86 PCI code. Signed-off-by: Thomas Petazzoni Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: x86@kernel.org Cc: Russell King Cc: Tony Luck Cc: Fenghua Yu Cc: linux-ia64@vger.kernel.org Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: David S. Miller Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf --- arch/mips/include/asm/pci.h | 5 ----- arch/powerpc/include/asm/pci.h | 5 ----- arch/s390/include/asm/pci.h | 4 ---- arch/x86/include/asm/pci.h | 28 -------------------------- arch/x86/kernel/x86_init.c | 21 ++++++++++++++++++++ drivers/pci/msi.c | 45 +++++++++++++++++++----------------------- include/linux/msi.h | 7 ++++++- 7 files changed, 47 insertions(+), 68 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index fa8e0aa..f194c08 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -136,11 +136,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } -#ifdef CONFIG_CPU_CAVIUM_OCTEON -/* MSI arch hook for OCTEON */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#endif - extern char * (*pcibios_plat_setup)(char *str); #ifdef CONFIG_OF diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index 6653f27..95145a1 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h @@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus); /* Decide whether to display the domain number in /proc */ extern int pci_proc_domain(struct pci_bus *bus); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs -#define arch_msi_check_device arch_msi_check_device - struct vm_area_struct; /* Map a range of PCI memory or I/O space for a device into user space */ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index 6e577ba..262b91b 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h @@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *); int pci_domain_nr(struct pci_bus *); int pci_proc_domain(struct pci_bus *); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs - #define ZPCI_BUS_NR 0 /* default bus number */ #define ZPCI_DEVFN 0 /* default device number */ diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index d9e9e6c..8c61de0 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -100,29 +100,6 @@ static inline void early_quirks(void) { } extern void pci_iommu_alloc(void); #ifdef CONFIG_PCI_MSI -/* MSI arch specific hooks */ -static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) -{ - return x86_msi.setup_msi_irqs(dev, nvec, type); -} - -static inline void x86_teardown_msi_irqs(struct pci_dev *dev) -{ - x86_msi.teardown_msi_irqs(dev); -} - -static inline void x86_teardown_msi_irq(unsigned int irq) -{ - x86_msi.teardown_msi_irq(irq); -} -static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq) -{ - x86_msi.restore_msi_irqs(dev, irq); -} -#define arch_setup_msi_irqs x86_setup_msi_irqs -#define arch_teardown_msi_irqs x86_teardown_msi_irqs -#define arch_teardown_msi_irq x86_teardown_msi_irq -#define arch_restore_msi_irqs x86_restore_msi_irqs /* implemented in arch/x86/kernel/apic/io_apic. */ struct msi_desc; int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); @@ -130,11 +107,6 @@ void native_teardown_msi_irq(unsigned int irq); void native_restore_msi_irqs(struct pci_dev *dev, int irq); int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, unsigned int irq_base, unsigned int irq_offset); -/* default to the implementation in drivers/lib/msi.c */ -#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS -#define HAVE_DEFAULT_MSI_RESTORE_IRQS -void default_teardown_msi_irqs(struct pci_dev *dev); -void default_restore_msi_irqs(struct pci_dev *dev, int irq); #else #define native_setup_msi_irqs NULL #define native_teardown_msi_irq NULL diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 45a14db..a2b189c 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -116,6 +116,27 @@ struct x86_msi_ops x86_msi = { .setup_hpet_msi = default_setup_hpet_msi, }; +/* MSI arch specific hooks */ +int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +{ + return x86_msi.setup_msi_irqs(dev, nvec, type); +} + +void arch_teardown_msi_irqs(struct pci_dev *dev) +{ + x86_msi.teardown_msi_irqs(dev); +} + +void arch_teardown_msi_irq(unsigned int irq) +{ + x86_msi.teardown_msi_irq(irq); +} + +void arch_restore_msi_irqs(struct pci_dev *dev, int irq) +{ + x86_msi.restore_msi_irqs(dev, irq); +} + struct x86_io_apic_ops x86_io_apic_ops = { .init = native_io_apic_init_mappings, .read = native_io_apic_read, diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index aca7578..aa2f697 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -30,20 +30,21 @@ static int pci_msi_enable = 1; /* Arch hooks */ -#ifndef arch_msi_check_device -int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) +int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) { - return 0; + return -EINVAL; } -#endif -#ifndef arch_setup_msi_irqs -# define arch_setup_msi_irqs default_setup_msi_irqs -# define HAVE_DEFAULT_MSI_SETUP_IRQS -#endif +void __weak arch_teardown_msi_irq(unsigned int irq) +{ +} -#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS -int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) +{ + return 0; +} + +int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) { struct msi_desc *entry; int ret; @@ -65,14 +66,11 @@ int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) return 0; } -#endif -#ifndef arch_teardown_msi_irqs -# define arch_teardown_msi_irqs default_teardown_msi_irqs -# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS -#endif - -#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS +/* + * We have a default implementation available as a separate non-weak + * function, as it is used by the Xen x86 PCI code + */ void default_teardown_msi_irqs(struct pci_dev *dev) { struct msi_desc *entry; @@ -89,15 +87,13 @@ void default_teardown_msi_irqs(struct pci_dev *dev) arch_teardown_msi_irq(entry->irq + i); } } -#endif -#ifndef arch_restore_msi_irqs -# define arch_restore_msi_irqs default_restore_msi_irqs -# define HAVE_DEFAULT_MSI_RESTORE_IRQS -#endif +void __weak arch_teardown_msi_irqs(struct pci_dev *dev) +{ + return default_teardown_msi_irqs(dev); +} -#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS -void default_restore_msi_irqs(struct pci_dev *dev, int irq) +void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq) { struct msi_desc *entry; @@ -114,7 +110,6 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq) if (entry) write_msi_msg(irq, &entry->msg); } -#endif static void msi_set_enable(struct pci_dev *dev, int enable) { diff --git a/include/linux/msi.h b/include/linux/msi.h index ee66f3a..18870b0 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -51,12 +51,17 @@ struct msi_desc { }; /* - * The arch hook for setup up msi irqs + * The arch hooks to setup up msi irqs. Those functions are + * implemented as weak symbols so that they /can/ be overriden by + * architecture specific code if needed. */ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); void arch_teardown_msi_irq(unsigned int irq); int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); void arch_teardown_msi_irqs(struct pci_dev *dev); int arch_msi_check_device(struct pci_dev* dev, int nvec, int type); +void arch_restore_msi_irqs(struct pci_dev *dev, int irq); + +void default_teardown_msi_irqs(struct pci_dev *dev); #endif /* LINUX_MSI_H */ -- 1.8.1.2 From thomas.petazzoni@free-electrons.com Mon Jul 15 13:53:17 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Jul 2013 13:53:24 +0200 (CEST) Received: from mail.free-electrons.com ([94.23.35.102]:37693 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827499Ab3GOLxAwPTcw (ORCPT ); Mon, 15 Jul 2013 13:53:00 +0200 Received: by mail.free-electrons.com (Postfix, from userid 106) id DAAAB7FB; Mon, 15 Jul 2013 13:52:53 +0200 (CEST) Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 0493E7AD; Mon, 15 Jul 2013 13:52:53 +0200 (CEST) From: Thomas Petazzoni To: Bjorn Helgaas , linux-pci@vger.kernel.org, Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement Cc: Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Subject: [PATCHv5 03/11] PCI: remove ARCH_SUPPORTS_MSI kconfig option Date: Mon, 15 Jul 2013 13:52:39 +0200 Message-Id: <1373889167-27878-4-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1373889167-27878-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1373889167-27878-1-git-send-email-thomas.petazzoni@free-electrons.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37294 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 5042 Lines: 164 Now that we have weak versions for each of the PCI MSI architecture functions, we can actually build the MSI support for all platforms, regardless of whether they provide or not architecture-specific versions of those functions. For this reason, the ARCH_SUPPORTS_MSI hidden kconfig boolean becomes useless, and this patch gets rid of it. Signed-off-by: Thomas Petazzoni Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: H. Peter Anvin Cc: x86@kernel.org Cc: Russell King Cc: Tony Luck Cc: Fenghua Yu Cc: linux-ia64@vger.kernel.org Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: David S. Miller Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf --- arch/arm/Kconfig | 1 - arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 -- arch/powerpc/Kconfig | 1 - arch/s390/Kconfig | 1 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - drivers/pci/Kconfig | 4 ---- 9 files changed, 13 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ba412e0..b173c1d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -441,7 +441,6 @@ config ARCH_NETX config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU - select ARCH_SUPPORTS_MSI select CPU_XSC3 select NEED_MACH_MEMORY_H select NEED_RET_TO_USER diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 5a768ad..098602b 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -9,7 +9,6 @@ config IA64 select PCI if (!IA64_HP_SIM) select ACPI if (!IA64_HP_SIM) select PM if (!IA64_HP_SIM) - select ARCH_SUPPORTS_MSI select HAVE_UNSTABLE_SCHED_CLOCK select HAVE_IDE select HAVE_OPROFILE diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4758a8f..00b2698 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -726,7 +726,6 @@ config CAVIUM_OCTEON_SOC select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE select HW_HAS_PCI - select ARCH_SUPPORTS_MSI select ZONE_DMA32 select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI @@ -762,7 +761,6 @@ config NLM_XLR_BOARD select CEVT_R4K select CSRC_R4K select IRQ_CPU - select ARCH_SUPPORTS_MSI select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 3bf72cd..183a165 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -727,7 +727,6 @@ config PCI default y if !40x && !CPM2 && !8xx && !PPC_83xx \ && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON default PCI_QSPAN if !4xx && !CPM2 && 8xx - select ARCH_SUPPORTS_MSI select GENERIC_PCI_IOMAP help Find out whether your system includes a PCI bus. PCI is the name of diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 22f75b5..e9982a3 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -428,7 +428,6 @@ menuconfig PCI bool "PCI support" default n depends on 64BIT - select ARCH_SUPPORTS_MSI select PCI_MSI help Enable PCI support. diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index a00cbd3..1570ad2 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -52,7 +52,6 @@ config SPARC32 config SPARC64 def_bool 64BIT - select ARCH_SUPPORTS_MSI select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_GRAPH_FP_TEST diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index 24565a7..74dff90 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -380,7 +380,6 @@ config PCI select PCI_DOMAINS select GENERIC_PCI_IOMAP select TILE_GXIO_TRIO if TILEGX - select ARCH_SUPPORTS_MSI if TILEGX select PCI_MSI if TILEGX ---help--- Enable PCI root complex support, so PCIe endpoint devices can diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b32ebf9..5db62ef 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2014,7 +2014,6 @@ menu "Bus options (PCI etc.)" config PCI bool "PCI support" default y - select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC) ---help--- Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 81944fb..b6a99f7 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -1,13 +1,9 @@ # # PCI configuration # -config ARCH_SUPPORTS_MSI - bool - config PCI_MSI bool "Message Signaled Interrupts (MSI and MSI-X)" depends on PCI - depends on ARCH_SUPPORTS_MSI help This allows device drivers to enable MSI (Message Signaled Interrupts). Message Signaled Interrupts enable a device to -- 1.8.1.2 From ddaney.cavm@gmail.com Tue Jul 16 00:17:33 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jul 2013 00:17:34 +0200 (CEST) Received: from mail-pb0-f54.google.com ([209.85.160.54]:34990 "EHLO mail-pb0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827451Ab3GOWRdYD5uK (ORCPT ); Tue, 16 Jul 2013 00:17:33 +0200 Received: by mail-pb0-f54.google.com with SMTP id ro2so11740610pbb.41 for ; Mon, 15 Jul 2013 15:17:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=GXVTnnwx1yOF7MV9q5uX3SuNj8MEe1hO7mc87Hj39Do=; b=aj++0CEFDeiHcTzocnD6xlPVVr5x6Ib5/9b8L1p7VkN3jkUlK+5UjoWVZ7jj58FKl2 zADjzv578Om87dT4/kexHvmCpU2NW2UV6iZ8s66FXCQZW8UFhxptO+oYdkVyYkdQy6Gd 0g1ZPMlr1SH9b5B3BfVfGYYpt9S6xBGQAOtfXkRNZjORorb3w4wcxgQoIwMwXR5MNzuP 6PpL+ujgvnt9LIF90NszJkkVOfu/ZHR9nu1S+pgGb2stB5s9VIeWwmE6zst2ZwVV9Jxi bqQzm1bTzKar8xtWs1oX+HGZWGDpGDXFFKeWIpCMrsHoXymkbmD//rImAYuw5rlLJBK7 ylnw== X-Received: by 10.66.193.166 with SMTP id hp6mr57635497pac.118.1373926646887; Mon, 15 Jul 2013 15:17:26 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id mr3sm62883049pbb.27.2013.07.15.15.17.25 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 15 Jul 2013 15:17:25 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6FMHOa8024660; Mon, 15 Jul 2013 15:17:24 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6FMHNHR024659; Mon, 15 Jul 2013 15:17:23 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Corey Minyard , Steven Rostedt , David Daney Subject: [PATCH] mips/ftrace: Fix function tracing return address to match Date: Mon, 15 Jul 2013 15:17:17 -0700 Message-Id: <1373926637-24627-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37295 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1208 Lines: 35 From: Corey Minyard Dynamic function tracing was not working on MIPS. When doing dynamic tracing, the tracer attempts to match up the passed in address with the one the compiler creates in the mcount tables. The MIPS code was passing in the return address from the tracing function call, but the compiler tables were the address of the function call. So they wouldn't match. Just subtracting 8 from the return address will give the address of the function call. Easy enough. Signed-off-by: Corey Minyard [david.daney@cavium.com: Adjusted code comment and patch Subject.] Signed-off-by: David Daney --- arch/mips/kernel/mcount.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S index a03e93c..539b629 100644 --- a/arch/mips/kernel/mcount.S +++ b/arch/mips/kernel/mcount.S @@ -83,7 +83,7 @@ _mcount: PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp) #endif - move a0, ra /* arg1: self return address */ + PTR_SUBU a0, ra, 8 /* arg1: self address */ .globl ftrace_call ftrace_call: nop /* a placeholder for the call to a real tracing function */ -- 1.7.11.7 From f.fainelli@gmail.com Tue Jul 16 14:32:07 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jul 2013 14:32:13 +0200 (CEST) Received: from mail-pd0-f174.google.com ([209.85.192.174]:59043 "EHLO mail-pd0-f174.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827510Ab3GPMcHJekPr (ORCPT ); Tue, 16 Jul 2013 14:32:07 +0200 Received: by mail-pd0-f174.google.com with SMTP id 10so628901pdc.19 for ; Tue, 16 Jul 2013 05:32:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type; bh=aeYRy3yLEUzhb+keBiqykrfJTbX/4DppQD20lsZtu48=; b=ZSGd/SHvuqyPAHnPX+GRnP6b1HQhdoO2m6ZDcePE5p+RD9TuJeRhd1pXv1UYYP3Een 1tozM4qEkI3jNXGiggxveyhMQFB8Ui0XaBSrSLZwr5uuceoShKg+jSXYy1EAV+eImA/5 /7rVVmOnQiIbAlQyD2QHPgrNq649sUTKdadp3J2AZx0RwFkTp4uLkMKfy7Ni5x5jVPVo 0hkqlfD6XLxeRp7FHOmNB4gV3+3431egxTqP7/HUcu1Rni6t5xQXm/On3KcH1oF/XbJW HSwczIiIoJAXYGsc4YqvxxX2qiXEbC77WBzlkYJMGX6cV+1jIPlatL0pj8dVP2h9qEoq rROg== X-Received: by 10.68.131.68 with SMTP id ok4mr1295767pbb.146.1373977920300; Tue, 16 Jul 2013 05:32:00 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.10.101 with HTTP; Tue, 16 Jul 2013 05:31:20 -0700 (PDT) In-Reply-To: <1372537073-27370-6-git-send-email-jogo@openwrt.org> References: <1372537073-27370-1-git-send-email-jogo@openwrt.org> <1372537073-27370-6-git-send-email-jogo@openwrt.org> From: Florian Fainelli Date: Tue, 16 Jul 2013 13:31:20 +0100 X-Google-Sender-Auth: VP9buYGN-DeARjSYGn6WZpyLSk4 Message-ID: Subject: Re: [PATCH 05/10] MIPS: bmips: merge CPU options into one option To: Jonas Gorski Cc: Linux-MIPS , Ralf Baechle , John Crispin , Maxime Bizon , Kevin Cernekee Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37297 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 468 Lines: 18 Hello Jonas, 2013/6/29 Jonas Gorski : [snip] > +config CPU_BMIPS > + bool "Broadcom BMIPS" > + depends on SYS_HAS_CPU_BMIPS > + select CPU_MIPS32 > + select CPU_BMIPS3300 if SYS_HAS_CPU_BMIPS3300 > + select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350 > + select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4380 As you already made me notice privately, this should be: select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380 -- Florian From jogo@openwrt.org Tue Jul 16 14:42:12 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jul 2013 14:42:16 +0200 (CEST) Received: from mail.nanl.de ([217.115.11.12]:44885 "EHLO mail.nanl.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6833452Ab3GPMmMP-Hzx (ORCPT ); Tue, 16 Jul 2013 14:42:12 +0200 Received: from mail-vb0-x22b.google.com (mail-vb0-x22b.google.com [IPv6:2607:f8b0:400c:c02::22b]) by mail.nanl.de (Postfix) with ESMTPSA id AE9E2402E1; Tue, 16 Jul 2013 12:41:47 +0000 (UTC) Received: by mail-vb0-f43.google.com with SMTP id e12so418855vbg.16 for ; Tue, 16 Jul 2013 05:42:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=Qd2KfSWC/0+OFIr/aR+aSIrL+vdrew/6RvRp3Yoftg4=; b=LJ2Z622tFFOyBVhOl2XErEd8Tx/37EfPGyB8f2tdZ8VjKlK7pdIhWloPLE0hFyKuih 7I7TEhjxFrNnjLTd5h4xC4OPnKWMWgKqSXVYOSdPmajnOaZRlOOXcvObnQSb3jb56SL5 ZI5opFCGrASOwdXwPsFZqlZvv0WX/rXAqdLkFIaD0Yb3DxzX1bEk+AKUgfuY6nATKKKr YDuMyQf1RCq2rbxmJ1UxSDwKCHyOTnuFnwergybPhwp+fa9QKgYeEPEef7Nki/ur01eR Kgle7QoIo3D6oxKpEQvP0iogh4HL8K9/qglRz1M1DoMnotG8JEfKnh+C6bzIhGob1ISc O4Lw== X-Received: by 10.220.77.74 with SMTP id f10mr397720vck.1.1373978525510; Tue, 16 Jul 2013 05:42:05 -0700 (PDT) MIME-Version: 1.0 Received: by 10.220.177.193 with HTTP; Tue, 16 Jul 2013 05:41:45 -0700 (PDT) In-Reply-To: References: <1372537073-27370-1-git-send-email-jogo@openwrt.org> <1372537073-27370-6-git-send-email-jogo@openwrt.org> From: Jonas Gorski Date: Tue, 16 Jul 2013 14:41:45 +0200 Message-ID: Subject: Re: [PATCH 05/10] MIPS: bmips: merge CPU options into one option To: Florian Fainelli Cc: Linux-MIPS , Ralf Baechle , John Crispin , Maxime Bizon , Kevin Cernekee Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37298 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jogo@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 809 Lines: 25 On Tue, Jul 16, 2013 at 2:31 PM, Florian Fainelli wrote: > Hello Jonas, > > 2013/6/29 Jonas Gorski : > [snip] > >> +config CPU_BMIPS >> + bool "Broadcom BMIPS" >> + depends on SYS_HAS_CPU_BMIPS >> + select CPU_MIPS32 >> + select CPU_BMIPS3300 if SYS_HAS_CPU_BMIPS3300 >> + select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350 >> + select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4380 > > As you already made me notice privately, this should be: > > select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380 I'm currently preparing a V2 that will fix this, the missed squash commit message in 6/10, and adds bcm47xx bmips selection (so that Ralf's cputype patch won't break bcm47xx and bcm63xx anymore). I marked the patches in patchwork accordingly. Jonas From f.fainelli@gmail.com Tue Jul 16 15:07:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jul 2013 15:07:25 +0200 (CEST) Received: from mail-pa0-f51.google.com ([209.85.220.51]:63926 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6832024Ab3GPNHXasTeU (ORCPT ); Tue, 16 Jul 2013 15:07:23 +0200 Received: by mail-pa0-f51.google.com with SMTP id lf11so766456pab.24 for ; Tue, 16 Jul 2013 06:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type; bh=Vizzfin9BU+lBpmsKAmcFvRjnQ4GTHc4XrqFJmU1tAE=; b=TNNNPxIyBWg3KJa7WZRzLBJHVFs8zLw7wJ/JV/aoOTf5b+E3ATQYnyyS5qRpnNYQg+ ArX7+b8FyMFkQBwMFjHg7NBD1w9Tt4T+tJ9CRKgFgVuRFU7I8NdzJXtLx6crHwe9h0Vl WWdTtaLnQ0wh7vuSJMNwcKfe0lxEX2cPFyldcXRD1Z4aco2mivi39jbKWm4ecEIQryck qLLNH7NGw8XlmsoJbzRubXdLbUe37UvGEL0FRfrn064DZd/lc2DZiYVWjXdMi14XbjMW wLg3PdEnG/6021zPRqi5vWbFhtD0Rtk52LgoAGOiuVv4ANg4914/OdiCU0Qvn4WRnfZ3 bfaA== X-Received: by 10.66.222.226 with SMTP id qp2mr2601167pac.102.1373980036750; Tue, 16 Jul 2013 06:07:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.10.101 with HTTP; Tue, 16 Jul 2013 06:06:36 -0700 (PDT) In-Reply-To: <1372537073-27370-1-git-send-email-jogo@openwrt.org> References: <1372537073-27370-1-git-send-email-jogo@openwrt.org> From: Florian Fainelli Date: Tue, 16 Jul 2013 14:06:36 +0100 X-Google-Sender-Auth: WWFFCS9_eR_sTrrGeCaTJFi8oic Message-ID: Subject: Re: [PATCH 00/10] MIPS: BCM63XX: improve BMIPS support To: Jonas Gorski Cc: Linux-MIPS , Ralf Baechle , John Crispin , Maxime Bizon , Kevin Cernekee Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37299 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2032 Lines: 49 Hello Jonas, 2013/6/29 Jonas Gorski : > This patchset aims at unifying the different BMIPS support code to allow > building a kernel that runs on multiple BCM63XX SoCs which might have > different BMIPS flavours on them, regardless of SMP support enabled in > the kernel. > > The first few patches clean up BMIPS itself and prepare it for multi-cpu > support, while the latter add support to BCM63XX for running a SMP kernel > with support for all SoCs, even those that do not have a SMP capable > CPU. > > This patchset is runtime tested on BCM6348, BCM6328 and BCM6368, to > verify that it actually does what it claims it does. > > Lacking hardware, it is only build tested for BMIPS4380 and BMIPS5000. > > Jonas Gorski (10): > MIPS: bmips: fix compilation for BMIPS5000 > MIPS: allow asm/cpu.h to be included from assembly > MIPS: bmips: add macros for testing the current bmips CPU > MIPS: bmips: change compile time checks to runtime checks > MIPS: bmips: merge CPU options into one option > MIPS: BCM63XX: let the individual SoCs select the appropriate CPUs > MIPS: bmips: add a helper function for registering smp ops > MIPS: BCM63XX: always register bmips smp ops > MIPS: BCM63XX: change the guard to a BMIPS4350 check > MIPS: BCM63XX: disable SMP also on BCM3368 After fixing the typo on BMIPS4350 vs BMIPS4380 and fixing the following (which I will submit just in a few minutes) @@ -187,7 +187,7 @@ static void bmips_boot_secondary(int cpu, struct task_struct } else { if (cpu_is_bmips4350() || cpu_is_bmips4380()) { /* Reset slave TP1 if booting from TP0 */ - if (cpu_logical_map(cpu) == 0) + if (cpu_logical_map(cpu) == 1) set_c0_brcm_cmt_ctrl(0x01); } else if (cpu_is_bmips5000()) { if (cpu & 0x01) it works just nicely on BMIPS4380. I plan on doing some testing on BMIPS5000 later this week. Thanks! -- Florian From jogo@openwrt.org Tue Jul 16 16:13:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jul 2013 16:13:44 +0200 (CEST) Received: from mail.nanl.de ([217.115.11.12]:44896 "EHLO mail.nanl.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827499Ab3GPONmZ5l5j (ORCPT ); Tue, 16 Jul 2013 16:13:42 +0200 Received: from mail-vb0-x230.google.com (mail-vb0-x230.google.com [IPv6:2607:f8b0:400c:c02::230]) by mail.nanl.de (Postfix) with ESMTPSA id E4B6545FA3; Tue, 16 Jul 2013 14:13:17 +0000 (UTC) Received: by mail-vb0-f48.google.com with SMTP id w15so482997vbf.21 for ; Tue, 16 Jul 2013 07:13:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=6UlhnlFWGc0IoLlA3/ZLbGEK7Tu0xJlU9haoXPAxK5w=; b=kvNmZ3n6T14O1eBk7BTaufFkBPXRDxEqQAAvZB02OEpAC0lUFXiRvO+HDcmSMid+XN 6kdiUxNsH6f1/t0F2rS/dtaygPinRNnKmfjRQOwlxKwxX5pVKF59+Enl7010PKEMxmdT 5EDyppLe2QN9c0C8AK7BNEDAIqaeb0LsukcBb3CpCizAVhQzdIO5EtemF5/sSXNlnpXv HEtzcrw6c+dnChw+nPdAPnCrqQdWDYHsDC1egiINFAbPbbX90PlrQNiiZ/9E2MtxzPRJ dIpb4bNUKfvz9Lyg+gdbGRxCDhqrG7Qa1HIwrlm4tbo2yS/R2eOP1vB30+32zLUW7z4r rm/g== X-Received: by 10.52.17.196 with SMTP id q4mr437649vdd.2.1373984016920; Tue, 16 Jul 2013 07:13:36 -0700 (PDT) MIME-Version: 1.0 Received: by 10.220.177.193 with HTTP; Tue, 16 Jul 2013 07:13:16 -0700 (PDT) In-Reply-To: References: <1372537073-27370-1-git-send-email-jogo@openwrt.org> From: Jonas Gorski Date: Tue, 16 Jul 2013 16:13:16 +0200 Message-ID: Subject: Re: [PATCH 00/10] MIPS: BCM63XX: improve BMIPS support To: Florian Fainelli Cc: Linux-MIPS , Ralf Baechle , John Crispin , Maxime Bizon , Kevin Cernekee Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37300 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jogo@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2274 Lines: 53 On Tue, Jul 16, 2013 at 3:06 PM, Florian Fainelli wrote: > Hello Jonas, > > 2013/6/29 Jonas Gorski : >> This patchset aims at unifying the different BMIPS support code to allow >> building a kernel that runs on multiple BCM63XX SoCs which might have >> different BMIPS flavours on them, regardless of SMP support enabled in >> the kernel. >> >> The first few patches clean up BMIPS itself and prepare it for multi-cpu >> support, while the latter add support to BCM63XX for running a SMP kernel >> with support for all SoCs, even those that do not have a SMP capable >> CPU. >> >> This patchset is runtime tested on BCM6348, BCM6328 and BCM6368, to >> verify that it actually does what it claims it does. >> >> Lacking hardware, it is only build tested for BMIPS4380 and BMIPS5000. >> >> Jonas Gorski (10): >> MIPS: bmips: fix compilation for BMIPS5000 >> MIPS: allow asm/cpu.h to be included from assembly >> MIPS: bmips: add macros for testing the current bmips CPU >> MIPS: bmips: change compile time checks to runtime checks >> MIPS: bmips: merge CPU options into one option >> MIPS: BCM63XX: let the individual SoCs select the appropriate CPUs >> MIPS: bmips: add a helper function for registering smp ops >> MIPS: BCM63XX: always register bmips smp ops >> MIPS: BCM63XX: change the guard to a BMIPS4350 check >> MIPS: BCM63XX: disable SMP also on BCM3368 > > After fixing the typo on BMIPS4350 vs BMIPS4380 and fixing the > following (which I will submit just in a few minutes) > > @@ -187,7 +187,7 @@ static void bmips_boot_secondary(int cpu, struct task_struct > } else { > if (cpu_is_bmips4350() || cpu_is_bmips4380()) { > /* Reset slave TP1 if booting from TP0 */ > - if (cpu_logical_map(cpu) == 0) > + if (cpu_logical_map(cpu) == 1) > set_c0_brcm_cmt_ctrl(0x01); > } else if (cpu_is_bmips5000()) { > if (cpu & 0x01) > > it works just nicely on BMIPS4380. I plan on doing some testing on > BMIPS5000 later this week. Great, thanks for testing. This change looks quite correct. I'll rebase my patchset then onto your patch. Regards Jonas From f.fainelli@gmail.com Tue Jul 16 16:27:25 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jul 2013 16:27:28 +0200 (CEST) Received: from mail-pb0-f47.google.com ([209.85.160.47]:63708 "EHLO mail-pb0-f47.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827499Ab3GPO1ZmODoB (ORCPT ); Tue, 16 Jul 2013 16:27:25 +0200 Received: by mail-pb0-f47.google.com with SMTP id rr13so759220pbb.34 for ; Tue, 16 Jul 2013 07:27:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type; bh=y9tbWHUCO2PBDlZbmewYozFDB+K2qY8v1nIUtp7Y4bQ=; b=mUEyi/l8fSFEOZ4t5yLU/gbVs+CXav8kiK1F4koNq7K4TojKnydT13/qtDydj6dQPL cdcf4slnMVrJYyZ7bs6udSip/rxLIZMhL5Ygb8Ad12Tv6nZhd81eCwFc3w5Ve/v5hWj0 oTFl/GHKLMboa240b2i3w2qwmn7DxEQaDaxJ5tA+eRrnlmdLznhKh9kNEYt5WepZXGO0 E4eR9Yg4Z4kM2YjNTNAnTRGYxanHIHr8qfSbSBsm0zmonJQhpZMtd5gSjIlmBFqqcogJ QC0GRh90HQ5jACFYWsEH9Lm8YCwg7YVSxxc73ew7vL1Fg1oI7mYvlp5UUKwTw7WGb2Uc azug== X-Received: by 10.66.9.71 with SMTP id x7mr3006971paa.37.1373984838711; Tue, 16 Jul 2013 07:27:18 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.10.101 with HTTP; Tue, 16 Jul 2013 07:26:38 -0700 (PDT) In-Reply-To: References: <1372537073-27370-1-git-send-email-jogo@openwrt.org> From: Florian Fainelli Date: Tue, 16 Jul 2013 15:26:38 +0100 X-Google-Sender-Auth: wRKFYxge9p54SVe_78ve47ka5Cc Message-ID: Subject: Re: [PATCH 00/10] MIPS: BCM63XX: improve BMIPS support To: Jonas Gorski Cc: Linux-MIPS , Ralf Baechle , John Crispin , Maxime Bizon , Kevin Cernekee Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37301 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2520 Lines: 65 2013/7/16 Jonas Gorski : > On Tue, Jul 16, 2013 at 3:06 PM, Florian Fainelli wrote: >> Hello Jonas, >> >> 2013/6/29 Jonas Gorski : >>> This patchset aims at unifying the different BMIPS support code to allow >>> building a kernel that runs on multiple BCM63XX SoCs which might have >>> different BMIPS flavours on them, regardless of SMP support enabled in >>> the kernel. >>> >>> The first few patches clean up BMIPS itself and prepare it for multi-cpu >>> support, while the latter add support to BCM63XX for running a SMP kernel >>> with support for all SoCs, even those that do not have a SMP capable >>> CPU. >>> >>> This patchset is runtime tested on BCM6348, BCM6328 and BCM6368, to >>> verify that it actually does what it claims it does. >>> >>> Lacking hardware, it is only build tested for BMIPS4380 and BMIPS5000. >>> >>> Jonas Gorski (10): >>> MIPS: bmips: fix compilation for BMIPS5000 >>> MIPS: allow asm/cpu.h to be included from assembly >>> MIPS: bmips: add macros for testing the current bmips CPU >>> MIPS: bmips: change compile time checks to runtime checks >>> MIPS: bmips: merge CPU options into one option >>> MIPS: BCM63XX: let the individual SoCs select the appropriate CPUs >>> MIPS: bmips: add a helper function for registering smp ops >>> MIPS: BCM63XX: always register bmips smp ops >>> MIPS: BCM63XX: change the guard to a BMIPS4350 check >>> MIPS: BCM63XX: disable SMP also on BCM3368 >> >> After fixing the typo on BMIPS4350 vs BMIPS4380 and fixing the >> following (which I will submit just in a few minutes) >> >> @@ -187,7 +187,7 @@ static void bmips_boot_secondary(int cpu, struct task_struct >> } else { >> if (cpu_is_bmips4350() || cpu_is_bmips4380()) { >> /* Reset slave TP1 if booting from TP0 */ >> - if (cpu_logical_map(cpu) == 0) >> + if (cpu_logical_map(cpu) == 1) >> set_c0_brcm_cmt_ctrl(0x01); >> } else if (cpu_is_bmips5000()) { >> if (cpu & 0x01) Another way would be to make the test be: cpu_logical_map(0) == 0, which seems more accurate with respect to the above comment. >> >> it works just nicely on BMIPS4380. I plan on doing some testing on >> BMIPS5000 later this week. > > Great, thanks for testing. This change looks quite correct. I'll > rebase my patchset then onto your patch. > > > Regards > Jonas -- Florian From Steven.Hill@imgtec.com Tue Jul 16 21:17:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jul 2013 21:17:59 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:53741 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827823Ab3GPTRz6UlWh (ORCPT ); Tue, 16 Jul 2013 21:17:55 +0200 Message-ID: <51E59BFF.3030808@imgtec.com> Date: Tue, 16 Jul 2013 14:16:15 -0500 From: "Steven J. Hill" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 MIME-Version: 1.0 To: Subject: Complete kernel source trees for ERLite-3. Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.159.90] X-SEF-Processed: 7_3_0_01192__2013_07_16_20_17_49 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37302 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1484 Lines: 39 Hello. If anyone is interested I have created the complete original kernel source trees for the v1.0.2, v1.1.0 and v1.2.0 firmware releases on the ERLite-3. They were made from the following components: COMMON * Cavium SDK 2.0.0 - free download from * git tag '2.6.32.13' V1.0.2 * GPL.ERLite-3.v1.0.2.4507738.tbz2 - free download from * source/kernel_4503552-gcc4cdf7.tgz * source/cavm-executive_4493936-g009d77b.tgz V1.1.0 * GPL.ER-e100.v1.1.0.4543695.tbz2 - free download from * source/kernel_4539683-g7b3312f.tgz * source/cavm-executive_4539683-g6868fcf.tgz V1.2.0 * GPL.ER-e100.v1.2.0.4574253.tbz2 - free download from * source/kernel_4567941-g0568484.tgz * source/cavm-executive_4567941-gcc0028b.tgz git repo: git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill.git branch: erlite3-2.6 tags: erlite3-v1.0.2, erlite3-v1.1.0, erlite3-v1.2.0 I also created a 'arch/mips/configs/erlite3_defconfig' config file to make things easier. I can confirm that using the 'erlite3-v1.0.2' tag my built kernel worked perfectly with my ERLite-3, since it has not had a firmware upgrade yet. All the existing modules including the proprietary ones worked. However, do not mix kernel and firmware versions if you are going to build the kernel from source. Special thanks to An-Cheng Huang for his help and answering all my questions. Steve From aaro.koskinen@iki.fi Tue Jul 16 21:55:53 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Jul 2013 21:55:58 +0200 (CEST) Received: from filtteri5.pp.htv.fi ([213.243.153.188]:49626 "EHLO filtteri5.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827823Ab3GPTzwYxkmD (ORCPT ); Tue, 16 Jul 2013 21:55:52 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri5.pp.htv.fi (Postfix) with ESMTP id 525FF5A6EAC; Tue, 16 Jul 2013 22:55:49 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp6.welho.com ([213.243.153.40]) by localhost (filtteri5.pp.htv.fi [213.243.153.188]) (amavisd-new, port 10024) with ESMTP id hkkxChkMnbAd; Tue, 16 Jul 2013 22:55:44 +0300 (EEST) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp6.welho.com (Postfix) with SMTP id 4BEF45BC003; Tue, 16 Jul 2013 22:55:43 +0300 (EEST) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Tue, 16 Jul 2013 22:55:43 +0300 Date: Tue, 16 Jul 2013 22:55:43 +0300 From: Aaro Koskinen To: "Steven J. Hill" Cc: linux-mips@linux-mips.org Subject: Re: Complete kernel source trees for ERLite-3. Message-ID: <20130716195543.GD14385@blackmetal.musicnaut.iki.fi> References: <51E59BFF.3030808@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <51E59BFF.3030808@imgtec.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37303 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 504 Lines: 11 On Tue, Jul 16, 2013 at 02:16:15PM -0500, Steven J. Hill wrote: > If anyone is interested I have created the complete original kernel > source trees for the v1.0.2, v1.1.0 and v1.2.0 firmware releases on > the ERLite-3. They were made from the following components: You should be also able to run mainline kernels starting from v3.11-rc1, but most likely only with your own userspace. The stuff you posted is of course a valuable reference when improving the mainline kernel support for this board. A. From kamal@canonical.com Wed Jul 17 00:53:59 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Jul 2013 00:54:17 +0200 (CEST) Received: from youngberry.canonical.com ([91.189.89.112]:35272 "EHLO youngberry.canonical.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835081Ab3GPWx7C1TVz (ORCPT ); Wed, 17 Jul 2013 00:53:59 +0200 Received: from c-67-160-231-162.hsd1.ca.comcast.net ([67.160.231.162] helo=fourier) by youngberry.canonical.com with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1UzE85-00042y-Dd; Tue, 16 Jul 2013 22:53:57 +0000 Received: from kamal by fourier with local (Exim 4.80) (envelope-from ) id 1UzE83-00070L-4D; Tue, 16 Jul 2013 15:53:55 -0700 From: Kamal Mostafa To: David Daney Cc: linux-mips@linux-mips.org, Ralf Baechle , Kamal Mostafa , kernel-team@lists.ubuntu.com Subject: [ 3.8.y.z extended stable ] Patch "MIPS: Octeon: Don't clobber bootloader data structures." has been added to staging queue Date: Tue, 16 Jul 2013 15:53:55 -0700 Message-Id: <1374015235-26892-1-git-send-email-kamal@canonical.com> X-Mailer: git-send-email 1.8.1.2 X-Extended-Stable: 3.8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37304 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kamal@canonical.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 597 Lines: 21 This is a note to let you know that I have just added a patch titled MIPS: Octeon: Don't clobber bootloader data structures. to the linux-3.8.y-queue branch of the 3.8.y.z extended stable tree which can be found at: http://kernel.ubuntu.com/git?p=ubuntu/linux.git;a=shortlog;h=refs/heads/linux-3.8.y-queue This patch is scheduled to be released in version 3.8.13.5. If you, or anyone else, feels it should not be added to this tree, please reply to this email. For more information about the 3.8.y.z tree, see https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable Thanks. -Kamal ------ From a884f06ff82f83c2e1a857b060a6a6d411789697 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 12 Jun 2013 17:28:33 +0000 Subject: MIPS: Octeon: Don't clobber bootloader data structures. Content-Length: 1425 Lines: 38 commit d949b4fe6d23dd92b5fa48cbf7af90ca32beed2e upstream. Commit abe77f90dc (MIPS: Octeon: Add kexec and kdump support) added a bootmem region for the kernel image itself. The problem is that this is rounded up to a 0x100000 boundary, which is memory that may not be owned by the kernel. Depending on the kernel's configuration based size, this 'extra' memory may contain data passed from the bootloader to the kernel itself, which if clobbered makes the kernel crash in various ways. The fix: Quit rounding the size up, so that we only use memory assigned to the kernel. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5449/ Signed-off-by: Ralf Baechle Signed-off-by: Kamal Mostafa --- arch/mips/cavium-octeon/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index d7e0a09..1271047 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -990,7 +990,7 @@ void __init plat_mem_setup(void) cvmx_bootmem_unlock(); /* Add the memory region for the kernel. */ kernel_start = (unsigned long) _text; - kernel_size = ALIGN(_end - _text, 0x100000); + kernel_size = _end - _text; /* Adjust for physical offset. */ kernel_start &= ~0xffffffff80000000ULL; -- 1.8.1.2 From f.fainelli@gmail.com Tue Jul 16 23:37:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Jul 2013 09:13:15 +0200 (CEST) Received: from mail-ee0-f47.google.com ([74.125.83.47]:37481 "EHLO mail-ee0-f47.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835056Ab3GPVhkpqvEJ convert rfc822-to-8bit (ORCPT ); Tue, 16 Jul 2013 23:37:40 +0200 Received: by mail-ee0-f47.google.com with SMTP id e49so641113eek.34 for ; Tue, 16 Jul 2013 14:37:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:organization:user-agent :in-reply-to:references:mime-version:content-transfer-encoding :content-type; bh=6Ciq+dPUd57ZMNBg6C7lTgzqqaC1KBlyqsZiS0dONdI=; b=jpeTV6F0j5+tfDs1035FPaXvAb1StPfTLPj4jlxZGJIwsD1GZGEjP2Nq9jxtYvSa9r 8A7QN8PrEB9g01Gt7wpJoBib/YZO7Zl5k5eq40+0sDM+WP87ZR1xXLfUvZdgfTMw9fC3 pYh/0lNKxd/wMUmcJfe28gEIPbibfpkTgP+gwCugJ7QzGlYOOE7Jvlnr58trJhD1/RFb P+w8RBnb/91UWz8/JFk5Uedz915onz46AYCOoz1eiAfDRQ7KCwA4mtiq7ePjtSt7sQgY qPT0n/Ksr2mviGdcnJry76+HKywOuX0GhCVPYL57TZTwYpn57VP3g8xqkcCKK48CEnjc hw+w== X-Received: by 10.15.61.67 with SMTP id h43mr3354967eex.102.1374010654977; Tue, 16 Jul 2013 14:37:34 -0700 (PDT) Received: from lenovo.localnet (cpc24-aztw25-2-0-cust938.aztw.cable.virginmedia.com. [92.233.35.171]) by mx.google.com with ESMTPSA id l42sm5763008eeo.14.2013.07.16.14.37.32 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 16 Jul 2013 14:37:33 -0700 (PDT) From: Florian Fainelli To: Jonas Gorski Cc: Linux-MIPS , Ralf Baechle , John Crispin , Maxime Bizon , Kevin Cernekee Subject: Re: [PATCH 00/10] MIPS: BCM63XX: improve BMIPS support Date: Tue, 16 Jul 2013 22:37:30 +0100 Message-ID: <3411491.V9mU8AUdtK@lenovo> Organization: OpenWrt User-Agent: KMail/4.10.4 (Linux/3.8.0-26-generic; KDE/4.10.4; x86_64; ; ) In-Reply-To: References: <1372537073-27370-1-git-send-email-jogo@openwrt.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37305 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1969 Lines: 42 Le mardi 16 juillet 2013 14:06:36 Florian Fainelli a crit : > Hello Jonas, > > 2013/6/29 Jonas Gorski : > > This patchset aims at unifying the different BMIPS support code to allow > > building a kernel that runs on multiple BCM63XX SoCs which might have > > different BMIPS flavours on them, regardless of SMP support enabled in > > the kernel. > > > > The first few patches clean up BMIPS itself and prepare it for multi-cpu > > support, while the latter add support to BCM63XX for running a SMP kernel > > with support for all SoCs, even those that do not have a SMP capable > > CPU. > > > > This patchset is runtime tested on BCM6348, BCM6328 and BCM6368, to > > verify that it actually does what it claims it does. > > > > Lacking hardware, it is only build tested for BMIPS4380 and BMIPS5000. > > > > Jonas Gorski (10): > > MIPS: bmips: fix compilation for BMIPS5000 > > MIPS: allow asm/cpu.h to be included from assembly > > MIPS: bmips: add macros for testing the current bmips CPU > > MIPS: bmips: change compile time checks to runtime checks > > MIPS: bmips: merge CPU options into one option > > MIPS: BCM63XX: let the individual SoCs select the appropriate CPUs > > MIPS: bmips: add a helper function for registering smp ops > > MIPS: BCM63XX: always register bmips smp ops > > MIPS: BCM63XX: change the guard to a BMIPS4350 check > > MIPS: BCM63XX: disable SMP also on BCM3368 > > After fixing the typo on BMIPS4350 vs BMIPS4380 and fixing the > following (which I will submit just in a few minutes) I just gave this patchset a try on a BMIPS5000 system, but unfortunately the kernel crashes early on due to a change in smp-bmips.c. It crashed in mem_init(), and adding a printk in bmips_ebase_setup() in the final else clause before the return did no longer make the kernel crash. This could be some nasty cache issue and simply changing the kernel size did help. Will investigate this more. -- Florian From tung7970@gmail.com Wed Jul 17 12:00:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Jul 2013 12:00:15 +0200 (CEST) Received: from mail-pb0-f44.google.com ([209.85.160.44]:62625 "EHLO mail-pb0-f44.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823064Ab3GQKAE4XHKL (ORCPT ); Wed, 17 Jul 2013 12:00:04 +0200 Received: by mail-pb0-f44.google.com with SMTP id uo1so1726282pbc.17 for ; Wed, 17 Jul 2013 02:59:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:mime-version:content-type :content-disposition:user-agent; bh=Gski+ArHpSihBb4cPMua6ET6KXkXgjSNv6qwcTzRVJY=; b=CSRjjo0DMpoCPQQHTSjPTDNIErLPFoLlcIUqwwIGP+PzICFDxpKlnQtZVoUgv9GW1Y 11cRH3fLzJZwB7rS+efamdfX5cUq5y2sjU+Sx6AevpidoQf9sq00x73Fhbl7YPxQlRaP WGr/rVjBQAv96oz4APcklkecjQJjGdF7uxgmu3m2emz2g/G4M9ywxEb/crxkNsklfD63 i0/fLIlZf45TeRxhQ3+CLN/viTQEej1KMInLWKMeCLWWX5RQAStkDmRUARF6KXGHhtov c0FSVxRPRtuxSKiDLMRTV4tdefcDNcqib88Sqpw91WU0f6JzZu5rd2ncTFEXuOzpWayu 8Avw== X-Received: by 10.68.171.99 with SMTP id at3mr6077905pbc.64.1374055197375; Wed, 17 Jul 2013 02:59:57 -0700 (PDT) Received: from hades.local ([116.59.227.231]) by mx.google.com with ESMTPSA id bg3sm6895762pbb.44.2013.07.17.02.59.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 17 Jul 2013 02:59:56 -0700 (PDT) Date: Wed, 17 Jul 2013 17:59:47 +0800 From: Tony Wu To: ralf@linux-mips.org, Jayachandran C Cc: linux-mips@linux-mips.org Subject: [PATCH 1/2] MIPS: tlbex: Fix typo in r3000 tlb store handler Message-ID: <20130717175840-tung7970@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37306 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tung7970@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 694 Lines: 24 Should test against handle_tlbs_end, not handle_tlbs. Signed-off-by: Tony Wu Cc: Jayachandran C --- arch/mips/mm/tlbex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 9ab0f90..605b6fc 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1803,7 +1803,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if (p >= handle_tlbs) + if (p >= handle_tlbs_end) panic("TLB store handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); -- 1.7.10.2 From tung7970@gmail.com Wed Jul 17 12:01:46 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Jul 2013 12:01:48 +0200 (CEST) Received: from mail-pd0-f177.google.com ([209.85.192.177]:54590 "EHLO mail-pd0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824770Ab3GQKBqOz1lM (ORCPT ); Wed, 17 Jul 2013 12:01:46 +0200 Received: by mail-pd0-f177.google.com with SMTP id p10so1657590pdj.8 for ; Wed, 17 Jul 2013 03:01:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=5x4TZyTQIR+JwivSz4s2GpgVdwcd74Ryl0x/YLsOgXM=; b=wxELLum1n+gWwCtim/kv49FiNntQWkjFQBumUBP3mU9aNzQiyKIXhLggfQ1P55Sjyv RXGqib5pRLoeEtPjV3B4hPzjBMekMwbAJAXlxen0Sl+ysQOwNC8pWVY2jRd/9+z0E2q5 0dZPkZ3OT38kY2CXwbt1c9UM4lfHLMM6fvlSa2/QqVJUdcJiEF3r3yuNCVLFWm0yYypt 6as9MWi8KbiBOMOz833XddXuOiLn+u7VmvVrHXnV4S1RoxOtyCRdAeqeK895ITN3YXTf 06Log6B0erGiTmqbJ+Xia3GHXzblICR7ws3i52CEMoaEbJO/Tcr2DaZo3uhuMPpB2vmb 9N1A== X-Received: by 10.66.27.143 with SMTP id t15mr2937752pag.171.1374055299660; Wed, 17 Jul 2013 03:01:39 -0700 (PDT) Received: from hades.local ([116.59.227.231]) by mx.google.com with ESMTPSA id om2sm6935106pbb.34.2013.07.17.03.01.35 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 17 Jul 2013 03:01:39 -0700 (PDT) Date: Wed, 17 Jul 2013 18:01:29 +0800 From: Tony Wu To: ralf@linux-mips.org, Jayachandran C Cc: linux-mips@linux-mips.org Subject: [PATCH 2/2] MIPS: tlbex: Guard tlbmiss_handler_setup_pgd Message-ID: <20130717180052-tung7970@googlemail.com> References: <20130717175840-tung7970@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130717175840-tung7970@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37307 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tung7970@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 688 Lines: 29 tlbmiss_handler_setup_pgd* are only referenced when CONFIG_MIPS_PGD_C0_CONTEXT is defined. Signed-off-by: Tony Wu Cc: Jayachandran C --- arch/mips/mm/tlb-funcs.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S index 30a494d..79bca31 100644 --- a/arch/mips/mm/tlb-funcs.S +++ b/arch/mips/mm/tlb-funcs.S @@ -16,10 +16,12 @@ #define FASTPATH_SIZE 128 +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT LEAF(tlbmiss_handler_setup_pgd) .space 16 * 4 END(tlbmiss_handler_setup_pgd) EXPORT(tlbmiss_handler_setup_pgd_end) +#endif LEAF(handle_tlbm) .space FASTPATH_SIZE * 4 -- 1.7.10.2 From jchandra@broadcom.com Wed Jul 17 13:25:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Jul 2013 13:25:45 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:1258 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819547Ab3GQLZljUslr (ORCPT ); Wed, 17 Jul 2013 13:25:41 +0200 Received: from [10.9.208.53] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 17 Jul 2013 04:21:37 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server (TLS) id 14.1.438.0; Wed, 17 Jul 2013 04:25:23 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.1.438.0; Wed, 17 Jul 2013 04:25:23 -0700 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 5B15CF2D72; Wed, 17 Jul 2013 04:25:22 -0700 (PDT) From: "Jayachandran C" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: "Ganesan Ramalingam" , "Jayachandran C" Subject: [PATCH 1/2] MIPS: Netlogic: Fix USB block's coherent DMA mask Date: Wed, 17 Jul 2013 16:57:25 +0530 Message-ID: <1374060446-25902-1-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-WSS-ID: 7DF8A1CB31W52891626-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37308 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 956 Lines: 29 From: Ganesan Ramalingam The on-chip USB controller on Netlogic XLP does not suppport DMA beyond 32-bit physical address. Set the coherent_dma_mask of the USB in its PCI fixup to support this. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C --- arch/mips/netlogic/xlp/usb-init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c index 9c401dd..ef3897e 100644 --- a/arch/mips/netlogic/xlp/usb-init.c +++ b/arch/mips/netlogic/xlp/usb-init.c @@ -119,7 +119,7 @@ static u64 xlp_usb_dmamask = ~(u32)0; static void nlm_usb_fixup_final(struct pci_dev *dev) { dev->dev.dma_mask = &xlp_usb_dmamask; - dev->dev.coherent_dma_mask = DMA_BIT_MASK(64); + dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); switch (dev->devfn) { case 0x10: dev->irq = PIC_EHCI_0_IRQ; -- 1.7.9.5 From jchandra@broadcom.com Wed Jul 17 13:26:01 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Jul 2013 13:26:05 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:1259 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823064Ab3GQLZlwbwM7 (ORCPT ); Wed, 17 Jul 2013 13:25:41 +0200 Received: from [10.9.208.57] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 17 Jul 2013 04:21:39 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.438.0; Wed, 17 Jul 2013 04:25:25 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.1.438.0; Wed, 17 Jul 2013 04:25:25 -0700 Received: from netl-snoppy.ban.broadcom.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 35FDFF2D73; Wed, 17 Jul 2013 04:25:23 -0700 (PDT) From: "Jayachandran C" To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: "Jayachandran C" Subject: [PATCH 2/2] MIPS: Netlogic: Add XLP PIC irqdomain Date: Wed, 17 Jul 2013 16:57:26 +0530 Message-ID: <1374060446-25902-2-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1374060446-25902-1-git-send-email-jchandra@broadcom.com> References: <1374060446-25902-1-git-send-email-jchandra@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7DF8A1C931W52891639-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37309 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3774 Lines: 139 Add a legacy irq domain for the XLP PIC interrupts. This will be used when interrupts are assigned from the device tree. This change is required after commit c5cdc67 "irqdomain: Remove temporary MIPS workaround code". Signed-off-by: Jayachandran C --- arch/mips/netlogic/common/irq.c | 68 ++++++++++++++++++++++++++++++------ arch/mips/netlogic/dts/xlp_evp.dts | 3 +- arch/mips/netlogic/dts/xlp_svp.dts | 3 +- 3 files changed, 61 insertions(+), 13 deletions(-) diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c index 73facb2..bfb2e25 100644 --- a/arch/mips/netlogic/common/irq.c +++ b/arch/mips/netlogic/common/irq.c @@ -40,6 +40,10 @@ #include #include +#include +#include +#include + #include #include #include @@ -223,17 +227,6 @@ static void nlm_init_node_irqs(int node) nodep->irqmask = irqmask; } -void __init arch_init_irq(void) -{ - /* Initialize the irq descriptors */ - nlm_init_percpu_irqs(); - nlm_init_node_irqs(0); - write_c0_eimr(nlm_current_node()->irqmask); -#if defined(CONFIG_CPU_XLR) - nlm_setup_fmn_irq(); -#endif -} - void nlm_smp_irq_init(int hwcpuid) { int node, cpu; @@ -266,3 +259,56 @@ asmlinkage void plat_irq_dispatch(void) /* top level irq handling */ do_IRQ(nlm_irq_to_xirq(node, i)); } + +#ifdef CONFIG_OF +static struct irq_domain *xlp_pic_domain; + +static const struct irq_domain_ops xlp_pic_irq_domain_ops = { + .xlate = irq_domain_xlate_onetwocell, +}; + +static int __init xlp_of_pic_init(struct device_node *node, + struct device_node *parent) +{ + const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1; + struct resource res; + int socid, ret; + + /* we need a hack to get the PIC's SoC chip id */ + ret = of_address_to_resource(node, 0, &res); + if (ret < 0) { + pr_err("PIC %s: reg property not found!\n", node->name); + return -EINVAL; + } + socid = (res.start >> 18) & 0x3; + xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs, + nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE, + &xlp_pic_irq_domain_ops, NULL); + if (xlp_pic_domain == NULL) { + pr_err("PIC %s: Creating legacy domain failed!\n", node->name); + return -EINVAL; + } + pr_info("Node %d: IRQ domain created for PIC@%pa\n", socid, + &res.start); + return 0; +} + +static struct of_device_id __initdata xlp_pic_irq_ids[] = { + { .compatible = "netlogic,xlp-pic", .data = xlp_of_pic_init }, + {}, +}; +#endif + +void __init arch_init_irq(void) +{ + /* Initialize the irq descriptors */ + nlm_init_percpu_irqs(); + nlm_init_node_irqs(0); + write_c0_eimr(nlm_current_node()->irqmask); +#if defined(CONFIG_CPU_XLR) + nlm_setup_fmn_irq(); +#endif +#if defined(CONFIG_OF) + of_irq_init(xlp_pic_irq_ids); +#endif +} diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts index e14f423..0640703 100644 --- a/arch/mips/netlogic/dts/xlp_evp.dts +++ b/arch/mips/netlogic/dts/xlp_evp.dts @@ -76,10 +76,11 @@ }; }; pic: pic@4000 { - interrupt-controller; + compatible = "netlogic,xlp-pic"; #address-cells = <0>; #interrupt-cells = <1>; reg = <0 0x4000 0x200>; + interrupt-controller; }; nor_flash@1,0 { diff --git a/arch/mips/netlogic/dts/xlp_svp.dts b/arch/mips/netlogic/dts/xlp_svp.dts index 8af4bdb..9c5db10 100644 --- a/arch/mips/netlogic/dts/xlp_svp.dts +++ b/arch/mips/netlogic/dts/xlp_svp.dts @@ -76,10 +76,11 @@ }; }; pic: pic@4000 { - interrupt-controller; + compatible = "netlogic,xlp-pic"; #address-cells = <0>; #interrupt-cells = <1>; reg = <0 0x4000 0x200>; + interrupt-controller; }; nor_flash@1,0 { -- 1.7.9.5 From paravoid@debian.org Thu Jul 18 16:53:12 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 16:53:26 +0200 (CEST) Received: from scrooge.tty.gr ([62.217.125.135]:46027 "EHLO mail.tty.gr" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6838429Ab3GRMZ7YY3G7 (ORCPT ); Thu, 18 Jul 2013 14:25:59 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=tty.gr; s=x; h=Content-Type:MIME-Version:Message-ID:Subject:To:From:Date; bh=P23XtTqmqZlwaqKBzwba+u7OQbO9VUYLFULHS2gtG3M=; b=csZJlp0SQzz6Fot6rLPWGDsPN6Jjao76esdMOBx6IXsQTBufmce8NS4cJG32E/H49V0sES0lpEanayHob4ejvJy2t/bkasFsXVJ5QjZC67t+qItV+GnXBjjUs092fCKr; Received: from [2001:648:2001:f000:223:aeff:fe91:b5f4] (helo=serenity.void.home) by mail.tty.gr (envelope-from ) with esmtpsa (tls_cipher TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80 (Debian GNU/Linux)) id 1UznHR-0007Ok-2c; Thu, 18 Jul 2013 15:25:57 +0300 Received: from paravoid by serenity.void.home with local (Exim 4.80) (envelope-from ) id 1UznHQ-0005Lr-OR; Thu, 18 Jul 2013 15:25:56 +0300 Date: Thu, 18 Jul 2013 15:25:56 +0300 From: Faidon Liambotis To: linux-mips@linux-mips.org, David Daney Subject: octeon: oops/panic with CONFIG_SERIO_I8042=y Message-ID: <20130718122556.GA19040@tty.gr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37310 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paravoid@debian.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3924 Lines: 71 Hi, My goal is to run a standard Debian kernel and its octeon variant[1] on the Ubiquity EdgeRouter Lite. The ERLite needs a couple of patches to boot and work (octeon-ethernet patch, octeon-usb driver) but these are already merged 3.11 and I'll file Debian bugs to enable those settings appropriately. 1: e.g. http://packages.debian.org/sid/linux-image-3.10-1-octeon However, when trying to boot a standard Debian kernel in the ERLite I get a 7s delay followed by an oops for a Data bus error on i8042_flush() and ending up with a panic. It looks like the kernel is built with CONFIG_SERIO_I8042=y. The Octeon machine Debian owns prints "i8042: No controller found" but works nevertheless. This isn't the case with the ERLite; I tried 3.2 & 3.10 and got the same oops which went away as soon as I disabled CONFIG_SERIO_I8042. Are there even any octeon machines with i8042 anyway? Should I request for the setting to be disabled irrespective of this bug? The oops is as follows: [ 1.702762] ehci-pci: EHCI PCI platform driver [ 1.707913] usbcore: registered new interface driver usb-storage [ 8.591312] Data bus error, epc == ffffffff81446838, ra == ffffffff814467f0 [ 8.598102] Oops[#1]: [ 8.600360] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0 #5 [ 8.606253] task: a80000041f869540 ti: a80000041f86c000 task.ti: a80000041f86c000 [ 8.613706] $ 0 : 0000000000000000 0000000000000000 0000000000000000 0000000000010000 [ 8.621684] $ 4 : 0000000000000000 a80000041f1bbb40 000000000000006f ffffffff816ffe60 [ 8.629662] $ 8 : 0000000000000000 000000000000005b 726564206e657720 696e746572666163 [ 8.637640] $12 : 0000000000000000 ffffffff8136b0dc ffffffff81790000 0000000000000000 [ 8.645619] $16 : 80011a0400000064 80011a0400000000 0000000000000010 ffffffff817a0000 [ 8.653597] $20 : ffffffff817a0000 0000000000000001 ffffffff81770e20 ffffffff817a0000 [ 8.661575] $24 : 0000000000000004 ffffffff81790000 [ 8.669553] $28 : a80000041f86c000 a80000041f86fd70 0000000000000000 ffffffff814467f0 [ 8.677532] Hi : 0000000000acd49d [ 8.681088] Lo : 0e5604189441f8e5 [ 8.684661] epc : ffffffff81446838 i8042_flush+0x80/0x118 [ 8.690194] Not tainted [ 8.692975] ra : ffffffff814467f0 i8042_flush+0x38/0x118 [ 8.698518] Status: 10008ce2 KX SX UX KERNEL EXL [ 8.703201] Cause : 4080801c [ 8.706064] PrId : 000d0601 (Cavium Octeon+) [ 8.710398] Modules linked in: [ 8.713439] Process swapper/0 (pid: 1, threadinfo=a80000041f86c000, task=a80000041f869540, tls=0000000000000000) [ 8.723580] Stack : ffffffff81700000 ffffffff81751158 0000000000000000 ffffffff8175f2f8 ffffffff817361d8 ffffffff8175f288 ffffffff81770e20 ffffffff816c0000 000000000000008c ffffffff817511ac 0000000000000000 ffffffff81780000 ffffffff81751158 ffffffff811004e0 ffffffff817361d8 0000000000000030 ffffffff81780000 0000000000000007 ffffffff8175f2f8 ffffffff81736b50 ffffffff81595080 0000000000000000 ffffffff81780000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ffffffff8159509c ffffffff81595080 0000000000000000 0000000000000000 ffffffff8111a124 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ... [ 8.788447] Call Trace: [ 8.790882] [] i8042_flush+0x80/0x118 [ 8.796092] [] i8042_init+0x54/0xf0 [ 8.801118] [] do_one_initcall+0xe0/0x130 [ 8.806658] [ 8.808132] Code: 14800017 27de0001 92020000 <305600ff> cac00003 24040032 17d2fff4 00200825 6684d338 [ 8.820195] ---[ end trace 76cca175541407ab ]--- [ 8.824650] note: swapper/0[1] exited with preempt_count 1 [ 8.830188] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 8.830188] Regards, Faidon From tung7970@gmail.com Thu Jul 18 16:55:57 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 16:56:01 +0200 (CEST) Received: from mail-pb0-f43.google.com ([209.85.160.43]:57048 "EHLO mail-pb0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6838172Ab3GRKrtO4wOV (ORCPT ); Thu, 18 Jul 2013 12:47:49 +0200 Received: by mail-pb0-f43.google.com with SMTP id md12so3010133pbc.2 for ; Thu, 18 Jul 2013 03:47:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=5x4TZyTQIR+JwivSz4s2GpgVdwcd74Ryl0x/YLsOgXM=; b=x8ItLZY12w8ddxUpL+JPKUU7x1SUwj+yTPQwRAqRY7xLDaBp9+HGx7oOFx0LkQundL cI9y3ySKrU3pnNT/kdyu9yzJvRAeQA6oDjwl2oHokQ2AZsSWhuXEqKZDJ+b/9bTk0vu+ uRA2Mk7S1Ujct+SObh5vqU35N9M42YL3zNck/tO/zTUgJXFnH9bDMriLSXsL6HGNPNrB FVJVSSIbrRyhAIR5dRuZ7I300nfQYdHy7kdG5REEjo9LrN21EN01oIi9cIfGKX//D9Xu 0niE6g7TC+N+3eFC0KhZl4U3oLOytZACFBHT+gZ0ZzURuI0xzBk+akuGeXk39w6Ly5ky 5qiQ== X-Received: by 10.68.243.65 with SMTP id ww1mr11629607pbc.62.1374144462827; Thu, 18 Jul 2013 03:47:42 -0700 (PDT) Received: from hades (111-243-154-117.dynamic.hinet.net. [111.243.154.117]) by mx.google.com with ESMTPSA id z14sm13177224pbt.0.2013.07.18.03.47.40 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Jul 2013 03:47:42 -0700 (PDT) Date: Thu, 18 Jul 2013 18:47:37 +0800 From: Tony Wu To: ralf@linux-mips.org, "Jayachandran C." Cc: linux-mips@linux-mips.org Subject: [PATCH v2 2/2] MIPS: tlbex: Guard tlbmiss_handler_setup_pgd Message-ID: <20130718184656-tung7970@googlemail.com> References: <20130718184440-tung7970@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130718184440-tung7970@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37311 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tung7970@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 687 Lines: 28 tlbmiss_handler_setup_pgd* are only referenced when CONFIG_MIPS_PGD_C0_CONTEXT is defined. Signed-off-by: Tony Wu Cc: Jayachandran C --- arch/mips/mm/tlb-funcs.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S index 30a494d..79bca31 100644 --- a/arch/mips/mm/tlb-funcs.S +++ b/arch/mips/mm/tlb-funcs.S @@ -16,10 +16,12 @@ #define FASTPATH_SIZE 128 +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT LEAF(tlbmiss_handler_setup_pgd) .space 16 * 4 END(tlbmiss_handler_setup_pgd) EXPORT(tlbmiss_handler_setup_pgd_end) +#endif LEAF(handle_tlbm) .space FASTPATH_SIZE * 4 -- 1.7.10.2 From tung7970@gmail.com Thu Jul 18 16:56:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 16:56:49 +0200 (CEST) Received: from mail-pa0-f47.google.com ([209.85.220.47]:49456 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6838164Ab3GRKp7UfYLw (ORCPT ); Thu, 18 Jul 2013 12:45:59 +0200 Received: by mail-pa0-f47.google.com with SMTP id kl14so3037043pab.20 for ; Thu, 18 Jul 2013 03:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:mime-version:content-type :content-disposition:user-agent; bh=EA+ykVqBhamyPl4nAm6Rmhbve9Z8daMF0j9jM1jrbGU=; b=Gh4HBqreYZAUJZdieRAJJ3bAYdGq7Dbl1hzDSFLi3yo+fiWbKT8C2qvgpFFMneyypn t5SKZ9iXIIIAQFbBo8CzIIwCqxwShU+zikUnrigE9jqHAh9rC0TilfLs+3yWB/sht4QT uoCvXsNHiPdhoFKcqgIi5wIIa6ZpiL13cJf8l9o0CRjYQxK8vu1B6p1mRFMbn16KHQin o3PnGiaqgY7TV+CW/p0qYOGNwvezIvCZXyLPuqHXmpW0cCkAHIcybpjuBrz+I9FG82Um LhAzCRt9S3VWbztIky5Ix6dpY2zyvuy1Rnu2BQ0bK9SSQugGEJwtATDxt7kePgEcrf/r uXPw== X-Received: by 10.68.189.228 with SMTP id gl4mr11537613pbc.57.1374144352897; Thu, 18 Jul 2013 03:45:52 -0700 (PDT) Received: from hades (111-243-154-117.dynamic.hinet.net. [111.243.154.117]) by mx.google.com with ESMTPSA id ib9sm13037893pbc.43.2013.07.18.03.45.49 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Jul 2013 03:45:52 -0700 (PDT) Date: Thu, 18 Jul 2013 18:45:47 +0800 From: Tony Wu To: ralf@linux-mips.org, "Jayachandran C." Cc: linux-mips@linux-mips.org Subject: [PATCH v2 1/2] MIPS: tlbex: Fix typo in r3000 tlb store handler Message-ID: <20130718184440-tung7970@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37312 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tung7970@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 853 Lines: 26 commit 6ba045f (MIPS: Move generated code to .text for microMIPS) causes a panic at boot. The handler builder should test against handle_tlbs_end, not handle_tlbs. Signed-off-by: Tony Wu Cc: Jayachandran C Acked-by: Jayachandran C. --- arch/mips/mm/tlbex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 9ab0f90..605b6fc 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1803,7 +1803,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if (p >= handle_tlbs) + if (p >= handle_tlbs_end) panic("TLB store handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); -- 1.7.10.2 From tung7970@gmail.com Thu Jul 18 16:57:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 16:57:14 +0200 (CEST) Received: from mail-pa0-f48.google.com ([209.85.220.48]:48788 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6838155Ab3GRKnUVLzZF (ORCPT ); Thu, 18 Jul 2013 12:43:20 +0200 Received: by mail-pa0-f48.google.com with SMTP id kp12so3056350pab.21 for ; Thu, 18 Jul 2013 03:43:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=EgK2CAQTLC9wDoXmPxosI658puj7lXl3CkgHeVRan+I=; b=y1YRN2t9QhIgTw+cecK5Pzyoxpo6nis26iQ81UUFs9ESFk66zYch5DXpvGHBhrb9GV 9koAcWDVR1wdZFYNgTqoYOTGdvNJEfBQsZ04/RBkDFwb92RFnjmxirRA02bGVPn/H83K p0FJitb9DHteemdbGi5UTV9DlWzBr2iJ2yTsz93Yf87KMDGyqB6UM9qPZeJj3TMM97DF 4E1CS3JL9Iag5reElFoFyE3oqw9Z6S2Hm0HHu7YGdm9Uyzxr2j3+HmF0tbGqLyaitGwT CH7qL+VYkPQBrm17BrHV8tHu/AMLNJwUw+F9T5ogNCBpBCu3EfCiQQVxMzZjxOlT10Wt P5nQ== X-Received: by 10.66.40.212 with SMTP id z20mr2996726pak.51.1374144193205; Thu, 18 Jul 2013 03:43:13 -0700 (PDT) Received: from hades (111-243-154-117.dynamic.hinet.net. [111.243.154.117]) by mx.google.com with ESMTPSA id te9sm16010844pab.6.2013.07.18.03.43.10 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Jul 2013 03:43:12 -0700 (PDT) Date: Thu, 18 Jul 2013 18:43:07 +0800 From: Tony Wu To: "Jayachandran C." Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: tlbex: Fix typo in r3000 tlb store handler Message-ID: <20130718184214-tung7970@googlemail.com> References: <20130717175840-tung7970@googlemail.com> <20130718064106.GA24373@jayachandranc.netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20130718064106.GA24373@jayachandranc.netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37313 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tung7970@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1226 Lines: 39 On Thu, Jul 18, 2013 at 12:11:07PM +0530, Jayachandran C. wrote: > On Wed, Jul 17, 2013 at 05:59:47PM +0800, Tony Wu wrote: > > Should test against handle_tlbs_end, not handle_tlbs. > > > > Signed-off-by: Tony Wu > > Cc: Jayachandran C > > --- > > arch/mips/mm/tlbex.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > > index 9ab0f90..605b6fc 100644 > > --- a/arch/mips/mm/tlbex.c > > +++ b/arch/mips/mm/tlbex.c > > @@ -1803,7 +1803,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void) > > uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); > > uasm_i_nop(&p); > > > > - if (p >= handle_tlbs) > > + if (p >= handle_tlbs_end) > > panic("TLB store handler fastpath space exceeded"); > > > > uasm_resolve_relocs(relocs, labels); > > Thanks for fixing this. > > Acked-by: Jayachandran C. > > You should add the commit which caused the trouble to the commit message, > like: > > commit 6ba045f (MIPS: Move generated code to .text for microMIPS) causes > a panic at boot. > > JC. Thanks for the comment. Will send the updated patch. Tony From jchandra@broadcom.com Thu Jul 18 17:00:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 17:00:23 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:4529 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6837379Ab3GRGv0JdgTv (ORCPT ); Thu, 18 Jul 2013 08:51:26 +0200 Received: from [10.9.208.57] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 17 Jul 2013 23:47:25 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.438.0; Wed, 17 Jul 2013 23:51:12 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) with Microsoft SMTP Server id 14.1.438.0; Wed, 17 Jul 2013 23:51:12 -0700 Received: from jayachandranc.netlogicmicro.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2FD69F2D74; Wed, 17 Jul 2013 23:51:10 -0700 (PDT) Date: Thu, 18 Jul 2013 12:23:30 +0530 From: "Jayachandran C." To: "Tony Wu" cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] MIPS: tlbex: Guard tlbmiss_handler_setup_pgd Message-ID: <20130718065329.GB24373@jayachandranc.netlogicmicro.com> References: <20130717175840-tung7970@googlemail.com> <20130717180052-tung7970@googlemail.com> MIME-Version: 1.0 In-Reply-To: <20130717180052-tung7970@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-WSS-ID: 7DF950F731W53208328-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37314 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1044 Lines: 36 On Wed, Jul 17, 2013 at 06:01:29PM +0800, Tony Wu wrote: > tlbmiss_handler_setup_pgd* are only referenced when > CONFIG_MIPS_PGD_C0_CONTEXT is defined. > > Signed-off-by: Tony Wu > Cc: Jayachandran C > --- > arch/mips/mm/tlb-funcs.S | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S > index 30a494d..79bca31 100644 > --- a/arch/mips/mm/tlb-funcs.S > +++ b/arch/mips/mm/tlb-funcs.S > @@ -16,10 +16,12 @@ > > #define FASTPATH_SIZE 128 > > +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT > LEAF(tlbmiss_handler_setup_pgd) > .space 16 * 4 > END(tlbmiss_handler_setup_pgd) > EXPORT(tlbmiss_handler_setup_pgd_end) > +#endif > > LEAF(handle_tlbm) > .space FASTPATH_SIZE * 4 There is a patchset planned which uses tlbmiss_handler_setup_pgd when CONFIG_MIPS_PGD_C0_CONTEXT is not defined, but it did not make it into 3.11. This change can be applied - but if it goes in, I will need to undo this as part of the scratch patchset. JC. From jchandra@broadcom.com Thu Jul 18 17:01:17 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 17:01:25 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:1534 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6837315Ab3GRGjHQ0wc5 (ORCPT ); Thu, 18 Jul 2013 08:39:07 +0200 Received: from [10.9.208.53] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 17 Jul 2013 23:32:50 -0700 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server (TLS) id 14.1.438.0; Wed, 17 Jul 2013 23:38:48 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.1.438.0; Wed, 17 Jul 2013 23:38:48 -0700 Received: from jayachandranc.netlogicmicro.com ( netl-snoppy.ban.broadcom.com [10.132.128.129]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id ADFACF2D73; Wed, 17 Jul 2013 23:38:47 -0700 (PDT) Date: Thu, 18 Jul 2013 12:11:07 +0530 From: "Jayachandran C." To: "Tony Wu" cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: tlbex: Fix typo in r3000 tlb store handler Message-ID: <20130718064106.GA24373@jayachandranc.netlogicmicro.com> References: <20130717175840-tung7970@googlemail.com> MIME-Version: 1.0 In-Reply-To: <20130717175840-tung7970@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-WSS-ID: 7DF953981R045497355-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37315 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jchandra@broadcom.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1033 Lines: 35 On Wed, Jul 17, 2013 at 05:59:47PM +0800, Tony Wu wrote: > Should test against handle_tlbs_end, not handle_tlbs. > > Signed-off-by: Tony Wu > Cc: Jayachandran C > --- > arch/mips/mm/tlbex.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > index 9ab0f90..605b6fc 100644 > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -1803,7 +1803,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void) > uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); > uasm_i_nop(&p); > > - if (p >= handle_tlbs) > + if (p >= handle_tlbs_end) > panic("TLB store handler fastpath space exceeded"); > > uasm_resolve_relocs(relocs, labels); Thanks for fixing this. Acked-by: Jayachandran C. You should add the commit which caused the trouble to the commit message, like: commit 6ba045f (MIPS: Move generated code to .text for microMIPS) causes a panic at boot. JC. From kamal@canonical.com Thu Jul 18 17:05:41 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 17:05:46 +0200 (CEST) Received: from youngberry.canonical.com ([91.189.89.112]:42481 "EHLO youngberry.canonical.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6836457Ab3GQWxoix67i (ORCPT ); Thu, 18 Jul 2013 00:53:44 +0200 Received: from c-67-160-231-162.hsd1.ca.comcast.net ([67.160.231.162] helo=fourier) by youngberry.canonical.com with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1UzaWf-0008FP-IL; Wed, 17 Jul 2013 22:48:49 +0000 Received: from kamal by fourier with local (Exim 4.80) (envelope-from ) id 1UzaWd-0002SH-Dx; Wed, 17 Jul 2013 15:48:47 -0700 From: Kamal Mostafa To: linux-kernel@vger.kernel.org, stable@vger.kernel.org, kernel-team@lists.ubuntu.com Cc: David Daney , linux-mips@linux-mips.org, Ralf Baechle , Kamal Mostafa Subject: [PATCH 102/145] MIPS: Octeon: Don't clobber bootloader data structures. Date: Wed, 17 Jul 2013 15:47:14 -0700 Message-Id: <1374101277-7915-103-git-send-email-kamal@canonical.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1374101277-7915-1-git-send-email-kamal@canonical.com> References: <1374101277-7915-1-git-send-email-kamal@canonical.com> X-Extended-Stable: 3.8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37316 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kamal@canonical.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1574 Lines: 44 3.8.13.5 -stable review patch. If anyone has any objections, please let me know. ------------------ From: David Daney commit d949b4fe6d23dd92b5fa48cbf7af90ca32beed2e upstream. Commit abe77f90dc (MIPS: Octeon: Add kexec and kdump support) added a bootmem region for the kernel image itself. The problem is that this is rounded up to a 0x100000 boundary, which is memory that may not be owned by the kernel. Depending on the kernel's configuration based size, this 'extra' memory may contain data passed from the bootloader to the kernel itself, which if clobbered makes the kernel crash in various ways. The fix: Quit rounding the size up, so that we only use memory assigned to the kernel. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5449/ Signed-off-by: Ralf Baechle Signed-off-by: Kamal Mostafa --- arch/mips/cavium-octeon/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index d7e0a09..1271047 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -990,7 +990,7 @@ void __init plat_mem_setup(void) cvmx_bootmem_unlock(); /* Add the memory region for the kernel. */ kernel_start = (unsigned long) _text; - kernel_size = ALIGN(_end - _text, 0x100000); + kernel_size = _end - _text; /* Adjust for physical offset. */ kernel_start &= ~0xffffffff80000000ULL; -- 1.8.1.2 From f.fainelli@gmail.com Thu Jul 18 17:07:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 17:07:41 +0200 (CEST) Received: from mail-ee0-f49.google.com ([74.125.83.49]:48603 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835808Ab3GQS4rJKWof (ORCPT ); Wed, 17 Jul 2013 20:56:47 +0200 Received: by mail-ee0-f49.google.com with SMTP id b57so1225555eek.8 for ; Wed, 17 Jul 2013 11:56:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer; bh=WJebr6rXe2cWpkT4TEWRmSDqt7VPPcHLErP5p19RWDw=; b=LjdTGHZdHCNKkGd8VFiWHGxSzEODW1Tk2W8N81RXgfomNYJ3KnnJ5EADTNQuGfdkVF h4zmPthmMVvr5BrE9RsHsOQNRXRVREhpFYASpCQxshQUxR4Uv3rLSpsLwnl1yeKQ7EnN m59Yb+wabh1M5kQ8y9mVsIVv3sB9YjFu/QSgXsXdT3Mzl/gH+yYMRGZPMKC2EBy+dFEL vmMmnHGsh+yv0xut2XC4Yv3K4pimyWEtvXKz6uf730QfEnYpf5m4t80WXtWp6366KvEJ DzsPh5CKleKbbpRtsWuexlJ5Ho+p9SKfbVv6a86K6MQVYgKSjzJL+mapTY/MNkzbsLhu 3mEQ== X-Received: by 10.14.204.137 with SMTP id h9mr7801456eeo.13.1374087401308; Wed, 17 Jul 2013 11:56:41 -0700 (PDT) Received: from localhost.localdomain (cpc24-aztw25-2-0-cust938.aztw.cable.virginmedia.com. [92.233.35.171]) by mx.google.com with ESMTPSA id n5sm12995504eed.9.2013.07.17.11.56.39 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 17 Jul 2013 11:56:40 -0700 (PDT) From: Florian Fainelli To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, blogic@openwrt.org, jogo@openwrt.org, cernekee@gmail.com, Florian Fainelli Subject: [PATCH 3.11-rc2] MIPS: BMIPS: fix thinko to release slave TP from reset Date: Wed, 17 Jul 2013 19:56:31 +0100 Message-Id: <1374087391-5650-1-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.8.1.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37317 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1311 Lines: 34 Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other than 0") introduced a thinko which will prevents slave CPUs from being released from reset on systems where we boot from TP0. The problem is that we are checking whether the slave CPU logical CPU map is 0, which is never true for systems booting from TP0, so we do not release the slave TP from reset and we are just stuck. Fix this by properly checking that the CPU we intend to boot really is the physical slave CPU (logical and physical value being 1). Signed-off-by: Florian Fainelli --- Ralf, John, This 3.11-rc2 material since the offending commit is in 3.11-rc1. Thanks! arch/mips/kernel/smp-bmips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index aea6c08..6744537 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -173,7 +173,7 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle) else { #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) /* Reset slave TP1 if booting from TP0 */ - if (cpu_logical_map(cpu) == 0) + if (cpu_logical_map(cpu) == 1) set_c0_brcm_cmt_ctrl(0x01); #elif defined(CONFIG_CPU_BMIPS5000) if (cpu & 0x01) -- 1.8.1.2 From ddaney.cavm@gmail.com Thu Jul 18 19:30:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 19:30:42 +0200 (CEST) Received: from mail-pd0-f169.google.com ([209.85.192.169]:35807 "EHLO mail-pd0-f169.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835855Ab3GRRUBEhxSy (ORCPT ); Thu, 18 Jul 2013 19:20:01 +0200 Received: by mail-pd0-f169.google.com with SMTP id y10so3319161pdj.0 for ; Thu, 18 Jul 2013 10:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=ruwju3mvtyshQ8dZfPrpPe9lgXeSWFFcw9R7mwPrJ0Q=; b=HE6L6QP0/KvDa6DEr3DlIaqdqaihFrlfyQ3UWAJ2y7FM20P37O/DXLi7jCHpuLoFU4 fRMxEg9V59C8nL9SQut+BYXhaYWbs/SktQy6Red9Y/ajT6psOJ6IYBtMEZPk+nbEfjHU YKKKr43VQCHaXdpp7yuFedJLnS5oLW0kg+f53lwqKRc1FUIDtBBWNXAApr2RSPlEM5YA 9m0OmImcbhaN/1BsOKsgIAMTEMhstkG0I9c8IuYzGfI0cTmMcr9o4AR155pEOXgSezLS xp0HAw2qeSTjRgLsf9Pn/lGRnNW9eZr3Do5IRjl23AJJzF+Jv6Bkvp9bai2TCm7bjure UUiw== X-Received: by 10.68.1.226 with SMTP id 2mr12869173pbp.150.1374167993574; Thu, 18 Jul 2013 10:19:53 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id mr3sm14812313pbb.27.2013.07.18.10.19.51 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 18 Jul 2013 10:19:52 -0700 (PDT) Message-ID: <51E823B7.6040200@gmail.com> Date: Thu, 18 Jul 2013 10:19:51 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 To: Aaro Koskinen , Ralf Baechle CC: Jayachandran C , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: tlbex: fix broken build in v3.11-rc1 References: <1373876517-14646-1-git-send-email-aaro.koskinen@iki.fi> In-Reply-To: <1373876517-14646-1-git-send-email-aaro.koskinen@iki.fi> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37318 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1016 Lines: 31 On 07/15/2013 01:21 AM, Aaro Koskinen wrote: > Commit 6ba045f9fbdafb48da42aa8576ea7a3980443136 (MIPS: Move generated code > to .text for microMIPS) deleted tlbmiss_handler_setup_pgd_array, but some > references were not converted. Fix that to enable building a MIPS kernel. > > Signed-off-by: Aaro Koskinen Yes, this appears to be needed. Acked-by: David Daney > --- > arch/mips/mm/tlbex.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > index 9ab0f90..cc34521 100644 > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -1466,7 +1466,7 @@ static void __cpuinit build_r4000_setup_pgd(void) > { > const int a0 = 4; > const int a1 = 5; > - u32 *p = tlbmiss_handler_setup_pgd_array; > + u32 *p = tlbmiss_handler_setup_pgd; > const int tlbmiss_handler_setup_pgd_size = > tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; > struct uasm_label *l = labels; > From ddaney.cavm@gmail.com Thu Jul 18 19:32:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 19:32:48 +0200 (CEST) Received: from mail-pa0-f44.google.com ([209.85.220.44]:53966 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6836140Ab3GRQ3EC8-OW (ORCPT ); Thu, 18 Jul 2013 18:29:04 +0200 Received: by mail-pa0-f44.google.com with SMTP id lj1so3418329pab.17 for ; Thu, 18 Jul 2013 09:28:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=KNzychshp3VOhp5p8/moN01wISkTnjo0JiiWc8RnXUo=; b=YnSIiYntpTpbGol8z5h9Mr3nJmT4VZ4HgDswCdaWkJVNwhpUi6C2HuarTrpjkvzACG Fi4XvGLeXt+utdpgIfU/oQgrNP++wY+G6HuPBSll62gpVuz3fwQwtLGfNttfChpUcuyZ H89IOHpJG1HCQnjpxabiDFOwXvkLS9DuIRvGkMLrXMDZ0UU44UxUcK9+RqbmUa4t3o4x /Syl45/ycLeqasjeCw9lCK9vmbvP2yFGzGXQyYbjit7n8C1qQ/P6AMp9cXOpPd1jqodf WCT1qXr5GHpvT21dC1npncuqMIA/Nm/gLPaaM3TeAggW0DBMIzLlEVch9ag+xPLywB49 LI8Q== X-Received: by 10.66.102.41 with SMTP id fl9mr14066424pab.169.1374164936910; Thu, 18 Jul 2013 09:28:56 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id zf3sm17605181pac.9.2013.07.18.09.28.55 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 18 Jul 2013 09:28:56 -0700 (PDT) Message-ID: <51E817C6.3030706@gmail.com> Date: Thu, 18 Jul 2013 09:28:54 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 To: Faidon Liambotis CC: linux-mips@linux-mips.org Subject: Re: octeon: oops/panic with CONFIG_SERIO_I8042=y References: <20130718122556.GA19040@tty.gr> In-Reply-To: <20130718122556.GA19040@tty.gr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37319 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 4327 Lines: 91 On 07/18/2013 05:25 AM, Faidon Liambotis wrote: > Hi, > > My goal is to run a standard Debian kernel and its octeon variant[1] on > the Ubiquity EdgeRouter Lite. The ERLite needs a couple of patches > to boot and work (octeon-ethernet patch, octeon-usb driver) but these > are already merged 3.11 and I'll file Debian bugs to enable those > settings appropriately. > > 1: e.g. http://packages.debian.org/sid/linux-image-3.10-1-octeon > > However, when trying to boot a standard Debian kernel in the ERLite I > get a 7s delay followed by an oops for a Data bus error on i8042_flush() > and ending up with a panic. It looks like the kernel is built with > CONFIG_SERIO_I8042=y. The Octeon machine Debian owns prints "i8042: No > controller found" but works nevertheless. This isn't the case with the > ERLite; I tried 3.2 & 3.10 and got the same oops which went away as soon > as I disabled CONFIG_SERIO_I8042. > > Are there even any octeon machines with i8042 anyway? Should I request > for the setting to be disabled irrespective of this bug? Yes. There is a rare board called NAC38 that was produced by ASUS in a 1U chassis. I don't think it is important to support this, so the best thing seems to be not to enable SERIO_I8042 David Daney > > The oops is as follows: > [ 1.702762] ehci-pci: EHCI PCI platform driver > [ 1.707913] usbcore: registered new interface driver usb-storage > [ 8.591312] Data bus error, epc == ffffffff81446838, ra == > ffffffff814467f0 > [ 8.598102] Oops[#1]: > [ 8.600360] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0 #5 > [ 8.606253] task: a80000041f869540 ti: a80000041f86c000 task.ti: > a80000041f86c000 > [ 8.613706] $ 0 : 0000000000000000 0000000000000000 > 0000000000000000 0000000000010000 > [ 8.621684] $ 4 : 0000000000000000 a80000041f1bbb40 > 000000000000006f ffffffff816ffe60 > [ 8.629662] $ 8 : 0000000000000000 000000000000005b > 726564206e657720 696e746572666163 > [ 8.637640] $12 : 0000000000000000 ffffffff8136b0dc > ffffffff81790000 0000000000000000 > [ 8.645619] $16 : 80011a0400000064 80011a0400000000 > 0000000000000010 ffffffff817a0000 > [ 8.653597] $20 : ffffffff817a0000 0000000000000001 > ffffffff81770e20 ffffffff817a0000 > [ 8.661575] $24 : 0000000000000004 ffffffff81790000 [ 8.669553] > $28 : a80000041f86c000 a80000041f86fd70 0000000000000000 ffffffff814467f0 > [ 8.677532] Hi : 0000000000acd49d > [ 8.681088] Lo : 0e5604189441f8e5 > [ 8.684661] epc : ffffffff81446838 i8042_flush+0x80/0x118 > [ 8.690194] Not tainted > [ 8.692975] ra : ffffffff814467f0 i8042_flush+0x38/0x118 > [ 8.698518] Status: 10008ce2 KX SX UX KERNEL EXL [ 8.703201] > Cause : 4080801c > [ 8.706064] PrId : 000d0601 (Cavium Octeon+) > [ 8.710398] Modules linked in: > [ 8.713439] Process swapper/0 (pid: 1, threadinfo=a80000041f86c000, > task=a80000041f869540, tls=0000000000000000) > [ 8.723580] Stack : ffffffff81700000 ffffffff81751158 > 0000000000000000 ffffffff8175f2f8 > ffffffff817361d8 ffffffff8175f288 ffffffff81770e20 ffffffff816c0000 > 000000000000008c ffffffff817511ac 0000000000000000 ffffffff81780000 > ffffffff81751158 ffffffff811004e0 ffffffff817361d8 0000000000000030 > ffffffff81780000 0000000000000007 ffffffff8175f2f8 ffffffff81736b50 > ffffffff81595080 0000000000000000 ffffffff81780000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > 0000000000000000 ffffffff8159509c ffffffff81595080 0000000000000000 > 0000000000000000 ffffffff8111a124 0000000000000000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > ... > [ 8.788447] Call Trace: > [ 8.790882] [] i8042_flush+0x80/0x118 > [ 8.796092] [] i8042_init+0x54/0xf0 > [ 8.801118] [] do_one_initcall+0xe0/0x130 > [ 8.806658] [ 8.808132] Code: 14800017 27de0001 92020000 > <305600ff> cac00003 24040032 17d2fff4 00200825 6684d338 [ > 8.820195] ---[ end trace 76cca175541407ab ]--- > [ 8.824650] note: swapper/0[1] exited with preempt_count 1 > [ 8.830188] Kernel panic - not syncing: Attempted to kill init! > exitcode=0x0000000b > [ 8.830188] > Regards, > Faidon > > From ddaney.cavm@gmail.com Thu Jul 18 19:45:39 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 19:46:02 +0200 (CEST) Received: from mail-pa0-f46.google.com ([209.85.220.46]:46702 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6834840Ab3GRRpjk2VFx (ORCPT ); Thu, 18 Jul 2013 19:45:39 +0200 Received: by mail-pa0-f46.google.com with SMTP id fa11so3484454pad.19 for ; Thu, 18 Jul 2013 10:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=matI9Jsyd8up33ltvOKzl7y9m0AvrrC4H6vH1vdbBtc=; b=pK9a9CWNxDkFDa0yvj+GoUw4nOmGYx2PLgXiOk87I4jm3ksI7AsDPefz90aYzM18br KqBLQaMmNrjhzhZn0dyQQBsRwpUuyy1SVFsyS4Hy/Zx9Juc7790oF8Si9yU0iqD8WqaW nt7J8WMS+HAyn/Rk5bjfnu7XLpxXXlElk8NrgLR3MaRtiMNGuICmDvhu3Ygw9HmABFfe DJepFGwgOR3Xv7rltjOGBAWSv9YrOrpIILku5KXKSrmJ3yreC7Kd+Thk8nWHkUjxKNUr 8TlQk937/y5VTEMQdGKFyfkNQmJ02tJZpPdogfIhUd9j20wGj+0cJFCXv2NkgJ5rEj1y bmrw== X-Received: by 10.66.233.104 with SMTP id tv8mr7153011pac.111.1374169524083; Thu, 18 Jul 2013 10:45:24 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id bb1sm5078127pbc.10.2013.07.18.10.45.22 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 18 Jul 2013 10:45:23 -0700 (PDT) Message-ID: <51E829B1.40406@gmail.com> Date: Thu, 18 Jul 2013 10:45:21 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 To: Faidon Liambotis , Ralf Baechle CC: linux-mips@linux-mips.org, Aaro Koskinen Subject: Re: [PATCH] MIPS: octeon: fix DT pruning bug with pip ports References: <1373580489-23142-1-git-send-email-paravoid@debian.org> In-Reply-To: <1373580489-23142-1-git-send-email-paravoid@debian.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37320 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1686 Lines: 46 On 07/11/2013 03:08 PM, Faidon Liambotis wrote: > During the pruning of the device tree octeon_fdt_pip_iface() is called > for each PIP interface and every port up to the port count is removed > from the device tree. However, the count was set to the return value of > cvmx_helper_interface_enumerate() which doesn't actually return the > count but just returns zero on success. This effectively removed *all* > ports from the tree. > > Use cvmx_helper_ports_on_interface() instead to fix this. This > successfully restores the 3 ports of my ERLite-3 and fixes the "kernel > assigns random MAC addresses" issue. > > Signed-off-by: Faidon Liambotis Yes, this seems to be correct. It doesn't seem to break my ebt3000 board so... Acked-by: David Daney Ralf, please try to get it merged for 3.11, thanks. > --- > arch/mips/cavium-octeon/octeon-platform.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c > index 389512e..250eb20 100644 > --- a/arch/mips/cavium-octeon/octeon-platform.c > +++ b/arch/mips/cavium-octeon/octeon-platform.c > @@ -334,9 +334,10 @@ static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) > char name_buffer[20]; > int iface; > int p; > - int count; > + int count = 0; > > - count = cvmx_helper_interface_enumerate(idx); > + if (cvmx_helper_interface_enumerate(idx) == 0) > + count = cvmx_helper_ports_on_interface(idx); > > snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); > iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); > From aaro.koskinen@iki.fi Thu Jul 18 20:03:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 20:03:57 +0200 (CEST) Received: from filtteri5.pp.htv.fi ([213.243.153.188]:57200 "EHLO filtteri5.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815753Ab3GRSDsnlmVD (ORCPT ); Thu, 18 Jul 2013 20:03:48 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri5.pp.htv.fi (Postfix) with ESMTP id 181675A6E57; Thu, 18 Jul 2013 21:03:47 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp4.welho.com ([213.243.153.38]) by localhost (filtteri5.pp.htv.fi [213.243.153.188]) (amavisd-new, port 10024) with ESMTP id 8pn2sDdonjxR; Thu, 18 Jul 2013 21:03:42 +0300 (EEST) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp4.welho.com (Postfix) with SMTP id 1E9A65BC005; Thu, 18 Jul 2013 21:03:41 +0300 (EEST) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Thu, 18 Jul 2013 21:03:39 +0300 Date: Thu, 18 Jul 2013 21:03:39 +0300 From: Aaro Koskinen To: David Daney Cc: Faidon Liambotis , linux-mips@linux-mips.org Subject: Re: octeon: oops/panic with CONFIG_SERIO_I8042=y Message-ID: <20130718180339.GH14385@blackmetal.musicnaut.iki.fi> References: <20130718122556.GA19040@tty.gr> <51E817C6.3030706@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <51E817C6.3030706@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37321 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1516 Lines: 32 Hi, On Thu, Jul 18, 2013 at 09:28:54AM -0700, David Daney wrote: > On 07/18/2013 05:25 AM, Faidon Liambotis wrote: > >My goal is to run a standard Debian kernel and its octeon variant[1] on > >the Ubiquity EdgeRouter Lite. The ERLite needs a couple of patches > >to boot and work (octeon-ethernet patch, octeon-usb driver) but these > >are already merged 3.11 and I'll file Debian bugs to enable those > >settings appropriately. > > > >1: e.g. http://packages.debian.org/sid/linux-image-3.10-1-octeon > > > >However, when trying to boot a standard Debian kernel in the ERLite I > >get a 7s delay followed by an oops for a Data bus error on i8042_flush() > >and ending up with a panic. It looks like the kernel is built with > >CONFIG_SERIO_I8042=y. The Octeon machine Debian owns prints "i8042: No > >controller found" but works nevertheless. This isn't the case with the > >ERLite; I tried 3.2 & 3.10 and got the same oops which went away as soon > >as I disabled CONFIG_SERIO_I8042. > > > >Are there even any octeon machines with i8042 anyway? Should I request > >for the setting to be disabled irrespective of this bug? > > Yes. There is a rare board called NAC38 that was produced by ASUS > in a 1U chassis. I don't think it is important to support this, so > the best thing seems to be not to enable SERIO_I8042 I think the real bug here is that IO space does not get properly initialized on Octeon when there is no PCI? So any drivers trying to probe IO space will produce some interesting results. A. From manuel.lauss@gmail.com Thu Jul 18 21:35:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 21:35:18 +0200 (CEST) Received: from mail-wi0-f170.google.com ([209.85.212.170]:46033 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819547Ab3GRTfOh0gT0 (ORCPT ); Thu, 18 Jul 2013 21:35:14 +0200 Received: by mail-wi0-f170.google.com with SMTP id ey16so1248166wid.5 for ; Thu, 18 Jul 2013 12:35:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=4apXvw27zL8Csn+hhjJkHiN88KmR0S1uVL40W3saB2A=; b=CBkSxKxHZzwF112Dwp0NpKPVdaOMosigVJTamEWXQkcwj812mF4QKeXLQ4nyc363Fv G941S/xaDn962J+QPm7xMW+A15J8MzD0/oQPWtkNR5ec4xhlQ+DIIzsDDVkaFydxC/LP dwFvf23dGKXER0x0CPjEIG2e+bLSMTunyIMpHgSeEZ3kGfxk4yrvsPwL0gNxP431c35P jliTvSmOSVpughaaPFFFwRK+1q7DdfaZP1m5Kwtp9mfIaffWciZh5QB+NCNwTEB0ckkm URa5qV63RLG0wcqfCco9EtX6xG4nwckAVJuqMzrsngHtPSLjaMlL+oREDTuJKJ1GZcFM SwOQ== X-Received: by 10.194.179.233 with SMTP id dj9mr9652758wjc.46.1374176109128; Thu, 18 Jul 2013 12:35:09 -0700 (PDT) MIME-Version: 1.0 Received: by 10.216.245.2 with HTTP; Thu, 18 Jul 2013 12:34:28 -0700 (PDT) In-Reply-To: <20130718180339.GH14385@blackmetal.musicnaut.iki.fi> References: <20130718122556.GA19040@tty.gr> <51E817C6.3030706@gmail.com> <20130718180339.GH14385@blackmetal.musicnaut.iki.fi> From: Manuel Lauss Date: Thu, 18 Jul 2013 21:34:28 +0200 Message-ID: Subject: Re: octeon: oops/panic with CONFIG_SERIO_I8042=y To: Aaro Koskinen Cc: David Daney , Faidon Liambotis , Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37322 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1866 Lines: 38 On Thu, Jul 18, 2013 at 8:03 PM, Aaro Koskinen wrote: > Hi, > > On Thu, Jul 18, 2013 at 09:28:54AM -0700, David Daney wrote: >> On 07/18/2013 05:25 AM, Faidon Liambotis wrote: >> >My goal is to run a standard Debian kernel and its octeon variant[1] on >> >the Ubiquity EdgeRouter Lite. The ERLite needs a couple of patches >> >to boot and work (octeon-ethernet patch, octeon-usb driver) but these >> >are already merged 3.11 and I'll file Debian bugs to enable those >> >settings appropriately. >> > >> >1: e.g. http://packages.debian.org/sid/linux-image-3.10-1-octeon >> > >> >However, when trying to boot a standard Debian kernel in the ERLite I >> >get a 7s delay followed by an oops for a Data bus error on i8042_flush() >> >and ending up with a panic. It looks like the kernel is built with >> >CONFIG_SERIO_I8042=y. The Octeon machine Debian owns prints "i8042: No >> >controller found" but works nevertheless. This isn't the case with the >> >ERLite; I tried 3.2 & 3.10 and got the same oops which went away as soon >> >as I disabled CONFIG_SERIO_I8042. >> > >> >Are there even any octeon machines with i8042 anyway? Should I request >> >for the setting to be disabled irrespective of this bug? >> >> Yes. There is a rare board called NAC38 that was produced by ASUS >> in a 1U chassis. I don't think it is important to support this, so >> the best thing seems to be not to enable SERIO_I8042 > > I think the real bug here is that IO space does not get properly > initialized on Octeon when there is no PCI? So any drivers trying to > probe IO space will produce some interesting results. This is not specific to Octeon, I've seen it on Alchemy as well. A lot of drivers, coming from x86, simply assume that x86-Port-IO space is always available without having to map it first. I'd say it's a bug in the various drivers. Manuel From sergei.shtylyov@cogentembedded.com Thu Jul 18 21:39:47 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 21:39:51 +0200 (CEST) Received: from mail-lb0-f175.google.com ([209.85.217.175]:62631 "EHLO mail-lb0-f175.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6817318Ab3GRTjrdeoiT (ORCPT ); Thu, 18 Jul 2013 21:39:47 +0200 Received: by mail-lb0-f175.google.com with SMTP id r10so2801223lbi.6 for ; Thu, 18 Jul 2013 12:39:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:organization:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=DFlJqxVSMctPAqsc9s0NK8cQ8YoKwJ2hpgyO6OD7W7g=; b=Zrb3Jhv5LkQjtYdrPehVySj3Z0g+lJm8x7yayt/ZjFHF1bpEkkgGzWUT7NrI1X1cSj rXC8HAxesrn3P77OdZgZnir7/RNh3g7Fbux7sV5I04gJ76y+OcR+XF3XVe549xlV92we NXLA+aiHm0A9cYWNkaXPr9HQkXrTJubYyq17RjsTlrYmBSwgRj+NmKCwnU9RAYiUoOc4 3CRZhvZJBONbSq2mcAZ7cUbPuEfNX/eeH/duELiaOHpVp+hnhJtLXg4JvnZ5we2JDOVO skOrMhBYwouOa4d3E5E7Tdpcc9ZvP++XlW+F7yt7W5HGSLkaQYeTYVEc7/CxSH2j5nlk NHZA== X-Received: by 10.152.87.234 with SMTP id bb10mr5978581lab.55.1374176381878; Thu, 18 Jul 2013 12:39:41 -0700 (PDT) Received: from wasted.dev.rtsoft.ru (ppp91-76-85-2.pppoe.mtu-net.ru. [91.76.85.2]) by mx.google.com with ESMTPSA id n3sm4682687lag.9.2013.07.18.12.39.39 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Jul 2013 12:39:40 -0700 (PDT) Message-ID: <51E84482.6090706@cogentembedded.com> Date: Thu, 18 Jul 2013 23:39:46 +0400 From: Sergei Shtylyov Organization: Cogent Embedded User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 MIME-Version: 1.0 To: Manuel Lauss CC: Aaro Koskinen , David Daney , Faidon Liambotis , Linux-MIPS Subject: Re: octeon: oops/panic with CONFIG_SERIO_I8042=y References: <20130718122556.GA19040@tty.gr> <51E817C6.3030706@gmail.com> <20130718180339.GH14385@blackmetal.musicnaut.iki.fi> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQkt2Gm/ALdg1S4iRU5V6cjZu5lnZKcPHqn50ThBsFqokk2Su9hzT32DPwbQr6AOIKKg1hkb Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37323 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sergei.shtylyov@cogentembedded.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1829 Lines: 42 Hello. On 07/18/2013 11:34 PM, Manuel Lauss wrote: >>>> My goal is to run a standard Debian kernel and its octeon variant[1] on >>>> the Ubiquity EdgeRouter Lite. The ERLite needs a couple of patches >>>> to boot and work (octeon-ethernet patch, octeon-usb driver) but these >>>> are already merged 3.11 and I'll file Debian bugs to enable those >>>> settings appropriately. >>>> 1: e.g. http://packages.debian.org/sid/linux-image-3.10-1-octeon >>>> However, when trying to boot a standard Debian kernel in the ERLite I >>>> get a 7s delay followed by an oops for a Data bus error on i8042_flush() >>>> and ending up with a panic. It looks like the kernel is built with >>>> CONFIG_SERIO_I8042=y. The Octeon machine Debian owns prints "i8042: No >>>> controller found" but works nevertheless. This isn't the case with the >>>> ERLite; I tried 3.2 & 3.10 and got the same oops which went away as soon >>>> as I disabled CONFIG_SERIO_I8042. >>>> Are there even any octeon machines with i8042 anyway? Should I request >>>> for the setting to be disabled irrespective of this bug? >>> Yes. There is a rare board called NAC38 that was produced by ASUS >>> in a 1U chassis. I don't think it is important to support this, so >>> the best thing seems to be not to enable SERIO_I8042 >> I think the real bug here is that IO space does not get properly >> initialized on Octeon when there is no PCI? So any drivers trying to >> probe IO space will produce some interesting results. > This is not specific to Octeon, I've seen it on Alchemy as well. A lot of > drivers, coming from x86, simply assume that x86-Port-IO space is > always available without having to map it first. I'd say it's a bug in > the various drivers. Drivers don't have to map I/O space in any way, it's a complete nonsense. > Manuel WBR, Sergei From rostedt@goodmis.org Thu Jul 18 22:11:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 22:11:11 +0200 (CEST) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:15663 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819780Ab3GRULG3hiNr (ORCPT ); Thu, 18 Jul 2013 22:11:06 +0200 X-Authority-Analysis: v=2.0 cv=e9yEuNV/ c=1 sm=0 a=Sro2XwOs0tJUSHxCKfOySw==:17 a=Drc5e87SC40A:10 a=m81s-13gt9IA:10 a=5SG0PmZfjMsA:10 a=IkcTkHD0fZMA:10 a=meVymXHHAAAA:8 a=KGjhK52YXX0A:10 a=DHlrDtQkiHoA:10 a=fk1lIlRQAAAA:8 a=zAyngx5bAAAA:8 a=AgRTik3wS6d53wTNwdcA:9 a=QEXdDO2ut3YA:10 a=gH_wm7_JyAQA:10 a=9g6PTisfegMA:10 a=DUX0N4f6TqGyh1Jp:21 a=K6UQCbUFnQzV_Gmk:21 a=Sro2XwOs0tJUSHxCKfOySw==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 67.255.60.225 Received: from [67.255.60.225] ([67.255.60.225:52250] helo=[192.168.23.10]) by hrndva-oedge01.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id E6/4F-18705-6DB48E15; Thu, 18 Jul 2013 20:11:03 +0000 Message-ID: <1374178262.6458.266.camel@gandalf.local.home> Subject: Re: [PATCH] mips/ftrace: Fix function tracing return address to match From: Steven Rostedt To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Corey Minyard , David Daney Date: Thu, 18 Jul 2013 16:11:02 -0400 In-Reply-To: <1373926637-24627-1-git-send-email-ddaney.cavm@gmail.com> References: <1373926637-24627-1-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.4.4-3 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37324 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1449 Lines: 40 On Mon, 2013-07-15 at 15:17 -0700, David Daney wrote: > From: Corey Minyard > > Dynamic function tracing was not working on MIPS. When doing dynamic > tracing, the tracer attempts to match up the passed in address with > the one the compiler creates in the mcount tables. The MIPS code was > passing in the return address from the tracing function call, but the > compiler tables were the address of the function call. So they > wouldn't match. > > Just subtracting 8 from the return address will give the address of > the function call. Easy enough. > > Signed-off-by: Corey Minyard > [david.daney@cavium.com: Adjusted code comment and patch Subject.] > Signed-off-by: David Daney > --- > arch/mips/kernel/mcount.S | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S > index a03e93c..539b629 100644 > --- a/arch/mips/kernel/mcount.S > +++ b/arch/mips/kernel/mcount.S > @@ -83,7 +83,7 @@ _mcount: > PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp) > #endif > > - move a0, ra /* arg1: self return address */ > + PTR_SUBU a0, ra, 8 /* arg1: self address */ > .globl ftrace_call > ftrace_call: > nop /* a placeholder for the call to a real tracing function */ I applied this patch to my Yeeloong Lemote laptop and it causes the system to crash. Not sure why. I'll try to investigate. -- Steve From ddaney.cavm@gmail.com Thu Jul 18 22:15:02 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 22:15:08 +0200 (CEST) Received: from mail-pd0-f177.google.com ([209.85.192.177]:44105 "EHLO mail-pd0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819780Ab3GRUPCMAu6b (ORCPT ); Thu, 18 Jul 2013 22:15:02 +0200 Received: by mail-pd0-f177.google.com with SMTP id p10so3439060pdj.36 for ; Thu, 18 Jul 2013 13:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=BmHSSlmo4ZjUU+u+rhu7BkmaxwK97h2RJFRi0gVkr3Y=; b=emR7u2cIvUJR2EF5qraTcrqda3HZ+PNymjmxxYXnsRVip+5jbtJ/TY1P//W4vpRhh0 Qz5Vm9u+jHB/OQ/VN6mf5rkX+eTf+SmDIph2cwKeyE5SzPyqkila953Rj6PmorzM0jzh g5/lE1wEsNgMjlGkze0tgXRbEk4HJQZGTzCzHt4dAJbn1ykcoyTVf0kujm3u0kmzE2ox mSrcoE+2bWySZOyN5VkBJI+RjOQj4PT7TCWrc9Fss3hpEht6qrCPgc0CSbW60aWz0muQ MOxl9k6XEKsLQ6vBP3jbyvcyYaxM8M7qXDOb43LSk9otQgSFODqLCjVyYVsyZKZ9ti7U MIiw== X-Received: by 10.66.139.227 with SMTP id rb3mr14866763pab.121.1374178495277; Thu, 18 Jul 2013 13:14:55 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id is3sm9173648pbc.25.2013.07.18.13.14.53 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 18 Jul 2013 13:14:54 -0700 (PDT) Message-ID: <51E84CBC.80206@gmail.com> Date: Thu, 18 Jul 2013 13:14:52 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 To: Steven Rostedt CC: linux-mips@linux-mips.org, ralf@linux-mips.org, Corey Minyard , David Daney Subject: Re: [PATCH] mips/ftrace: Fix function tracing return address to match References: <1373926637-24627-1-git-send-email-ddaney.cavm@gmail.com> <1374178262.6458.266.camel@gandalf.local.home> In-Reply-To: <1374178262.6458.266.camel@gandalf.local.home> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37325 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1718 Lines: 53 On 07/18/2013 01:11 PM, Steven Rostedt wrote: > On Mon, 2013-07-15 at 15:17 -0700, David Daney wrote: >> From: Corey Minyard >> >> Dynamic function tracing was not working on MIPS. When doing dynamic >> tracing, the tracer attempts to match up the passed in address with >> the one the compiler creates in the mcount tables. The MIPS code was >> passing in the return address from the tracing function call, but the >> compiler tables were the address of the function call. So they >> wouldn't match. >> >> Just subtracting 8 from the return address will give the address of >> the function call. Easy enough. >> >> Signed-off-by: Corey Minyard >> [david.daney@cavium.com: Adjusted code comment and patch Subject.] >> Signed-off-by: David Daney >> --- >> arch/mips/kernel/mcount.S | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S >> index a03e93c..539b629 100644 >> --- a/arch/mips/kernel/mcount.S >> +++ b/arch/mips/kernel/mcount.S >> @@ -83,7 +83,7 @@ _mcount: >> PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp) >> #endif >> >> - move a0, ra /* arg1: self return address */ >> + PTR_SUBU a0, ra, 8 /* arg1: self address */ >> .globl ftrace_call >> ftrace_call: >> nop /* a placeholder for the call to a real tracing function */ > > I applied this patch to my Yeeloong Lemote laptop and it causes the > system to crash. Not sure why. I'll try to investigate. > There is an mcount ABI difference based on which GCC version you are using, although I wouldn't think it would effect this bit. We are using GCC-4.7 FWIW. David Daney > -- Steve > > > > From rostedt@goodmis.org Thu Jul 18 22:26:07 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 22:26:13 +0200 (CEST) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:10888 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823426Ab3GRU0HWzGtU (ORCPT ); Thu, 18 Jul 2013 22:26:07 +0200 X-Authority-Analysis: v=2.0 cv=e9yEuNV/ c=1 sm=0 a=Sro2XwOs0tJUSHxCKfOySw==:17 a=Drc5e87SC40A:10 a=m81s-13gt9IA:10 a=5SG0PmZfjMsA:10 a=IkcTkHD0fZMA:10 a=meVymXHHAAAA:8 a=KGjhK52YXX0A:10 a=DHlrDtQkiHoA:10 a=VwQbUJbxAAAA:8 a=4nTBI54OEixUBHPdUOkA:9 a=QEXdDO2ut3YA:10 a=X_FumI7QcasA:10 a=8MU9W6P4Xn4A:10 a=Sro2XwOs0tJUSHxCKfOySw==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 67.255.60.225 Received: from [67.255.60.225] ([67.255.60.225:51162] helo=[192.168.23.10]) by hrndva-oedge01.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 9A/C6-18705-85F48E15; Thu, 18 Jul 2013 20:26:00 +0000 Message-ID: <1374179160.6458.269.camel@gandalf.local.home> Subject: Re: [PATCH] mips/ftrace: Fix function tracing return address to match From: Steven Rostedt To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Corey Minyard , David Daney Date: Thu, 18 Jul 2013 16:26:00 -0400 In-Reply-To: <51E84CBC.80206@gmail.com> References: <1373926637-24627-1-git-send-email-ddaney.cavm@gmail.com> <1374178262.6458.266.camel@gandalf.local.home> <51E84CBC.80206@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.4.4-3 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37327 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 426 Lines: 17 On Thu, 2013-07-18 at 13:14 -0700, David Daney wrote: > There is an mcount ABI difference based on which GCC version you are > using, although I wouldn't think it would effect this bit. > > We are using GCC-4.7 FWIW. > > David Daney I'm using 4.6.3 which I downloaded from https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ I can down load the 4.7 version and see if that makes a difference. -- Steve From rostedt@goodmis.org Thu Jul 18 22:27:09 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 22:27:13 +0200 (CEST) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:31855 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823114Ab3GRU1JQg4FQ (ORCPT ); Thu, 18 Jul 2013 22:27:09 +0200 X-Authority-Analysis: v=2.0 cv=P6i4d18u c=1 sm=0 a=Sro2XwOs0tJUSHxCKfOySw==:17 a=Drc5e87SC40A:10 a=m81s-13gt9IA:10 a=5SG0PmZfjMsA:10 a=IkcTkHD0fZMA:10 a=meVymXHHAAAA:8 a=KGjhK52YXX0A:10 a=DHlrDtQkiHoA:10 a=VwQbUJbxAAAA:8 a=18CPOQ8VckTwq7bigWQA:9 a=QEXdDO2ut3YA:10 a=sdKmmMAnKywA:10 a=k6k8nn4gJnwA:10 a=Sro2XwOs0tJUSHxCKfOySw==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 67.255.60.225 Received: from [67.255.60.225] ([67.255.60.225:51146] helo=[192.168.23.10]) by hrndva-oedge02.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 70/67-18468-59F48E15; Thu, 18 Jul 2013 20:27:02 +0000 Message-ID: <1374179221.6458.270.camel@gandalf.local.home> Subject: Re: [PATCH] mips/ftrace: Fix function tracing return address to match From: Steven Rostedt To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Corey Minyard , David Daney Date: Thu, 18 Jul 2013 16:27:01 -0400 In-Reply-To: <1374179160.6458.269.camel@gandalf.local.home> References: <1373926637-24627-1-git-send-email-ddaney.cavm@gmail.com> <1374178262.6458.266.camel@gandalf.local.home> <51E84CBC.80206@gmail.com> <1374179160.6458.269.camel@gandalf.local.home> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.4.4-3 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37328 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 262 Lines: 10 On Thu, 2013-07-18 at 16:26 -0400, Steven Rostedt wrote: > I can down load the 4.7 version and see if that makes a difference. I guess I can't. There is no 4.7 version for MIPS :-p https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.7.3/ -- Steve From David.Daney@caviumnetworks.com Thu Jul 18 22:37:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 22:37:51 +0200 (CEST) Received: from mail-bn1lp0156.outbound.protection.outlook.com ([207.46.163.156]:51782 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6827417Ab3GRUhpUq-7F (ORCPT ); Thu, 18 Jul 2013 22:37:45 +0200 Received: from BY2PRD0712HT001.namprd07.prod.outlook.com (10.255.246.34) by BLUPR07MB113.namprd07.prod.outlook.com (10.242.200.28) with Microsoft SMTP Server (TLS) id 15.0.731.12; Thu, 18 Jul 2013 20:37:37 +0000 Received: from dl.caveonetworks.com (64.2.3.195) by pod51018.outlook.com (10.255.246.34) with Microsoft SMTP Server (TLS) id 14.16.329.3; Thu, 18 Jul 2013 20:37:34 +0000 Message-ID: <51E8520E.2050604@caviumnetworks.com> Date: Thu, 18 Jul 2013 13:37:34 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 To: Steven Rostedt CC: David Daney , , , Corey Minyard , David Daney Subject: Re: [PATCH] mips/ftrace: Fix function tracing return address to match References: <1373926637-24627-1-git-send-email-ddaney.cavm@gmail.com> <1374178262.6458.266.camel@gandalf.local.home> <51E84CBC.80206@gmail.com> <1374179160.6458.269.camel@gandalf.local.home> In-Reply-To: <1374179160.6458.269.camel@gandalf.local.home> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.195] X-Forefront-PRVS: 0911D5CE78 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(479174003)(377424004)(24454002)(51704005)(189002)(199002)(377454003)(56776001)(83072001)(49866001)(53416003)(46102001)(80316001)(74706001)(47776003)(76786001)(81542001)(47736001)(59896001)(74366001)(74502001)(56816003)(83322001)(79102001)(47976001)(76796001)(53806001)(65956001)(51856001)(65806001)(81342001)(33656001)(47446002)(54356001)(80022001)(64126003)(77096001)(31966008)(36756003)(16406001)(4396001)(50986001)(59766001)(66066001)(76482001)(74662001)(69226001)(23676002)(74876001)(50466002)(77982001)(19580385001)(54316002)(63696002)(19580395003);DIR:OUT;SFP:;SCL:1;SRVR:BLUPR07MB113;H:BY2PRD0712HT001.namprd07.prod.outlook.com;CLIP:64.2.3.195;RD:InfoNoRecords;MX:1;A:1;LANG:en; X-OriginatorOrg: DuplicateDomain-a3ec847f-e37f-4d9a-9900-9d9d96f75f58.caviumnetworks.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37329 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 614 Lines: 24 On 07/18/2013 01:26 PM, Steven Rostedt wrote: > On Thu, 2013-07-18 at 13:14 -0700, David Daney wrote: > >> There is an mcount ABI difference based on which GCC version you are >> using, although I wouldn't think it would effect this bit. >> >> We are using GCC-4.7 FWIW. >> >> David Daney > > I'm using 4.6.3 which I downloaded from > https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ I would expect that version to be fine too. The option in question is -mmcount-ra-address, which I added to GCC-4.5 > > I can down load the 4.7 version and see if that makes a difference. > > -- Steve > > > From manuel.lauss@gmail.com Thu Jul 18 22:43:13 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 22:45:51 +0200 (CEST) Received: from mail-wi0-f182.google.com ([209.85.212.182]:64722 "EHLO mail-wi0-f182.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824769Ab3GRUnNe6ze2 (ORCPT ); Thu, 18 Jul 2013 22:43:13 +0200 Received: by mail-wi0-f182.google.com with SMTP id m6so3663986wiv.9 for ; Thu, 18 Jul 2013 13:43:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=bEAOUrG6d1r4lfTnGm5FVFznEHK9rJMZBHhvM5DpK+g=; b=MqSD3Gy2f/Qjnj7uE42PYPeHxF6ZHgK8H1ybHEvzO3Eh0DSXrklGDP/vqIm8jVxxoI xUzH6QNBMWyuO3+KJMkALnOYA6FpDENJhTWsXJ3G3pN55CUq7Eo3dbszli8Oo2nomDdc LOryhSqwnejodPS8JzUSYou2+/mFkfQgfypCcwEt3pRdIlKeMM7Jd3D6N5NeqkSPKT5Y t+FJc7xLiBa1FsaycBtWgG45WY/PZqN55G6JdbN5AI34K5Oge47vCwZ7YzHuD73AsL9z tYyCEOKcB+MtcTH5gN/z2HT+Ppst7lGSjGcuy+lIjzpyoaP4DeEJAAjsgkMRw6AI8w4/ TjWA== X-Received: by 10.180.90.73 with SMTP id bu9mr9316103wib.32.1374180188160; Thu, 18 Jul 2013 13:43:08 -0700 (PDT) MIME-Version: 1.0 Received: by 10.216.245.2 with HTTP; Thu, 18 Jul 2013 13:42:28 -0700 (PDT) In-Reply-To: <51E84482.6090706@cogentembedded.com> References: <20130718122556.GA19040@tty.gr> <51E817C6.3030706@gmail.com> <20130718180339.GH14385@blackmetal.musicnaut.iki.fi> <51E84482.6090706@cogentembedded.com> From: Manuel Lauss Date: Thu, 18 Jul 2013 22:42:28 +0200 Message-ID: Subject: Re: octeon: oops/panic with CONFIG_SERIO_I8042=y To: Sergei Shtylyov Cc: Aaro Koskinen , David Daney , Faidon Liambotis , Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37330 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2011 Lines: 54 On Thu, Jul 18, 2013 at 9:39 PM, Sergei Shtylyov wrote: > Hello. > > > On 07/18/2013 11:34 PM, Manuel Lauss wrote: > >>>>> My goal is to run a standard Debian kernel and its octeon variant[1] on >>>>> the Ubiquity EdgeRouter Lite. The ERLite needs a couple of patches >>>>> to boot and work (octeon-ethernet patch, octeon-usb driver) but these >>>>> are already merged 3.11 and I'll file Debian bugs to enable those >>>>> settings appropriately. > > >>>>> 1: e.g. http://packages.debian.org/sid/linux-image-3.10-1-octeon > > >>>>> However, when trying to boot a standard Debian kernel in the ERLite I >>>>> get a 7s delay followed by an oops for a Data bus error on >>>>> i8042_flush() >>>>> and ending up with a panic. It looks like the kernel is built with >>>>> CONFIG_SERIO_I8042=y. The Octeon machine Debian owns prints "i8042: No >>>>> controller found" but works nevertheless. This isn't the case with the >>>>> ERLite; I tried 3.2 & 3.10 and got the same oops which went away as >>>>> soon >>>>> as I disabled CONFIG_SERIO_I8042. > > >>>>> Are there even any octeon machines with i8042 anyway? Should I request >>>>> for the setting to be disabled irrespective of this bug? > > >>>> Yes. There is a rare board called NAC38 that was produced by ASUS >>>> in a 1U chassis. I don't think it is important to support this, so >>>> the best thing seems to be not to enable SERIO_I8042 > > >>> I think the real bug here is that IO space does not get properly >>> initialized on Octeon when there is no PCI? So any drivers trying to >>> probe IO space will produce some interesting results. > > >> This is not specific to Octeon, I've seen it on Alchemy as well. A lot of >> drivers, coming from x86, simply assume that x86-Port-IO space is >> always available without having to map it first. I'd say it's a bug in >> the various drivers. > > > Drivers don't have to map I/O space in any way, it's a complete nonsense. > isn't that what ioport_map is for? Manuel From sergei.shtylyov@cogentembedded.com Thu Jul 18 22:49:18 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 22:49:21 +0200 (CEST) Received: from mail-la0-f43.google.com ([209.85.215.43]:48966 "EHLO mail-la0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824769Ab3GRUtRo5MZ8 (ORCPT ); Thu, 18 Jul 2013 22:49:17 +0200 Received: by mail-la0-f43.google.com with SMTP id fh20so1135848lab.16 for ; Thu, 18 Jul 2013 13:49:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:organization:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding:x-gm-message-state; bh=BxmUDm2OoI4ApnSb6Qy3nXqR9L5yuswc+FF0fwHzF4o=; b=hiyK3DmdeGE8IhnzJJvB8X83G9DChxdp71I2vK83rRfTf/zsOAsDw+TFyLd1RH9CWM jLy/oGRsbCg7G9ByAKTiTuf6j3x+T9LV5GwTSeerr+BTDR4e1PTQjyGX9AFkhm7Kuznm nG9WxbIg5ZOiEBGFBB0X0sqCz8G/oxtUiPnvtFTUGob10IgQz0O1TfYIcPOY0Mtr9M5/ EEHUUabfmw8QqMlj2AazJwG+LK8/BfG+l/zB/iOP767UwnHS5H+kOdrp2FtMScIeEN4I r15mdQXQ4fZSb8yTPT/a6Tu3yFjn+ML1wFjV5XfSmouvuQVGPtWp9Utg2npBp7zxIikK adOA== X-Received: by 10.152.19.40 with SMTP id b8mr5973210lae.34.1374180551794; Thu, 18 Jul 2013 13:49:11 -0700 (PDT) Received: from wasted.dev.rtsoft.ru (ppp91-76-85-2.pppoe.mtu-net.ru. [91.76.85.2]) by mx.google.com with ESMTPSA id i9sm4771367lai.4.2013.07.18.13.49.10 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Jul 2013 13:49:10 -0700 (PDT) Message-ID: <51E854CD.9070405@cogentembedded.com> Date: Fri, 19 Jul 2013 00:49:17 +0400 From: Sergei Shtylyov Organization: Cogent Embedded User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 MIME-Version: 1.0 To: Manuel Lauss CC: Aaro Koskinen , David Daney , Faidon Liambotis , Linux-MIPS Subject: Re: octeon: oops/panic with CONFIG_SERIO_I8042=y References: <20130718122556.GA19040@tty.gr> <51E817C6.3030706@gmail.com> <20130718180339.GH14385@blackmetal.musicnaut.iki.fi> <51E84482.6090706@cogentembedded.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQnjwB/4u0zheKOQe0ocWepUCyjVaKex8zwAEkVcMhnffwIO1zmGBkvuH3pRvY1eFYexuX/4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37331 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sergei.shtylyov@cogentembedded.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2173 Lines: 50 On 07/19/2013 12:42 AM, Manuel Lauss wrote: >> On 07/18/2013 11:34 PM, Manuel Lauss wrote: >>>>>> My goal is to run a standard Debian kernel and its octeon variant[1] on >>>>>> the Ubiquity EdgeRouter Lite. The ERLite needs a couple of patches >>>>>> to boot and work (octeon-ethernet patch, octeon-usb driver) but these >>>>>> are already merged 3.11 and I'll file Debian bugs to enable those >>>>>> settings appropriately. >>>>>> 1: e.g. http://packages.debian.org/sid/linux-image-3.10-1-octeon >>>>>> However, when trying to boot a standard Debian kernel in the ERLite I >>>>>> get a 7s delay followed by an oops for a Data bus error on >>>>>> i8042_flush() >>>>>> and ending up with a panic. It looks like the kernel is built with >>>>>> CONFIG_SERIO_I8042=y. The Octeon machine Debian owns prints "i8042: No >>>>>> controller found" but works nevertheless. This isn't the case with the >>>>>> ERLite; I tried 3.2 & 3.10 and got the same oops which went away as >>>>>> soon >>>>>> as I disabled CONFIG_SERIO_I8042. >>>>>> Are there even any octeon machines with i8042 anyway? Should I request >>>>>> for the setting to be disabled irrespective of this bug? >>>>> Yes. There is a rare board called NAC38 that was produced by ASUS >>>>> in a 1U chassis. I don't think it is important to support this, so >>>>> the best thing seems to be not to enable SERIO_I8042 >>>> I think the real bug here is that IO space does not get properly >>>> initialized on Octeon when there is no PCI? So any drivers trying to >>>> probe IO space will produce some interesting results. >>> This is not specific to Octeon, I've seen it on Alchemy as well. A lot of >>> drivers, coming from x86, simply assume that x86-Port-IO space is >>> always available without having to map it first. I'd say it's a bug in >>> the various drivers. >> Drivers don't have to map I/O space in any way, it's a complete nonsense. > isn't that what ioport_map is for? ioport_map() permits to use ioread*()/iowrite*(). in*()/out*() don't need it. It's a job of the arch platform code to map I/O ports into specific memory range if true I/O space doesn't exist. > Manuel WBR, Sergei From ddaney.cavm@gmail.com Thu Jul 18 22:56:07 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Jul 2013 22:56:10 +0200 (CEST) Received: from mail-pd0-f181.google.com ([209.85.192.181]:43481 "EHLO mail-pd0-f181.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824795Ab3GRU4HGfUKi (ORCPT ); Thu, 18 Jul 2013 22:56:07 +0200 Received: by mail-pd0-f181.google.com with SMTP id 14so3463543pdj.40 for ; Thu, 18 Jul 2013 13:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=WYA0gWFjea0oGw+PseujxpmEobdNy0gO/Q176LpNRiI=; b=syATgUgsH3LgsQsJi55Sl2/liG52jQxJjpn1tq9KYiHPGK6vb4+KaMCNyQwPeCMQxg z1m0YfJ5eY/msefbhsU9VOTYm3YyQv+4cvmlbh548UsoJyccCeJ756JBBG3bfwj8mAkq nhyke1dZO1wSjGUbDy4ZvahEKxGFDqHx4z8kwrvIPxJZ/dvbPcGYwpnSBPT6KhK5fbpL u5TcfNF9KQJR1OJgpN19B8UW3H2VsZx+9c0UDQDXRK8Dwvq6A+2zIcsmHy8hlA3/2Xlq 0qyOwFVgK/VKDQvj1YJEMfuYDuNS4tBnoX76DYJzw2GrHuodUMf69qEGHX+Abkdw7RuP s/8g== X-Received: by 10.66.14.196 with SMTP id r4mr15147566pac.57.1374180960805; Thu, 18 Jul 2013 13:56:00 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id iq3sm15527713pbb.20.2013.07.18.13.55.59 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 18 Jul 2013 13:55:59 -0700 (PDT) Message-ID: <51E8565E.9050300@gmail.com> Date: Thu, 18 Jul 2013 13:55:58 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 To: Sergei Shtylyov CC: Manuel Lauss , Aaro Koskinen , Faidon Liambotis , Linux-MIPS Subject: Re: octeon: oops/panic with CONFIG_SERIO_I8042=y References: <20130718122556.GA19040@tty.gr> <51E817C6.3030706@gmail.com> <20130718180339.GH14385@blackmetal.musicnaut.iki.fi> <51E84482.6090706@cogentembedded.com> <51E854CD.9070405@cogentembedded.com> In-Reply-To: <51E854CD.9070405@cogentembedded.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37332 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2502 Lines: 65 On 07/18/2013 01:49 PM, Sergei Shtylyov wrote: > On 07/19/2013 12:42 AM, Manuel Lauss wrote: > >>> On 07/18/2013 11:34 PM, Manuel Lauss wrote: > >>>>>>> My goal is to run a standard Debian kernel and its octeon >>>>>>> variant[1] on >>>>>>> the Ubiquity EdgeRouter Lite. The ERLite needs a couple of patches >>>>>>> to boot and work (octeon-ethernet patch, octeon-usb driver) but >>>>>>> these >>>>>>> are already merged 3.11 and I'll file Debian bugs to enable those >>>>>>> settings appropriately. > >>>>>>> 1: e.g. http://packages.debian.org/sid/linux-image-3.10-1-octeon > >>>>>>> However, when trying to boot a standard Debian kernel in the >>>>>>> ERLite I >>>>>>> get a 7s delay followed by an oops for a Data bus error on >>>>>>> i8042_flush() >>>>>>> and ending up with a panic. It looks like the kernel is built with >>>>>>> CONFIG_SERIO_I8042=y. The Octeon machine Debian owns prints >>>>>>> "i8042: No >>>>>>> controller found" but works nevertheless. This isn't the case >>>>>>> with the >>>>>>> ERLite; I tried 3.2 & 3.10 and got the same oops which went away as >>>>>>> soon >>>>>>> as I disabled CONFIG_SERIO_I8042. > >>>>>>> Are there even any octeon machines with i8042 anyway? Should I >>>>>>> request >>>>>>> for the setting to be disabled irrespective of this bug? > >>>>>> Yes. There is a rare board called NAC38 that was produced by ASUS >>>>>> in a 1U chassis. I don't think it is important to support this, so >>>>>> the best thing seems to be not to enable SERIO_I8042 > >>>>> I think the real bug here is that IO space does not get properly >>>>> initialized on Octeon when there is no PCI? So any drivers trying to >>>>> probe IO space will produce some interesting results. > >>>> This is not specific to Octeon, I've seen it on Alchemy as well. A >>>> lot of >>>> drivers, coming from x86, simply assume that x86-Port-IO space is >>>> always available without having to map it first. I'd say it's a bug in >>>> the various drivers. > >>> Drivers don't have to map I/O space in any way, it's a complete >>> nonsense. > >> isn't that what ioport_map is for? > > ioport_map() permits to use ioread*()/iowrite*(). in*()/out*() don't > need it. It's a job of the arch platform code to map I/O ports into > specific memory range if true I/O space doesn't exist. Yes, somebody should write a patch to do that. Probably we should allocate 64K worth of contiguous pages for this if PCI is not enabled. Who wants to write the patch? I can test it. David Daney From cminyard@mvista.com Fri Jul 19 02:24:15 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Jul 2013 02:24:22 +0200 (CEST) Received: from mail-ob0-f179.google.com ([209.85.214.179]:48859 "EHLO mail-ob0-f179.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6834875Ab3GSAYOSX51S (ORCPT ); Fri, 19 Jul 2013 02:24:14 +0200 Received: by mail-ob0-f179.google.com with SMTP id xk17so4397145obc.38 for ; Thu, 18 Jul 2013 17:24:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :x-gm-message-state; bh=hcrrQ5GUrGrDe2+/UV7y40cEhxO1/TXnAtWQb0byUDQ=; b=T3RXnMcnTZ575beoyK5m/HHkosebpJ+VWS8oF+HYd2rmpIz9L9bBEXnymwBBKi/7Wd aO34o9AT3rtaGdprnAeg5mzJd2gH8VRvdg/LxW3SddpS/2XNazuKqZVhgjPhU2jxAnvk IfQ+7ojzimd7g/TtRO2x8EPShiM8zVpR3pf+EAI4f7tCk1RxtV3g9FBC3/mszKfsQmN8 j8sBvfyirrBnRy0+KafZHRWJhPiVTRXLJyzt5fxQg6CvJzs003j1e+Yw1ZsrKZ/EkxFD 42U1viWp2qAIJa7Q5+W7okEVKB2X1ozvpb5KsrjgBeRAzKKWsa1Bz43TMhVWAFjXMiLZ Uapw== X-Received: by 10.60.138.137 with SMTP id qq9mr15983151oeb.8.1374193447204; Thu, 18 Jul 2013 17:24:07 -0700 (PDT) Received: from [192.168.27.116] (pool-173-74-121-95.dllstx.fios.verizon.net. [173.74.121.95]) by mx.google.com with ESMTPSA id o8sm18241285obx.11.2013.07.18.17.24.05 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Jul 2013 17:24:06 -0700 (PDT) Message-ID: <51E88726.1000705@mvista.com> Date: Thu, 18 Jul 2013 19:24:06 -0500 From: Corey Minyard User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130623 Thunderbird/17.0.7 MIME-Version: 1.0 To: Steven Rostedt CC: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, David Daney Subject: Re: [PATCH] mips/ftrace: Fix function tracing return address to match References: <1373926637-24627-1-git-send-email-ddaney.cavm@gmail.com> <1374178262.6458.266.camel@gandalf.local.home> In-Reply-To: <1374178262.6458.266.camel@gandalf.local.home> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQlq8BsOwZkFRdjy7gnqJzq0nK6tGwqcuOfqwrAK+MlW6DEvQL44wP12+Oww9EvJeqNQddO4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37333 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cminyard@mvista.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1696 Lines: 44 On 07/18/2013 03:11 PM, Steven Rostedt wrote: > On Mon, 2013-07-15 at 15:17 -0700, David Daney wrote: >> From: Corey Minyard >> >> Dynamic function tracing was not working on MIPS. When doing dynamic >> tracing, the tracer attempts to match up the passed in address with >> the one the compiler creates in the mcount tables. The MIPS code was >> passing in the return address from the tracing function call, but the >> compiler tables were the address of the function call. So they >> wouldn't match. >> >> Just subtracting 8 from the return address will give the address of >> the function call. Easy enough. >> >> Signed-off-by: Corey Minyard >> [david.daney@cavium.com: Adjusted code comment and patch Subject.] >> Signed-off-by: David Daney >> --- >> arch/mips/kernel/mcount.S | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S >> index a03e93c..539b629 100644 >> --- a/arch/mips/kernel/mcount.S >> +++ b/arch/mips/kernel/mcount.S >> @@ -83,7 +83,7 @@ _mcount: >> PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp) >> #endif >> >> - move a0, ra /* arg1: self return address */ >> + PTR_SUBU a0, ra, 8 /* arg1: self address */ >> .globl ftrace_call >> ftrace_call: >> nop /* a placeholder for the call to a real tracing function */ > I applied this patch to my Yeeloong Lemote laptop and it causes the > system to crash. Not sure why. I'll try to investigate. > > -- Steve > > That is bizarre. That value should just be used for comparisons, it isn't dereferenced or anything like that. What tracing do you have enabled? -corey From yuasa@linux-mips.org Fri Jul 19 11:26:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Jul 2013 11:26:23 +0200 (CEST) Received: from mo11.iij4u.or.jp ([210.138.174.79]:36247 "EHLO mo.iij4u.or.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816642Ab3GSJ0TXA84F (ORCPT ); Fri, 19 Jul 2013 11:26:19 +0200 Received: by mo.iij4u.or.jp (mo11) id r6J9QFAX024288; Fri, 19 Jul 2013 18:26:15 +0900 Received: from delta (sannin29190.nirai.ne.jp [203.160.29.190]) by mbox.iij4u.or.jp (mbox10) id r6J9QCet018504 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 19 Jul 2013 18:26:14 +0900 Date: Fri, 19 Jul 2013 18:26:11 +0900 From: Yoichi Yuasa To: ralf@linux-mips.org Cc: yuasa@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH] MIPS: ar7: fix redefined UNCAC_BASE and IO_BASE Message-Id: <20130719182611.41aeb79b5711b3c9f849d594@linux-mips.org> X-Mailer: Sylpheed 3.2.0beta5 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37334 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3456 Lines: 83 In file included from arch/mips/include/asm/mach-ar7/spaces.h:23:0, from arch/mips/include/asm/addrspace.h:13, from arch/mips/include/asm/barrier.h:11, from arch/mips/include/asm/bitops.h:18, from include/linux/bitops.h:22, from include/linux/kernel.h:10, from include/asm-generic/bug.h:13, from arch/mips/include/asm/bug.h:41, from include/linux/bug.h:4, from include/linux/page-flags.h:9, from kernel/bounds.c:9: arch/mips/include/asm/mach-generic/spaces.h:28:0: warning: "IO_BASE" redefined [enabled by default] In file included from arch/mips/include/asm/addrspace.h:13:0, from arch/mips/include/asm/barrier.h:11, from arch/mips/include/asm/bitops.h:18, from include/linux/bitops.h:22, from include/linux/kernel.h:10, from include/asm-generic/bug.h:13, from arch/mips/include/asm/bug.h:41, from include/linux/bug.h:4, from include/linux/page-flags.h:9, from kernel/bounds.c:9: arch/mips/include/asm/mach-ar7/spaces.h:21:0: note: this is the location of the previous definition In file included from arch/mips/include/asm/mach-ar7/spaces.h:23:0, from arch/mips/include/asm/addrspace.h:13, from arch/mips/include/asm/barrier.h:11, from arch/mips/include/asm/bitops.h:18, from include/linux/bitops.h:22, from include/linux/kernel.h:10, from include/asm-generic/bug.h:13, from arch/mips/include/asm/bug.h:41, from include/linux/bug.h:4, from include/linux/page-flags.h:9, from kernel/bounds.c:9: arch/mips/include/asm/mach-generic/spaces.h:29:0: warning: "UNCAC_BASE" redefined [enabled by default] In file included from arch/mips/include/asm/addrspace.h:13:0, from arch/mips/include/asm/barrier.h:11, from arch/mips/include/asm/bitops.h:18, from include/linux/bitops.h:22, from include/linux/kernel.h:10, from include/asm-generic/bug.h:13, from arch/mips/include/asm/bug.h:41, from include/linux/bug.h:4, from include/linux/page-flags.h:9, from kernel/bounds.c:9: arch/mips/include/asm/mach-ar7/spaces.h:20:0: note: this is the location of the previous definition In file included from arch/mips/include/asm/mach-ar7/spaces.h:23:0, Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/mach-generic/spaces.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index 5b2f2e6..c5d12b4 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -20,13 +20,22 @@ #endif #ifdef CONFIG_32BIT + +#ifndef CAC_BASE #ifdef CONFIG_KVM_GUEST #define CAC_BASE _AC(0x40000000, UL) #else #define CAC_BASE _AC(0x80000000, UL) #endif +#endif + +#ifndef IO_BASE #define IO_BASE _AC(0xa0000000, UL) +#endif + +#ifndef UNCAC_BASE #define UNCAC_BASE _AC(0xa0000000, UL) +#endif #ifndef MAP_BASE #ifdef CONFIG_KVM_GUEST -- 1.7.9.5 From markos.chandras@gmail.com Fri Jul 19 13:36:22 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Jul 2013 13:36:27 +0200 (CEST) Received: from mail-wg0-f53.google.com ([74.125.82.53]:38331 "EHLO mail-wg0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816822Ab3GSLgWacqMU (ORCPT ); Fri, 19 Jul 2013 13:36:22 +0200 Received: by mail-wg0-f53.google.com with SMTP id y10so3866941wgg.8 for ; Fri, 19 Jul 2013 04:36:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type; bh=kJ2Y/S5S7AHnlHGK8tAJ/0OanKF1ZjC7GrFTcuEm3gQ=; b=0Ri8pgg1AlyDq3NEPgSvtxecWYGu51uHbra7nn3NgozegARjJAthKCy23avkRsAgrt hfI/s/2NQ9qILFwqOJ6YseVmy3owGWNvoGnSyPo8PYAuvNM/OiKzanFm8q1WnCs+RZr6 BT9wqzXb0y5bFgPIfD7PfQE0ZQKkxbx5fj4JOubvkZ7dKhY0+RfoCj8ptTAIOn7/OBwm uwaxBjVsWmH2xktjkL0hX0uWpXEj4AtKc2E9hFaOOGdX82nR7N0T5QX+J2zKYivkLFWx j7/tg/+1C3xZkuFZrtRKej46P81wNXiCRYwXmy/WPSQzUd4zB9kOwh1OLbx1CpcS1Qvn IZfQ== X-Received: by 10.194.8.72 with SMTP id p8mr11957323wja.71.1374233776837; Fri, 19 Jul 2013 04:36:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.194.163.138 with HTTP; Fri, 19 Jul 2013 04:35:36 -0700 (PDT) In-Reply-To: <20130719182611.41aeb79b5711b3c9f849d594@linux-mips.org> References: <20130719182611.41aeb79b5711b3c9f849d594@linux-mips.org> From: Markos Chandras Date: Fri, 19 Jul 2013 12:35:36 +0100 X-Google-Sender-Auth: 9YN29yFa3EcTX5ZDlFDrJqEC8Xw Message-ID: Subject: Re: [PATCH] MIPS: ar7: fix redefined UNCAC_BASE and IO_BASE To: Yoichi Yuasa Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37335 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hwoarang@gentoo.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3900 Lines: 94 On 19 July 2013 10:26, Yoichi Yuasa wrote: > In file included from arch/mips/include/asm/mach-ar7/spaces.h:23:0, > from arch/mips/include/asm/addrspace.h:13, > from arch/mips/include/asm/barrier.h:11, > from arch/mips/include/asm/bitops.h:18, > from include/linux/bitops.h:22, > from include/linux/kernel.h:10, > from include/asm-generic/bug.h:13, > from arch/mips/include/asm/bug.h:41, > from include/linux/bug.h:4, > from include/linux/page-flags.h:9, > from kernel/bounds.c:9: > arch/mips/include/asm/mach-generic/spaces.h:28:0: warning: "IO_BASE" redefined [enabled by default] > In file included from arch/mips/include/asm/addrspace.h:13:0, > from arch/mips/include/asm/barrier.h:11, > from arch/mips/include/asm/bitops.h:18, > from include/linux/bitops.h:22, > from include/linux/kernel.h:10, > from include/asm-generic/bug.h:13, > from arch/mips/include/asm/bug.h:41, > from include/linux/bug.h:4, > from include/linux/page-flags.h:9, > from kernel/bounds.c:9: > arch/mips/include/asm/mach-ar7/spaces.h:21:0: note: this is the location of the previous definition > In file included from arch/mips/include/asm/mach-ar7/spaces.h:23:0, > from arch/mips/include/asm/addrspace.h:13, > from arch/mips/include/asm/barrier.h:11, > from arch/mips/include/asm/bitops.h:18, > from include/linux/bitops.h:22, > from include/linux/kernel.h:10, > from include/asm-generic/bug.h:13, > from arch/mips/include/asm/bug.h:41, > from include/linux/bug.h:4, > from include/linux/page-flags.h:9, > from kernel/bounds.c:9: > arch/mips/include/asm/mach-generic/spaces.h:29:0: warning: "UNCAC_BASE" redefined [enabled by default] > In file included from arch/mips/include/asm/addrspace.h:13:0, > from arch/mips/include/asm/barrier.h:11, > from arch/mips/include/asm/bitops.h:18, > from include/linux/bitops.h:22, > from include/linux/kernel.h:10, > from include/asm-generic/bug.h:13, > from arch/mips/include/asm/bug.h:41, > from include/linux/bug.h:4, > from include/linux/page-flags.h:9, > from kernel/bounds.c:9: > arch/mips/include/asm/mach-ar7/spaces.h:20:0: note: this is the location of the previous definition > In file included from arch/mips/include/asm/mach-ar7/spaces.h:23:0, > > Signed-off-by: Yoichi Yuasa > --- > arch/mips/include/asm/mach-generic/spaces.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h > index 5b2f2e6..c5d12b4 100644 > --- a/arch/mips/include/asm/mach-generic/spaces.h > +++ b/arch/mips/include/asm/mach-generic/spaces.h > @@ -20,13 +20,22 @@ > #endif > > #ifdef CONFIG_32BIT > + > +#ifndef CAC_BASE > #ifdef CONFIG_KVM_GUEST > #define CAC_BASE _AC(0x40000000, UL) > #else > #define CAC_BASE _AC(0x80000000, UL) > #endif > +#endif > + > +#ifndef IO_BASE > #define IO_BASE _AC(0xa0000000, UL) > +#endif > + > +#ifndef UNCAC_BASE > #define UNCAC_BASE _AC(0xa0000000, UL) > +#endif > > #ifndef MAP_BASE > #ifdef CONFIG_KVM_GUEST > -- > 1.7.9.5 > > Hi, Isn't this similar to http://patchwork.linux-mips.org/patch/5583/ ? -- Regards, Markos Chandras - Gentoo Linux Developer http://dev.gentoo.org/~hwoarang From cernekee@gmail.com Fri Jul 19 17:34:58 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Jul 2013 17:35:14 +0200 (CEST) Received: from mail-pa0-f54.google.com ([209.85.220.54]:62288 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816743Ab3GSPe567zio (ORCPT ); Fri, 19 Jul 2013 17:34:57 +0200 Received: by mail-pa0-f54.google.com with SMTP id kx10so4567010pab.13 for ; Fri, 19 Jul 2013 08:34:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=JuxQFi2bP7k/R3RMc9PpqHE5Iw7moWKzq44OIYoTp0k=; b=tZb65nvJT/EHXWh1IvTocKH0gVZN3fhKBPCyfDZ/fAMw6vt+SGsKuEMjRogU4XnafH OALBYNz5SucBG/ztzQ7LbQUOwOHlO1/A8zFofb1nxG4fTYhC9FfZzwFaCHCZ4Vt/1RHD YFXbKz409vYH2ZwB9XtZfMroDDvpHb6MxDmQTfp8I64CvrfqcGRreY4bhOKHXUT68qIi 4cIYRS/3JWonPPKm8Mf4ZPgWkD6tFKrf8xTZL1yVp6HdPbaFg649rbphtaw25mikIxzC hktruqWxPcT8y+BJsIPi1L4xjN3V8zrXLafAvs+vX69fewUHrYYnPTtCINVKmBJdE+uK +WFA== MIME-Version: 1.0 X-Received: by 10.66.163.130 with SMTP id yi2mr18870055pab.7.1374248091050; Fri, 19 Jul 2013 08:34:51 -0700 (PDT) Received: by 10.68.223.194 with HTTP; Fri, 19 Jul 2013 08:34:50 -0700 (PDT) In-Reply-To: <20130618164744.GA21210@linux-mips.org> References: <1371233403-30153-1-git-send-email-kdasu.kdev@gmail.com> <20130618164744.GA21210@linux-mips.org> Date: Fri, 19 Jul 2013 08:34:50 -0700 Message-ID: Subject: Re: [PATCH] MIPS: Fix get_user_page_fast() for mips with cache alias From: Kevin Cernekee To: Ralf Baechle Cc: Kamal Dasu , linux-mips@linux-mips.org, John Crispin Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37336 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 882 Lines: 21 On Tue, Jun 18, 2013 at 9:47 AM, Ralf Baechle wrote: > On Fri, Jun 14, 2013 at 02:10:03PM -0400, Kamal Dasu wrote: > >> get_user_pages_fast() is missing cache flushes for MIPS platforms >> with cache alias. Filesystem failures observed with DirectIO >> operations due to missing flush_anon_page() that use page coloring >> logic to work with cache aliases. This fix falls through to take >> slow_irqon path that calls get_user_pages() that has required >> logic for platforms where cpu_has_dc_aliases is true. > > A bit unsatisfying to always fall back to the slow variant yet I like > the patch because of it's simplicity but I wonder if there's not a > better solution. Hi Ralf, What are your thoughts on pushing this fix to the stable tree for 3.4+? Without Kamal's patch, ntfs-3g is completely broken on MIPS platforms that have cache aliases. Thanks. From glikely@secretlab.ca Sat Jul 20 14:22:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Jul 2013 14:22:53 +0200 (CEST) Received: from mail-wi0-f182.google.com ([209.85.212.182]:60726 "EHLO mail-wi0-f182.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819547Ab3GTMWsfsjM1 (ORCPT ); Sat, 20 Jul 2013 14:22:48 +0200 Received: by mail-wi0-f182.google.com with SMTP id m6so517920wiv.3 for ; Sat, 20 Jul 2013 05:22:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:subject:to:cc:in-reply-to:references:date:message-id :x-gm-message-state; bh=XcdXracHRIgimbtu8T9qLQjEqC1u44dVNmZNhfb2zZc=; b=Xzv/DHI+8xdMbPoT5KRAwqOO6Si8F9BZOIp1eG0chYmnbuuMj5s2hfBcIJkIE6Tp7u GwD6i8JR3YK906dv46BkdMJqor6F2Co6kI9aLjqd+LKd04Fwk5Uj9AHjknw3Skx/clgz Cq23xAsccW6IJjr29xSqU2qL836SGAi2xnI18L3cqgPYBa1XFfUOM59es9lVVIRhwS2C uDxYQck00fLSqMhnMhX4atev2wOgZAaZE5M2JCqPBDEb7HvxW06ivf/Rxy1lPF1t62pV uOGQ9D5DG09njlj8vFXQXrqf26lna210K8LN5hs9bY0mNBXqzKwMFUR1jLUFCwgMVyYh 6Sag== X-Received: by 10.180.211.202 with SMTP id ne10mr13976194wic.39.1374322962843; Sat, 20 Jul 2013 05:22:42 -0700 (PDT) Received: from localhost (dab-bhx1-h-1-2.dab.02.net. [82.132.228.222]) by mx.google.com with ESMTPSA id fd3sm54041091wic.10.2013.07.20.05.22.39 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 20 Jul 2013 05:22:41 -0700 (PDT) Received: by localhost (Postfix, from userid 1000) id C7AC63E0C52; Fri, 19 Jul 2013 22:39:45 -0700 (PDT) From: Grant Likely Subject: Re: [PATCH v2] of: Specify initrd location using 64-bit To: Rob Herring , Santosh Shilimkar Cc: Rob Herring , Geert Uytterhoeven , Sebastian Andrzej Siewior , Jean-Christophe PLAGNIOL-VILLARD , Vineet Gupta , Russell King , Catalin Marinas , Will Deacon , Mark Salter , Aurelien Jacquiot , James Hogan , Michal Simek , Ralf Baechle , Jonas Bonn , Benjamin Herrenschmidt , Paul Mackerras , x86@kernel.org, arm@kernel.org, Chris Zankel , Max Filippov , Nicolas Pitre , linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org, devicetree-discuss@lists.ozlabs.org In-Reply-To: <51D1F5E2.6070609@gmail.com> References: <1372702835-5333-1-git-send-email-santosh.shilimkar@ti.com> <51D1F5E2.6070609@gmail.com> Date: Sat, 20 Jul 2013 06:39:45 +0100 Message-Id: <20130720053945.C7AC63E0C52@localhost> X-Gm-Message-State: ALoCoQm/K43/6HzALS48mveYhOuqpq66Tu66wkLB3IrH6JO2mTIn7bQ+j/UUO8Dy1HUycyrR7B6d Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37337 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@linaro.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1071 Lines: 26 On Mon, 01 Jul 2013 16:34:26 -0500, Rob Herring wrote: > On 07/01/2013 01:20 PM, Santosh Shilimkar wrote: > > On some PAE architectures, the entire range of physical memory could reside > > outside the 32-bit limit. These systems need the ability to specify the > > initrd location using 64-bit numbers. > > > > This patch globally modifies the early_init_dt_setup_initrd_arch() function to > > use 64-bit numbers instead of the current unsigned long. > > > > There has been quite a bit of debate about whether to use u64 or phys_addr_t. > > It was concluded to stick to u64 to be consistent with rest of the device > > tree code. As summarized by Geert, "The address to load the initrd is decided > > by the bootloader/user and set at that point later in time. The dtb should not > > be tied to the kernel you are booting" > > That was quoting me. Otherwise: > > Acked-by: Rob Herring > > Unless Grant feels compelled to pick this up for 3.11, I think it has to > wait for 3.12. Nope, 3.12 is fine. Applied. g. From aaro.koskinen@iki.fi Sat Jul 20 19:39:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Jul 2013 19:39:34 +0200 (CEST) Received: from filtteri1.pp.htv.fi ([213.243.153.184]:50244 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815746Ab3GTRjb0Ppn9 (ORCPT ); Sat, 20 Jul 2013 19:39:31 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id 70F8C21B80F; Sat, 20 Jul 2013 20:39:27 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp5.welho.com ([213.243.153.39]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id CUcsIlYAM3zf; Sat, 20 Jul 2013 20:39:22 +0300 (EEST) Received: from blackmetal.pp.htv.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp5.welho.com (Postfix) with ESMTP id 7A7535BC006; Sat, 20 Jul 2013 20:39:17 +0300 (EEST) From: Aaro Koskinen To: Ralf Baechle , David Daney , Faidon Liambotis , linux-mips@linux-mips.org Cc: Aaro Koskinen Subject: [PATCH] MIPS: cavium-octeon: fix I/O space setup on non-PCI systems Date: Sat, 20 Jul 2013 20:38:51 +0300 Message-Id: <1374341931-10591-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.8.3.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37338 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1679 Lines: 49 Fix I/O space setup, so that on non-PCI systems using inb()/outb() won't crash the system. Some drivers may try to probe I/O space and for that purpose we can just allocate some normal memory. Drivers trying to reserve a region will fail early as we set the size to 0. Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused the originally reported crash. Reported-by: Faidon Liambotis Signed-off-by: Aaro Koskinen --- arch/mips/pci/pci-octeon.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 95c2ea8..1bfdcc8c 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -587,13 +588,16 @@ static int __init octeon_pci_setup(void) octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; /* PCI I/O and PCI MEM values */ - set_io_port_base(OCTEON_PCI_IOSPACE_BASE); - ioport_resource.start = 0; - ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; if (!octeon_is_pci_host()) { pr_notice("Not in host mode, PCI Controller not initialized\n"); + set_io_port_base((unsigned long)vzalloc(IO_SPACE_LIMIT)); + ioport_resource.start = MAX_RESOURCE; + ioport_resource.end = 0; return 0; } + set_io_port_base(OCTEON_PCI_IOSPACE_BASE); + ioport_resource.start = 0; + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; pr_notice("%s Octeon big bar support\n", (octeon_dma_bar_type == -- 1.8.3.2 From yuasa@linux-mips.org Mon Jul 22 07:04:59 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jul 2013 07:05:02 +0200 (CEST) Received: from mo10.iij4u.or.jp ([210.138.174.78]:35613 "EHLO mo.iij4u.or.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815757Ab3GVFE4GKxOe (ORCPT ); Mon, 22 Jul 2013 07:04:56 +0200 Received: by mo.iij4u.or.jp (mo10) id r6M54bUe016120; Mon, 22 Jul 2013 14:04:37 +0900 Received: from delta (sannin29190.nirai.ne.jp [203.160.29.190]) by mbox.iij4u.or.jp (mbox10) id r6M54YGb008000 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 22 Jul 2013 14:04:36 +0900 Date: Mon, 22 Jul 2013 14:04:33 +0900 From: Yoichi Yuasa To: Markos Chandras Cc: yuasa@linux-mips.org, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: ar7: fix redefined UNCAC_BASE and IO_BASE Message-Id: <20130722140433.b905a6248b414c9f43e64b0c@linux-mips.org> In-Reply-To: References: <20130719182611.41aeb79b5711b3c9f849d594@linux-mips.org> X-Mailer: Sylpheed 3.2.0beta5 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37339 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 264 Lines: 15 Hi, On Fri, 19 Jul 2013 12:35:36 +0100 Markos Chandras wrote: > > Hi, > > Isn't this similar to http://patchwork.linux-mips.org/patch/5583/ ? Sure, thank you for pointing out. I think that it is better to also include CAC_BASE. Yoichi From santosh.shilimkar@ti.com Mon Jul 22 16:50:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jul 2013 16:50:58 +0200 (CEST) Received: from comal.ext.ti.com ([198.47.26.152]:35984 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824768Ab3GVOuwhcE8Q (ORCPT ); Mon, 22 Jul 2013 16:50:52 +0200 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r6MEo4xM027754; Mon, 22 Jul 2013 09:50:04 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r6MEo4Ft028910; Mon, 22 Jul 2013 09:50:04 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Mon, 22 Jul 2013 09:50:04 -0500 Received: from [158.218.103.117] (ula0393909.am.dhcp.ti.com [158.218.103.117]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r6MEo2Ql022892; Mon, 22 Jul 2013 09:50:02 -0500 Message-ID: <51ED469A.9000801@ti.com> Date: Mon, 22 Jul 2013 10:50:02 -0400 From: Santosh Shilimkar User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Grant Likely CC: Rob Herring , Rob Herring , Geert Uytterhoeven , Sebastian Andrzej Siewior , Jean-Christophe PLAGNIOL-VILLARD , Vineet Gupta , Russell King , Catalin Marinas , Will Deacon , Mark Salter , Aurelien Jacquiot , James Hogan , Michal Simek , Ralf Baechle , Jonas Bonn , Benjamin Herrenschmidt , Paul Mackerras , , , Chris Zankel , Max Filippov , Nicolas Pitre , , , , , , Subject: Re: [PATCH v2] of: Specify initrd location using 64-bit References: <1372702835-5333-1-git-send-email-santosh.shilimkar@ti.com> <51D1F5E2.6070609@gmail.com> <20130720053945.C7AC63E0C52@localhost> In-Reply-To: <20130720053945.C7AC63E0C52@localhost> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37340 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: santosh.shilimkar@ti.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1166 Lines: 30 On Saturday 20 July 2013 01:39 AM, Grant Likely wrote: > On Mon, 01 Jul 2013 16:34:26 -0500, Rob Herring wrote: >> On 07/01/2013 01:20 PM, Santosh Shilimkar wrote: >>> On some PAE architectures, the entire range of physical memory could reside >>> outside the 32-bit limit. These systems need the ability to specify the >>> initrd location using 64-bit numbers. >>> >>> This patch globally modifies the early_init_dt_setup_initrd_arch() function to >>> use 64-bit numbers instead of the current unsigned long. >>> >>> There has been quite a bit of debate about whether to use u64 or phys_addr_t. >>> It was concluded to stick to u64 to be consistent with rest of the device >>> tree code. As summarized by Geert, "The address to load the initrd is decided >>> by the bootloader/user and set at that point later in time. The dtb should not >>> be tied to the kernel you are booting" >> >> That was quoting me. Otherwise: >> >> Acked-by: Rob Herring >> >> Unless Grant feels compelled to pick this up for 3.11, I think it has to >> wait for 3.12. > > Nope, 3.12 is fine. Applied. > Thanks Grant. Regards, Santosh From plagnioj@jcrosoft.com Mon Jul 22 17:04:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jul 2013 17:04:53 +0200 (CEST) Received: from 7.mo2.mail-out.ovh.net ([188.165.48.182]:59623 "EHLO mo2.mail-out.ovh.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6825727Ab3GVPEn4oBvL (ORCPT ); Mon, 22 Jul 2013 17:04:43 +0200 Received: from mail95.ha.ovh.net (gw6.ovh.net [213.251.189.206]) by mo2.mail-out.ovh.net (Postfix) with SMTP id 81C0FDC42C2 for ; Mon, 22 Jul 2013 17:04:40 +0200 (CEST) Received: from b0.ovh.net (HELO queueout) (213.186.33.50) by b0.ovh.net with SMTP; 22 Jul 2013 17:04:40 +0200 Received: from ns203013.ovh.net (HELO localhost) (plagnioj%jcrosoft.com@91.121.171.124) by ns0.ovh.net with SMTP; 22 Jul 2013 17:04:38 +0200 Date: Mon, 22 Jul 2013 17:01:35 +0200 From: Jean-Christophe PLAGNIOL-VILLARD To: Santosh Shilimkar Cc: grant.likely@linaro.org, Rob Herring , Geert Uytterhoeven , Sebastian Andrzej Siewior , Vineet Gupta , Russell King , Catalin Marinas , Will Deacon , Mark Salter , Aurelien Jacquiot , James Hogan , Michal Simek , Ralf Baechle , Jonas Bonn , Benjamin Herrenschmidt , Paul Mackerras , x86@kernel.org, arm@kernel.org, Chris Zankel , Max Filippov , robherring2@gmail.com, Nicolas Pitre , linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org, devicetree-discuss@lists.ozlabs.org X-Ovh-Mailout: 178.32.228.2 (mo2.mail-out.ovh.net) Subject: Re: [PATCH v2] of: Specify initrd location using 64-bit Message-ID: <20130722150135.GI16015@ns203013.ovh.net> References: <1372702835-5333-1-git-send-email-santosh.shilimkar@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1372702835-5333-1-git-send-email-santosh.shilimkar@ti.com> X-PGP-Key: http://uboot.jcrosoft.org/plagnioj.asc X-PGP-key-fingerprint: 6309 2BBA 16C8 3A07 1772 CC24 DEFC FFA3 279C CE7C User-Agent: Mutt/1.5.21 (2010-09-15) X-Ovh-Tracer-Id: 5277655814110751709 X-Ovh-Remote: 91.121.171.124 (ns203013.ovh.net) X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) X-OVH-SPAMSTATE: OK X-OVH-SPAMSCORE: -100 X-OVH-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeijedrfedvucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeijedrfedvucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37341 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: plagnioj@jcrosoft.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 10678 Lines: 279 On 14:20 Mon 01 Jul , Santosh Shilimkar wrote: > On some PAE architectures, the entire range of physical memory could reside > outside the 32-bit limit. These systems need the ability to specify the > initrd location using 64-bit numbers. > > This patch globally modifies the early_init_dt_setup_initrd_arch() function to > use 64-bit numbers instead of the current unsigned long. > > There has been quite a bit of debate about whether to use u64 or phys_addr_t. > It was concluded to stick to u64 to be consistent with rest of the device > tree code. As summarized by Geert, "The address to load the initrd is decided > by the bootloader/user and set at that point later in time. The dtb should not > be tied to the kernel you are booting" > > More details on the discussion can be found here: > https://lkml.org/lkml/2013/6/20/690 > https://lkml.org/lkml/2012/9/13/544 > > Cc: Grant Likely > Cc: Rob Herring > Cc: Geert Uytterhoeven > Cc: Sebastian Andrzej Siewior > Cc: Jean-Christophe PLAGNIOL-VILLARD > Cc: Vineet Gupta > Cc: Russell King > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Salter > Cc: Aurelien Jacquiot > Cc: James Hogan > Cc: Michal Simek > Cc: Ralf Baechle > Cc: Jonas Bonn > Cc: Benjamin Herrenschmidt > Cc: Paul Mackerras > Cc: x86@kernel.org > Cc: arm@kernel.org > Cc: Chris Zankel > Cc: Max Filippov > Cc: bigeasy@linutronix.de > Cc: robherring2@gmail.com > Cc: Nicolas Pitre Acked-by: Jean-Christophe PLAGNIOL-VILLARD > > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-c6x-dev@linux-c6x.org > Cc: linux-mips@linux-mips.org > Cc: linuxppc-dev@lists.ozlabs.org > Cc: linux-xtensa@linux-xtensa.org > Cc: devicetree-discuss@lists.ozlabs.org > > Signed-off-by: Santosh Shilimkar > --- > arch/arc/mm/init.c | 5 ++--- > arch/arm/mm/init.c | 2 +- > arch/arm64/mm/init.c | 3 +-- > arch/c6x/kernel/devicetree.c | 3 +-- > arch/metag/mm/init.c | 5 ++--- > arch/microblaze/kernel/prom.c | 3 +-- > arch/mips/kernel/prom.c | 3 +-- > arch/openrisc/kernel/prom.c | 3 +-- > arch/powerpc/kernel/prom.c | 3 +-- > arch/x86/kernel/devicetree.c | 3 +-- > arch/xtensa/kernel/setup.c | 3 +-- > drivers/of/fdt.c | 10 ++++++---- > include/linux/of_fdt.h | 3 +-- > 13 files changed, 20 insertions(+), 29 deletions(-) > > diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c > index 4a17736..7991e08 100644 > --- a/arch/arc/mm/init.c > +++ b/arch/arc/mm/init.c > @@ -157,9 +157,8 @@ void __init free_initrd_mem(unsigned long start, unsigned long end) > #endif > > #ifdef CONFIG_OF_FLATTREE > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > - pr_err("%s(%lx, %lx)\n", __func__, start, end); > + pr_err("%s(%llx, %llx)\n", __func__, start, end); > } > #endif /* CONFIG_OF_FLATTREE */ > diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c > index 9a5cdc0..afeaef7 100644 > --- a/arch/arm/mm/init.c > +++ b/arch/arm/mm/init.c > @@ -76,7 +76,7 @@ static int __init parse_tag_initrd2(const struct tag *tag) > __tagtable(ATAG_INITRD2, parse_tag_initrd2); > > #ifdef CONFIG_OF_FLATTREE > -void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > phys_initrd_start = start; > phys_initrd_size = end - start; > diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c > index f497ca7..7047708 100644 > --- a/arch/arm64/mm/init.c > +++ b/arch/arm64/mm/init.c > @@ -44,8 +44,7 @@ static unsigned long phys_initrd_size __initdata = 0; > > phys_addr_t memstart_addr __read_mostly = 0; > > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > phys_initrd_start = start; > phys_initrd_size = end - start; > diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c > index bdb56f0..287d0e6 100644 > --- a/arch/c6x/kernel/devicetree.c > +++ b/arch/c6x/kernel/devicetree.c > @@ -33,8 +33,7 @@ void __init early_init_devtree(void *params) > > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c > index d05b845..bdc4811 100644 > --- a/arch/metag/mm/init.c > +++ b/arch/metag/mm/init.c > @@ -419,10 +419,9 @@ void free_initrd_mem(unsigned long start, unsigned long end) > #endif > > #ifdef CONFIG_OF_FLATTREE > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > - pr_err("%s(%lx, %lx)\n", > + pr_err("%s(%llx, %llx)\n", > __func__, start, end); > } > #endif /* CONFIG_OF_FLATTREE */ > diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c > index 0a2c68f..62e2e8f 100644 > --- a/arch/microblaze/kernel/prom.c > +++ b/arch/microblaze/kernel/prom.c > @@ -136,8 +136,7 @@ void __init early_init_devtree(void *params) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c > index 5712bb5..32b8788 100644 > --- a/arch/mips/kernel/prom.c > +++ b/arch/mips/kernel/prom.c > @@ -58,8 +58,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/openrisc/kernel/prom.c b/arch/openrisc/kernel/prom.c > index 5869e3f..150215a 100644 > --- a/arch/openrisc/kernel/prom.c > +++ b/arch/openrisc/kernel/prom.c > @@ -96,8 +96,7 @@ void __init early_init_devtree(void *params) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c > index 8b6f7a9..2f3e252 100644 > --- a/arch/powerpc/kernel/prom.c > +++ b/arch/powerpc/kernel/prom.c > @@ -550,8 +550,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c > index b158152..2fbad6b 100644 > --- a/arch/x86/kernel/devicetree.c > +++ b/arch/x86/kernel/devicetree.c > @@ -52,8 +52,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) > } > > #ifdef CONFIG_BLK_DEV_INITRD > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (unsigned long)__va(start); > initrd_end = (unsigned long)__va(end); > diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c > index 6dd25ec..d45e602 100644 > --- a/arch/xtensa/kernel/setup.c > +++ b/arch/xtensa/kernel/setup.c > @@ -170,8 +170,7 @@ static int __init parse_tag_fdt(const bp_tag_t *tag) > > __tagtable(BP_TAG_FDT, parse_tag_fdt); > > -void __init early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end) > +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) > { > initrd_start = (void *)__va(start); > initrd_end = (void *)__va(end); > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c > index 808be06..21123b8 100644 > --- a/drivers/of/fdt.c > +++ b/drivers/of/fdt.c > @@ -550,7 +550,8 @@ int __init of_flat_dt_match(unsigned long node, const char *const *compat) > */ > void __init early_init_dt_check_for_initrd(unsigned long node) > { > - unsigned long start, end, len; > + u64 start, end; > + unsigned long len; > __be32 *prop; > > pr_debug("Looking for initrd properties... "); > @@ -558,15 +559,16 @@ void __init early_init_dt_check_for_initrd(unsigned long node) > prop = of_get_flat_dt_prop(node, "linux,initrd-start", &len); > if (!prop) > return; > - start = of_read_ulong(prop, len/4); > + start = of_read_number(prop, len/4); > > prop = of_get_flat_dt_prop(node, "linux,initrd-end", &len); > if (!prop) > return; > - end = of_read_ulong(prop, len/4); > + end = of_read_number(prop, len/4); > > early_init_dt_setup_initrd_arch(start, end); > - pr_debug("initrd_start=0x%lx initrd_end=0x%lx\n", start, end); > + pr_debug("initrd_start=0x%llx initrd_end=0x%llx\n", > + (unsigned long long)start, (unsigned long long)end); > } > #else > inline void early_init_dt_check_for_initrd(unsigned long node) > diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h > index ed136ad..4a17939 100644 > --- a/include/linux/of_fdt.h > +++ b/include/linux/of_fdt.h > @@ -106,8 +106,7 @@ extern u64 dt_mem_next_cell(int s, __be32 **cellp); > * physical addresses. > */ > #ifdef CONFIG_BLK_DEV_INITRD > -extern void early_init_dt_setup_initrd_arch(unsigned long start, > - unsigned long end); > +extern void early_init_dt_setup_initrd_arch(u64 start, u64 end); > #endif > > /* Early flat tree scan hooks */ > -- > 1.7.9.5 > From ddaney.cavm@gmail.com Mon Jul 22 19:14:25 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jul 2013 19:14:31 +0200 (CEST) Received: from mail-pb0-f52.google.com ([209.85.160.52]:44830 "EHLO mail-pb0-f52.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824793Ab3GVROZmJwPt (ORCPT ); Mon, 22 Jul 2013 19:14:25 +0200 Received: by mail-pb0-f52.google.com with SMTP id xa12so7266814pbc.25 for ; Mon, 22 Jul 2013 10:14:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=F/SeiZsMDudGY0KK63pAj9pDh7ExM904xMMAQRw1KEg=; b=Z+WsL4rDhHNEmFiHp+F0uTdjzHPe6W7RdCMPjRwJSH9iZ0+TfkbunFvnXiY0jNv/rC eQT+NLXGyW5hNL/U5GlB4XF0z1n2zLB7OJUNNOxvmu4lTIKGWBuitHZ2hB2udYCSe+he DdkEB8EgdVVH93l6LxQ25aUbgtR+zF/R+4JQsE9JM5H6dzdpToj849uEGsgE7emdYmTz kO6P4lnFKHRhTZwz3GKaFNGEEM2TSqijRYGfy2OKGXTjXcH38pmZcStXyOkY9I+Z5XIi MIgaBHM0dSsoX+doLZtlzWRXRViwzExidlZLCiMqoNRrsrOmVK9yBfYchHM+cja5eVc+ +LNw== X-Received: by 10.66.253.40 with SMTP id zx8mr33376174pac.71.1374513257951; Mon, 22 Jul 2013 10:14:17 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id td5sm7866069pac.16.2013.07.22.10.14.15 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 22 Jul 2013 10:14:16 -0700 (PDT) Message-ID: <51ED6866.1020702@gmail.com> Date: Mon, 22 Jul 2013 10:14:14 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Aaro Koskinen , Ralf Baechle CC: David Daney , Faidon Liambotis , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: cavium-octeon: fix I/O space setup on non-PCI systems References: <1374341931-10591-1-git-send-email-aaro.koskinen@iki.fi> In-Reply-To: <1374341931-10591-1-git-send-email-aaro.koskinen@iki.fi> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37342 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2017 Lines: 64 On 07/20/2013 10:38 AM, Aaro Koskinen wrote: > Fix I/O space setup, so that on non-PCI systems using inb()/outb() > won't crash the system. Some drivers may try to probe I/O space and for > that purpose we can just allocate some normal memory. Drivers trying to > reserve a region will fail early as we set the size to 0. > > Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused > the originally reported crash. > > Reported-by: Faidon Liambotis > Signed-off-by: Aaro Koskinen NACK. This doesn't handle the following cases: 1) CONFIG_PCI=n 2) SoCs with PCIe I think we need to move the 'if (!octeon_is_pci_host())' block to a place where it will always run. David Daney > --- > arch/mips/pci/pci-octeon.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c > index 95c2ea8..1bfdcc8c 100644 > --- a/arch/mips/pci/pci-octeon.c > +++ b/arch/mips/pci/pci-octeon.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -587,13 +588,16 @@ static int __init octeon_pci_setup(void) > octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; > > /* PCI I/O and PCI MEM values */ > - set_io_port_base(OCTEON_PCI_IOSPACE_BASE); > - ioport_resource.start = 0; > - ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; > if (!octeon_is_pci_host()) { > pr_notice("Not in host mode, PCI Controller not initialized\n"); > + set_io_port_base((unsigned long)vzalloc(IO_SPACE_LIMIT)); > + ioport_resource.start = MAX_RESOURCE; > + ioport_resource.end = 0; > return 0; > } > + set_io_port_base(OCTEON_PCI_IOSPACE_BASE); > + ioport_resource.start = 0; > + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; > > pr_notice("%s Octeon big bar support\n", > (octeon_dma_bar_type == > From aaro.koskinen@iki.fi Mon Jul 22 21:55:49 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jul 2013 21:55:53 +0200 (CEST) Received: from filtteri1.pp.htv.fi ([213.243.153.184]:50595 "EHLO filtteri1.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825721Ab3GVTztqR0jz (ORCPT ); Mon, 22 Jul 2013 21:55:49 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri1.pp.htv.fi (Postfix) with ESMTP id 2FCD321B77E; Mon, 22 Jul 2013 22:55:46 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp4.welho.com ([213.243.153.38]) by localhost (filtteri1.pp.htv.fi [213.243.153.184]) (amavisd-new, port 10024) with ESMTP id IICZrZM0gFjv; Mon, 22 Jul 2013 22:55:42 +0300 (EEST) Received: from blackmetal.pp.htv.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp4.welho.com (Postfix) with ESMTP id E6C725BC005; Mon, 22 Jul 2013 22:55:41 +0300 (EEST) From: Aaro Koskinen To: Ralf Baechle , David Daney , Faidon Liambotis , linux-mips@linux-mips.org Cc: Aaro Koskinen Subject: [PATCH v2] MIPS: cavium-octeon: fix I/O space setup on non-PCI systems Date: Mon, 22 Jul 2013 22:55:01 +0300 Message-Id: <1374522901-30290-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.8.3.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37343 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3005 Lines: 92 Fix I/O space setup, so that on non-PCI systems using inb()/outb() won't crash the system. Some drivers may try to probe I/O space and for that purpose we can just allocate some normal memory initially. Drivers trying to reserve a region will fail early as we set the size to 0. If a real I/O space is present, the PCI/PCIe support code will re-adjust the values accordingly. Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused the originally reported crash. Reported-by: Faidon Liambotis Signed-off-by: Aaro Koskinen --- v2: Address the issues found from the first version of the patch (http://marc.info/?t=137434204000002&r=1&w=2). arch/mips/cavium-octeon/setup.c | 28 ++++++++++++++++++++++++++++ arch/mips/pci/pci-octeon.c | 9 +++++---- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 48b08eb..6775bd1 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -8,6 +8,7 @@ * written by Ralf Baechle */ #include +#include #include #include #include @@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) return err; } device_initcall(edac_devinit); + +static void __initdata *octeon_dummy_iospace; + +static int __init octeon_no_pci_init(void) +{ + /* + * Initially assume there is no PCI. The PCI/PCIe platform code will + * later re-initialize these to correct values if they are present. + */ + octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); + set_io_port_base((unsigned long)octeon_dummy_iospace); + ioport_resource.start = MAX_RESOURCE; + ioport_resource.end = 0; + return 0; +} +arch_initcall(octeon_no_pci_init); + +static int __init octeon_no_pci_release(void) +{ + /* + * Release the allocated memory if a real IO space is there. + */ + if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) + vfree(octeon_dummy_iospace); + return 0; +} +late_initcall(octeon_no_pci_release); diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 95c2ea8..59cccd9 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -586,15 +586,16 @@ static int __init octeon_pci_setup(void) else octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; - /* PCI I/O and PCI MEM values */ - set_io_port_base(OCTEON_PCI_IOSPACE_BASE); - ioport_resource.start = 0; - ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; if (!octeon_is_pci_host()) { pr_notice("Not in host mode, PCI Controller not initialized\n"); return 0; } + /* PCI I/O and PCI MEM values */ + set_io_port_base(OCTEON_PCI_IOSPACE_BASE); + ioport_resource.start = 0; + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; + pr_notice("%s Octeon big bar support\n", (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); -- 1.8.3.2 From ddaney.cavm@gmail.com Mon Jul 22 22:09:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jul 2013 22:09:07 +0200 (CEST) Received: from mail-gg0-f169.google.com ([209.85.161.169]:33790 "EHLO mail-gg0-f169.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825721Ab3GVUJFF2eF4 (ORCPT ); Mon, 22 Jul 2013 22:09:05 +0200 Received: by mail-gg0-f169.google.com with SMTP id b1so2194506ggn.14 for ; Mon, 22 Jul 2013 13:08:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=1InLe7v7NjYHXLBQ8G3rpRIS6+3D3UpshVdu4cvW1YE=; b=y36pr2CQr+Am2RQEYFJVJMMFBUNtODkzttcDbqciBP0jsgXqQbrdicFOIxQnftZpN+ r75Yzcc5Xur6zm1lwcqCidlMifFxfWTfP3w6mS770LU8v+LOv3atCsZ/ejAT3g8S/jP8 l5aY8wAXgqzPFsffXalVCw5zYIZqcfAUUFscKq6+3H5XBow5b9yms+FiIeIiSI9TGHaK RT4nkxm+CX8xmCam9PQpLbQYEZCvVcD9wiOwiCLvJWEH6nBbpLtCk3dT56XvsfK5pAEO iirdv8u2OtKj7sKW1sH5nhhgWDCKyPyQq224yU8vesW1JUHO9SMjcexLReOZuHDleNcZ w6DQ== X-Received: by 10.236.137.142 with SMTP id y14mr14011567yhi.65.1374523738992; Mon, 22 Jul 2013 13:08:58 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id o32sm41094422yhi.5.2013.07.22.13.08.57 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 22 Jul 2013 13:08:58 -0700 (PDT) Message-ID: <51ED9153.4080904@gmail.com> Date: Mon, 22 Jul 2013 13:08:51 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Aaro Koskinen , Ralf Baechle CC: David Daney , Faidon Liambotis , linux-mips@linux-mips.org Subject: Re: [PATCH v2] MIPS: cavium-octeon: fix I/O space setup on non-PCI systems References: <1374522901-30290-1-git-send-email-aaro.koskinen@iki.fi> In-Reply-To: <1374522901-30290-1-git-send-email-aaro.koskinen@iki.fi> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37344 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3383 Lines: 101 On 07/22/2013 12:55 PM, Aaro Koskinen wrote: > Fix I/O space setup, so that on non-PCI systems using inb()/outb() > won't crash the system. Some drivers may try to probe I/O space and for > that purpose we can just allocate some normal memory initially. Drivers > trying to reserve a region will fail early as we set the size to 0. If > a real I/O space is present, the PCI/PCIe support code will re-adjust > the values accordingly. > > Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused > the originally reported crash. > > Reported-by: Faidon Liambotis > Signed-off-by: Aaro Koskinen > --- > > v2: Address the issues found from the first version of the patch > (http://marc.info/?t=137434204000002&r=1&w=2). > > arch/mips/cavium-octeon/setup.c | 28 ++++++++++++++++++++++++++++ > arch/mips/pci/pci-octeon.c | 9 +++++---- > 2 files changed, 33 insertions(+), 4 deletions(-) > > diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c > index 48b08eb..6775bd1 100644 > --- a/arch/mips/cavium-octeon/setup.c > +++ b/arch/mips/cavium-octeon/setup.c > @@ -8,6 +8,7 @@ > * written by Ralf Baechle > */ > #include > +#include > #include > #include > #include > @@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) > return err; > } > device_initcall(edac_devinit); > + > +static void __initdata *octeon_dummy_iospace; > + > +static int __init octeon_no_pci_init(void) > +{ > + /* > + * Initially assume there is no PCI. The PCI/PCIe platform code will > + * later re-initialize these to correct values if they are present. > + */ > + octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); > + set_io_port_base((unsigned long)octeon_dummy_iospace); > + ioport_resource.start = MAX_RESOURCE; > + ioport_resource.end = 0; > + return 0; > +} > +arch_initcall(octeon_no_pci_init); > + Do we have any guarantee that this will happen before the arch/mips/pci/* arch_initcalls ? If not, can we move this to a core_iitcall? David Daney > +static int __init octeon_no_pci_release(void) > +{ > + /* > + * Release the allocated memory if a real IO space is there. > + */ > + if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) > + vfree(octeon_dummy_iospace); > + return 0; > +} > +late_initcall(octeon_no_pci_release); > diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c > index 95c2ea8..59cccd9 100644 > --- a/arch/mips/pci/pci-octeon.c > +++ b/arch/mips/pci/pci-octeon.c > @@ -586,15 +586,16 @@ static int __init octeon_pci_setup(void) > else > octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; > > - /* PCI I/O and PCI MEM values */ > - set_io_port_base(OCTEON_PCI_IOSPACE_BASE); > - ioport_resource.start = 0; > - ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; > if (!octeon_is_pci_host()) { > pr_notice("Not in host mode, PCI Controller not initialized\n"); > return 0; > } > > + /* PCI I/O and PCI MEM values */ > + set_io_port_base(OCTEON_PCI_IOSPACE_BASE); > + ioport_resource.start = 0; > + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; > + > pr_notice("%s Octeon big bar support\n", > (octeon_dma_bar_type == > OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); > From aaro.koskinen@iki.fi Mon Jul 22 22:39:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jul 2013 22:39:25 +0200 (CEST) Received: from filtteri2.pp.htv.fi ([213.243.153.185]:39012 "EHLO filtteri2.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824761Ab3GVUjXYosUY (ORCPT ); Mon, 22 Jul 2013 22:39:23 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri2.pp.htv.fi (Postfix) with ESMTP id 91ACA19BE32; Mon, 22 Jul 2013 23:39:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp5.welho.com ([213.243.153.39]) by localhost (filtteri2.pp.htv.fi [213.243.153.185]) (amavisd-new, port 10024) with ESMTP id ubda5iXSwWYu; Mon, 22 Jul 2013 23:39:18 +0300 (EEST) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp5.welho.com (Postfix) with SMTP id 5CCB85BC003; Mon, 22 Jul 2013 23:39:17 +0300 (EEST) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Mon, 22 Jul 2013 23:39:12 +0300 Date: Mon, 22 Jul 2013 23:39:12 +0300 From: Aaro Koskinen To: David Daney Cc: Ralf Baechle , David Daney , Faidon Liambotis , linux-mips@linux-mips.org Subject: Re: [PATCH v2] MIPS: cavium-octeon: fix I/O space setup on non-PCI systems Message-ID: <20130722203912.GA31864@blackmetal.musicnaut.iki.fi> References: <1374522901-30290-1-git-send-email-aaro.koskinen@iki.fi> <51ED9153.4080904@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <51ED9153.4080904@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37345 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2575 Lines: 71 On Mon, Jul 22, 2013 at 01:08:51PM -0700, David Daney wrote: > On 07/22/2013 12:55 PM, Aaro Koskinen wrote: > >Fix I/O space setup, so that on non-PCI systems using inb()/outb() > >won't crash the system. Some drivers may try to probe I/O space and for > >that purpose we can just allocate some normal memory initially. Drivers > >trying to reserve a region will fail early as we set the size to 0. If > >a real I/O space is present, the PCI/PCIe support code will re-adjust > >the values accordingly. > > > >Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused > >the originally reported crash. > > > >Reported-by: Faidon Liambotis > >Signed-off-by: Aaro Koskinen > >--- > > > > v2: Address the issues found from the first version of the patch > > (http://marc.info/?t=137434204000002&r=1&w=2). > > > > arch/mips/cavium-octeon/setup.c | 28 ++++++++++++++++++++++++++++ > > arch/mips/pci/pci-octeon.c | 9 +++++---- > > 2 files changed, 33 insertions(+), 4 deletions(-) > > > >diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c > >index 48b08eb..6775bd1 100644 > >--- a/arch/mips/cavium-octeon/setup.c > >+++ b/arch/mips/cavium-octeon/setup.c > >@@ -8,6 +8,7 @@ > > * written by Ralf Baechle > > */ > > #include > >+#include > > #include > > #include > > #include > >@@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) > > return err; > > } > > device_initcall(edac_devinit); > >+ > >+static void __initdata *octeon_dummy_iospace; > >+ > >+static int __init octeon_no_pci_init(void) > >+{ > >+ /* > >+ * Initially assume there is no PCI. The PCI/PCIe platform code will > >+ * later re-initialize these to correct values if they are present. > >+ */ > >+ octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); > >+ set_io_port_base((unsigned long)octeon_dummy_iospace); > >+ ioport_resource.start = MAX_RESOURCE; > >+ ioport_resource.end = 0; > >+ return 0; > >+} > >+arch_initcall(octeon_no_pci_init); > >+ > > Do we have any guarantee that this will happen before the > arch/mips/pci/* arch_initcalls ? Yes, it's guaranteed by the linking order ie. in which order the obj-y stuff gets listed in mips/Makefile. Currently cavium-octeon/ is processed before pci/. Quoting including/linux/init.h: /* initcalls are now grouped by functionality into separate * subsections. Ordering inside the subsections is determined * by link order. A. From David.Daney@caviumnetworks.com Mon Jul 22 22:58:19 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jul 2013 22:58:22 +0200 (CEST) Received: from mail-by2lp0244.outbound.protection.outlook.com ([207.46.163.244]:30722 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6826533Ab3GVU6TNgWDg (ORCPT ); Mon, 22 Jul 2013 22:58:19 +0200 Received: from BL2PRD0712HT004.namprd07.prod.outlook.com (10.255.236.37) by BLUPR07MB146.namprd07.prod.outlook.com (10.242.200.14) with Microsoft SMTP Server (TLS) id 15.0.731.16; Mon, 22 Jul 2013 20:58:10 +0000 Received: from dl.caveonetworks.com (64.2.3.195) by pod51018.outlook.com (10.255.236.37) with Microsoft SMTP Server (TLS) id 14.16.329.3; Mon, 22 Jul 2013 20:58:07 +0000 Message-ID: <51ED9CDD.2090507@caviumnetworks.com> Date: Mon, 22 Jul 2013 13:58:05 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Aaro Koskinen CC: David Daney , Ralf Baechle , David Daney , Faidon Liambotis , Subject: Re: [PATCH v2] MIPS: cavium-octeon: fix I/O space setup on non-PCI systems References: <1374522901-30290-1-git-send-email-aaro.koskinen@iki.fi> <51ED9153.4080904@gmail.com> <20130722203912.GA31864@blackmetal.musicnaut.iki.fi> In-Reply-To: <20130722203912.GA31864@blackmetal.musicnaut.iki.fi> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.195] X-Forefront-PRVS: 0915875B28 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(51704005)(164054003)(189002)(24454002)(199002)(377454003)(479174003)(19580405001)(56776001)(76786001)(81542001)(74502001)(47976001)(54316002)(54356001)(23756003)(74662001)(50986001)(53806001)(47736001)(69226001)(66066001)(53416003)(31966008)(19580385001)(65956001)(77096001)(80022001)(76796001)(64126003)(51856001)(36756003)(47446002)(15202345003)(19580395003)(15395725003)(50466002)(33656001)(59896001)(79102001)(80316001)(47776003)(74876001)(49866001)(4396001)(59766001)(16406001)(56816003)(77982001)(81342001)(46102001)(74706001)(76482001)(83322001)(65806001)(74366001)(83072001)(63696002)(6606295002);DIR:OUT;SFP:;SCL:1;SRVR:BLUPR07MB146;H:BL2PRD0712HT004.namprd07.prod.outlook.com;CLIP:64.2.3.195;RD:InfoNoRecords;MX:1;A:1;LANG:en; X-OriginatorOrg: DuplicateDomain-a3ec847f-e37f-4d9a-9900-9d9d96f75f58.caviumnetworks.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37346 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3041 Lines: 86 On 07/22/2013 01:39 PM, Aaro Koskinen wrote: > On Mon, Jul 22, 2013 at 01:08:51PM -0700, David Daney wrote: >> On 07/22/2013 12:55 PM, Aaro Koskinen wrote: >>> Fix I/O space setup, so that on non-PCI systems using inb()/outb() >>> won't crash the system. Some drivers may try to probe I/O space and for >>> that purpose we can just allocate some normal memory initially. Drivers >>> trying to reserve a region will fail early as we set the size to 0. If >>> a real I/O space is present, the PCI/PCIe support code will re-adjust >>> the values accordingly. >>> >>> Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused >>> the originally reported crash. >>> >>> Reported-by: Faidon Liambotis >>> Signed-off-by: Aaro Koskinen >>> --- >>> >>> v2: Address the issues found from the first version of the patch >>> (http://marc.info/?t=137434204000002&r=1&w=2). >>> >>> arch/mips/cavium-octeon/setup.c | 28 ++++++++++++++++++++++++++++ >>> arch/mips/pci/pci-octeon.c | 9 +++++---- >>> 2 files changed, 33 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c >>> index 48b08eb..6775bd1 100644 >>> --- a/arch/mips/cavium-octeon/setup.c >>> +++ b/arch/mips/cavium-octeon/setup.c >>> @@ -8,6 +8,7 @@ >>> * written by Ralf Baechle >>> */ >>> #include >>> +#include >>> #include >>> #include >>> #include >>> @@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) >>> return err; >>> } >>> device_initcall(edac_devinit); >>> + >>> +static void __initdata *octeon_dummy_iospace; >>> + >>> +static int __init octeon_no_pci_init(void) >>> +{ >>> + /* >>> + * Initially assume there is no PCI. The PCI/PCIe platform code will >>> + * later re-initialize these to correct values if they are present. >>> + */ >>> + octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); >>> + set_io_port_base((unsigned long)octeon_dummy_iospace); >>> + ioport_resource.start = MAX_RESOURCE; >>> + ioport_resource.end = 0; >>> + return 0; >>> +} >>> +arch_initcall(octeon_no_pci_init); >>> + >> >> Do we have any guarantee that this will happen before the >> arch/mips/pci/* arch_initcalls ? > > Yes, it's guaranteed by the linking order ie. in which order the obj-y > stuff gets listed in mips/Makefile. Currently cavium-octeon/ is processed > before pci/. > Yes, I understand that. The problem is when we start to use things like GCC's LTO, where we effectively compile the entire kernel as a single file. Will this still work then? I would rather not screw around with it. Can you test it by making it a core_initcall() instead? If that works you can add Acked-by: me. Thanks, David Daney > Quoting including/linux/init.h: > > /* initcalls are now grouped by functionality into separate > * subsections. Ordering inside the subsections is determined > * by link order. > > A. > From aaro.koskinen@iki.fi Tue Jul 23 00:27:08 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 00:27:11 +0200 (CEST) Received: from filtteri6.pp.htv.fi ([213.243.153.189]:33734 "EHLO filtteri6.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6826582Ab3GVW1IbfI4T (ORCPT ); Tue, 23 Jul 2013 00:27:08 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri6.pp.htv.fi (Postfix) with ESMTP id D3A8B56F731; Tue, 23 Jul 2013 01:27:06 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp4.welho.com ([213.243.153.38]) by localhost (filtteri6.pp.htv.fi [213.243.153.189]) (amavisd-new, port 10024) with ESMTP id 0lhb4+K-1BnO; Tue, 23 Jul 2013 01:27:02 +0300 (EEST) Received: from musicnaut.iki.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp4.welho.com (Postfix) with SMTP id 9717E5BC005; Tue, 23 Jul 2013 01:27:01 +0300 (EEST) Received: by musicnaut.iki.fi (sSMTP sendmail emulation); Tue, 23 Jul 2013 01:26:57 +0300 Date: Tue, 23 Jul 2013 01:26:57 +0300 From: Aaro Koskinen To: David Daney Cc: David Daney , Ralf Baechle , David Daney , Faidon Liambotis , linux-mips@linux-mips.org Subject: Re: [PATCH v2] MIPS: cavium-octeon: fix I/O space setup on non-PCI systems Message-ID: <20130722222657.GC31864@blackmetal.musicnaut.iki.fi> References: <1374522901-30290-1-git-send-email-aaro.koskinen@iki.fi> <51ED9153.4080904@gmail.com> <20130722203912.GA31864@blackmetal.musicnaut.iki.fi> <51ED9CDD.2090507@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <51ED9CDD.2090507@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37347 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3138 Lines: 83 Hi, On Mon, Jul 22, 2013 at 01:58:05PM -0700, David Daney wrote: > On 07/22/2013 01:39 PM, Aaro Koskinen wrote: > >On Mon, Jul 22, 2013 at 01:08:51PM -0700, David Daney wrote: > >>On 07/22/2013 12:55 PM, Aaro Koskinen wrote: > >>>Fix I/O space setup, so that on non-PCI systems using inb()/outb() > >>>won't crash the system. Some drivers may try to probe I/O space and for > >>>that purpose we can just allocate some normal memory initially. Drivers > >>>trying to reserve a region will fail early as we set the size to 0. If > >>>a real I/O space is present, the PCI/PCIe support code will re-adjust > >>>the values accordingly. > >>> > >>>Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused > >>>the originally reported crash. > >>> > >>>Reported-by: Faidon Liambotis > >>>Signed-off-by: Aaro Koskinen > >>>--- > >>> > >>> v2: Address the issues found from the first version of the patch > >>> (http://marc.info/?t=137434204000002&r=1&w=2). > >>> > >>> arch/mips/cavium-octeon/setup.c | 28 ++++++++++++++++++++++++++++ > >>> arch/mips/pci/pci-octeon.c | 9 +++++---- > >>> 2 files changed, 33 insertions(+), 4 deletions(-) > >>> > >>>diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c > >>>index 48b08eb..6775bd1 100644 > >>>--- a/arch/mips/cavium-octeon/setup.c > >>>+++ b/arch/mips/cavium-octeon/setup.c > >>>@@ -8,6 +8,7 @@ > >>> * written by Ralf Baechle > >>> */ > >>> #include > >>>+#include > >>> #include > >>> #include > >>> #include > >>>@@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) > >>> return err; > >>> } > >>> device_initcall(edac_devinit); > >>>+ > >>>+static void __initdata *octeon_dummy_iospace; > >>>+ > >>>+static int __init octeon_no_pci_init(void) > >>>+{ > >>>+ /* > >>>+ * Initially assume there is no PCI. The PCI/PCIe platform code will > >>>+ * later re-initialize these to correct values if they are present. > >>>+ */ > >>>+ octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); > >>>+ set_io_port_base((unsigned long)octeon_dummy_iospace); > >>>+ ioport_resource.start = MAX_RESOURCE; > >>>+ ioport_resource.end = 0; > >>>+ return 0; > >>>+} > >>>+arch_initcall(octeon_no_pci_init); > >>>+ > >> > >>Do we have any guarantee that this will happen before the > >>arch/mips/pci/* arch_initcalls ? > > > >Yes, it's guaranteed by the linking order ie. in which order the obj-y > >stuff gets listed in mips/Makefile. Currently cavium-octeon/ is processed > >before pci/. > > Yes, I understand that. The problem is when we start to use things > like GCC's LTO, where we effectively compile the entire kernel as a > single file. Will this still work then? I would rather not screw > around with it. > > Can you test it by making it a core_initcall() instead? If that > works you can add Acked-by: me. Well, I can of course change that, and it seems to work as well. I will wait for additional comments couple of days, and then post v3 with the change. Thanks, A. From chenhuacai@gmail.com Tue Jul 23 09:34:58 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:35:03 +0200 (CEST) Received: from mail-pa0-f50.google.com ([209.85.220.50]:38063 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823044Ab3GWHe6MENxR (ORCPT ); Tue, 23 Jul 2013 09:34:58 +0200 Received: by mail-pa0-f50.google.com with SMTP id fb1so8084390pad.9 for ; Tue, 23 Jul 2013 00:34:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer; bh=D70wkEaxA1fvoy1BM9EQlJ6g9VfxF4fhmPmwB9BYd0A=; b=XR70rYnZuNww+HXVxgNEvzOTmgT0SYpSYLoDBrm24ebVOaTfVdTwSDs0L+kcuSILRh owFFrJ1qlFHOSQOE/vvWleG72IYomn2k5ZHL6g+8qTA3HVkcN05AnMQJbYArSyntYS1g POt9yOZ4lNgtGjMyse5gBL84C12+wcIlhQ5P8d+YiMdUX9AD77R/2f6TqNrrlCwagJIi jHzS61HoH+aPG8NJlKYxmx1NF2OpIYNMENkiKrURh/apdlcM6f7PBbz06TzoOfopAdLa 2fQfUly4odK7ownetSGrqsMGON/dUX05jufRD/8BwO2wTHTLAuOvnwbeWp1xzEKExHP8 xW2w== X-Received: by 10.66.146.66 with SMTP id ta2mr36434243pab.11.1374564890979; Tue, 23 Jul 2013 00:34:50 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.34.44 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:34:49 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 00/13] MIPS: Add Loongson-3 based machines support Date: Tue, 23 Jul 2013 15:34:00 +0800 Message-Id: <1374564853-10762-1-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37348 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 7648 Lines: 160 This patchset is prepared for the next 3.12 release for Linux/MIPS. Loongson-3 is a multi-core MIPS family CPU, it is MIPS64R2 compatible and has the same IMP field (0x6300) as Loongson-2. These patches make Linux kernel support Loongson-3 CPU and Loongson-3 based computers (including Laptop, Mini-ITX, All-In-One PC, etc.) V1 -> V2: 1, Split the first patch to two patches, one is constant definition and the other is CPU probing, cache initializing, etc. 2, Remove Kconfig options in the first 9 patches and put all of them in the 10th patch. 3, Use "make savedefconfig" to generate the new default config file. 4, Rework serial port support to use PORT and PORT_M macros. 5, Fix some compile warnings. V2 -> V3: 1, Improve cache flushing code (use cpu_has_coherent_cache macro and remove #ifdef clauses). 2, Improve platform-specific code to correctly set driver's dma_mask/ coherent_dma_mask so no longer need workarounds for each driver ( SATA, graphics card, sound card, etc.) 3, Use PCI quirk to provide vgabios and loongson3_read_bios() go away. 4, Improve CPU hotplug code and split the poweroff failure related code to another patch (this issue affect all MIPS CPU, not only Loongson). 5, Some other small fixes. V3 -> V4: 1, Include swiotlb.h in radeon_ttm.c if SWIOTLB configured. 2, Remove "Reviewed-by" in patches which are added by mistake. 3, Sync the code to upstream. V4 -> V5: 1, Split the drm patch to three patches. 2, Use platform-specific pincfgs to replace old alsa quirks. V5 -> V6: 1, For better management, two non-Loongson-specific patches are sent independently. 2, Introduce cpu_has_coherent_cache feature and split cache flushing changes to a separate patch. 3, Remove PRID_IMP_LOONGSON3 and use PRID_IMP_LOONGSON2 since they are the same. 4, Don't define RTC_ALWAYS_BCD for Loongson-3 since BCD format can be checked by RTC_CONTROL at runtime. 5, Don't modify dma-default.c for Loongson since it is unnecessary. 6, Don't define SAREA_MAX since it is useless. 7, Increase the default boost of internal mic for Lemote A1004. 8, Fix a #ifdef issue in dma-coherence.h. 9, Some other small fixes. V6 -> V7: 1, Fix boot failure when NR_CPUS is more than present cpus. 2, Fix error messages after poweroff & reboot. 3, Update the default config file. 4, Sync the code to upstream. V7 -> V8: 1, Add WEAK_ORDERING/WEAK_REORDERING_BEYOND_LLSC for Loongson-3. 2, Fix a deadlock of cpu-hotplug. 3, Include swiotlb.h in arch-specific code to avoid driver modification. 4, Remove the patch "drm: Handle io prot correctly for MIPS" since it is already in upstream code. 5, Remove the patch "ALSA: HDA: Make hda sound card usable for Loongson" since it is already in upstream code. 6, Use LZMA compression and do some adjustment of config file to reduce kernel size. V8 -> V9: 1, Fix spurious IPI interrupt. 2, remove __dev* attributes since CONFIG_HOTPLUG is going away as an option. 3, Use dev_info() to print messages in fixup-loongson3.c. 4, Update the default config file. 5, Sync the code to upstream. V9 -> V10: 1, Rework "Introduce and use cpu_has_coherent_cache feature". 2, Handle the case that System BIOS doesn't contain a VGA BIOS. 3, Sync the code to upstream (mostly indentation adjustment). V10 -> V11: 1, Remove normal labels and useless nops in inline assembler. 2, Sync the code to upstream (Prepared for 3.12). Huacai Chen(13): MIPS: Loongson: Add basic Loongson-3 definition. MIPS: Loongson: Add basic Loongson-3 CPU support. MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature. MIPS: Loongson 3: Add Lemote-3A machtypes definition. MIPS: Loongson: Add UEFI-like firmware interface support. MIPS: Loongson 3: Add HT-linked PCI support. MIPS: Loongson 3: Add IRQ init and dispatch support. MIPS: Loongson 3: Add serial port support. MIPS: Loongson: Add swiotlb to support big memory (>4GB). MIPS: Loongson: Add Loongson-3 Kconfig options. MIPS: Loongson 3: Add Loongson-3 SMP support. MIPS: Loongson 3: Add CPU hotplug support. MIPS: Loongson: Add a Loongson-3 default config file. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/Kconfig | 30 ++ arch/mips/configs/loongson3_defconfig | 329 +++++++++++++++ arch/mips/include/asm/addrspace.h | 6 + arch/mips/include/asm/bootinfo.h | 24 +- arch/mips/include/asm/cpu-features.h | 3 + arch/mips/include/asm/cpu.h | 5 +- arch/mips/include/asm/dma-mapping.h | 5 + arch/mips/include/asm/mach-loongson/boot_param.h | 151 +++++++ .../asm/mach-loongson/cpu-feature-overrides.h | 6 + .../mips/include/asm/mach-loongson/dma-coherence.h | 23 + arch/mips/include/asm/mach-loongson/irq.h | 24 + arch/mips/include/asm/mach-loongson/loongson.h | 26 +- arch/mips/include/asm/mach-loongson/machine.h | 6 + arch/mips/include/asm/mach-loongson/pci.h | 5 + arch/mips/include/asm/mach-loongson/spaces.h | 15 + arch/mips/include/asm/module.h | 2 + arch/mips/include/asm/pgtable-bits.h | 7 + arch/mips/include/asm/smp.h | 1 + arch/mips/kernel/cpu-probe.c | 14 +- arch/mips/loongson/Kconfig | 52 +++ arch/mips/loongson/Makefile | 6 + arch/mips/loongson/Platform | 1 + arch/mips/loongson/common/Makefile | 5 + arch/mips/loongson/common/dma-swiotlb.c | 163 +++++++ arch/mips/loongson/common/env.c | 67 +++- arch/mips/loongson/common/init.c | 14 +- arch/mips/loongson/common/machtype.c | 4 + arch/mips/loongson/common/mem.c | 42 ++ arch/mips/loongson/common/pci.c | 6 +- arch/mips/loongson/common/reset.c | 16 + arch/mips/loongson/common/serial.c | 26 +- arch/mips/loongson/common/setup.c | 8 +- arch/mips/loongson/common/uart_base.c | 9 +- arch/mips/loongson/loongson-3/Makefile | 6 + arch/mips/loongson/loongson-3/irq.c | 97 +++++ arch/mips/loongson/loongson-3/smp.c | 444 ++++++++++++++++++++ arch/mips/loongson/loongson-3/smp.h | 24 + arch/mips/mm/c-r4k.c | 79 ++++- arch/mips/mm/tlb-r4k.c | 2 +- arch/mips/mm/tlbex.c | 1 + arch/mips/pci/Makefile | 1 + arch/mips/pci/fixup-loongson3.c | 68 +++ arch/mips/pci/ops-loongson3.c | 104 +++++ 43 files changed, 1869 insertions(+), 58 deletions(-) create mode 100644 arch/mips/configs/loongson3_defconfig create mode 100644 arch/mips/include/asm/mach-loongson/boot_param.h create mode 100644 arch/mips/include/asm/mach-loongson/irq.h create mode 100644 arch/mips/include/asm/mach-loongson/spaces.h create mode 100644 arch/mips/loongson/common/dma-swiotlb.c create mode 100644 arch/mips/loongson/loongson-3/Makefile create mode 100644 arch/mips/loongson/loongson-3/irq.c create mode 100644 arch/mips/loongson/loongson-3/smp.c create mode 100644 arch/mips/loongson/loongson-3/smp.h create mode 100644 arch/mips/pci/fixup-loongson3.c create mode 100644 arch/mips/pci/ops-loongson3.c -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:35:22 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:35:37 +0200 (CEST) Received: from mail-pa0-f52.google.com ([209.85.220.52]:38264 "EHLO mail-pa0-f52.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822679Ab3GWHfIsmtBG (ORCPT ); Tue, 23 Jul 2013 09:35:08 +0200 Received: by mail-pa0-f52.google.com with SMTP id kq13so2505985pab.25 for ; Tue, 23 Jul 2013 00:35:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=wfSHqp+/WgxZwPRtUcbQ4X0EAp9PPr2KVuvfrMEt6as=; b=pXFx3q9+Nvb995MFkDBsvzM9025vt5ZJrAYsyXy8lCQb3+mbcmEKYIEP8+YsI7QM5Y xw+I0d2PVFZi+zLug8rP1x56eecutGwo5FQdmFrLx+Lzxz/ydFMIMqfCcXib8F3PhuW7 WlWRuL7DyVx9NY6lRMHXNSHp2XBSHcQta8fsrc8+BiLbTk3wHRiQkDnvMtcqeI6oXZxp Fc/g+mgRnPXTu4U3EHMMCD+t9m+HyXa/LSu1nEirM2hmWkk7hppxPXdtQgxTSBMP63Yy skeGBCIPq2zSAX6y8Fo2+0yenEayp8x9rCcq6FHRjsv6Maie6FqapoY/CBMLR6wMcuwF S0qA== X-Received: by 10.68.201.98 with SMTP id jz2mr34949605pbc.56.1374564902309; Tue, 23 Jul 2013 00:35:02 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.34.51 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:35:01 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 01/13] MIPS: Loongson: Add basic Loongson-3 definition Date: Tue, 23 Jul 2013 15:34:01 +0800 Message-Id: <1374564853-10762-2-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37349 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 5433 Lines: 139 Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2. Loongson-3 has a hardware-maintained cache, system software doesn't need to maintain coherency. Loongson-3A is the first revision of Loongson-3, and it is the quad- core version of Loongson-2G. Loongson-3A has a simplified version named Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two HyperTransport controller but 2Gq has only one. HT0 is used for cross- chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq cannot support NUMA but 3A can. For software, Loongson-2Gq is simply identified as Loongson-3A. Exsisting Loongson family CPUs: Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs. Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit single-core MIPS CPUs. Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are 64-bit multi-core MIPS CPUs. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/include/asm/addrspace.h | 6 ++++++ arch/mips/include/asm/cpu.h | 5 +++-- arch/mips/include/asm/mach-loongson/spaces.h | 15 +++++++++++++++ arch/mips/include/asm/module.h | 2 ++ arch/mips/include/asm/pgtable-bits.h | 7 +++++++ arch/mips/loongson/Platform | 1 + 6 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/spaces.h diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 13d61c0..fdbadf3 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -116,7 +116,13 @@ #define K_CALG_UNCACHED 2 #define K_CALG_NONCOHERENT 3 #define K_CALG_COH_EXCL 4 + +#ifdef CONFIG_CPU_LOONGSON3 +#define K_CALG_COH_SHAREABLE 3 +#else #define K_CALG_COH_SHAREABLE 5 +#endif + #define K_CALG_NOTUSED 6 #define K_CALG_UNCACHED_ACCEL 7 diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 632bbe5..64abb0f 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -202,6 +202,7 @@ #define PRID_REV_LOONGSON1B 0x0020 #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 +#define PRID_REV_LOONGSON3A 0x0005 /* * Older processors used to encode processor version and revision in two @@ -271,8 +272,8 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, - CPU_XLR, CPU_XLP, + CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, + CPU_CAVIUM_OCTEON2, CPU_XLR, CPU_XLP, CPU_LAST }; diff --git a/arch/mips/include/asm/mach-loongson/spaces.h b/arch/mips/include/asm/mach-loongson/spaces.h new file mode 100644 index 0000000..1e82804 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/spaces.h @@ -0,0 +1,15 @@ +#ifndef __ASM_MACH_LOONGSON_SPACES_H_ +#define __ASM_MACH_LOONGSON_SPACES_H_ + +#ifndef CAC_BASE +#if defined(CONFIG_64BIT) +#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_CPU_LOONGSON3) +#define CAC_BASE _AC(0x9800000000000000, UL) +#else +#define CAC_BASE _AC(0xa800000000000000, UL) +#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_CPU_LOONGSON3 */ +#endif /* CONFIG_64BIT */ +#endif /* CONFIG_CAC_BASE */ + +#include +#endif diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index 44b705d..c2edae3 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -126,6 +126,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON1 " #elif defined CONFIG_CPU_LOONGSON2 #define MODULE_PROC_FAMILY "LOONGSON2 " +#elif defined CONFIG_CPU_LOONGSON3 +#define MODULE_PROC_FAMILY "LOONGSON3 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " #elif defined CONFIG_CPU_XLR diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 32aea48..6c1e99e 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -235,6 +235,13 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) +#elif defined(CONFIG_CPU_LOONGSON3) + +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* LOONGSON */ +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ +#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* LOONGSON */ + #else #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ diff --git a/arch/mips/loongson/Platform b/arch/mips/loongson/Platform index 29692e5..6205372 100644 --- a/arch/mips/loongson/Platform +++ b/arch/mips/loongson/Platform @@ -30,3 +30,4 @@ platform-$(CONFIG_MACH_LOONGSON) += loongson/ cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson -mno-branch-likely load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000 load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000 +load-$(CONFIG_CPU_LOONGSON3) += 0xffffffff80200000 -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:35:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:36:11 +0200 (CEST) Received: from mail-pb0-f49.google.com ([209.85.160.49]:36622 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827432Ab3GWHfUpRoZU (ORCPT ); Tue, 23 Jul 2013 09:35:20 +0200 Received: by mail-pb0-f49.google.com with SMTP id jt11so8019790pbb.36 for ; Tue, 23 Jul 2013 00:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=6X0GUBJb5SNKttHZNdOymjI/kJ2PXMT9I+YfC/ApMps=; b=nVniTJ3BTXCKcsze4pPwFvOujgP3TV3yQBUnOKhrjxqS4pqC24IC8uNxrCiBv0WPKi 6mWZB6MFcQoBb+4yAQ37wJ82H8Zv4O2ZAFPgR25pLRaXgE6p2PymLIuQvYssf8SI9zIu LEV83ermWMVJtdnFI65y6gvwuGCy9eXyN/4jU+0QYxXbOM28XkO9kmCHkSW4hWqMSUVg m5/7Oz2zAQsx3vkJkqs80qYFIqtwF5cZvXjhMJ9+ul1xfIHe9SsFYE0ZGHzFQa2RqUBI RTgbUNgVr8Yj6af9DMYxQxELgaHZgj924mZOPTD2EMErNQ+S1QvPpVmhn+ZT4f6bZOU5 AMxA== X-Received: by 10.66.5.195 with SMTP id u3mr35435175pau.79.1374564912287; Tue, 23 Jul 2013 00:35:12 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.35.02 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:35:11 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 02/13] MIPS: Loongson: Add basic Loongson-3 CPU support Date: Tue, 23 Jul 2013 15:34:02 +0800 Message-Id: <1374564853-10762-3-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37350 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 4851 Lines: 164 Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/kernel/cpu-probe.c | 14 +++++++--- arch/mips/mm/c-r4k.c | 62 +++++++++++++++++++++++++++++++++++++++++- arch/mips/mm/tlb-r4k.c | 2 +- arch/mips/mm/tlbex.c | 1 + 4 files changed, 73 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c7b1b3c..e38dc86 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -603,17 +603,23 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) MIPS_CPU_LLSC; c->tlbsize = 64; break; - case PRID_IMP_LOONGSON2: - c->cputype = CPU_LOONGSON2; - __cpu_name[cpu] = "ICT Loongson-2"; - + case PRID_IMP_LOONGSON2: /* Loongson-2/3 have the same PRID_IMP field */ switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_LOONGSON2E: + c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2E"; set_elf_platform(cpu, "loongson2e"); break; case PRID_REV_LOONGSON2F: + c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2F"; set_elf_platform(cpu, "loongson2f"); break; + case PRID_REV_LOONGSON3A: + c->cputype = CPU_LOONGSON3; + __cpu_name[cpu] = "ICT Loongson-3A"; + set_elf_platform(cpu, "loongson3a"); + break; } set_isa(c, MIPS_CPU_ISA_III); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 21813be..10d1846 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -971,6 +971,31 @@ static void __cpuinit probe_pcache(void) c->dcache.waybit = 0; break; + case CPU_LOONGSON3: + config1 = read_c0_config1(); + if ((lsize = ((config1 >> 19) & 7))) + c->icache.linesz = 2 << lsize; + else + c->icache.linesz = lsize; + c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + icache_size = c->icache.sets * + c->icache.ways * + c->icache.linesz; + c->icache.waybit = 0; + + if ((lsize = ((config1 >> 10) & 7))) + c->dcache.linesz = 2 << lsize; + else + c->dcache.linesz = lsize; + c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.ways = 1 + ((config1 >> 7) & 7); + dcache_size = c->dcache.sets * + c->dcache.ways * + c->dcache.linesz; + c->dcache.waybit = 0; + break; + default: if (!(config & MIPS_CONF_M)) panic("Don't know how to probe P-caches on this cpu."); @@ -1192,6 +1217,34 @@ static void __init loongson2_sc_init(void) } #endif +#if defined(CONFIG_CPU_LOONGSON3) +static void __init loongson3_sc_init(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config2, lsize; + + config2 = read_c0_config2(); + if ((lsize = ((config2 >> 4) & 15))) + c->scache.linesz = 2 << lsize; + else + c->scache.linesz = lsize; + c->scache.sets = 64 << ((config2 >> 8) & 15); + c->scache.ways = 1 + (config2 & 15); + + scache_size = c->scache.sets * + c->scache.ways * + c->scache.linesz; + /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ + scache_size *= 4; + c->scache.waybit = 0; + pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", + scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); + if (scache_size) + c->options |= MIPS_CPU_INCLUSIVE_CACHES; + return; +} +#endif + extern int r5k_sc_init(void); extern int rm7k_sc_init(void); extern int mips_sc_init(void); @@ -1240,11 +1293,18 @@ static void __cpuinit setup_scache(void) #endif return; -#if defined(CONFIG_CPU_LOONGSON2) case CPU_LOONGSON2: +#if defined(CONFIG_CPU_LOONGSON2) loongson2_sc_init(); +#endif return; + + case CPU_LOONGSON3: +#if defined(CONFIG_CPU_LOONGSON3) + loongson3_sc_init(); #endif + return; + case CPU_XLP: /* don't need to worry about L2, fully coherent */ return; diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index c643de4..d3e9326 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -51,7 +51,7 @@ extern void build_tlb_refill_handler(void); #endif /* CONFIG_MIPS_MT_SMTC */ -#if defined(CONFIG_CPU_LOONGSON2) +#if defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_LOONGSON3) /* * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, * unfortrunately, itlb is not totally transparent to software. diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 9ab0f90..9360854 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -600,6 +600,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BMIPS4380: case CPU_BMIPS5000: case CPU_LOONGSON2: + case CPU_LOONGSON3: case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:36:29 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:36:36 +0200 (CEST) Received: from mail-pb0-f51.google.com ([209.85.160.51]:60968 "EHLO mail-pb0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822995Ab3GWHfY0YfCe (ORCPT ); Tue, 23 Jul 2013 09:35:24 +0200 Received: by mail-pb0-f51.google.com with SMTP id um15so8109162pbc.10 for ; Tue, 23 Jul 2013 00:35:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=KsP1B5UKB/i0UVuGIoXMenj82g8qUm2pL3JNdxnMZNU=; b=SDKp5vuDrHfD2MDpaB88oAz9QvBbiTCEHE0T7CQp0U2pUliIHUMyKobO1T44WP5XYT a61yJyhqDCU9GuTJZqX2pIeU3lwtcX5DlMffEgaNwkuJuLd5dxIS7i+uFWoXKYLrEpAd 1jrceuU4gS5aFVMQabvJXpc5Y0bRuTIrV7E12zg/xLLuTo4lHPBrrsUmBHHiHMpZc/fL SNHox57irKfmrO7yQizE4cqeY95LYySmvxadMumMzicTIQqM8Mc+o75uaUHoHBf4z8db EKN6xztEzIiAN1wrV0272quUnG3MOsO2a5HSCs/cdayLkzTUea9D6Hd829gIDFQ/xPp3 2DWA== X-Received: by 10.68.171.194 with SMTP id aw2mr35049381pbc.197.1374564917898; Tue, 23 Jul 2013 00:35:17 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.35.12 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:35:16 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 03/13] MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature Date: Tue, 23 Jul 2013 15:34:03 +0800 Message-Id: <1374564853-10762-4-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37351 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3302 Lines: 102 Loongson-3 maintains cache coherency by hardware. So we introduce a cpu feature named cpu_has_coherent_cache and use it to modify MIPS's cache flushing functions. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/include/asm/cpu-features.h | 3 +++ .../asm/mach-loongson/cpu-feature-overrides.h | 6 ++++++ arch/mips/mm/c-r4k.c | 17 ++++++++++++++++- 3 files changed, 25 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1dc0860..75f3577 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -127,6 +127,9 @@ #ifndef cpu_has_pindexed_dcache #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) #endif +#ifndef cpu_has_coherent_cache +#define cpu_has_coherent_cache 0 +#endif #ifndef cpu_has_local_ebase #define cpu_has_local_ebase 1 #endif diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index c0f3ef4..1b03d31 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -58,5 +58,11 @@ #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 #define cpu_has_local_ebase 0 +#ifdef CONFIG_CPU_SUPPORTS_COHERENT_CACHE +#define cpu_has_coherent_cache 1 +#else +#define cpu_has_coherent_cache 0 +#endif + #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 10d1846..8a972e8 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -344,7 +344,10 @@ static void __cpuinit r4k_blast_scache_setup(void) static inline void local_r4k___flush_cache_all(void * args) { -#if defined(CONFIG_CPU_LOONGSON2) + if (cpu_has_coherent_cache && !cpu_has_dc_aliases) + return; + +#if defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_LOONGSON3) r4k_blast_scache(); return; #endif @@ -398,6 +401,9 @@ static inline void local_r4k_flush_cache_range(void * args) struct vm_area_struct *vma = args; int exec = vma->vm_flags & VM_EXEC; + if (cpu_has_coherent_cache && !cpu_has_dc_aliases) + return; + if (!(has_valid_asid(vma->vm_mm))) return; @@ -468,6 +474,9 @@ static inline void local_r4k_flush_cache_page(void *args) pte_t *ptep; void *vaddr; + if (cpu_has_coherent_cache && !cpu_has_dc_aliases) + return; + /* * If ownes no valid ASID yet, cannot possibly have gotten * this page into the cache. @@ -541,6 +550,9 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma, static inline void local_r4k_flush_data_cache_page(void * addr) { + if (cpu_has_coherent_cache && !cpu_has_dc_aliases) + return; + r4k_blast_dcache_page((unsigned long) addr); } @@ -673,6 +685,9 @@ static void local_r4k_flush_cache_sigtramp(void * arg) unsigned long sc_lsize = cpu_scache_line_size(); unsigned long addr = (unsigned long) arg; + if (cpu_has_coherent_cache && !cpu_has_dc_aliases) + return; + R4600_HIT_CACHEOP_WAR_IMPL; if (dc_lsize) protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:36:57 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:37:15 +0200 (CEST) Received: from mail-pa0-f48.google.com ([209.85.220.48]:59948 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824793Ab3GWHfbJZgIP (ORCPT ); Tue, 23 Jul 2013 09:35:31 +0200 Received: by mail-pa0-f48.google.com with SMTP id kp1so3724921pab.21 for ; Tue, 23 Jul 2013 00:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=uuxvCSWnUMLRTdHYW/hpuf6/tCnu8e4mW+RHPI/TmcU=; b=mwKKYQoAwVcMMqLG1YPKy4n3MdKtmQt7huoajuXAXulVvzGXkaq9yzFierG8/Nrhyz BvRsLya0eTRE85iUY/ZkF17+44zjH5F6v6oNVNKq2crL03ie+ECG8/0KyIbDe7orIa/r INjWIkoEgRsOeTlpPRq5m05WC8uDZow/+migOoVFW9v7raIdpRbQaZJOko2y6gf467GI VpOBqEOLkUQ9fzOJ6cVCBLqnO5d9GXHOkoZYloiTZ+cDbUHki8wig4QYwIx5nYQgjf3I 30DHOCTJ9zbLVoN+7uVB1JqCSj77LvwXXFFuXrDmHEnJlOUqyAX6yjPonjCgu4fmZblm bYIw== X-Received: by 10.68.60.132 with SMTP id h4mr34971652pbr.177.1374564923444; Tue, 23 Jul 2013 00:35:23 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.35.18 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:35:22 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 04/13] MIPS: Loongson 3: Add Lemote-3A machtypes definition Date: Tue, 23 Jul 2013 15:34:04 +0800 Message-Id: <1374564853-10762-5-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37352 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2645 Lines: 85 Add four Loongson-3 based machine types: MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops; MACH_LEMOTE_A1101 is mini-itx; MACH_LEMOTE_A1205 is all-in-one machine. The most significant differrent between A1004/A1201 and A1101/A1205 is the laptops have EC but others don't. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/include/asm/bootinfo.h | 24 +++++++++++++++--------- arch/mips/include/asm/mach-loongson/machine.h | 6 ++++++ arch/mips/loongson/common/machtype.c | 4 ++++ 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index 4d2cdea..09956a0 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -61,15 +61,21 @@ /* * Valid machtype for Loongson family */ -#define MACH_LOONGSON_UNKNOWN 0 -#define MACH_LEMOTE_FL2E 1 -#define MACH_LEMOTE_FL2F 2 -#define MACH_LEMOTE_ML2F7 3 -#define MACH_LEMOTE_YL2F89 4 -#define MACH_DEXXON_GDIUM2F10 5 -#define MACH_LEMOTE_NAS 6 -#define MACH_LEMOTE_LL2F 7 -#define MACH_LOONGSON_END 8 +enum loongson_machine_type { + MACH_LOONGSON_UNKNOWN, + MACH_LEMOTE_FL2E, + MACH_LEMOTE_FL2F, + MACH_LEMOTE_ML2F7, + MACH_LEMOTE_YL2F89, + MACH_DEXXON_GDIUM2F10, + MACH_LEMOTE_NAS, + MACH_LEMOTE_LL2F, + MACH_LEMOTE_A1004, + MACH_LEMOTE_A1101, + MACH_LEMOTE_A1201, + MACH_LEMOTE_A1205, + MACH_LOONGSON_END +}; /* * Valid machtype for group INGENIC diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index 3810d5c..1b1f592 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -24,4 +24,10 @@ #endif +#ifdef CONFIG_LEMOTE_MACH3A + +#define LOONGSON_MACHTYPE MACH_LEMOTE_A1101 + +#endif /* CONFIG_LEMOTE_MACH3A */ + #endif /* __ASM_MACH_LOONGSON_MACHINE_H */ diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c index 4becd4f..1a47979 100644 --- a/arch/mips/loongson/common/machtype.c +++ b/arch/mips/loongson/common/machtype.c @@ -27,6 +27,10 @@ static const char *system_types[] = { [MACH_DEXXON_GDIUM2F10] "dexxon-gdium-2f", [MACH_LEMOTE_NAS] "lemote-nas-2f", [MACH_LEMOTE_LL2F] "lemote-lynloong-2f", + [MACH_LEMOTE_A1004] "lemote-3a-notebook-a1004", + [MACH_LEMOTE_A1101] "lemote-3a-itx-a1101", + [MACH_LEMOTE_A1201] "lemote-2gq-notebook-a1201", + [MACH_LEMOTE_A1205] "lemote-2gq-aio-a1205", [MACH_LOONGSON_END] NULL, }; -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:37:31 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:37:47 +0200 (CEST) Received: from mail-pa0-f49.google.com ([209.85.220.49]:46737 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827445Ab3GWHfgv91rS (ORCPT ); Tue, 23 Jul 2013 09:35:36 +0200 Received: by mail-pa0-f49.google.com with SMTP id bi5so3980658pad.36 for ; Tue, 23 Jul 2013 00:35:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=baaJyzsII2aoP5VnvqeUZqODbFwsF325clzOMy5vrdU=; b=QKCQpwqUfFqULtp5JzKDMVCo5ZoA7fXOmaHArHVxgpozOSB7XnbCg9kfppZ9zZ+3l0 X3z6F7Iw06fl0q1H9gLSA8Wy+csBRePAqfnaiI8n4F+V/l4D+7cFbvzHtzyqH7qLdOfQ iJKp2qD2UBaOeb7Ns8j5OwhvgbTNAQ/vj09LchCT3IeFHsESoTZckgFRSdiI9S+3izBU sO5yEl4wvDsux4VhpPFaBEUVszu5DDPJXas66JZab4B56FoRRxYWtbtWf6jnMP5USUHO /Kn7jlUa+Da3TMGQnL1wz4E9CX3mEQCMnazpwWS1+bwOMV0HrHP9ZQosCqPUQ0VGXQV5 e1mQ== X-Received: by 10.68.169.97 with SMTP id ad1mr34468292pbc.84.1374564929358; Tue, 23 Jul 2013 00:35:29 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.35.23 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:35:28 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 05/13] MIPS: Loongson: Add UEFI-like firmware interface support Date: Tue, 23 Jul 2013 15:34:05 +0800 Message-Id: <1374564853-10762-6-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37353 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 14230 Lines: 473 The new UEFI-like firmware interface has 3 advantages: 1, Firmware export a physical memory map which is similar to X86's E820 map, so prom_init_memory() will be more elegant that #ifdef clauses can be removed. 2, Firmware export a pci irq routing table, we no longer need pci irq routing fixup in kernel's code. 3, Firmware has a built-in vga bios, and its address is exported, the linux kernel no longer need an embedded blob. With the new interface, Loongson-3A/2G and all their successors can use a unified kernel. All Loongson-based machines support this new interface except 2E/2F series. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/include/asm/mach-loongson/boot_param.h | 151 ++++++++++++++++++++++ arch/mips/include/asm/mach-loongson/loongson.h | 4 +- arch/mips/loongson/common/env.c | 67 ++++++++-- arch/mips/loongson/common/init.c | 9 +- arch/mips/loongson/common/mem.c | 42 ++++++ arch/mips/loongson/common/pci.c | 6 +- arch/mips/loongson/common/reset.c | 16 +++ 7 files changed, 275 insertions(+), 20 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/boot_param.h diff --git a/arch/mips/include/asm/mach-loongson/boot_param.h b/arch/mips/include/asm/mach-loongson/boot_param.h new file mode 100644 index 0000000..4c5a1ba --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/boot_param.h @@ -0,0 +1,151 @@ +#ifndef __ASM_MACH_LOONGSON_BOOT_PARAM_H_ +#define __ASM_MACH_LOONGSON_BOOT_PARAM_H_ + +#define SYSTEM_RAM_LOW 1 +#define SYSTEM_RAM_HIGH 2 +#define MEM_RESERVED 3 +#define PCI_IO 4 +#define PCI_MEM 5 +#define LOONGSON_CFG_REG 6 +#define VIDEO_ROM 7 +#define ADAPTER_ROM 8 +#define ACPI_TABLE 9 +#define MAX_MEMORY_TYPE 10 + +#define LOONGSON3_BOOT_MEM_MAP_MAX 128 +struct efi_memory_map_loongson{ + u16 vers; /* version of efi_memory_map */ + u32 nr_map; /* number of memory_maps */ + u32 mem_freq; /* memory frequence */ + struct mem_map{ + u32 node_id; /* node_id which memory attached to */ + u32 mem_type; /* system memory, pci memory, pci io, etc. */ + u64 mem_start; /* memory map start address */ + u32 mem_size; /* each memory_map size, not the total size */ + }map[LOONGSON3_BOOT_MEM_MAP_MAX]; +}__attribute__((packed)); + +enum loongson_cpu_type +{ + Loongson_2E, + Loongson_2F, + Loongson_3A, + Loongson_3B, + Loongson_1A, + Loongson_1B +}; + +/* + * Capability and feature descriptor structure for MIPS CPU + */ +struct efi_cpuinfo_loongson { + u16 vers; /* version of efi_cpuinfo_loongson */ + u32 processor_id; /* PRID, e.g. 6305, 6306 */ + enum loongson_cpu_type cputype; /* 3A, 3B, etc. */ + u32 total_node; /* num of total numa nodes */ + u32 cpu_startup_core_id; /* Core id */ + u32 cpu_clock_freq; /* cpu_clock */ + u32 nr_cpus; +}__attribute__((packed)); + +struct system_loongson{ + u16 vers; /* version of system_loongson */ + u32 ccnuma_smp; /* 0: no numa; 1: has numa */ + u32 sing_double_channel; /* 1:single; 2:double */ +}__attribute__((packed)); + +struct irq_source_routing_table { + u16 vers; + u16 size; + u16 rtr_bus; + u16 rtr_devfn; + u32 vendor; + u32 device; + u32 PIC_type; /* conform use HT or PCI to route to CPU-PIC */ + u64 ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */ + u64 ht_enable; /* irqs used in this PIC */ + u32 node_id; /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */ + u64 pci_mem_start_addr; + u64 pci_mem_end_addr; + u64 pci_io_start_addr; + u64 pci_io_end_addr; + u64 pci_config_addr; +}__attribute__((packed)); + +struct interface_info{ + u16 vers; /* version of the specificition */ + u16 size; + u8 flag; + char description[64]; +}__attribute__((packed)); + +#define MAX_RESOURCE_NUMBER 128 +struct resource_loongson { + u64 start; /* resource start address */ + u64 end; /* resource end address */ + char name[64]; + u32 flags; +}; + +struct archdev_data {}; /* arch specific additions */ + +struct board_devices{ + char name[64]; /* hold the device name */ + u32 num_resources; /* number of device_resource */ + struct resource_loongson resource[MAX_RESOURCE_NUMBER]; /* for each device's resource */ + /* arch specific additions */ + struct archdev_data archdata; +}; + +struct loongson_special_attribute{ + u16 vers; /* version of this special */ + char special_name[64]; /* special_atribute_name */ + u32 loongson_special_type; /* type of special device */ + struct resource_loongson resource[MAX_RESOURCE_NUMBER]; /* for each device's resource */ +}; + +struct loongson_params{ + u64 memory_offset; /* efi_memory_map_loongson struct offset */ + u64 cpu_offset; /* efi_cpuinfo_loongson struct offset */ + u64 system_offset; /* system_loongson struct offset */ + u64 irq_offset; /* irq_source_routing_table struct offset */ + u64 interface_offset; /* interface_info struct offset */ + u64 special_offset; /* loongson_special_attribute struct offset */ + u64 boarddev_table_offset; /* board_devices offset */ +}; + +struct smbios_tables { + u16 vers; /* version of smbios */ + u64 vga_bios; /* vga_bios address */ + struct loongson_params lp; +}; + +struct efi_reset_system_t{ + u64 ResetCold; + u64 ResetWarm; + u64 ResetType; + u64 Shutdown; +}; + +struct efi_loongson { + u64 mps; /* MPS table */ + u64 acpi; /* ACPI table (IA64 ext 0.71) */ + u64 acpi20; /* ACPI table (ACPI 2.0) */ + struct smbios_tables smbios; /* SM BIOS table */ + u64 sal_systab; /* SAL system table */ + u64 boot_info; /* boot info table */ +}; + +struct boot_params{ + struct efi_loongson efi; + struct efi_reset_system_t reset_system; +}; + +extern u32 nr_cpus_loongson; +extern enum loongson_cpu_type cputype; +extern struct efi_memory_map_loongson *emap; +extern u64 ht_control_base; +extern u64 pci_mem_start_addr, pci_mem_end_addr; +extern u64 loongson_pciio_base; +extern u64 vgabios_addr; +#endif diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index b286534..5913ea0 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -24,8 +24,8 @@ extern void mach_prepare_reboot(void); extern void mach_prepare_shutdown(void); /* environment arguments from bootloader */ -extern unsigned long cpu_clock_freq; -extern unsigned long memsize, highmemsize; +extern u32 cpu_clock_freq; +extern u32 memsize, highmemsize; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c index 0a18fcf..dad9f0c 100644 --- a/arch/mips/loongson/common/env.c +++ b/arch/mips/loongson/common/env.c @@ -18,37 +18,53 @@ * option) any later version. */ #include - #include - #include +#include + +struct boot_params *boot_p; +struct loongson_params *loongson_p; + +struct efi_cpuinfo_loongson *ecpu; +struct efi_memory_map_loongson *emap; +struct system_loongson *esys; +struct irq_source_routing_table *eirq_source; + +u64 ht_control_base; +u64 pci_mem_start_addr, pci_mem_end_addr; +u64 loongson_pciio_base; +u64 vgabios_addr; +u64 poweroff_addr, restart_addr; -unsigned long cpu_clock_freq; +enum loongson_cpu_type cputype; +unsigned int nr_cpus_loongson = NR_CPUS; + +u32 cpu_clock_freq; EXPORT_SYMBOL(cpu_clock_freq); -unsigned long memsize, highmemsize; #define parse_even_earlier(res, option, p) \ do { \ unsigned int tmp __maybe_unused; \ \ if (strncmp(option, (char *)p, strlen(option)) == 0) \ - tmp = strict_strtol((char *)p + strlen(option"="), 10, &res); \ + tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \ } while (0) void __init prom_init_env(void) { /* pmon passes arguments in 32bit pointers */ - int *_prom_envp; - unsigned long bus_clock; unsigned int processor_id; + +#ifndef CONFIG_UEFI_FIRMWARE_INTERFACE + int *_prom_envp; long l; + extern u32 memsize, highmemsize; /* firmware arguments are initialized in head.S */ _prom_envp = (int *)fw_arg2; l = (long)*_prom_envp; while (l != 0) { - parse_even_earlier(bus_clock, "busclock", l); parse_even_earlier(cpu_clock_freq, "cpuclock", l); parse_even_earlier(memsize, "memsize", l); parse_even_earlier(highmemsize, "highmemsize", l); @@ -57,8 +73,32 @@ void __init prom_init_env(void) } if (memsize == 0) memsize = 256; - if (bus_clock == 0) - bus_clock = 66000000; +#else + /* firmware arguments are initialized in head.S */ + boot_p = (struct boot_params *)fw_arg2; + loongson_p = &(boot_p->efi.smbios.lp); + + ecpu = (struct efi_cpuinfo_loongson *)((u64)loongson_p + loongson_p->cpu_offset); + emap = (struct efi_memory_map_loongson *)((u64)loongson_p + loongson_p->memory_offset); + eirq_source = (struct irq_source_routing_table *)((u64)loongson_p + loongson_p->irq_offset); + + cputype = ecpu->cputype; + nr_cpus_loongson = ecpu->nr_cpus; + cpu_clock_freq = ecpu->cpu_clock_freq; + if (nr_cpus_loongson > NR_CPUS || nr_cpus_loongson == 0) + nr_cpus_loongson = NR_CPUS; + + pci_mem_start_addr = eirq_source->pci_mem_start_addr; + pci_mem_end_addr = eirq_source->pci_mem_end_addr; + loongson_pciio_base = eirq_source->pci_io_start_addr; + + poweroff_addr = boot_p->reset_system.Shutdown; + restart_addr = boot_p->reset_system.ResetWarm; + pr_info("Shutdown Addr: %llx Reset Addr: %llx\n", poweroff_addr, restart_addr); + + ht_control_base = 0x90000EFDFB000000; /* has no interface now */ + vgabios_addr = boot_p->efi.smbios.vga_bios; +#endif if (cpu_clock_freq == 0) { processor_id = (¤t_cpu_data)->processor_id; switch (processor_id & PRID_REV_MASK) { @@ -68,12 +108,13 @@ void __init prom_init_env(void) case PRID_REV_LOONGSON2F: cpu_clock_freq = 797000000; break; + case PRID_REV_LOONGSON3A: + cpu_clock_freq = 900000000; + break; default: cpu_clock_freq = 100000000; break; } } - - pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", - bus_clock, cpu_clock_freq, memsize, highmemsize); + pr_info("CpuClock = %u\n", cpu_clock_freq); } diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index ae7af1f..81ba3b4 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -17,10 +17,6 @@ unsigned long __maybe_unused _loongson_addrwincfg_base; void __init prom_init(void) { - /* init base address of io space */ - set_io_port_base((unsigned long) - ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); - #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG _loongson_addrwincfg_base = (unsigned long) ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); @@ -28,6 +24,11 @@ void __init prom_init(void) prom_init_cmdline(); prom_init_env(); + + /* init base address of io space */ + set_io_port_base((unsigned long) + ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); + prom_init_memory(); /*init the uart base address */ diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c index 8626a42..406246b 100644 --- a/arch/mips/loongson/common/mem.c +++ b/arch/mips/loongson/common/mem.c @@ -11,9 +11,14 @@ #include #include +#include #include #include +#ifndef CONFIG_UEFI_FIRMWARE_INTERFACE + +u32 memsize, highmemsize; + void __init prom_init_memory(void) { add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); @@ -49,6 +54,43 @@ void __init prom_init_memory(void) #endif /* !CONFIG_64BIT */ } +#else /* CONFIG_UEFI_FIRMWARE_INTERFACE */ + +void __init prom_init_memory(void) +{ + int i; + u32 node_id; + u32 mem_type; + + /* parse memory information */ + for (i = 0; i < emap->nr_map; i++){ + node_id = emap->map[i].node_id; + mem_type = emap->map[i].mem_type; + + if (node_id == 0) { + switch (mem_type) { + case SYSTEM_RAM_LOW: + add_memory_region(emap->map[i].mem_start, + (u64)emap->map[i].mem_size << 20, + BOOT_MEM_RAM); + break; + case SYSTEM_RAM_HIGH: + add_memory_region(emap->map[i].mem_start, + (u64)emap->map[i].mem_size << 20, + BOOT_MEM_RAM); + break; + case MEM_RESERVED: + add_memory_region(emap->map[i].mem_start, + (u64)emap->map[i].mem_size << 20, + BOOT_MEM_RESERVED); + break; + } + } + } +} + +#endif /* CONFIG_UEFI_FIRMWARE_INTERFACE */ + /* override of arch/mips/mm/cache.c: __uncached_access */ int __uncached_access(struct file *file, unsigned long addr) { diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c index fa77844..a06fd5f 100644 --- a/arch/mips/loongson/common/pci.c +++ b/arch/mips/loongson/common/pci.c @@ -11,6 +11,7 @@ #include #include +#include static struct resource loongson_pci_mem_resource = { .name = "pci memory space", @@ -82,7 +83,10 @@ static int __init pcibios_init(void) setup_pcimap(); loongson_pci_controller.io_map_base = mips_io_port_base; - +#ifdef CONFIG_UEFI_FIRMWARE_INTERFACE + loongson_pci_mem_resource.start = pci_mem_start_addr; + loongson_pci_mem_resource.end = pci_mem_end_addr; +#endif register_pci_controller(&loongson_pci_controller); return 0; diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c index 65bfbb5..9453565 100644 --- a/arch/mips/loongson/common/reset.c +++ b/arch/mips/loongson/common/reset.c @@ -37,17 +37,33 @@ static inline void loongson_reboot(void) static void loongson_restart(char *command) { +#ifndef CONFIG_UEFI_FIRMWARE_INTERFACE /* do preparation for reboot */ mach_prepare_reboot(); /* reboot via jumping to boot base address */ loongson_reboot(); +#else + extern u64 restart_addr; + void (*fw_restart)(void) = (void *)restart_addr; + + fw_restart(); + while (1) {} +#endif } static void loongson_poweroff(void) { +#ifndef CONFIG_UEFI_FIRMWARE_INTERFACE mach_prepare_shutdown(); unreachable(); +#else + extern u64 poweroff_addr; + void (*fw_poweroff)(void) = (void *)poweroff_addr; + + fw_poweroff(); + while (1) {} +#endif } static void loongson_halt(void) -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:38:03 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:38:19 +0200 (CEST) Received: from mail-pa0-f43.google.com ([209.85.220.43]:34282 "EHLO mail-pa0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823044Ab3GWHfnKpyuz (ORCPT ); Tue, 23 Jul 2013 09:35:43 +0200 Received: by mail-pa0-f43.google.com with SMTP id hz11so7997144pad.30 for ; Tue, 23 Jul 2013 00:35:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=yfAqBPfF38KDugd230ywwcppJZKaHxRPnZzsRR0/z9Q=; b=UtkJe/WGOff/D/LXYIPGfH4yqQuSsUgLwFVJql+OHrP9rlkz+wOwlqN6Y5564royY6 tIX5C2xC9OyCF336CA6UVCAbhG1FKKrgu5yud7R5wwqMVD2P+20vsj4qoYeYYt7FDnom 65ZUCGicV9TGAze/8YpOTAfu13brxljUtYMOgcKOifEmV5DRdx5/s+LhnhN7VZjlIKwR HkEpNOpPZ9zWTW1u6MVxsJ2GsxHS0gvTjcAF+WsHzFzyuk4tWGMH8eYSjKg9B1dfMomq gEKlvtCOfrzqLlQ/UEr9YPyXuov4+CSjTvBwA61Bu+tz3BVcEdjrNjCD6G3uSjLnaeGd 8CWg== X-Received: by 10.68.171.194 with SMTP id aw2mr35050553pbc.197.1374564935833; Tue, 23 Jul 2013 00:35:35 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.35.29 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:35:34 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 06/13] MIPS: Loongson 3: Add HT-linked PCI support Date: Tue, 23 Jul 2013 15:34:06 +0800 Message-Id: <1374564853-10762-7-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37354 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 8582 Lines: 263 Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With UEFI-like firmware interface, We don't need fixup for PCI irq routing. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/include/asm/mach-loongson/loongson.h | 7 ++ arch/mips/include/asm/mach-loongson/pci.h | 5 + arch/mips/pci/Makefile | 1 + arch/mips/pci/fixup-loongson3.c | 68 +++++++++++++++ arch/mips/pci/ops-loongson3.c | 104 ++++++++++++++++++++++++ 5 files changed, 185 insertions(+), 0 deletions(-) create mode 100644 arch/mips/pci/fixup-loongson3.c create mode 100644 arch/mips/pci/ops-loongson3.c diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 5913ea0..4f28b1f 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -15,6 +15,7 @@ #include #include #include +#include /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); @@ -101,7 +102,13 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PCICFG_BASE 0x1fe80000 #define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) + +#if defined(CONFIG_HT_PCI) +#define LOONGSON_PCIIO_BASE loongson_pciio_base +#else #define LOONGSON_PCIIO_BASE 0x1fd00000 +#endif + #define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ #define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index bc99dab..1212774 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -40,8 +40,13 @@ extern struct pci_ops loongson_pci_ops; #else /* loongson2f/32bit & loongson2e */ /* this pci memory space is mapped by pcimap in pci.c */ +#ifdef CONFIG_CPU_LOONGSON3 +#define LOONGSON_PCI_MEM_START 0x40000000UL +#define LOONGSON_PCI_MEM_END 0x7effffffUL +#else #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE #define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2) +#endif /* this is an offset from mips_io_port_base */ #define LOONGSON_PCI_IO_START 0x00004000UL diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c382042..cec66a4 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o +obj-$(CONFIG_LEMOTE_MACH3A) += fixup-loongson3.o ops-loongson3.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c new file mode 100644 index 0000000..7b9a9c4 --- /dev/null +++ b/arch/mips/pci/fixup-loongson3.c @@ -0,0 +1,68 @@ +/* + * fixup-loongson3.c + * + * Copyright (C) 2012 Lemote, Inc. + * Author: Xiang Yu, xiangy@lemote.com + * Chen Huacai, chenhc@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include + +static void print_fixup_info(const struct pci_dev * pdev) +{ + dev_info(&pdev->dev, "Device %x:%x, irq %d\n", + pdev->vendor, pdev->device, pdev->irq); +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + print_fixup_info(dev); + return dev->irq; +} + +static void pci_fixup_radeon(struct pci_dev *pdev) +{ + if (pdev->resource[PCI_ROM_RESOURCE].start) + return; + + if (!vgabios_addr) + return; + + pdev->resource[PCI_ROM_RESOURCE].start = vgabios_addr; + pdev->resource[PCI_ROM_RESOURCE].end = vgabios_addr + 256*1024 - 1; + pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_COPY; + + dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n", + PCI_ROM_RESOURCE, &pdev->resource[PCI_ROM_RESOURCE]); +} + +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, + PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon); + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c new file mode 100644 index 0000000..b29d333 --- /dev/null +++ b/arch/mips/pci/ops-loongson3.c @@ -0,0 +1,104 @@ +#include +#include +#include + +#include + +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define HT1LO_PCICFG_BASE 0x1a000000 +#define HT1LO_PCICFG_BASE_TP1 0x1b000000 + +static int loongson3_pci_config_access(unsigned char access_type, + struct pci_bus *bus, unsigned int devfn, + int where, u32 *data) +{ + unsigned char busnum = bus->number; + u_int64_t addr, type; + void *addrp; + int device = PCI_SLOT(devfn); + int function = PCI_FUNC(devfn); + int reg = where & ~3; + + if (busnum == 0) { + if (device > 31) + return PCIBIOS_DEVICE_NOT_FOUND; + addr = (device << 11) | (function << 8) | reg; + addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE) | (addr & 0xffff)); + type = 0; + + } else { + addr = (busnum << 16) | (device << 11) | (function << 8) | reg; + addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE_TP1) | (addr)); + type = 0x10000; + } + + if (access_type == PCI_ACCESS_WRITE) + *(volatile unsigned int *)addrp = cpu_to_le32(*data); + else { + *data = le32_to_cpu(*(volatile unsigned int *)addrp); + if (*data == 0xffffffff) { + *data = -1; + return PCIBIOS_DEVICE_NOT_FOUND; + } + } + return PCIBIOS_SUCCESSFUL; +} + +static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data = 0; + int ret = loongson3_pci_config_access(PCI_ACCESS_READ, + bus, devfn, where, &data); + + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + int ret; + + if (size == 4) + data = val; + else { + ret = loongson3_pci_config_access(PCI_ACCESS_READ, + bus, devfn, where, &data); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + } + + ret = loongson3_pci_config_access(PCI_ACCESS_WRITE, + bus, devfn, where, &data); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops loongson_pci_ops = { + .read = loongson3_pci_pcibios_read, + .write = loongson3_pci_pcibios_write +}; -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:38:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:38:41 +0200 (CEST) Received: from mail-pb0-f52.google.com ([209.85.160.52]:47279 "EHLO mail-pb0-f52.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827461Ab3GWHftyK0cP (ORCPT ); Tue, 23 Jul 2013 09:35:49 +0200 Received: by mail-pb0-f52.google.com with SMTP id xa12so8025279pbc.25 for ; Tue, 23 Jul 2013 00:35:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=HGYJPcdtxBz1+5xnYgY61LBsiWD7PeypJvcCIhNUXTA=; b=cHBfMgT6lnt2LKFH564XtfHm1IA/BtjxyfGOaSLbpSGWewN9zlqtEglXkjVbIQZZC1 nn68WLZ7xZRG4sMQ8vXqFv2aTGHUThoPgxb+bxt6zVdYgWIHeSOMzA2y0ndN4YNr1l++ Wk2xUyKDiq10Nobva4UKR8+xUyrCYjahTIlVcRnDh2V7l3D1IgrogqqZoyMaDjZ0iws+ lYzDnbTS9Totc+F3MxMdgPiSF3r4LsUEzWPwULdjNeZ/1jPfDrLKTGvHHk4oyDNvq0YU 98rFhWetCFGUqZkGfQXNx6JF8Zz1BjrNKFvNb1Qx2hmfWdEJaZ/Va3od67VVnoSR+a7/ omfQ== X-Received: by 10.68.19.67 with SMTP id c3mr35177086pbe.145.1374564943143; Tue, 23 Jul 2013 00:35:43 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.35.36 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:35:42 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 07/13] MIPS: Loongson 3: Add IRQ init and dispatch support Date: Tue, 23 Jul 2013 15:34:07 +0800 Message-Id: <1374564853-10762-8-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37355 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 6975 Lines: 205 IRQ routing path of Loongson-3: Devices(most) --> I8259 --> HT Controller --> IRQ Routing Table --> CPU ^ | Device(legacy devices such as UART) --> Bonito ---| IRQ Routing Table route 32 INTs to CPU's INT0~INT3(IP2~IP5 of CP0), 32 INTs include 16 HT INTs(mostly), 4 PCI INTs, 1 LPC INT, etc. IP6 is used for IPI and IP7 is used for internal MIPS timer. LOONGSON_INT_ROUTER_* are IRQ Routing Table registers. I8259 IRQs are 1:1 mapped to HT1 INTs. LOONGSON_HT1_* are configuration registers of HT1 controller. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/include/asm/mach-loongson/irq.h | 24 +++++++ arch/mips/include/asm/mach-loongson/loongson.h | 9 +++ arch/mips/loongson/Makefile | 6 ++ arch/mips/loongson/loongson-3/Makefile | 4 + arch/mips/loongson/loongson-3/irq.c | 87 ++++++++++++++++++++++++ 5 files changed, 130 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/irq.h create mode 100644 arch/mips/loongson/loongson-3/Makefile create mode 100644 arch/mips/loongson/loongson-3/irq.c diff --git a/arch/mips/include/asm/mach-loongson/irq.h b/arch/mips/include/asm/mach-loongson/irq.h new file mode 100644 index 0000000..4787cd0 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/irq.h @@ -0,0 +1,24 @@ +#ifndef __ASM_MACH_LOONGSON_IRQ_H_ +#define __ASM_MACH_LOONGSON_IRQ_H_ + +#include + +/* cpu core interrupt numbers */ +#define MIPS_CPU_IRQ_BASE 56 + +#ifdef CONFIG_CPU_LOONGSON3 + +#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* uart */ +#define LOONGSON_I8259_IRQ (MIPS_CPU_IRQ_BASE + 3) /* i8259 */ +#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ + +#define LOONGSON_HT1_CFG_BASE ht_control_base +#define LOONGSON_HT1_INT_VECTOR_BASE LOONGSON_HT1_CFG_BASE + 0x80 +#define LOONGSON_HT1_INT_EN_BASE LOONGSON_HT1_CFG_BASE + 0xa0 +#define LOONGSON_HT1_INT_VECTOR(n) LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * n) +#define LOONGSON_HT1_INTN_EN(n) LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * n) + +#endif + +#include_next +#endif /* __ASM_MACH_LOONGSON_IRQ_H_ */ diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 4f28b1f..40b4892 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -62,6 +62,12 @@ extern int mach_i8259_irq(void); #define LOONGSON_REG(x) \ (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) +#define LOONGSON3_REG8(base, x) \ + (*(volatile u8 *)((char *)TO_UNCAC(base) + (x))) + +#define LOONGSON3_REG32(base, x) \ + (*(volatile u32 *)((char *)TO_UNCAC(base) + (x))) + #define LOONGSON_IRQ_BASE 32 #define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ @@ -87,6 +93,9 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_REG_BASE 0x1fe00000 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) +#define LOONGSON3_REG_BASE 0x3ff00000 +#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ +#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1) #define LOONGSON_LIO1_BASE 0x1ff00000 #define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile index 0dc0055..7429994 100644 --- a/arch/mips/loongson/Makefile +++ b/arch/mips/loongson/Makefile @@ -15,3 +15,9 @@ obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ # obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/ + +# +# All Loongson-3 family machines +# + +obj-$(CONFIG_CPU_LOONGSON3) += loongson-3/ diff --git a/arch/mips/loongson/loongson-3/Makefile b/arch/mips/loongson/loongson-3/Makefile new file mode 100644 index 0000000..b9968cd --- /dev/null +++ b/arch/mips/loongson/loongson-3/Makefile @@ -0,0 +1,4 @@ +# +# Makefile for Loongson-3 family machines +# +obj-y += irq.o diff --git a/arch/mips/loongson/loongson-3/irq.c b/arch/mips/loongson/loongson-3/irq.c new file mode 100644 index 0000000..27aef31 --- /dev/null +++ b/arch/mips/loongson/loongson-3/irq.c @@ -0,0 +1,87 @@ +#include +#include +#include +#include + +#include +#include +#include + +#define LOONGSON_INT_ROUTER_OFFSET 0x1400 +#define LOONGSON_INT_ROUTER_INTEN LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24) +#define LOONGSON_INT_ROUTER_INTENSET LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28) +#define LOONGSON_INT_ROUTER_INTENCLR LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c) +#define LOONGSON_INT_ROUTER_ENTRY(n) LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n) +#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a) +#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18) + +#define LOONGSON_INT_CORE0_INT0 0x11 /* route to int 0 of core 0 */ +#define LOONGSON_INT_CORE0_INT1 0x21 /* route to int 1 of core 0 */ + +extern void loongson3_ipi_interrupt(struct pt_regs *regs); + +static void ht_irqdispatch(void) +{ + unsigned int i, irq; + unsigned int ht_irq[] = {1, 3, 4, 5, 6, 7, 8, 12, 14, 15}; + + irq = LOONGSON_HT1_INT_VECTOR(0); + LOONGSON_HT1_INT_VECTOR(0) = irq; + + for (i = 0; i < (sizeof(ht_irq) / sizeof(*ht_irq)); i++) { + if (irq & (0x1 << ht_irq[i])) + do_IRQ(ht_irq[i]); + } +} + +void mach_irq_dispatch(unsigned int pending) +{ + if (pending & CAUSEF_IP7) + do_IRQ(LOONGSON_TIMER_IRQ); +#if defined(CONFIG_SMP) + else if (pending & CAUSEF_IP6) + loongson3_ipi_interrupt(NULL); +#endif + else if (pending & CAUSEF_IP3) + ht_irqdispatch(); + else if (pending & CAUSEF_IP2) + do_IRQ(LOONGSON_UART_IRQ); + else { + printk(KERN_ERR "%s : spurious interrupt\n", __func__); + spurious_interrupt(); + } +} + +static struct irqaction cascade_irqaction = { + .handler = no_action, + .name = "cascade", +}; + +void irq_router_init(void) +{ + int i; + + /* route LPC int to cpu core0 int 0 */ + LOONGSON_INT_ROUTER_LPC = LOONGSON_INT_CORE0_INT0; + /* route HT1 int0 ~ int7 to cpu core0 INT1*/ + for (i = 0; i < 8; i++) + LOONGSON_INT_ROUTER_HT1(i) = LOONGSON_INT_CORE0_INT1; + /* enable HT1 interrupt */ + LOONGSON_HT1_INTN_EN(0) = 0xffffffff; + /* enable router interrupt intenset */ + LOONGSON_INT_ROUTER_INTENSET = LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10; +} + +void __init mach_init_irq(void) +{ + clear_c0_status(ST0_IM | ST0_BEV); + + irq_router_init(); + mips_cpu_irq_init(); + init_i8259_irqs(); + + /* setup i8259 irq */ + setup_irq(LOONGSON_I8259_IRQ, &cascade_irqaction); + + set_c0_status(STATUSF_IP2 | STATUSF_IP6); +} -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:38:57 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:39:12 +0200 (CEST) Received: from mail-pa0-f44.google.com ([209.85.220.44]:64117 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6826530Ab3GWHf5aghqZ (ORCPT ); Tue, 23 Jul 2013 09:35:57 +0200 Received: by mail-pa0-f44.google.com with SMTP id jh10so167759pab.17 for ; Tue, 23 Jul 2013 00:35:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=8bTrhv2I5wlQVOk9nTB4qgvjMmvFTreuBr2hFPuh6E8=; b=uHFZsiatmap5TMRCh350JA7fKrh6z6lWHnKXvii+DiNwXFzs3l452z1a656t7A8AwG osO9iNDFHUmc0FfPkcnFFyuq0u5dU1JPJUWH6Y5QemcNmok+Pswb6d8EGdzuYNZLNmqj Ir1uo7Q3r0Iygq+KvZGDVKtK5BkapNE4TuKjOyX1qFlasF1gDkE0bj+0h/Mu4EhprwV8 faRyF7k1Yl7vmUD7cN9UwfDjX3CDuMHkQaoPwpJ6LEkOurTRFKSLBP9PqGolnmTF7x59 XfhyImN3g0RWCtEXOIERTdyEXGRFRxJpQhFmq78SbJzU7XJoRhYEbgbaL38zj7Vsk9G/ OCQA== X-Received: by 10.68.163.165 with SMTP id yj5mr34861243pbb.141.1374564950828; Tue, 23 Jul 2013 00:35:50 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.35.43 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:35:49 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 08/13] MIPS: Loongson 3: Add serial port support Date: Tue, 23 Jul 2013 15:34:08 +0800 Message-Id: <1374564853-10762-9-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37356 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3429 Lines: 99 Loongson family machines has three types of serial port: PCI UART, LPC UART and CPU internal UART. Loongson-2E and parts of Loongson-2F based machines use PCI UART; most Loongson-2F based machines use LPC UART; Loongson-2G/3A has both LPC and CPU UART but usually use CPU UART. Port address of UARTs: CPU UART: REG_BASE + OFFSET; LPC UART: LIO1_BASE + OFFSET; PCI UART: PCIIO_BASE + OFFSET. Since LPC UART are linked in "Local Bus", both CPU UART and LPC UART are called "CPU provided serial port". Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/loongson/common/serial.c | 26 +++++++++++++++----------- arch/mips/loongson/common/uart_base.c | 9 ++++++++- 2 files changed, 23 insertions(+), 12 deletions(-) diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c index 5f2b78a..bd2b709 100644 --- a/arch/mips/loongson/common/serial.c +++ b/arch/mips/loongson/common/serial.c @@ -19,19 +19,19 @@ #include #include -#define PORT(int) \ +#define PORT(int, clk) \ { \ .irq = int, \ - .uartclk = 1843200, \ + .uartclk = clk, \ .iotype = UPIO_PORT, \ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ .regshift = 0, \ } -#define PORT_M(int) \ +#define PORT_M(int, clk) \ { \ .irq = MIPS_CPU_IRQ_BASE + (int), \ - .uartclk = 3686400, \ + .uartclk = clk, \ .iotype = UPIO_MEM, \ .membase = (void __iomem *)NULL, \ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ @@ -40,13 +40,17 @@ static struct plat_serial8250_port uart8250_data[][2] = { [MACH_LOONGSON_UNKNOWN] {}, - [MACH_LEMOTE_FL2E] {PORT(4), {} }, - [MACH_LEMOTE_FL2F] {PORT(3), {} }, - [MACH_LEMOTE_ML2F7] {PORT_M(3), {} }, - [MACH_LEMOTE_YL2F89] {PORT_M(3), {} }, - [MACH_DEXXON_GDIUM2F10] {PORT_M(3), {} }, - [MACH_LEMOTE_NAS] {PORT_M(3), {} }, - [MACH_LEMOTE_LL2F] {PORT(3), {} }, + [MACH_LEMOTE_FL2E] {PORT(4, 1843200), {} }, + [MACH_LEMOTE_FL2F] {PORT(3, 1843200), {} }, + [MACH_LEMOTE_ML2F7] {PORT_M(3, 3686400), {} }, + [MACH_LEMOTE_YL2F89] {PORT_M(3, 3686400), {} }, + [MACH_DEXXON_GDIUM2F10] {PORT_M(3, 3686400), {} }, + [MACH_LEMOTE_NAS] {PORT_M(3, 3686400), {} }, + [MACH_LEMOTE_LL2F] {PORT(3, 1843200), {} }, + [MACH_LEMOTE_A1004] {PORT_M(2, 33177600), {} }, + [MACH_LEMOTE_A1101] {PORT_M(2, 25000000), {} }, + [MACH_LEMOTE_A1201] {PORT_M(2, 25000000), {} }, + [MACH_LEMOTE_A1205] {PORT_M(2, 25000000), {} }, [MACH_LOONGSON_END] {}, }; diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c index e192ad0..1e1eeea 100644 --- a/arch/mips/loongson/common/uart_base.c +++ b/arch/mips/loongson/common/uart_base.c @@ -35,9 +35,16 @@ void prom_init_loongson_uart_base(void) case MACH_DEXXON_GDIUM2F10: case MACH_LEMOTE_NAS: default: - /* The CPU provided serial port */ + /* The CPU provided serial port (LPC) */ loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8; break; + case MACH_LEMOTE_A1004: + case MACH_LEMOTE_A1101: + case MACH_LEMOTE_A1201: + case MACH_LEMOTE_A1205: + /* The CPU provided serial port (CPU) */ + loongson_uart_base = LOONGSON_REG_BASE + 0x1e0; + break; } _loongson_uart_base = -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:39:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:39:34 +0200 (CEST) Received: from mail-pd0-f181.google.com ([209.85.192.181]:36371 "EHLO mail-pd0-f181.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822679Ab3GWHgFmYJji (ORCPT ); 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If memory is more than 4GB, CONFIG_SWIOTLB and ZONE_DMA32 should be selected. In this way, DMA pages are allocated below 4GB preferably. However, CONFIG_SWIOTLB+ZONE_DMA32 is not enough, so, we provide a platform-specific dma_map_ops::set_dma_mask() to make sure each driver's dma_mask and coherent_dma_mask is below 32-bit. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/include/asm/dma-mapping.h | 5 + .../mips/include/asm/mach-loongson/dma-coherence.h | 23 +++ arch/mips/loongson/common/Makefile | 5 + arch/mips/loongson/common/dma-swiotlb.c | 163 ++++++++++++++++++++ 4 files changed, 196 insertions(+), 0 deletions(-) create mode 100644 arch/mips/loongson/common/dma-swiotlb.c diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 84238c5..06412aa 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -49,9 +49,14 @@ static inline int dma_mapping_error(struct device *dev, u64 mask) static inline int dma_set_mask(struct device *dev, u64 mask) { + struct dma_map_ops *ops = get_dma_ops(dev); + if(!dev->dma_mask || !dma_supported(dev, mask)) return -EIO; + if (ops->set_dma_mask) + return ops->set_dma_mask(dev, mask); + *dev->dma_mask = mask; return 0; diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index e143305..3d752e8 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -11,18 +11,34 @@ #ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H #define __ASM_MACH_LOONGSON_DMA_COHERENCE_H +#ifdef CONFIG_SWIOTLB +#include +#endif + struct device; +extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); +extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) { +#ifdef CONFIG_CPU_LOONGSON3 + return virt_to_phys(addr) < 0x10000000 ? + (virt_to_phys(addr) | 0x0000000080000000) : virt_to_phys(addr); +#else return virt_to_phys(addr) | 0x80000000; +#endif } static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) { +#ifdef CONFIG_CPU_LOONGSON3 + return page_to_phys(page) < 0x10000000 ? + (page_to_phys(page) | 0x0000000080000000) : page_to_phys(page); +#else return page_to_phys(page) | 0x80000000; +#endif } static inline unsigned long plat_dma_addr_to_phys(struct device *dev, @@ -30,6 +46,9 @@ static inline unsigned long plat_dma_addr_to_phys(struct device *dev, { #if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); +#elif defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT) + return (dma_addr < 0x90000000 && dma_addr >= 0x80000000) ? + (dma_addr & 0x0fffffff) : dma_addr; #else return dma_addr & 0x7fffffff; #endif @@ -65,7 +84,11 @@ static inline int plat_dma_mapping_error(struct device *dev, static inline int plat_device_is_coherent(struct device *dev) { +#ifdef CONFIG_DMA_NONCOHERENT return 0; +#else + return 1; +#endif /* CONFIG_DMA_NONCOHERENT */ } #endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */ diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index 4c57b3e..f1e2283 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -25,3 +25,8 @@ obj-$(CONFIG_CS5536) += cs5536/ # obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o + +# +# Big Memory Support +# +obj-$(CONFIG_LOONGSON_BIGMEM) += dma-swiotlb.o diff --git a/arch/mips/loongson/common/dma-swiotlb.c b/arch/mips/loongson/common/dma-swiotlb.c new file mode 100644 index 0000000..6741f1b --- /dev/null +++ b/arch/mips/loongson/common/dma-swiotlb.c @@ -0,0 +1,163 @@ +#include +#include +#include +#include +#include +#include + +#include +#include + +static void *loongson_dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs) +{ + void *ret; + + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) + return ret; + + /* ignore region specifiers */ + gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); + +#ifdef CONFIG_ZONE_DMA + if (dev == NULL) + gfp |= __GFP_DMA; + else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24)) + gfp |= __GFP_DMA; + else +#endif +#ifdef CONFIG_ZONE_DMA32 + if (dev == NULL) + gfp |= __GFP_DMA32; + else if (dev->coherent_dma_mask <= DMA_BIT_MASK(32)) + gfp |= __GFP_DMA32; + else +#endif + ; + gfp |= __GFP_NORETRY; + + ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp); + mb(); + return ret; +} + +static void loongson_dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs) +{ + int order = get_order(size); + + if (dma_release_from_coherent(dev, order, vaddr)) + return; + + swiotlb_free_coherent(dev, size, vaddr, dma_handle); +} + +static dma_addr_t loongson_dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size, + dir, attrs); + mb(); + return daddr; +} + +static int loongson_dma_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + int r = swiotlb_map_sg_attrs(dev, sg, nents, dir, NULL); + mb(); + + return r; +} + +static void loongson_dma_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) +{ + swiotlb_sync_single_for_device(dev, dma_handle, size, dir); + mb(); +} + +static void loongson_dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, int nents, + enum dma_data_direction dir) +{ + swiotlb_sync_sg_for_device(dev, sg, nents, dir); + mb(); +} + +static dma_addr_t loongson_unity_phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + return (paddr < 0x10000000) ? + (paddr | 0x0000000080000000) : paddr; +} + +static phys_addr_t loongson_unity_dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + return (daddr < 0x90000000 && daddr >= 0x80000000) ? + (daddr & 0x0fffffff) : daddr; +} + +struct loongson_dma_map_ops { + struct dma_map_ops dma_map_ops; + dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr); + phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr); +}; + +dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + struct loongson_dma_map_ops *ops = container_of(get_dma_ops(dev), + struct loongson_dma_map_ops, dma_map_ops); + + return ops->phys_to_dma(dev, paddr); +} + +phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + struct loongson_dma_map_ops *ops = container_of(get_dma_ops(dev), + struct loongson_dma_map_ops, dma_map_ops); + + return ops->dma_to_phys(dev, daddr); +} + +static int loongson_dma_set_mask(struct device *dev, u64 mask) +{ + /* Loongson doesn't support DMA above 32-bit */ + if (mask > DMA_BIT_MASK(32)) { + *dev->dma_mask = DMA_BIT_MASK(32); + return -EIO; + } + + *dev->dma_mask = mask; + + return 0; +} + +static struct loongson_dma_map_ops loongson_linear_dma_map_ops = { + .dma_map_ops = { + .alloc = loongson_dma_alloc_coherent, + .free = loongson_dma_free_coherent, + .map_page = loongson_dma_map_page, + .unmap_page = swiotlb_unmap_page, + .map_sg = loongson_dma_map_sg, + .unmap_sg = swiotlb_unmap_sg_attrs, + .sync_single_for_cpu = swiotlb_sync_single_for_cpu, + .sync_single_for_device = loongson_dma_sync_single_for_device, + .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, + .sync_sg_for_device = loongson_dma_sync_sg_for_device, + .mapping_error = swiotlb_dma_mapping_error, + .dma_supported = swiotlb_dma_supported, + .set_dma_mask = loongson_dma_set_mask + }, + .phys_to_dma = loongson_unity_phys_to_dma, + .dma_to_phys = loongson_unity_dma_to_phys +}; + +void __init plat_swiotlb_setup(void) +{ + swiotlb_init(1); + mips_dma_map_ops = &loongson_linear_dma_map_ops.dma_map_ops; +} -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:39:50 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:39:57 +0200 (CEST) Received: from mail-pa0-f46.google.com ([209.85.220.46]:46744 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827592Ab3GWHgP30-hj (ORCPT ); Tue, 23 Jul 2013 09:36:15 +0200 Received: by mail-pa0-f46.google.com with SMTP id fa1so2681330pad.19 for ; Tue, 23 Jul 2013 00:36:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=HjG/2aTxj/RwzFHwMoAOYufuDQaOzzqEwC2AEvt5EpU=; b=Tct4J5yPrxiXer1iLUVYlUuQ1JWF9NG0Jl7V1EEvf+wbQTVo3vaDT+jGQPQ68Darlk Dp3x/a0PiRZepEkyOYXjizsKHsawPaFlguaxxhQ2InyDasEgQ/rK9xKcRuK+4Ii1ZfG0 tsZkNCgUoCfAfWafaTfWVenfLqbmCAg9tn0g1iesRNehVT4JGZuZpvv63BYbuWwjpsRr tsMXNKKfN6uoyHoLlY4dI7Ae9F4xMA8zRKZRUSWRekyCFPhy7FCQ3SykENPcH5oV8p9z RAiX3IMvX+6QF9JkBe28s6V7U+QwHbXw6c9awGr6/WoZdyyAPaHBUDNzrsOwUvPzyGOE 8JwA== X-Received: by 10.68.218.199 with SMTP id pi7mr35080974pbc.19.1374564968909; Tue, 23 Jul 2013 00:36:08 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.35.59 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:36:07 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 10/13] MIPS: Loongson: Add Loongson-3 Kconfig options Date: Tue, 23 Jul 2013 15:34:10 +0800 Message-Id: <1374564853-10762-11-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37358 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3821 Lines: 148 Added Kconfig options include: Loongson-3 CPU and machine definition, CPU cache features, UEFI-like firmware interface, HT-linked PCI, and big memory support. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/Kconfig | 29 ++++++++++++++++++++++++ arch/mips/loongson/Kconfig | 52 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9f8fe64..5ad608f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1505,6 +1505,19 @@ config CPU_LOONGSON2 select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES +config CPU_LOONGSON3 + bool "Loongson 3 CPU" + depends on SYS_HAS_CPU_LOONGSON3 + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select CPU_SUPPORTS_HUGEPAGES + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + help + The Loongson 3 processor implements the MIPS III instruction set + with many extensions. + config CPU_LOONGSON1 bool select CPU_MIPS32 @@ -1531,6 +1544,11 @@ config SYS_HAS_CPU_LOONGSON2F select CPU_SUPPORTS_ADDRWINCFG if 64BIT select CPU_SUPPORTS_UNCACHED_ACCELERATED +config SYS_HAS_CPU_LOONGSON3 + bool + select CPU_SUPPORTS_CPUFREQ + select CPU_SUPPORTS_COHERENT_CACHE + config SYS_HAS_CPU_LOONGSON1B bool @@ -1665,6 +1683,8 @@ config CPU_SUPPORTS_HUGEPAGES bool config CPU_SUPPORTS_UNCACHED_ACCELERATED bool +config CPU_SUPPORTS_COHERENT_CACHE + bool config MIPS_PGD_C0_CONTEXT bool default y if 64BIT && CPU_MIPSR2 && !CPU_XLP @@ -2398,6 +2418,15 @@ config PCI your box. Other bus systems are ISA, EISA, or VESA. If you have PCI, say Y, otherwise N. +config HT_PCI + bool "Support for HT-linked PCI" + select PCI_DOMAINS + help + Loongson family machines use Hyper-Transport bus for inter-core + connection and device connection. The PCI bus is a subordinate + linked at HT. Choose Y unless you are using Loongson 2E/2F based + machines. + config PCI_DOMAINS bool diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 263beb9..dd951b8 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -59,6 +59,33 @@ config LEMOTE_MACH2F These family machines include fuloong2f mini PC, yeeloong2f notebook, LingLoong allinone PC and so forth. + +config LEMOTE_MACH3A + bool "Lemote Loongson 3A family machines" + select ARCH_SPARSEMEM_ENABLE + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select GENERIC_HARDIRQS_NO__DO_IRQ + select BOOT_ELF32 + select BOARD_SCACHE + select CSRC_R4K + select CEVT_R4K + select CPU_HAS_WB + select HW_HAS_PCI + select ISA + select I8259 + select IRQ_CPU + select SYS_HAS_CPU_LOONGSON3 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN + select LOONGSON_MC146818 + select UEFI_FIRMWARE_INTERFACE + help + Lemote Loongson 3A family machines utilize the 3A revision of + Loongson processor and RS780/SBX00 chipset. endchoice config CS5536 @@ -86,8 +113,33 @@ config LOONGSON_UART_BASE default y depends on EARLY_PRINTK || SERIAL_8250 +config LOONGSON_BIGMEM + bool "Soft IOMMU Support for Big Memory (>4GB)" + depends on CPU_LOONGSON3 + select SWIOTLB + select ZONE_DMA32 + +config IOMMU_HELPER + bool + +config NEED_SG_DMA_LENGTH + bool + +config SWIOTLB + bool + select IOMMU_HELPER + select NEED_SG_DMA_LENGTH + select NEED_DMA_MAP_STATE + config LOONGSON_MC146818 bool default n +config ARCH_SPARSEMEM_ENABLE + bool + select SPARSEMEM_STATIC + +config UEFI_FIRMWARE_INTERFACE + bool + endif # MACH_LOONGSON -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:40:13 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:40:19 +0200 (CEST) Received: from mail-pd0-f173.google.com ([209.85.192.173]:37749 "EHLO mail-pd0-f173.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6834807Ab3GWHgVIW1is (ORCPT ); Tue, 23 Jul 2013 09:36:21 +0200 Received: by mail-pd0-f173.google.com with SMTP id bv13so536032pdb.32 for ; Tue, 23 Jul 2013 00:36:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=MUvXUBS1cWDlVh6LYiiGc/YB+iQ05F5k2s/Zegyr3PQ=; b=XoXx0zedViaOcbEf6T9kdLx0DP8TofCAe9L/Nf3lCJynAPFZWe0+BAmFvkHJN80yZ1 sL93/3ctrAScChrKWYH8SDswsJSxryrIrVhpt4uomJjvRc+j7IeB0a/JTDIqVQ4KMLkV XPyNJN8DvUe9CUYYPeBb0+IPuLJE7WcdpoMOgnuIqlF8qV0wB0pcSj4Nlsj1qgsYcWXb +a7ROcMtVS0BveB/2a5a8508Dzb8bDQ08Xun+I8nn1b61IQhhBoLDWm4zQCycqWpPl+O yorVxg89cpfW0K1bAqqDs048jP03EPte69+abZlzQoUHg3zSswMLz0o4p53gvDepb25u VGgw== X-Received: by 10.68.240.72 with SMTP id vy8mr34932289pbc.161.1374564974487; Tue, 23 Jul 2013 00:36:14 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.36.09 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:36:13 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 11/13] MIPS: Loongson 3: Add Loongson-3 SMP support Date: Tue, 23 Jul 2013 15:34:11 +0800 Message-Id: <1374564853-10762-12-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37359 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 14917 Lines: 421 IPI registers of Loongson-3 include IPI_SET, IPI_CLEAR, IPI_STATUS, IPI_EN and IPI_MAILBOX_BUF. Each bit of IPI_STATUS indicate a type of IPI and IPI_EN indicate whether the IPI is enabled. The sender write 1 to IPI_SET bits generate IPIs in IPI_STATUS, and receiver write 1 to bits of IPI_CLEAR to clear IPIs. IPI_MAILBOX_BUF are used to deliver more information about IPIs. Why we change code in arch/mips/loongson/common/setup.c? If without this change, when SMP configured, system cannot boot since it hang at printk() in cgroup_init_early(). The root cause is: console_trylock() \-->down_trylock(&console_sem) \-->raw_spin_unlock_irqrestore(&sem->lock, flags) \-->_raw_spin_unlock_irqrestore()(SMP/UP have different versions) \-->__raw_spin_unlock_irqrestore() (following is the SMP case) \-->do_raw_spin_unlock() \-->arch_spin_unlock() \-->nudge_writes() \-->mb() \-->wbflush() \-->__wbflush() In previous code __wbflush() is initialized in plat_mem_setup(), but cgroup_init_early() is called before plat_mem_setup(). Therefore, In this patch we make changes to avoid boot failure. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/loongson/common/init.c | 5 + arch/mips/loongson/common/setup.c | 8 +- arch/mips/loongson/loongson-3/Makefile | 2 + arch/mips/loongson/loongson-3/smp.c | 280 ++++++++++++++++++++++++++++++++ arch/mips/loongson/loongson-3/smp.h | 24 +++ 5 files changed, 314 insertions(+), 5 deletions(-) create mode 100644 arch/mips/loongson/loongson-3/smp.c create mode 100644 arch/mips/loongson/loongson-3/smp.h diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index 81ba3b4..d6c501b 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -12,6 +12,8 @@ #include +extern struct plat_smp_ops loongson3_smp_ops; + /* Loongson CPU address windows config space base address */ unsigned long __maybe_unused _loongson_addrwincfg_base; @@ -33,6 +35,9 @@ void __init prom_init(void) /*init the uart base address */ prom_init_uart_base(); +#if defined(CONFIG_SMP) + register_smp_ops(&loongson3_smp_ops); +#endif } void __init prom_free_prom_memory(void) diff --git a/arch/mips/loongson/common/setup.c b/arch/mips/loongson/common/setup.c index 8223f8a..bb4ac92 100644 --- a/arch/mips/loongson/common/setup.c +++ b/arch/mips/loongson/common/setup.c @@ -18,9 +18,6 @@ #include #endif -void (*__wbflush)(void); -EXPORT_SYMBOL(__wbflush); - static void wbflush_loongson(void) { asm(".set\tpush\n\t" @@ -32,10 +29,11 @@ static void wbflush_loongson(void) ".set mips0\n\t"); } +void (*__wbflush)(void) = wbflush_loongson; +EXPORT_SYMBOL(__wbflush); + void __init plat_mem_setup(void) { - __wbflush = wbflush_loongson; - #ifdef CONFIG_VT #if defined(CONFIG_VGA_CONSOLE) conswitchp = &vga_con; diff --git a/arch/mips/loongson/loongson-3/Makefile b/arch/mips/loongson/loongson-3/Makefile index b9968cd..70152b2 100644 --- a/arch/mips/loongson/loongson-3/Makefile +++ b/arch/mips/loongson/loongson-3/Makefile @@ -2,3 +2,5 @@ # Makefile for Loongson-3 family machines # obj-y += irq.o + +obj-$(CONFIG_SMP) += smp.o diff --git a/arch/mips/loongson/loongson-3/smp.c b/arch/mips/loongson/loongson-3/smp.c new file mode 100644 index 0000000..cb996d5 --- /dev/null +++ b/arch/mips/loongson/loongson-3/smp.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2010, 2011, 2012, Lemote, Inc. + * Author: Chen Huacai, chenhc@lemote.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "smp.h" + +/* read a 64bit value from ipi register */ +uint64_t loongson3_ipi_read64(void * addr) +{ + return *((volatile uint64_t *)addr); +}; + +/* write a 64bit value to ipi register */ +void loongson3_ipi_write64(uint64_t action, void * addr) +{ + *((volatile uint64_t *)addr) = action; + __wbflush(); +}; + +/* read a 32bit value from ipi register */ +uint32_t loongson3_ipi_read32(void * addr) +{ + return *((volatile uint32_t *)addr); +}; + +/* write a 32bit value to ipi register */ +void loongson3_ipi_write32(uint32_t action, void * addr) +{ + *((volatile uint32_t *)addr) = action; + __wbflush(); +}; + +static void *ipi_set0_regs[] = { + (void *)(smp_core_group0_base + smp_core0_offset + SET0), + (void *)(smp_core_group0_base + smp_core1_offset + SET0), + (void *)(smp_core_group0_base + smp_core2_offset + SET0), + (void *)(smp_core_group0_base + smp_core3_offset + SET0), + (void *)(smp_core_group1_base + smp_core0_offset + SET0), + (void *)(smp_core_group1_base + smp_core1_offset + SET0), + (void *)(smp_core_group1_base + smp_core2_offset + SET0), + (void *)(smp_core_group1_base + smp_core3_offset + SET0), + (void *)(smp_core_group2_base + smp_core0_offset + SET0), + (void *)(smp_core_group2_base + smp_core1_offset + SET0), + (void *)(smp_core_group2_base + smp_core2_offset + SET0), + (void *)(smp_core_group2_base + smp_core3_offset + SET0), + (void *)(smp_core_group3_base + smp_core0_offset + SET0), + (void *)(smp_core_group3_base + smp_core1_offset + SET0), + (void *)(smp_core_group3_base + smp_core2_offset + SET0), + (void *)(smp_core_group3_base + smp_core3_offset + SET0), +}; + +static void *ipi_clear0_regs[] = { + (void *)(smp_core_group0_base + smp_core0_offset + CLEAR0), + (void *)(smp_core_group0_base + smp_core1_offset + CLEAR0), + (void *)(smp_core_group0_base + smp_core2_offset + CLEAR0), + (void *)(smp_core_group0_base + smp_core3_offset + CLEAR0), + (void *)(smp_core_group1_base + smp_core0_offset + CLEAR0), + (void *)(smp_core_group1_base + smp_core1_offset + CLEAR0), + (void *)(smp_core_group1_base + smp_core2_offset + CLEAR0), + (void *)(smp_core_group1_base + smp_core3_offset + CLEAR0), + (void *)(smp_core_group2_base + smp_core0_offset + CLEAR0), + (void *)(smp_core_group2_base + smp_core1_offset + CLEAR0), + (void *)(smp_core_group2_base + smp_core2_offset + CLEAR0), + (void *)(smp_core_group2_base + smp_core3_offset + CLEAR0), + (void *)(smp_core_group3_base + smp_core0_offset + CLEAR0), + (void *)(smp_core_group3_base + smp_core1_offset + CLEAR0), + (void *)(smp_core_group3_base + smp_core2_offset + CLEAR0), + (void *)(smp_core_group3_base + smp_core3_offset + CLEAR0), +}; + +static void *ipi_status0_regs[] = { + (void *)(smp_core_group0_base + smp_core0_offset + STATUS0), + (void *)(smp_core_group0_base + smp_core1_offset + STATUS0), + (void *)(smp_core_group0_base + smp_core2_offset + STATUS0), + (void *)(smp_core_group0_base + smp_core3_offset + STATUS0), + (void *)(smp_core_group1_base + smp_core0_offset + STATUS0), + (void *)(smp_core_group1_base + smp_core1_offset + STATUS0), + (void *)(smp_core_group1_base + smp_core2_offset + STATUS0), + (void *)(smp_core_group1_base + smp_core3_offset + STATUS0), + (void *)(smp_core_group2_base + smp_core0_offset + STATUS0), + (void *)(smp_core_group2_base + smp_core1_offset + STATUS0), + (void *)(smp_core_group2_base + smp_core2_offset + STATUS0), + (void *)(smp_core_group2_base + smp_core3_offset + STATUS0), + (void *)(smp_core_group3_base + smp_core0_offset + STATUS0), + (void *)(smp_core_group3_base + smp_core1_offset + STATUS0), + (void *)(smp_core_group3_base + smp_core2_offset + STATUS0), + (void *)(smp_core_group3_base + smp_core3_offset + STATUS0), +}; + +static void *ipi_en0_regs[] = { + (void *)(smp_core_group0_base + smp_core0_offset + EN0), + (void *)(smp_core_group0_base + smp_core1_offset + EN0), + (void *)(smp_core_group0_base + smp_core2_offset + EN0), + (void *)(smp_core_group0_base + smp_core3_offset + EN0), + (void *)(smp_core_group1_base + smp_core0_offset + EN0), + (void *)(smp_core_group1_base + smp_core1_offset + EN0), + (void *)(smp_core_group1_base + smp_core2_offset + EN0), + (void *)(smp_core_group1_base + smp_core3_offset + EN0), + (void *)(smp_core_group2_base + smp_core0_offset + EN0), + (void *)(smp_core_group2_base + smp_core1_offset + EN0), + (void *)(smp_core_group2_base + smp_core2_offset + EN0), + (void *)(smp_core_group2_base + smp_core3_offset + EN0), + (void *)(smp_core_group3_base + smp_core0_offset + EN0), + (void *)(smp_core_group3_base + smp_core1_offset + EN0), + (void *)(smp_core_group3_base + smp_core2_offset + EN0), + (void *)(smp_core_group3_base + smp_core3_offset + EN0), +}; + +static volatile void *ipi_mailbox_buf[] = { + (void *)(smp_core_group0_base + smp_core0_offset + BUF), + (void *)(smp_core_group0_base + smp_core1_offset + BUF), + (void *)(smp_core_group0_base + smp_core2_offset + BUF), + (void *)(smp_core_group0_base + smp_core3_offset + BUF), + (void *)(smp_core_group1_base + smp_core0_offset + BUF), + (void *)(smp_core_group1_base + smp_core1_offset + BUF), + (void *)(smp_core_group1_base + smp_core2_offset + BUF), + (void *)(smp_core_group1_base + smp_core3_offset + BUF), + (void *)(smp_core_group2_base + smp_core0_offset + BUF), + (void *)(smp_core_group2_base + smp_core1_offset + BUF), + (void *)(smp_core_group2_base + smp_core2_offset + BUF), + (void *)(smp_core_group2_base + smp_core3_offset + BUF), + (void *)(smp_core_group3_base + smp_core0_offset + BUF), + (void *)(smp_core_group3_base + smp_core1_offset + BUF), + (void *)(smp_core_group3_base + smp_core2_offset + BUF), + (void *)(smp_core_group3_base + smp_core3_offset + BUF), +}; + +/* + * Simple enough, just poke the appropriate ipi register + */ +static void loongson3_send_ipi_single(int cpu, unsigned int action) +{ + loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]); +} + +static void loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu(i, mask) + loongson3_ipi_write32((u32)action, ipi_set0_regs[i]); +} + +void loongson3_ipi_interrupt(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + unsigned int action; + + /* Load the ipi register to figure out what we're supposed to do */ + action = loongson3_ipi_read32(ipi_status0_regs[cpu]); + + /* Clear the ipi register to clear the interrupt */ + loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu]); + + if (action & SMP_RESCHEDULE_YOURSELF) { + scheduler_ipi(); + } + + if (action & SMP_CALL_FUNCTION) { + smp_call_function_interrupt(); + } +} + +/* + * SMP init and finish on secondary CPUs + */ +void __cpuinit loongson3_init_secondary(void) +{ + int i; + unsigned int imask = STATUSF_IP7 | STATUSF_IP6 | + STATUSF_IP3 | STATUSF_IP2; + + /* Set interrupt mask, but don't enable */ + change_c0_status(ST0_IM, imask); + + for (i = 0; i < nr_cpus_loongson; i++) { + loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]); + } +} + +void __cpuinit loongson3_smp_finish(void) +{ + write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); + local_irq_enable(); + loongson3_ipi_write64(0, (void *)(ipi_mailbox_buf[smp_processor_id()]+0x0)); + printk(KERN_INFO "CPU#%d finished, CP0_ST=%x\n", + smp_processor_id(), read_c0_status()); +} + +void __init loongson3_smp_setup(void) +{ + int i, num; + + init_cpu_possible(cpu_none_mask); + set_cpu_possible(0, true); + + __cpu_number_map[0] = 0; + __cpu_logical_map[0] = 0; + + /* For unified kernel, NR_CPUS is the maximum possible value, + * nr_cpus_loongson is the really present value */ + for (i = 1, num = 0; i < nr_cpus_loongson; i++) { + set_cpu_possible(i, true); + __cpu_number_map[i] = ++num; + __cpu_logical_map[num] = i; + } + printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); +} + +void __init loongson3_prepare_cpus(unsigned int max_cpus) +{ +} + +/* + * Setup the PC, SP, and GP of a secondary processor and start it runing! + */ +void __cpuinit loongson3_boot_secondary(int cpu, struct task_struct *idle) +{ + volatile unsigned long startargs[4]; + + printk(KERN_INFO "Booting CPU#%d...\n", cpu); + + /* startargs[] are initial PC, SP and GP for secondary CPU */ + startargs[0] = (unsigned long)&smp_bootstrap; + startargs[1] = (unsigned long)__KSTK_TOS(idle); + startargs[2] = (unsigned long)task_thread_info(idle); + startargs[3] = 0; + + printk(KERN_DEBUG "CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", + cpu, startargs[0], startargs[1], startargs[2]); + + loongson3_ipi_write64(startargs[3], (void *)(ipi_mailbox_buf[cpu]+0x18)); + loongson3_ipi_write64(startargs[2], (void *)(ipi_mailbox_buf[cpu]+0x10)); + loongson3_ipi_write64(startargs[1], (void *)(ipi_mailbox_buf[cpu]+0x8)); + loongson3_ipi_write64(startargs[0], (void *)(ipi_mailbox_buf[cpu]+0x0)); +} + +/* + * Final cleanup after all secondaries booted + */ +void __init loongson3_cpus_done(void) +{ +} + +struct plat_smp_ops loongson3_smp_ops = { + .send_ipi_single = loongson3_send_ipi_single, + .send_ipi_mask = loongson3_send_ipi_mask, + .init_secondary = loongson3_init_secondary, + .smp_finish = loongson3_smp_finish, + .cpus_done = loongson3_cpus_done, + .boot_secondary = loongson3_boot_secondary, + .smp_setup = loongson3_smp_setup, + .prepare_cpus = loongson3_prepare_cpus, +}; diff --git a/arch/mips/loongson/loongson-3/smp.h b/arch/mips/loongson/loongson-3/smp.h new file mode 100644 index 0000000..dc9ce69 --- /dev/null +++ b/arch/mips/loongson/loongson-3/smp.h @@ -0,0 +1,24 @@ +/* for Loongson-3A smp support */ + +/* 4 groups(nodes) in maximum in numa case */ +#define smp_core_group0_base 0x900000003ff01000 +#define smp_core_group1_base 0x900010003ff01000 +#define smp_core_group2_base 0x900020003ff01000 +#define smp_core_group3_base 0x900030003ff01000 + +/* 4 cores in each group(node) */ +#define smp_core0_offset 0x000 +#define smp_core1_offset 0x100 +#define smp_core2_offset 0x200 +#define smp_core3_offset 0x300 + +/* ipi registers offsets */ +#define STATUS0 0x00 +#define EN0 0x04 +#define SET0 0x08 +#define CLEAR0 0x0c +#define STATUS1 0x10 +#define MASK1 0x14 +#define SET1 0x18 +#define CLEAR1 0x1c +#define BUF 0x20 -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:40:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:40:59 +0200 (CEST) Received: from mail-pd0-f170.google.com ([209.85.192.170]:50554 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6834832Ab3GWHg3KUf0n (ORCPT ); Tue, 23 Jul 2013 09:36:29 +0200 Received: by mail-pd0-f170.google.com with SMTP id x11so7818777pdj.15 for ; Tue, 23 Jul 2013 00:36:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=ekQ1DKIVgW2RTkaGSZNtLyReWGhK8I96jQOdxh2NxKY=; b=RxKE+5qKE+hcHtkNvwaombc5F3ylsT21snecxrrSraUw3kSM+CCTHDMJzmrGfkSBN2 90awPseaWhdwYtz0ktidsHH8MDaU2MQaxEHRr/iLHvAwIGdhQBdQB7XIjnVQ1CPsgf0f PJwjJ8fsXAJjyLUhDE8wgUqgknsiaCLPYq6Dvys3Puh0jLEPbf0L44JeVNChiM4w1bxB 4dH1slNx8UIY8WrtyIXlC8kTQlXq3jbK5uuYUq7xKlhYFYBHeDwICJNbitfV/9yXQkq+ 9MTVqBr9atXdcAiFxtSeojUWwhktkLJ8MpmUBi296GNL95HSZ4OC5FN/J47mau7tjwp/ Xhvw== X-Received: by 10.68.166.5 with SMTP id zc5mr35205299pbb.16.1374564982585; Tue, 23 Jul 2013 00:36:22 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.36.14 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:36:21 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 12/13] MIPS: Loongson 3: Add CPU hotplug support Date: Tue, 23 Jul 2013 15:34:12 +0800 Message-Id: <1374564853-10762-13-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37360 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 10315 Lines: 318 Tips of Loongson's CPU hotplug: 1, To fully shutdown a core in Loongson 3, the target core should go to CKSEG1 and flush all L1 cache entries at first. Then, another core (usually Core 0) can safely disable the clock of the target core. So play_dead() call loongson3_play_dead() via CKSEG1 (both uncached and unmmaped). 2, The default clocksource of Loongson is MIPS. Since clock source is a global device, timekeeping need the CP0' Count registers of each core be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI to ask Core-0's Count. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/Kconfig | 1 + arch/mips/include/asm/mach-loongson/loongson.h | 6 +- arch/mips/include/asm/smp.h | 1 + arch/mips/loongson/loongson-3/irq.c | 10 ++ arch/mips/loongson/loongson-3/smp.c | 168 +++++++++++++++++++++++- 5 files changed, 181 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5ad608f..c9ebaa5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -273,6 +273,7 @@ config LASAT config MACH_LOONGSON bool "Loongson family of machines" select SYS_SUPPORTS_ZBOOT + select SYS_SUPPORTS_HOTPLUG_CPU help This enables the support of Loongson family of machines. diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 40b4892..d4bae71 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -247,6 +247,9 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) +/* Chip Config */ +#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) + /* pcimap */ #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f @@ -262,9 +265,6 @@ static inline void do_perfcnt_IRQ(void) #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ #include extern struct cpufreq_frequency_table loongson2_clockmod_table[]; - -/* Chip Config */ -#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) #endif /* diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index eb60087..efa02ac 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -42,6 +42,7 @@ extern int __cpu_logical_map[NR_CPUS]; #define SMP_ICACHE_FLUSH 0x4 /* Used by kexec crashdump to save all cpu's state */ #define SMP_DUMP 0x8 +#define SMP_ASK_C0COUNT 0x10 extern volatile cpumask_t cpu_callin_map; diff --git a/arch/mips/loongson/loongson-3/irq.c b/arch/mips/loongson/loongson-3/irq.c index 27aef31..83f84e6 100644 --- a/arch/mips/loongson/loongson-3/irq.c +++ b/arch/mips/loongson/loongson-3/irq.c @@ -85,3 +85,13 @@ void __init mach_init_irq(void) set_c0_status(STATUSF_IP2 | STATUSF_IP6); } + +#ifdef CONFIG_HOTPLUG_CPU + +void fixup_irqs(void) +{ + irq_cpu_offline(); + clear_c0_status(ST0_IM); +} + +#endif diff --git a/arch/mips/loongson/loongson-3/smp.c b/arch/mips/loongson/loongson-3/smp.c index cb996d5..0d61e65 100644 --- a/arch/mips/loongson/loongson-3/smp.c +++ b/arch/mips/loongson/loongson-3/smp.c @@ -30,6 +30,9 @@ #include "smp.h" +DEFINE_PER_CPU(int, cpu_state); +DEFINE_PER_CPU(uint32_t, core0_c0count); + /* read a 64bit value from ipi register */ uint64_t loongson3_ipi_read64(void * addr) { @@ -169,8 +172,8 @@ static void loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int act void loongson3_ipi_interrupt(struct pt_regs *regs) { - int cpu = smp_processor_id(); - unsigned int action; + int i, cpu = smp_processor_id(); + unsigned int action, c0count; /* Load the ipi register to figure out what we're supposed to do */ action = loongson3_ipi_read32(ipi_status0_regs[cpu]); @@ -185,14 +188,24 @@ void loongson3_ipi_interrupt(struct pt_regs *regs) if (action & SMP_CALL_FUNCTION) { smp_call_function_interrupt(); } + + if (action & SMP_ASK_C0COUNT) { + BUG_ON(cpu != 0); + c0count = read_c0_count(); + for (i=1; i < nr_cpus_loongson; i++) + per_cpu(core0_c0count, i) = c0count; + } } +#define MAX_LOOPS 1200 /* * SMP init and finish on secondary CPUs */ void __cpuinit loongson3_init_secondary(void) { int i; + uint32_t initcount; + unsigned int cpu = smp_processor_id(); unsigned int imask = STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP3 | STATUSF_IP2; @@ -202,6 +215,19 @@ void __cpuinit loongson3_init_secondary(void) for (i = 0; i < nr_cpus_loongson; i++) { loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]); } + + per_cpu(cpu_state, cpu) = CPU_ONLINE; + + i = 0; + __get_cpu_var(core0_c0count) = 0; + loongson3_send_ipi_single(0, SMP_ASK_C0COUNT); + while (!__get_cpu_var(core0_c0count)) + i++; + + if (i > MAX_LOOPS) + i = MAX_LOOPS; + initcount = __get_cpu_var(core0_c0count) + i; + write_c0_count(initcount); } void __cpuinit loongson3_smp_finish(void) @@ -235,6 +261,8 @@ void __init loongson3_smp_setup(void) void __init loongson3_prepare_cpus(unsigned int max_cpus) { + init_cpu_present(cpu_possible_mask); + per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; } /* @@ -268,6 +296,138 @@ void __init loongson3_cpus_done(void) { } +#ifdef CONFIG_HOTPLUG_CPU + +extern void fixup_irqs(void); +extern void (*flush_cache_all)(void); + +static int loongson3_cpu_disable(void) +{ + unsigned long flags; + unsigned int cpu = smp_processor_id(); + + if (cpu == 0) + return -EBUSY; + + set_cpu_online(cpu, false); + cpu_clear(cpu, cpu_callin_map); + local_irq_save(flags); + fixup_irqs(); + local_irq_restore(flags); + flush_cache_all(); + local_flush_tlb_all(); + + return 0; +} + + +static void loongson3_cpu_die(unsigned int cpu) +{ + while (per_cpu(cpu_state, cpu) != CPU_DEAD) + cpu_relax(); + + mb(); +} + +/* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and + * flush all L1 entries at first. Then, another core (usually Core 0) can + * safely disable the clock of the target core. loongson3_play_dead() is + * called via CKSEG1 (uncached and unmmaped) */ +void loongson3_play_dead(int *state_addr) +{ + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " li $t0, 0x80000000 \n" /* KSEG0 */ + " li $t1, 512 \n" /* num of L1 entries */ + "1: cache 0, 0($t0) \n" /* flush L1 ICache */ + " cache 0, 1($t0) \n" + " cache 0, 2($t0) \n" + " cache 0, 3($t0) \n" + " cache 1, 0($t0) \n" /* flush L1 DCache */ + " cache 1, 1($t0) \n" + " cache 1, 2($t0) \n" + " cache 1, 3($t0) \n" + " addiu $t0, $t0, 0x20 \n" + " bnez $t1, 1b \n" + " addiu $t1, $t1, -1 \n" + " li $t0, 0x7 \n" /* *state_addr = CPU_DEAD; */ + " sw $t0, 0($a0) \n" + " sync \n" + " cache 21, 0($a0) \n" /* flush entry of *state_addr */ + " .set pop \n"); + + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set mips64 \n" + " mfc0 $t2, $15, 1 \n" + " andi $t2, 0x3ff \n" + " dli $t0, 0x900000003ff01000 \n" + " andi $t3, $t2, 0x3 \n" + " sll $t3, 8 \n" /* get cpu id */ + " or $t0, $t0, $t3 \n" + " andi $t1, $t2, 0xc \n" + " dsll $t1, 42 \n" /* get node id */ + " or $t0, $t0, $t1 \n" + "1: li $a0, 0x100 \n" /* wait for init loop */ + "2: bnez $a0, 2b \n" /* idle loop */ + " addiu $a0, -1 \n" + " lw $v0, 0x20($t0) \n" /* get PC via mailbox */ + " beqz $v0, 1b \n" + " nop \n" + " ld $sp, 0x28($t0) \n" /* get SP via mailbox */ + " ld $gp, 0x30($t0) \n" /* get GP via mailbox */ + " ld $a1, 0x38($t0) \n" + " jr $v0 \n" /* jump to initial PC */ + " nop \n" + " .set pop \n"); +} + +void play_dead(void) +{ + int *state_addr; + unsigned int cpu = smp_processor_id(); + void (*play_dead_at_ckseg1)(int *); + + idle_task_exit(); + play_dead_at_ckseg1 = (void *)CKSEG1ADDR((unsigned long)loongson3_play_dead); + state_addr = &per_cpu(cpu_state, cpu); + mb(); + play_dead_at_ckseg1(state_addr); +} + +#define CPU_POST_DEAD_FROZEN (CPU_POST_DEAD | CPU_TASKS_FROZEN) +static int __cpuinit loongson3_cpu_callback(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + + switch (action) { + case CPU_POST_DEAD: + case CPU_POST_DEAD_FROZEN: + printk(KERN_INFO "Disable clock for CPU#%d\n", cpu); + LOONGSON_CHIPCFG0 &= ~(1 << (12 + cpu)); + break; + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: + printk(KERN_INFO "Enable clock for CPU#%d\n", cpu); + LOONGSON_CHIPCFG0 |= 1 << (12 + cpu); + break; + } + + return NOTIFY_OK; +} + +static int __cpuinit register_loongson3_notifier(void) +{ + hotcpu_notifier(loongson3_cpu_callback, 0); + return 0; +} +early_initcall(register_loongson3_notifier); + +#endif + struct plat_smp_ops loongson3_smp_ops = { .send_ipi_single = loongson3_send_ipi_single, .send_ipi_mask = loongson3_send_ipi_mask, @@ -277,4 +437,8 @@ struct plat_smp_ops loongson3_smp_ops = { .boot_secondary = loongson3_boot_secondary, .smp_setup = loongson3_smp_setup, .prepare_cpus = loongson3_prepare_cpus, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_disable = loongson3_cpu_disable, + .cpu_die = loongson3_cpu_die, +#endif }; -- 1.7.7.3 From chenhuacai@gmail.com Tue Jul 23 09:41:15 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 09:41:20 +0200 (CEST) Received: from mail-pb0-f54.google.com ([209.85.160.54]:63895 "EHLO mail-pb0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6834868Ab3GWHgfnhXT0 (ORCPT ); Tue, 23 Jul 2013 09:36:35 +0200 Received: by mail-pb0-f54.google.com with SMTP id ro2so8083383pbb.41 for ; Tue, 23 Jul 2013 00:36:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Qjt/G2fBZS+qWfSaSlEA7yLE8/J1vgwJdIcodrbf8vo=; b=Zv389m6YL2ffAdUXekEkT03qvx0Qv2HVesVsDgnvHVR2wvGgKWLYOxgCDK9BdzfrwA CGV/+iG3+/BA9SJpwZhyZDxO+T0uGykQ9Kprr6lIBaRxdRhrAONiw+JDJKHBNSnW6IbQ rSGG91J8URKJ4Vz2j3vJRnO6Og0lkfFQFJvmEumeuShHKx4eMg+1VtmqGiH18p57E2x0 pzAAAhX/oGkEB3BE5ly0yNKSCOaPkJEjL8P2vr26jkq6/labdDvd5EPnWWLLVE0CvCYX +rEAqj0VLPoMDoLZ7nSSVr0/17LSqk5ykctO4EQv5gmZoxIjGhxW2f9anvtH25iyC9LH 3Fwg== X-Received: by 10.68.252.169 with SMTP id zt9mr21947999pbc.87.1374564989085; Tue, 23 Jul 2013 00:36:29 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPSA id bb1sm30359772pbc.10.2013.07.23.00.36.23 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 23 Jul 2013 00:36:28 -0700 (PDT) From: Huacai Chen To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V11 13/13] MIPS: Loongson: Add a Loongson-3 default config file Date: Tue, 23 Jul 2013 15:34:13 +0800 Message-Id: <1374564853-10762-14-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1374564853-10762-1-git-send-email-chenhc@lemote.com> References: <1374564853-10762-1-git-send-email-chenhc@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37361 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chenhc@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 9006 Lines: 346 Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/configs/loongson3_defconfig | 329 +++++++++++++++++++++++++++++++++ 1 files changed, 329 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/loongson3_defconfig diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig new file mode 100644 index 0000000..712dd39 --- /dev/null +++ b/arch/mips/configs/loongson3_defconfig @@ -0,0 +1,329 @@ +CONFIG_MACH_LOONGSON=y +CONFIG_LEMOTE_MACH3A=y +CONFIG_LOONGSON_BIGMEM=y +CONFIG_CPU_LOONGSON3=y +CONFIG_64BIT=y +CONFIG_PAGE_SIZE_16KB=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_KSM=y +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +CONFIG_HZ_256=y +CONFIG_PREEMPT=y +CONFIG_KEXEC=y +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZMA=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CPUSETS=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_BLK_CGROUP=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SYSFS_DEPRECATED=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_IOSCHED_DEADLINE=m +CONFIG_CFQ_GROUP_IOSCHED=y +CONFIG_PCI=y +CONFIG_HT_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=m +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM_PERFORMANCE=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_SHPC=m +CONFIG_BINFMT_MISC=m +CONFIG_MIPS32_COMPAT=y +CONFIG_MIPS32_O32=y +CONFIG_MIPS32_N32=y +CONFIG_PM_RUNTIME=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_IP_VS=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_SCTP=m +CONFIG_L2TP=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_RAID_ATTRS=m +CONFIG_SCSI_TGT=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_PATA_ATIIXP=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_NETDEVICES=y +CONFIG_TUN=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FUJITSU is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_IGB=y +# CONFIG_NET_VENDOR_I825XX is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_RACAL is not set +CONFIG_R8169=y +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_TOSHIBA is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_ATH_CARDS=m +CONFIG_ATH9K=m +CONFIG_HOSTAP=m +CONFIG_INPUT_POLLDEV=m +CONFIG_INPUT_SPARSEKMAP=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_XTKBD=m +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_SERIAL=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_RAW=m +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=16 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_HW_RANDOM=y +CONFIG_RAW_DRIVER=m +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_PIIX4=y +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM93=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_DRM=y +CONFIG_DRM_RADEON=y +CONFIG_DRM_RADEON_KMS=y +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB_RADEON=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=m +CONFIG_BACKLIGHT_GENERIC=m +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +# CONFIG_SND_ISA is not set +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_PATCH_LOADER=y +# CONFIG_SND_USB is not set +CONFIG_HID_A4TECH=m +CONFIG_HID_SUNPLUS=m +CONFIG_USB=y +CONFIG_USB_MON=y +CONFIG_USB_XHCI_HCD=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_STORAGE=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_DMADEVICES=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=936 +CONFIG_FAT_DEFAULT_IOCHARSET="gb2312" +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_CIFS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_RCU_CPU_STALL_VERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_DEFLATE=m -- 1.7.7.3 From Markos.Chandras@imgtec.com Tue Jul 23 16:41:14 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 16:41:17 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:13398 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824793Ab3GWOlOImp-I (ORCPT ); Tue, 23 Jul 2013 16:41:14 +0200 From: Markos Chandras To: CC: Markos Chandras Subject: [PATCH] MIPS: Set default CPU type for BCM47XX platforms Date: Tue, 23 Jul 2013 15:40:37 +0100 Message-ID: <1374590437-18150-1-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 1.8.3.2 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.58] X-SEF-Processed: 7_3_0_01192__2013_07_23_15_41_08 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37362 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1196 Lines: 42 If neither BCM47XX_SSD nor BCM47XX_BCMA is selected, then no CPU type is available leading to build problems. We fix this problem by using MIPS32r1 as the default CPU type for the BCM47XX platform. Signed-off-by: Markos Chandras Acked-by: Steven J. Hill --- This patch is for the upstream-sfr/mips-for-linux-next tree --- arch/mips/Kconfig | 1 + arch/mips/bcm47xx/Kconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c3abed3..e12764c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -114,6 +114,7 @@ config BCM47XX select FW_CFE select HW_HAS_PCI select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 select NO_EXCEPT_FILL select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig index ba61192..2b8b118 100644 --- a/arch/mips/bcm47xx/Kconfig +++ b/arch/mips/bcm47xx/Kconfig @@ -2,7 +2,6 @@ if BCM47XX config BCM47XX_SSB bool "SSB Support for Broadcom BCM47XX" - select SYS_HAS_CPU_MIPS32_R1 select SSB select SSB_DRIVER_MIPS select SSB_DRIVER_EXTIF -- 1.8.3.2 From wsa@the-dreams.de Tue Jul 23 20:02:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 20:02:27 +0200 (CEST) Received: from sauhun.de ([89.238.76.85]:44804 "EHLO pokefinder.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827461Ab3GWSCXDMVy0 (ORCPT ); Tue, 23 Jul 2013 20:02:23 +0200 Received: from p5b387ff2.dip0.t-ipconnect.de ([91.56.127.242]:10490 helo=localhost) by pokefinder.org with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.69) (envelope-from ) id 1V1guk-0001Q8-38; Tue, 23 Jul 2013 20:02:22 +0200 From: Wolfram Sang To: linux-kernel@vger.kernel.org Cc: Wolfram Sang , Ralf Baechle , linux-mips@linux-mips.org Subject: [PATCH 01/27] arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource Date: Tue, 23 Jul 2013 20:01:34 +0200 Message-Id: <1374602524-3398-2-git-send-email-wsa@the-dreams.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1374602524-3398-1-git-send-email-wsa@the-dreams.de> References: <1374602524-3398-1-git-send-email-wsa@the-dreams.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37363 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wsa@the-dreams.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 804 Lines: 28 devm_ioremap_resource does sanity checks on the given resource. No need to duplicate this in the driver. Signed-off-by: Wolfram Sang --- Please apply via the subsystem-tree. arch/mips/lantiq/xway/dma.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index 08f7ebd..78a91fa 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -220,10 +220,6 @@ ltq_dma_init(struct platform_device *pdev) int i; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - panic("Failed to get dma resource"); - - /* remap dma register range */ ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(ltq_dma_membase)) panic("Failed to remap dma resource"); -- 1.7.10.4 From wsa@the-dreams.de Tue Jul 23 20:03:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 20:03:25 +0200 (CEST) Received: from sauhun.de ([89.238.76.85]:44858 "EHLO pokefinder.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825727Ab3GWSDXIHjaI (ORCPT ); Tue, 23 Jul 2013 20:03:23 +0200 Received: from p5b387ff2.dip0.t-ipconnect.de ([91.56.127.242]:51467 helo=localhost) by pokefinder.org with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.69) (envelope-from ) id 1V1gud-0001Q5-C2; Tue, 23 Jul 2013 20:02:17 +0200 From: Wolfram Sang To: linux-kernel@vger.kernel.org Cc: Wolfram Sang , alsa-devel@alsa-project.org, Bjorn Helgaas , Daniel Lezcano , Dan Williams , David Woodhouse , devel@driverdev.osuosl.org, Dmitry Torokhov , dri-devel@lists.freedesktop.org, Eduardo Valentin , Eric Miao , Felipe Balbi , Giuseppe Cavallaro , Grant Likely , Greg Kroah-Hartman , Haojian Zhuang , "James E.J. Bottomley" , Jaroslav Kysela , Liam Girdwood , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-input@vger.kernel.org, linux-media@vger.kernel.org, linux-mips@linux-mips.org, linux-mtd@lists.infradead.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-pwm@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-scsi@vger.kernel.org, linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Mark Brown , Mauro Carvalho Chehab , netdev@vger.kernel.org, "Rafael J. Wysocki" , Ralf Baechle , Russell King , Santosh Y , Stephen Warren , Takashi Iwai , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , Thierry Reding , Vinayak Holikatti , Vinod Koul , Wan ZongShun , Wim Van Sebroeck , Zhang Rui Subject: [PATCH 00/27] devm cleanup, part #1, take #3 Date: Tue, 23 Jul 2013 20:01:33 +0200 Message-Id: <1374602524-3398-1-git-send-email-wsa@the-dreams.de> X-Mailer: git-send-email 1.7.10.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37364 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wsa@the-dreams.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 5196 Lines: 95 Here is another bit of cleaning up the devm usage. It is again removing the resource check with devm_ioremap_resource, because a) new drivers came in and b) coccinelle had a bug and missed to find a couple of occasions. Unlike last time, I think it is better if these patches go in via the subsystem trees to reduce merge conflicts. And there is one driver which I fixed manually because the original code needed some bigger update. All is based on v3.11-rc2 and the branch can be found at: git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git devm_no_resource_check Other things which happened: I wanted to get rid of devm_request_and_ioremap, luckily other people are already working on it. Hooray! I already sent a patch series picking another low hanging fruit, i.e. drivers can skip devm_pinctrl handling if they are using only the default pin setup. And not devm related, there is still my proposal to rename INIT_COMPLETION to reinit_completion, that probably needs some more persistence... Yay, so much to clean up \o/ Regards, Wolfram Wolfram Sang (27): arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource drivers/amba: don't check resource with devm_ioremap_resource drivers/cpuidle: don't check resource with devm_ioremap_resource drivers/dma: don't check resource with devm_ioremap_resource drivers/gpu/host1x/drm: don't check resource with devm_ioremap_resource drivers/i2c/busses: don't check resource with devm_ioremap_resource drivers/input/serio: don't check resource with devm_ioremap_resource drivers/iommu: don't check resource with devm_ioremap_resource drivers/media/platform: don't check resource with devm_ioremap_resource drivers/memory: don't check resource with devm_ioremap_resource drivers/mtd/nand: don't check resource with devm_ioremap_resource drivers/net/ethernet/stmicro/stmmac: don't check resource with devm_ioremap_resource drivers/pci/host: don't check resource with devm_ioremap_resource drivers/pinctrl: don't check resource with devm_ioremap_resource drivers/pwm: don't check resource with devm_ioremap_resource drivers/scsi/ufs: don't check resource with devm_ioremap_resource drivers/spi: don't check resource with devm_ioremap_resource drivers/staging/imx-drm: don't check resource with devm_ioremap_resource drivers/usb/phy: don't check resource with devm_ioremap_resource drivers/watchdog: don't check resource with devm_ioremap_resource sound/soc/au1x: don't check resource with devm_ioremap_resource sound/soc/cirrus: don't check resource with devm_ioremap_resource sound/soc/nuc900: don't check resource with devm_ioremap_resource sound/soc/pxa: don't check resource with devm_ioremap_resource sound/soc/tegra: don't check resource with devm_ioremap_resource sound/soc/txx9: don't check resource with devm_ioremap_resource thermal: ti-bandgap: cleanup resource allocation arch/mips/lantiq/xway/dma.c | 4 ---- drivers/amba/tegra-ahb.c | 2 -- drivers/cpuidle/cpuidle-kirkwood.c | 3 --- drivers/dma/mmp_pdma.c | 3 --- drivers/dma/mmp_tdma.c | 3 --- drivers/gpu/host1x/drm/hdmi.c | 3 --- drivers/i2c/busses/i2c-stu300.c | 3 --- drivers/input/serio/olpc_apsp.c | 3 --- drivers/iommu/tegra-smmu.c | 2 -- drivers/media/platform/coda.c | 5 ----- drivers/memory/tegra20-mc.c | 2 -- drivers/memory/tegra30-mc.c | 2 -- drivers/mtd/nand/mxc_nand.c | 5 ----- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 --- drivers/pci/host/pcie-designware.c | 12 ------------ drivers/pinctrl/pinctrl-imx.c | 3 --- drivers/pinctrl/pinctrl-rockchip.c | 5 ----- drivers/pinctrl/pinctrl-u300.c | 3 --- drivers/pwm/pwm-lpc32xx.c | 3 --- drivers/pwm/pwm-renesas-tpu.c | 5 ----- drivers/scsi/ufs/ufshcd-pltfrm.c | 6 ------ drivers/spi/spi-bcm2835.c | 6 ------ drivers/staging/imx-drm/imx-tve.c | 5 ----- drivers/thermal/ti-soc-thermal/ti-bandgap.c | 20 ++++---------------- drivers/usb/phy/phy-rcar-usb.c | 5 ----- drivers/watchdog/nuc900_wdt.c | 5 ----- drivers/watchdog/ts72xx_wdt.c | 10 ---------- sound/soc/au1x/psc-ac97.c | 3 --- sound/soc/cirrus/ep93xx-ac97.c | 3 --- sound/soc/cirrus/ep93xx-i2s.c | 3 --- sound/soc/nuc900/nuc900-ac97.c | 3 --- sound/soc/pxa/mmp-sspa.c | 3 --- sound/soc/tegra/tegra20_ac97.c | 7 ------- sound/soc/txx9/txx9aclc-ac97.c | 3 --- 34 files changed, 4 insertions(+), 152 deletions(-) -- 1.7.10.4 From john@phrozen.org Tue Jul 23 20:08:48 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Jul 2013 20:08:50 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:34719 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827465Ab3GWSIsICHsJ (ORCPT ); Tue, 23 Jul 2013 20:08:48 +0200 Message-ID: <51EEC52E.9020405@phrozen.org> Date: Tue, 23 Jul 2013 20:02:22 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130116 Icedove/10.0.12 MIME-Version: 1.0 To: Wolfram Sang CC: linux-kernel@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 01/27] arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource References: <1374602524-3398-1-git-send-email-wsa@the-dreams.de> <1374602524-3398-2-git-send-email-wsa@the-dreams.de> In-Reply-To: <1374602524-3398-2-git-send-email-wsa@the-dreams.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37365 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 244 Lines: 7 On 23/07/13 20:01, Wolfram Sang wrote: > devm_ioremap_resource does sanity checks on the given resource. No need to > duplicate this in the driver. > > Signed-off-by: Wolfram Sang Acked-by: John Crispin From gregkh@linuxfoundation.org Wed Jul 24 00:28:05 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 24 Jul 2013 00:28:07 +0200 (CEST) Received: from mail.linuxfoundation.org ([140.211.169.12]:43331 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825727Ab3GWW2FMiB9z (ORCPT ); Wed, 24 Jul 2013 00:28:05 +0200 Received: from localhost (c-76-28-172-123.hsd1.wa.comcast.net [76.28.172.123]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id 1F7CDAC3; Tue, 23 Jul 2013 22:27:58 +0000 (UTC) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, David Daney , Ralf Baechle , linux-mips@linux-mips.org Subject: [ 091/103] MIPS: Octeon: Dont clobber bootloader data structures. Date: Tue, 23 Jul 2013 15:26:42 -0700 Message-Id: <20130723220431.420250347@linuxfoundation.org> X-Mailer: git-send-email 1.8.3.rc0.20.gb99dd2e In-Reply-To: <20130723220418.532514378@linuxfoundation.org> References: <20130723220418.532514378@linuxfoundation.org> User-Agent: quilt/0.60-5.1.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37366 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1465 Lines: 42 3.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: David Daney commit d949b4fe6d23dd92b5fa48cbf7af90ca32beed2e upstream. Commit abe77f90dc (MIPS: Octeon: Add kexec and kdump support) added a bootmem region for the kernel image itself. The problem is that this is rounded up to a 0x100000 boundary, which is memory that may not be owned by the kernel. Depending on the kernel's configuration based size, this 'extra' memory may contain data passed from the bootloader to the kernel itself, which if clobbered makes the kernel crash in various ways. The fix: Quit rounding the size up, so that we only use memory assigned to the kernel. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5449/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/cavium-octeon/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -996,7 +996,7 @@ void __init plat_mem_setup(void) cvmx_bootmem_unlock(); /* Add the memory region for the kernel. */ kernel_start = (unsigned long) _text; - kernel_size = ALIGN(_end - _text, 0x100000); + kernel_size = _end - _text; /* Adjust for physical offset. */ kernel_start &= ~0xffffffff80000000ULL; From f.fainelli@gmail.com Wed Jul 24 19:14:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 24 Jul 2013 19:14:45 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:3044 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835041Ab3GXROfCOEiX (ORCPT ); Wed, 24 Jul 2013 19:14:35 +0200 Received: from [10.9.208.57] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 24 Jul 2013 09:08:36 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.438.0; Wed, 24 Jul 2013 09:12:23 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.1.438.0; Wed, 24 Jul 2013 09:12:23 -0700 Received: from fainelli-desktop.broadcom.com ( dhcp-lab-brsb-10.bri.broadcom.com [10.178.7.10]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id A6A85F2D73; Wed, 24 Jul 2013 09:12:22 -0700 (PDT) From: "Florian Fainelli" To: ralf@linux-mips.org cc: linux-mips@linux-mips.org, cernekee@gmail.com, jogo@openwrt.org, blogic@openwrt.org, "Florian Fainelli" Subject: [PATCH 2/2] MIPS: BMIPS: fix slave CPU booting when physical CPU is not 0 Date: Wed, 24 Jul 2013 17:12:11 +0100 Message-ID: <1374682331-14171-3-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1374682331-14171-1-git-send-email-f.fainelli@gmail.com> References: <1374682331-14171-1-git-send-email-f.fainelli@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7DF1238E31W55346927-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37367 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: f.fainelli@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2052 Lines: 57 From: Florian Fainelli The current BMIPS SMP code assumes that the slave CPU is physical and logical CPU 1, but on some systems such as BCM3368, the slave CPU is physical CPU0. Fix the code to read the physical CPU (thread ID) we are running this code on, and adjust the relocation vector address based on it. This allows bringing up the second CPU on BCM3368 for instance. Signed-off-by: Florian Fainelli --- arch/mips/kernel/bmips_vec.S | 6 +++++- arch/mips/kernel/smp-bmips.c | 10 ++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S index f739aed..bd79c4f 100644 --- a/arch/mips/kernel/bmips_vec.S +++ b/arch/mips/kernel/bmips_vec.S @@ -54,7 +54,11 @@ LEAF(bmips_smp_movevec) /* set up CPU1 CBR; move BASE to 0xa000_0000 */ li k0, 0xff400000 mtc0 k0, $22, 6 - li k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1 + /* set up relocation vector address based on thread ID */ + mfc0 k1, $22, 3 + srl k1, 16 + andi k1, 0x8000 + or k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0 or k0, k1 li k1, 0xa0080000 sw k1, 0(k0) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 89417c9..159abc8 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -196,9 +196,15 @@ static void bmips_init_secondary(void) #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) void __iomem *cbr = BMIPS_GET_CBR(); unsigned long old_vec; + unsigned long relo_vector; + int boot_cpu; - old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1); - __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1); + boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); + relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : + BMIPS_RELO_VECTOR_CONTROL_1; + + old_vec = __raw_readl(cbr + relo_vector); + __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); #elif defined(CONFIG_CPU_BMIPS5000) -- 1.8.1.2 From f.fainelli@gmail.com Wed Jul 24 19:15:04 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 24 Jul 2013 19:15:07 +0200 (CEST) Received: from mms1.broadcom.com ([216.31.210.17]:3054 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835046Ab3GXROjlcJ6J (ORCPT ); Wed, 24 Jul 2013 19:14:39 +0200 Received: from [10.9.208.57] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 24 Jul 2013 09:08:34 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.438.0; Wed, 24 Jul 2013 09:12:22 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) with Microsoft SMTP Server id 14.1.438.0; Wed, 24 Jul 2013 09:12:22 -0700 Received: from fainelli-desktop.broadcom.com ( dhcp-lab-brsb-10.bri.broadcom.com [10.178.7.10]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2C753F2D72; Wed, 24 Jul 2013 09:12:20 -0700 (PDT) From: "Florian Fainelli" To: ralf@linux-mips.org cc: linux-mips@linux-mips.org, cernekee@gmail.com, jogo@openwrt.org, blogic@openwrt.org, "Florian Fainelli" Subject: [PATCH 1/2] MIPS: BMIPS: do not change interrupt routing depending on boot CPU Date: Wed, 24 Jul 2013 17:12:10 +0100 Message-ID: <1374682331-14171-2-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1374682331-14171-1-git-send-email-f.fainelli@gmail.com> References: <1374682331-14171-1-git-send-email-f.fainelli@gmail.com> MIME-Version: 1.0 X-WSS-ID: 7DF1238831W55346902-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37368 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: f.fainelli@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1306 Lines: 37 From: Florian Fainelli Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other than 0") changed the interupt routing when we are booting from physical CPU 0, but the settings are actually correct if we are booting from physical CPU 0 or CPU 1. Revert that specific change. Signed-off-by: Florian Fainelli --- arch/mips/kernel/smp-bmips.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index c0bb4d5..89417c9 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -79,15 +79,9 @@ static void __init bmips_smp_setup(void) * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output - * - * If booting from TP1, leave the existing CMT interrupt routing - * such that TP0 responds to SW1 and TP1 responds to SW0. */ - if (boot_cpu == 0) - change_c0_brcm_cmt_intr(0xf8018000, + change_c0_brcm_cmt_intr(0xf8018000, (0x02 << 27) | (0x03 << 15)); - else - change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27)); /* single core, 2 threads (2 pipelines) */ max_cpus = 2; -- 1.8.1.2 From f.fainelli@gmail.com Wed Jul 24 19:15:24 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 24 Jul 2013 19:15:31 +0200 (CEST) Received: from mms3.broadcom.com ([216.31.210.19]:1521 "EHLO mms3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835051Ab3GXROknldt0 (ORCPT ); Wed, 24 Jul 2013 19:14:40 +0200 Received: from [10.9.208.57] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 24 Jul 2013 09:02:37 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.438.0; Wed, 24 Jul 2013 09:12:20 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.1.438.0; Wed, 24 Jul 2013 09:12:19 -0700 Received: from fainelli-desktop.broadcom.com ( dhcp-lab-brsb-10.bri.broadcom.com [10.178.7.10]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id A6590F2D73; Wed, 24 Jul 2013 09:12:18 -0700 (PDT) From: "Florian Fainelli" To: ralf@linux-mips.org cc: linux-mips@linux-mips.org, cernekee@gmail.com, jogo@openwrt.org, blogic@openwrt.org, "Florian Fainelli" Subject: [PATCH 0/2] MIPS: BMIPS: couple of SMP fixes Date: Wed, 24 Jul 2013 17:12:09 +0100 Message-ID: <1374682331-14171-1-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 X-WSS-ID: 7DF125172L851696336-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37369 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: f.fainelli@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 438 Lines: 18 From: Florian Fainelli Ralf, Here are two more BMIPS SMP fixes targetted at 3.11-rcX, thanks! Florian Fainelli (2): MIPS: BMIPS: do not change interrupt routing depending on boot CPU MIPS: BMIPS: fix slave CPU booting when physical CPU is not 0 arch/mips/kernel/bmips_vec.S | 6 +++++- arch/mips/kernel/smp-bmips.c | 18 +++++++++--------- 2 files changed, 14 insertions(+), 10 deletions(-) -- 1.8.1.2 From Steven.Hill@imgtec.com Thu Jul 25 07:40:34 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 25 Jul 2013 07:40:37 +0200 (CEST) Received: from home.bethel-hill.org ([63.228.164.32]:58689 "EHLO home.bethel-hill.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6816841Ab3GYFkeud9ca (ORCPT ); Thu, 25 Jul 2013 07:40:34 +0200 Received: by home.bethel-hill.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1V2EHp-0006wS-WF; Thu, 25 Jul 2013 00:40:26 -0500 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: "Steven J. Hill" , Ralf Baechle , David Daney Subject: [PATCH] MIPS: Octeon: Move declaration of 'fixup_irqs' to common header. Date: Thu, 25 Jul 2013 00:40:17 -0500 Message-Id: <1374730817-9040-1-git-send-email-Steven.Hill@imgtec.com> X-Mailer: git-send-email 1.7.9.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37370 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1082 Lines: 36 To prepare for CPU hotplug of CM-based platforms. Signed-off-by: Steven J. Hill --- arch/mips/cavium-octeon/smp.c | 2 -- arch/mips/include/asm/irq.h | 1 + 2 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 138cc80..a63dbc0 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -255,8 +255,6 @@ static void octeon_cpus_done(void) /* State of each CPU. */ DEFINE_PER_CPU(int, cpu_state); -extern void fixup_irqs(void); - static int octeon_cpu_disable(void) { unsigned int cpu = smp_processor_id(); diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 7bc2cdb..8994ca8 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -126,6 +126,7 @@ extern void do_IRQ_no_affinity(unsigned int irq); extern void arch_init_irq(void); extern void spurious_interrupt(void); +extern void fixup_irqs(void); extern int allocate_irqno(void); extern void alloc_legacy_irqno(void); -- 1.7.2.5 From Markos.Chandras@imgtec.com Thu Jul 25 17:11:38 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 25 Jul 2013 17:11:44 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:48097 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6823013Ab3GYPLiFfUfc (ORCPT ); Thu, 25 Jul 2013 17:11:38 +0200 From: Markos Chandras To: CC: Markos Chandras Subject: [PATCH] MIPS: powertv: Fix arguments for free_reserved_area() Date: Thu, 25 Jul 2013 16:11:28 +0100 Message-ID: <1374765088-27101-1-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 1.8.3.2 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.58] X-SEF-Processed: 7_3_0_01192__2013_07_25_16_11_32 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37371 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markos.chandras@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1292 Lines: 38 Commit 6e7582bf35b8a5a330fd08b398ae445bac86917a "MIPS: PowerTV: use free_reserved_area() to simplify code" merged in 3.11-rc1, broke the build for the powertv defconfig with the following build error: arch/mips/powertv/asic/asic_devices.c: In function 'platform_release_memory': arch/mips/powertv/asic/asic_devices.c:533:7: error: passing argument 1 of 'free_reserved_area' makes pointer from integer without a cast [-Werror] The free_reserved_area() function expects a void * pointer for the start address and a void * pointer for the end one. Signed-off-by: Markos Chandras --- This patch is for the upstream-sfr/mips-for-linux-next tree --- arch/mips/powertv/asic/asic_devices.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c index 9f64c23..0238af1 100644 --- a/arch/mips/powertv/asic/asic_devices.c +++ b/arch/mips/powertv/asic/asic_devices.c @@ -529,8 +529,7 @@ EXPORT_SYMBOL(asic_resource_get); */ void platform_release_memory(void *ptr, int size) { - free_reserved_area((unsigned long)ptr, (unsigned long)(ptr + size), - -1, NULL); + free_reserved_area(ptr, ptr + size, -1, NULL); } EXPORT_SYMBOL(platform_release_memory); -- 1.8.3.2 From amurray@embedded-bits.co.uk Thu Jul 25 18:14:38 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 25 Jul 2013 18:14:40 +0200 (CEST) Received: from mail-wg0-f54.google.com ([74.125.82.54]:60794 "EHLO mail-wg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827441Ab3GYQOiWs3q9 (ORCPT ); Thu, 25 Jul 2013 18:14:38 +0200 Received: by mail-wg0-f54.google.com with SMTP id n12so1817951wgh.21 for ; Thu, 25 Jul 2013 09:14:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=nPASqlh82n6ekLjHgSRC+0KioVg3+SfECVxbprXRgLo=; b=FxZuAmWx2Pvwtjog0BNjz87m9RdVZjbgQa+3RtLRzw5mx23Rmz5zVFXL/zAJzkW71X Nxxr22WvpNYzet/Pce4bo1yxExyBWAe89sFRZhqbRFww4AGiWnHM9vtFNamzOemKQTf9 77rEM6YwrVr9KUycWfXsiRCNpyWRngqAC8UXYWEjlbzSTISFTJGCRdfla58KkblaA/Qg bUASf3rq+DP+6P5a3uvJFVj20hhomwwdIhpRYaVDgP1BDdJSagxmpFl0QygfmO//y949 4N9KSpO31FLQ3NzEl72AjeGFwAINrvavPrpO8PyDb88JhGx/Pm7zV6HIVQVP402coJTL OAqg== X-Received: by 10.194.158.130 with SMTP id wu2mr31682090wjb.12.1374768872807; Thu, 25 Jul 2013 09:14:32 -0700 (PDT) Received: from localhost.localdomain (host-89-242-62-51.as13285.net. [89.242.62.51]) by mx.google.com with ESMTPSA id i1sm4770580wiz.6.2013.07.25.09.14.30 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 25 Jul 2013 09:14:31 -0700 (PDT) From: Andrew Murray To: linux-mips@linux-mips.org Cc: jason@lakedaemon.net, ralf@linux-mips.org, Andrew Murray , Andrew Murray , Liviu Dudau , Gabor Juhos Subject: [PATCH] of/pci: Use of_pci_range_parser Date: Thu, 25 Jul 2013 17:14:25 +0100 Message-Id: <1374768865-23619-1-git-send-email-amurray@embedded-bits.co.uk> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmfvSQe272IPOplFmA+kv3leK740+mKrb9N3iUSKrz+VEIPWdN2TL4IWIOfsJJdNclGeuGy Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37372 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: amurray@embedded-bits.co.uk Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3013 Lines: 99 This patch converts the pci_load_of_ranges function to use the new common of_pci_range_parser. Signed-off-by: Andrew Murray Signed-off-by: Andrew Murray Signed-off-by: Liviu Dudau Signed-off-by: Gabor Juhos Reviewed-by: Rob Herring Reviewed-by: Grant Likely Tested-by: Linus Walleij Acked-by: Ralf Baechle --- This is a resend of the second patch in the of_pci_range_parser patch series [1] rebased for 3.11-rc2. The first patch in the series which this depends on [2] is now in 3.11-rc1. [1] http://patchwork.linux-mips.org/patch/5217/ [2] http://patchwork.linux-mips.org/patch/5218/ --- arch/mips/pci/pci.c | 50 ++++++++++++++++++-------------------------------- 1 file changed, 18 insertions(+), 32 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 594e60d..4f2e17d 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -121,51 +121,37 @@ static void pcibios_scanbus(struct pci_controller *hose) #ifdef CONFIG_OF void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) { - const __be32 *ranges; - int rlen; - int pna = of_n_addr_cells(node); - int np = pna + 5; + struct of_pci_range range; + struct of_pci_range_parser parser; pr_info("PCI host bridge %s ranges:\n", node->full_name); - ranges = of_get_property(node, "ranges", &rlen); - if (ranges == NULL) - return; hose->of_node = node; - while ((rlen -= np * 4) >= 0) { - u32 pci_space; + if (of_pci_range_parser_init(&parser, node)) + return; + + for_each_of_pci_range(&parser, &range) { struct resource *res = NULL; - u64 addr, size; - - pci_space = be32_to_cpup(&ranges[0]); - addr = of_translate_address(node, ranges + 3); - size = of_read_number(ranges + pna + 3, 2); - ranges += np; - switch ((pci_space >> 24) & 0x3) { - case 1: /* PCI IO space */ + + switch (range.flags & IORESOURCE_TYPE_BITS) { + case IORESOURCE_IO: pr_info(" IO 0x%016llx..0x%016llx\n", - addr, addr + size - 1); + range.cpu_addr, + range.cpu_addr + range.size - 1); hose->io_map_base = - (unsigned long)ioremap(addr, size); + (unsigned long)ioremap(range.cpu_addr, + range.size); res = hose->io_resource; - res->flags = IORESOURCE_IO; break; - case 2: /* PCI Memory space */ - case 3: /* PCI 64 bits Memory space */ + case IORESOURCE_MEM: pr_info(" MEM 0x%016llx..0x%016llx\n", - addr, addr + size - 1); + range.cpu_addr, + range.cpu_addr + range.size - 1); res = hose->mem_resource; - res->flags = IORESOURCE_MEM; break; } - if (res != NULL) { - res->start = addr; - res->name = node->full_name; - res->end = res->start + size - 1; - res->parent = NULL; - res->sibling = NULL; - res->child = NULL; - } + if (res != NULL) + of_pci_range_to_resource(&range, node, res); } } -- 1.7.9.5 From ddaney.cavm@gmail.com Thu Jul 25 19:05:12 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 25 Jul 2013 19:05:24 +0200 (CEST) Received: from mail-pa0-f48.google.com ([209.85.220.48]:46789 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825732Ab3GYRFMAl0X4 (ORCPT ); Thu, 25 Jul 2013 19:05:12 +0200 Received: by mail-pa0-f48.google.com with SMTP id kp13so993340pab.7 for ; Thu, 25 Jul 2013 10:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=ycuKg9S4Zo/L1723qFFoJUsuxGdm18LebFBb/3oQbsU=; b=HQRL7T8Dld40JJNO24OGQ0ZXqd3mtYDHv0zLl5/BGAD0xjVGExCXQ5JyqNoZV5VvOT UxKOyXmEhM9LXEDPSv1p5qfiO5Yvqr85KlEsev/Ln4A3vYZW4REIY0WVd9ujqzTxv4KS yhhGuE60YXc4/sJJpvDBqCYA8SbQaZdYyFUA5KESlQnAzStfeAKUFBsO7ZpwTuD//vTp AhwIg6DIDcwK7Wt476xb0IYa1ppiw9m5aTO4A6bvxblb9EFXKzuNatpjUAeXiUYVt+Yj Sm1TBiTq8O0E8zUymAwzPMpiy9B4aleEHKPNUF0nh+GBr4mcfYgvFvwYYqtOyLWMezrA /FJw== X-Received: by 10.66.182.166 with SMTP id ef6mr49308419pac.35.1374771904965; Thu, 25 Jul 2013 10:05:04 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id nm10sm55061839pbc.28.2013.07.25.10.05.02 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 25 Jul 2013 10:05:03 -0700 (PDT) Message-ID: <51F15ABD.4010404@gmail.com> Date: Thu, 25 Jul 2013 10:05:01 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: "Steven J. Hill" , Ralf Baechle CC: linux-mips@linux-mips.org, David Daney Subject: Re: [PATCH] MIPS: Octeon: Move declaration of 'fixup_irqs' to common header. References: <1374730817-9040-1-git-send-email-Steven.Hill@imgtec.com> In-Reply-To: <1374730817-9040-1-git-send-email-Steven.Hill@imgtec.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37373 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1272 Lines: 41 On 07/24/2013 10:40 PM, Steven J. Hill wrote: > To prepare for CPU hotplug of CM-based platforms. > > Signed-off-by: Steven J. Hill It still builds after this, so... Acked-by: David Daney > --- > arch/mips/cavium-octeon/smp.c | 2 -- > arch/mips/include/asm/irq.h | 1 + > 2 files changed, 1 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c > index 138cc80..a63dbc0 100644 > --- a/arch/mips/cavium-octeon/smp.c > +++ b/arch/mips/cavium-octeon/smp.c > @@ -255,8 +255,6 @@ static void octeon_cpus_done(void) > /* State of each CPU. */ > DEFINE_PER_CPU(int, cpu_state); > > -extern void fixup_irqs(void); > - > static int octeon_cpu_disable(void) > { > unsigned int cpu = smp_processor_id(); > diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h > index 7bc2cdb..8994ca8 100644 > --- a/arch/mips/include/asm/irq.h > +++ b/arch/mips/include/asm/irq.h > @@ -126,6 +126,7 @@ extern void do_IRQ_no_affinity(unsigned int irq); > > extern void arch_init_irq(void); > extern void spurious_interrupt(void); > +extern void fixup_irqs(void); > > extern int allocate_irqno(void); > extern void alloc_legacy_irqno(void); > From aaro.koskinen@iki.fi Thu Jul 25 19:29:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 25 Jul 2013 19:29:26 +0200 (CEST) Received: from filtteri5.pp.htv.fi ([213.243.153.188]:35020 "EHLO filtteri5.pp.htv.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827441Ab3GYR3XmjtYR (ORCPT ); Thu, 25 Jul 2013 19:29:23 +0200 Received: from localhost (localhost [127.0.0.1]) by filtteri5.pp.htv.fi (Postfix) with ESMTP id D6E525A6DAF; Thu, 25 Jul 2013 20:29:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at pp.htv.fi Received: from smtp4.welho.com ([213.243.153.38]) by localhost (filtteri5.pp.htv.fi [213.243.153.188]) (amavisd-new, port 10024) with ESMTP id Aor6W0LK5Te3; Thu, 25 Jul 2013 20:29:18 +0300 (EEST) Received: from blackmetal.pp.htv.fi (cs181064211.pp.htv.fi [82.181.64.211]) by smtp4.welho.com (Postfix) with ESMTP id 8E8195BC012; Thu, 25 Jul 2013 20:29:18 +0300 (EEST) From: Aaro Koskinen To: Ralf Baechle , David Daney , Faidon Liambotis , linux-mips@linux-mips.org Cc: Aaro Koskinen Subject: [PATCH v3] MIPS: cavium-octeon: fix I/O space setup on non-PCI systems Date: Thu, 25 Jul 2013 20:26:48 +0300 Message-Id: <1374773208-2827-1-git-send-email-aaro.koskinen@iki.fi> X-Mailer: git-send-email 1.8.3.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37374 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aaro.koskinen@iki.fi Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3153 Lines: 96 Fix I/O space setup, so that on non-PCI systems using inb()/outb() won't crash the system. Some drivers may try to probe I/O space and for that purpose we can just allocate some normal memory initially. Drivers trying to reserve a region will fail early as we set the size to 0. If a real I/O space is present, the PCI/PCIe support code will re-adjust the values accordingly. Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused the originally reported crash. Reported-by: Faidon Liambotis Signed-off-by: Aaro Koskinen Acked-by: David Daney --- v3: Move octeon_no_pci_init() to core_initcall (http://marc.info/?t=137452306500001&r=1&w=2). v2: Address the issues found from the first version of the patch (http://marc.info/?t=137434204000002&r=1&w=2). arch/mips/cavium-octeon/setup.c | 28 ++++++++++++++++++++++++++++ arch/mips/pci/pci-octeon.c | 9 +++++---- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 48b08eb..b212ae1 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -8,6 +8,7 @@ * written by Ralf Baechle */ #include +#include #include #include #include @@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) return err; } device_initcall(edac_devinit); + +static void __initdata *octeon_dummy_iospace; + +static int __init octeon_no_pci_init(void) +{ + /* + * Initially assume there is no PCI. The PCI/PCIe platform code will + * later re-initialize these to correct values if they are present. + */ + octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); + set_io_port_base((unsigned long)octeon_dummy_iospace); + ioport_resource.start = MAX_RESOURCE; + ioport_resource.end = 0; + return 0; +} +core_initcall(octeon_no_pci_init); + +static int __init octeon_no_pci_release(void) +{ + /* + * Release the allocated memory if a real IO space is there. + */ + if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) + vfree(octeon_dummy_iospace); + return 0; +} +late_initcall(octeon_no_pci_release); diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 95c2ea8..59cccd9 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -586,15 +586,16 @@ static int __init octeon_pci_setup(void) else octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; - /* PCI I/O and PCI MEM values */ - set_io_port_base(OCTEON_PCI_IOSPACE_BASE); - ioport_resource.start = 0; - ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; if (!octeon_is_pci_host()) { pr_notice("Not in host mode, PCI Controller not initialized\n"); return 0; } + /* PCI I/O and PCI MEM values */ + set_io_port_base(OCTEON_PCI_IOSPACE_BASE); + ioport_resource.start = 0; + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; + pr_notice("%s Octeon big bar support\n", (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); -- 1.8.3.2 From thierry.reding@gmail.com Thu Jul 25 20:38:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 25 Jul 2013 20:38:23 +0200 (CEST) Received: from mail-bk0-f49.google.com ([209.85.214.49]:47997 "EHLO mail-bk0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825732Ab3GYSiKQLaQZ (ORCPT ); Thu, 25 Jul 2013 20:38:10 +0200 Received: by mail-bk0-f49.google.com with SMTP id r7so444353bkg.22 for ; Thu, 25 Jul 2013 11:38:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=nFMy1r3GQVgAlHgbiSUOG5Eq5Iz8v6jRsNbHRa911FI=; b=yzmciiWujY0ChSO8QpxT3TmWJX1rtnjTN7mNJkXE4Ku59TyEbc8p7xtjNKCdEecKsp df4xNtMa4jJ+Mn5yzVep56TidBLMNLeO7vS81Pica1ITGhAWYGljnT0fbc/QNar3bMHZ LjXjk9F8LIiIncEuzH32H0mflxXDm9R/dhKMVo6qYmoEbtsl8yXEy3noW+cV5dzbEZod jzIyoxoZpH2LKuJnf69ZwJoGqn21V4jb/wMjsCFy7Np6YL1UJ3Pu7/RN6Zf49UCjljhe vnUleY/vsacoYnFKzftYAjxk5+Ty+/WHbYYmTq/Lo8QSEmVe8Mk4ChPZnAG7LHCnoRLG Nwng== X-Received: by 10.204.73.2 with SMTP id o2mr6608969bkj.143.1374777484761; Thu, 25 Jul 2013 11:38:04 -0700 (PDT) Received: from localhost (dotsec.net. [62.75.224.215]) by mx.google.com with ESMTPSA id cb7sm11551320bkb.16.2013.07.25.11.37.56 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 25 Jul 2013 11:38:03 -0700 (PDT) Date: Thu, 25 Jul 2013 11:37:54 -0700 From: Thierry Reding To: Bjorn Helgaas Cc: Thomas Petazzoni , linux-pci@vger.kernel.org, Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Maen Suleiman , Lior Amsalem , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Subject: Re: [PATCHv5 02/11] PCI: use weak functions for MSI arch-specific functions Message-ID: <20130725183752.GA18584@dhcp-172-17-186-34.nvidia.com> References: <1373889167-27878-1-git-send-email-thomas.petazzoni@free-electrons.com> <1373889167-27878-3-git-send-email-thomas.petazzoni@free-electrons.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="UlVJffcvxoiEqYs2" Content-Disposition: inline In-Reply-To: <1373889167-27878-3-git-send-email-thomas.petazzoni@free-electrons.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37375 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 11066 Lines: 322 --UlVJffcvxoiEqYs2 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jul 15, 2013 at 01:52:38PM +0200, Thomas Petazzoni wrote: > Until now, the MSI architecture-specific functions could be overloaded > using a fairly complex set of #define and compile-time > conditionals. In order to prepare for the introduction of the msi_chip > infrastructure, it is desirable to switch all those functions to use > the 'weak' mechanism. This commit converts all the architectures that > were overidding those MSI functions to use the new strategy. >=20 > Note that we keep a separate, non-weak, function > default_teardown_msi_irqs() for the default behavior of the > arch_teardown_msi_irqs(), as the default behavior is needed by the Xen > x86 PCI code. >=20 > Signed-off-by: Thomas Petazzoni > Cc: Benjamin Herrenschmidt > Cc: Paul Mackerras > Cc: linuxppc-dev@lists.ozlabs.org > Cc: Martin Schwidefsky > Cc: Heiko Carstens > Cc: linux390@de.ibm.com > Cc: linux-s390@vger.kernel.org > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: H. Peter Anvin > Cc: x86@kernel.org > Cc: Russell King > Cc: Tony Luck > Cc: Fenghua Yu > Cc: linux-ia64@vger.kernel.org > Cc: Ralf Baechle > Cc: linux-mips@linux-mips.org > Cc: David S. Miller > Cc: sparclinux@vger.kernel.org > Cc: Chris Metcalf > --- > arch/mips/include/asm/pci.h | 5 ----- > arch/powerpc/include/asm/pci.h | 5 ----- > arch/s390/include/asm/pci.h | 4 ---- > arch/x86/include/asm/pci.h | 28 -------------------------- > arch/x86/kernel/x86_init.c | 21 ++++++++++++++++++++ > drivers/pci/msi.c | 45 +++++++++++++++++++-----------------= ------ > include/linux/msi.h | 7 ++++++- > 7 files changed, 47 insertions(+), 68 deletions(-) Bjorn, any chance that we can get your Acked-by on this? Thierry >=20 > diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h > index fa8e0aa..f194c08 100644 > --- a/arch/mips/include/asm/pci.h > +++ b/arch/mips/include/asm/pci.h > @@ -136,11 +136,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_= dev *dev, int channel) > return channel ? 15 : 14; > } > =20 > -#ifdef CONFIG_CPU_CAVIUM_OCTEON > -/* MSI arch hook for OCTEON */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#endif > - > extern char * (*pcibios_plat_setup)(char *str); > =20 > #ifdef CONFIG_OF > diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pc= i.h > index 6653f27..95145a1 100644 > --- a/arch/powerpc/include/asm/pci.h > +++ b/arch/powerpc/include/asm/pci.h > @@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus); > /* Decide whether to display the domain number in /proc */ > extern int pci_proc_domain(struct pci_bus *bus); > =20 > -/* MSI arch hooks */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#define arch_teardown_msi_irqs arch_teardown_msi_irqs > -#define arch_msi_check_device arch_msi_check_device > - > struct vm_area_struct; > /* Map a range of PCI memory or I/O space for a device into user space */ > int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, > diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h > index 6e577ba..262b91b 100644 > --- a/arch/s390/include/asm/pci.h > +++ b/arch/s390/include/asm/pci.h > @@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *); > int pci_domain_nr(struct pci_bus *); > int pci_proc_domain(struct pci_bus *); > =20 > -/* MSI arch hooks */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#define arch_teardown_msi_irqs arch_teardown_msi_irqs > - > #define ZPCI_BUS_NR 0 /* default bus number */ > #define ZPCI_DEVFN 0 /* default device number */ > =20 > diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h > index d9e9e6c..8c61de0 100644 > --- a/arch/x86/include/asm/pci.h > +++ b/arch/x86/include/asm/pci.h > @@ -100,29 +100,6 @@ static inline void early_quirks(void) { } > extern void pci_iommu_alloc(void); > =20 > #ifdef CONFIG_PCI_MSI > -/* MSI arch specific hooks */ > -static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int = type) > -{ > - return x86_msi.setup_msi_irqs(dev, nvec, type); > -} > - > -static inline void x86_teardown_msi_irqs(struct pci_dev *dev) > -{ > - x86_msi.teardown_msi_irqs(dev); > -} > - > -static inline void x86_teardown_msi_irq(unsigned int irq) > -{ > - x86_msi.teardown_msi_irq(irq); > -} > -static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq) > -{ > - x86_msi.restore_msi_irqs(dev, irq); > -} > -#define arch_setup_msi_irqs x86_setup_msi_irqs > -#define arch_teardown_msi_irqs x86_teardown_msi_irqs > -#define arch_teardown_msi_irq x86_teardown_msi_irq > -#define arch_restore_msi_irqs x86_restore_msi_irqs > /* implemented in arch/x86/kernel/apic/io_apic. */ > struct msi_desc; > int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); > @@ -130,11 +107,6 @@ void native_teardown_msi_irq(unsigned int irq); > void native_restore_msi_irqs(struct pci_dev *dev, int irq); > int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, > unsigned int irq_base, unsigned int irq_offset); > -/* default to the implementation in drivers/lib/msi.c */ > -#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS > -#define HAVE_DEFAULT_MSI_RESTORE_IRQS > -void default_teardown_msi_irqs(struct pci_dev *dev); > -void default_restore_msi_irqs(struct pci_dev *dev, int irq); > #else > #define native_setup_msi_irqs NULL > #define native_teardown_msi_irq NULL > diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c > index 45a14db..a2b189c 100644 > --- a/arch/x86/kernel/x86_init.c > +++ b/arch/x86/kernel/x86_init.c > @@ -116,6 +116,27 @@ struct x86_msi_ops x86_msi =3D { > .setup_hpet_msi =3D default_setup_hpet_msi, > }; > =20 > +/* MSI arch specific hooks */ > +int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > +{ > + return x86_msi.setup_msi_irqs(dev, nvec, type); > +} > + > +void arch_teardown_msi_irqs(struct pci_dev *dev) > +{ > + x86_msi.teardown_msi_irqs(dev); > +} > + > +void arch_teardown_msi_irq(unsigned int irq) > +{ > + x86_msi.teardown_msi_irq(irq); > +} > + > +void arch_restore_msi_irqs(struct pci_dev *dev, int irq) > +{ > + x86_msi.restore_msi_irqs(dev, irq); > +} > + > struct x86_io_apic_ops x86_io_apic_ops =3D { > .init =3D native_io_apic_init_mappings, > .read =3D native_io_apic_read, > diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c > index aca7578..aa2f697 100644 > --- a/drivers/pci/msi.c > +++ b/drivers/pci/msi.c > @@ -30,20 +30,21 @@ static int pci_msi_enable =3D 1; > =20 > /* Arch hooks */ > =20 > -#ifndef arch_msi_check_device > -int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) > +int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) > { > - return 0; > + return -EINVAL; > } > -#endif > =20 > -#ifndef arch_setup_msi_irqs > -# define arch_setup_msi_irqs default_setup_msi_irqs > -# define HAVE_DEFAULT_MSI_SETUP_IRQS > -#endif > +void __weak arch_teardown_msi_irq(unsigned int irq) > +{ > +} > =20 > -#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS > -int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > +int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) > +{ > + return 0; > +} > + > +int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > { > struct msi_desc *entry; > int ret; > @@ -65,14 +66,11 @@ int default_setup_msi_irqs(struct pci_dev *dev, int n= vec, int type) > =20 > return 0; > } > -#endif > =20 > -#ifndef arch_teardown_msi_irqs > -# define arch_teardown_msi_irqs default_teardown_msi_irqs > -# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS > -#endif > - > -#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS > +/* > + * We have a default implementation available as a separate non-weak > + * function, as it is used by the Xen x86 PCI code > + */ > void default_teardown_msi_irqs(struct pci_dev *dev) > { > struct msi_desc *entry; > @@ -89,15 +87,13 @@ void default_teardown_msi_irqs(struct pci_dev *dev) > arch_teardown_msi_irq(entry->irq + i); > } > } > -#endif > =20 > -#ifndef arch_restore_msi_irqs > -# define arch_restore_msi_irqs default_restore_msi_irqs > -# define HAVE_DEFAULT_MSI_RESTORE_IRQS > -#endif > +void __weak arch_teardown_msi_irqs(struct pci_dev *dev) > +{ > + return default_teardown_msi_irqs(dev); > +} > =20 > -#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS > -void default_restore_msi_irqs(struct pci_dev *dev, int irq) > +void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq) > { > struct msi_desc *entry; > =20 > @@ -114,7 +110,6 @@ void default_restore_msi_irqs(struct pci_dev *dev, in= t irq) > if (entry) > write_msi_msg(irq, &entry->msg); > } > -#endif > =20 > static void msi_set_enable(struct pci_dev *dev, int enable) > { > diff --git a/include/linux/msi.h b/include/linux/msi.h > index ee66f3a..18870b0 100644 > --- a/include/linux/msi.h > +++ b/include/linux/msi.h > @@ -51,12 +51,17 @@ struct msi_desc { > }; > =20 > /* > - * The arch hook for setup up msi irqs > + * The arch hooks to setup up msi irqs. Those functions are > + * implemented as weak symbols so that they /can/ be overriden by > + * architecture specific code if needed. > */ > int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); > void arch_teardown_msi_irq(unsigned int irq); > int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); > void arch_teardown_msi_irqs(struct pci_dev *dev); > int arch_msi_check_device(struct pci_dev* dev, int nvec, int type); > +void arch_restore_msi_irqs(struct pci_dev *dev, int irq); > + > +void default_teardown_msi_irqs(struct pci_dev *dev); > =20 > #endif /* LINUX_MSI_H */ > --=20 > 1.8.1.2 >=20 --UlVJffcvxoiEqYs2 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJR8XCAAAoJEN0jrNd/PrOhc4IP/ReCIiTdM/QpDygqfxxQ8A/V 1PX/w19tIcUH8ZUhu53XAbjGwK+fN7ANuQInKersQeWfu2rjvoaPi4nxuLBkoFwg aTsdyawR1xlHKgwJFfXgnbCdDmoJ4m5vp7Fh+9drcsnWGBxCBq4dFxeTGcRJnooh F7yAGnt3aPCGsG0hOPfEVBjvH0I0vj8XB8At7nX0LZXGSUQbIGRj8CtVqITkFAZB bfUA0B1O2+PqwtYaO5oSkfmcYW04jBJ6Y9eX2etd5uyQzBl65nYZiwmVoeDfagJf 3Djg5+33jVA8k1UIx26A1y4MYOCZM5rZN7A89UzuN3vl9FEUc2HyRkTg0zmVtIfZ LUoapqX8CzUsqW2uxmhUpQLwopXsFn6KYPWjFGHIfxHfAV+f1AAE3c7mBodRwJLr WDvIFDUANldpylzr9ln97q22MCRZoPqSnNHQj3lkJhOQFu8AhrxdPWHC6NZx5jdx +WDVU9clw5M1ZPidH8Yqn/rFt+UiDTW9jcRdZRZXbn4XCQQGAyFkOof63NU2N+w7 HAPV2Xs8qrsEzUAviPqRHFLY5SOLcYNfDLX4XLczIvvp/p+WsY0cX0K4VyWi8CWt q0TyUOfBA9i6Aoz+uVDKRTFHbIndDPRWISRH5FGEr86BLBdGyw2xupKvDsQOrOQM ObJh9T/Vi3CgYzhO0Hcc =CAXR -----END PGP SIGNATURE----- --UlVJffcvxoiEqYs2-- From bhelgaas@google.com Thu Jul 25 22:27:43 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 25 Jul 2013 22:27:46 +0200 (CEST) Received: from mail-oa0-f50.google.com ([209.85.219.50]:47495 "EHLO mail-oa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827499Ab3GYU1nFz4-J (ORCPT ); Thu, 25 Jul 2013 22:27:43 +0200 Received: by mail-oa0-f50.google.com with SMTP id k7so5504472oag.37 for ; Thu, 25 Jul 2013 13:27:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=JD73KBRIguZxtZypW3GMOCBzoYrYJvBWKHcKYT+wQKw=; b=Y3QhuGRkHGk9UeFRImrxi1/D48oy8/nL5pvQde8KRk9TX5ErqzADyZFpxkCDKKGd/s EYh+EiXXoCH5Lmvy1tAdnZjof2RtMLxl2utSn3rxMcGMNZ52kV8Fit8JNhj4cZWY1mKP yzonyI1zawGbcxodV95Niwv/HNravaiZqKnXHTTCbjgLQ35IFQFY4pGpxpyStfwdI4/H MEM0Tq2OBGeYtXMYsOnJfZzmGWeLxWRI+S+6pH0wtDupodLBAAHNS/3PU4yMcQ9NJmFC gWECmxuHdSM2Bo3WhMX7IQdVjiQeoFxYsuFpvPUJHNWFOqr7SMvPUem1zNbLPdJ1dbRJ TM4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=JD73KBRIguZxtZypW3GMOCBzoYrYJvBWKHcKYT+wQKw=; b=ZSBsTRBh3xspx5vhCOSqAEltWQQHO8naaQAdHArIaA95Yt/A+EZ6BfO0lzLQrGkW14 KJ8RkdzSnOLKmUxs5VhAyFGkklHtg7FU3NR5lfmoua6WcYe3pL9rmK3uIcfZQVB/EscY kJG2ZEx7FP2SwwXtWzyaWO31GsyvwxdrbhKYSnMbGxV5r7IJPsqo9BVigFEle5Ua7t4J SSmcVUUnNchuhfvwOd6HkDqQlnCH0VOMET/X7bnAELoS0SZ6KnwU0Lus9kVp4xL4qAo1 OZ6xM9WVA62ANxoSQMfWRh59zWSO462nMIaVdsqQHpUzzJvDPs78OmXmscXeclnVI/bb QZKA== X-Received: by 10.42.158.9 with SMTP id f9mr19877472icx.111.1374784056137; Thu, 25 Jul 2013 13:27:36 -0700 (PDT) MIME-Version: 1.0 Received: by 10.64.22.227 with HTTP; Thu, 25 Jul 2013 13:27:15 -0700 (PDT) In-Reply-To: <1373889167-27878-3-git-send-email-thomas.petazzoni@free-electrons.com> References: <1373889167-27878-1-git-send-email-thomas.petazzoni@free-electrons.com> <1373889167-27878-3-git-send-email-thomas.petazzoni@free-electrons.com> From: Bjorn Helgaas Date: Thu, 25 Jul 2013 14:27:15 -0600 Message-ID: Subject: Re: [PATCHv5 02/11] PCI: use weak functions for MSI arch-specific functions To: Thomas Petazzoni Cc: "linux-pci@vger.kernel.org" , Russell King , Grant Likely , Rob Herring , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Ezequiel Garcia , linux-arm , Maen Suleiman , Lior Amsalem , Thierry Reding , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , "x86@kernel.org" , Tony Luck , Fenghua Yu , "linux-ia64@vger.kernel.org" , Ralf Baechle , "linux-mips@linux-mips.org" , "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf Content-Type: text/plain; charset=ISO-8859-1 X-Gm-Message-State: ALoCoQmu5VWcU/AyL7ilHydAdk0fzUDcRYN8c38VVmYUpEh5WYG4SVxSWPUBf+aRVOHKzSVX+k24r1UY06BkVUDodDqv/O8sq47io4CAL3m4pPQv6wh1UCxe4G3PxUCEXkd78YuGyJ3Ra3WU8fCHnVF5s0zibQKCFJxz2Unx0BXNiJmIcupYAxxXVnKVff2Rtp5PCzHQzILO0b1Fo1ontFMSXZAldDJbMw== Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37376 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bhelgaas@google.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 10138 Lines: 283 On Mon, Jul 15, 2013 at 5:52 AM, Thomas Petazzoni wrote: > Until now, the MSI architecture-specific functions could be overloaded > using a fairly complex set of #define and compile-time > conditionals. In order to prepare for the introduction of the msi_chip > infrastructure, it is desirable to switch all those functions to use > the 'weak' mechanism. This commit converts all the architectures that > were overidding those MSI functions to use the new strategy. > > Note that we keep a separate, non-weak, function > default_teardown_msi_irqs() for the default behavior of the > arch_teardown_msi_irqs(), as the default behavior is needed by the Xen > x86 PCI code. > > Signed-off-by: Thomas Petazzoni > Cc: Benjamin Herrenschmidt > Cc: Paul Mackerras > Cc: linuxppc-dev@lists.ozlabs.org > Cc: Martin Schwidefsky > Cc: Heiko Carstens > Cc: linux390@de.ibm.com > Cc: linux-s390@vger.kernel.org > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: H. Peter Anvin > Cc: x86@kernel.org > Cc: Russell King > Cc: Tony Luck > Cc: Fenghua Yu > Cc: linux-ia64@vger.kernel.org > Cc: Ralf Baechle > Cc: linux-mips@linux-mips.org > Cc: David S. Miller > Cc: sparclinux@vger.kernel.org > Cc: Chris Metcalf Acked-by: Bjorn Helgaas > --- > arch/mips/include/asm/pci.h | 5 ----- > arch/powerpc/include/asm/pci.h | 5 ----- > arch/s390/include/asm/pci.h | 4 ---- > arch/x86/include/asm/pci.h | 28 -------------------------- > arch/x86/kernel/x86_init.c | 21 ++++++++++++++++++++ > drivers/pci/msi.c | 45 +++++++++++++++++++----------------------- > include/linux/msi.h | 7 ++++++- > 7 files changed, 47 insertions(+), 68 deletions(-) > > diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h > index fa8e0aa..f194c08 100644 > --- a/arch/mips/include/asm/pci.h > +++ b/arch/mips/include/asm/pci.h > @@ -136,11 +136,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) > return channel ? 15 : 14; > } > > -#ifdef CONFIG_CPU_CAVIUM_OCTEON > -/* MSI arch hook for OCTEON */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#endif > - > extern char * (*pcibios_plat_setup)(char *str); > > #ifdef CONFIG_OF > diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h > index 6653f27..95145a1 100644 > --- a/arch/powerpc/include/asm/pci.h > +++ b/arch/powerpc/include/asm/pci.h > @@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus); > /* Decide whether to display the domain number in /proc */ > extern int pci_proc_domain(struct pci_bus *bus); > > -/* MSI arch hooks */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#define arch_teardown_msi_irqs arch_teardown_msi_irqs > -#define arch_msi_check_device arch_msi_check_device > - > struct vm_area_struct; > /* Map a range of PCI memory or I/O space for a device into user space */ > int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, > diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h > index 6e577ba..262b91b 100644 > --- a/arch/s390/include/asm/pci.h > +++ b/arch/s390/include/asm/pci.h > @@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *); > int pci_domain_nr(struct pci_bus *); > int pci_proc_domain(struct pci_bus *); > > -/* MSI arch hooks */ > -#define arch_setup_msi_irqs arch_setup_msi_irqs > -#define arch_teardown_msi_irqs arch_teardown_msi_irqs > - > #define ZPCI_BUS_NR 0 /* default bus number */ > #define ZPCI_DEVFN 0 /* default device number */ > > diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h > index d9e9e6c..8c61de0 100644 > --- a/arch/x86/include/asm/pci.h > +++ b/arch/x86/include/asm/pci.h > @@ -100,29 +100,6 @@ static inline void early_quirks(void) { } > extern void pci_iommu_alloc(void); > > #ifdef CONFIG_PCI_MSI > -/* MSI arch specific hooks */ > -static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > -{ > - return x86_msi.setup_msi_irqs(dev, nvec, type); > -} > - > -static inline void x86_teardown_msi_irqs(struct pci_dev *dev) > -{ > - x86_msi.teardown_msi_irqs(dev); > -} > - > -static inline void x86_teardown_msi_irq(unsigned int irq) > -{ > - x86_msi.teardown_msi_irq(irq); > -} > -static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq) > -{ > - x86_msi.restore_msi_irqs(dev, irq); > -} > -#define arch_setup_msi_irqs x86_setup_msi_irqs > -#define arch_teardown_msi_irqs x86_teardown_msi_irqs > -#define arch_teardown_msi_irq x86_teardown_msi_irq > -#define arch_restore_msi_irqs x86_restore_msi_irqs > /* implemented in arch/x86/kernel/apic/io_apic. */ > struct msi_desc; > int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); > @@ -130,11 +107,6 @@ void native_teardown_msi_irq(unsigned int irq); > void native_restore_msi_irqs(struct pci_dev *dev, int irq); > int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, > unsigned int irq_base, unsigned int irq_offset); > -/* default to the implementation in drivers/lib/msi.c */ > -#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS > -#define HAVE_DEFAULT_MSI_RESTORE_IRQS > -void default_teardown_msi_irqs(struct pci_dev *dev); > -void default_restore_msi_irqs(struct pci_dev *dev, int irq); > #else > #define native_setup_msi_irqs NULL > #define native_teardown_msi_irq NULL > diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c > index 45a14db..a2b189c 100644 > --- a/arch/x86/kernel/x86_init.c > +++ b/arch/x86/kernel/x86_init.c > @@ -116,6 +116,27 @@ struct x86_msi_ops x86_msi = { > .setup_hpet_msi = default_setup_hpet_msi, > }; > > +/* MSI arch specific hooks */ > +int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > +{ > + return x86_msi.setup_msi_irqs(dev, nvec, type); > +} > + > +void arch_teardown_msi_irqs(struct pci_dev *dev) > +{ > + x86_msi.teardown_msi_irqs(dev); > +} > + > +void arch_teardown_msi_irq(unsigned int irq) > +{ > + x86_msi.teardown_msi_irq(irq); > +} > + > +void arch_restore_msi_irqs(struct pci_dev *dev, int irq) > +{ > + x86_msi.restore_msi_irqs(dev, irq); > +} > + > struct x86_io_apic_ops x86_io_apic_ops = { > .init = native_io_apic_init_mappings, > .read = native_io_apic_read, > diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c > index aca7578..aa2f697 100644 > --- a/drivers/pci/msi.c > +++ b/drivers/pci/msi.c > @@ -30,20 +30,21 @@ static int pci_msi_enable = 1; > > /* Arch hooks */ > > -#ifndef arch_msi_check_device > -int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) > +int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) > { > - return 0; > + return -EINVAL; > } > -#endif > > -#ifndef arch_setup_msi_irqs > -# define arch_setup_msi_irqs default_setup_msi_irqs > -# define HAVE_DEFAULT_MSI_SETUP_IRQS > -#endif > +void __weak arch_teardown_msi_irq(unsigned int irq) > +{ > +} > > -#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS > -int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > +int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) > +{ > + return 0; > +} > + > +int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > { > struct msi_desc *entry; > int ret; > @@ -65,14 +66,11 @@ int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > > return 0; > } > -#endif > > -#ifndef arch_teardown_msi_irqs > -# define arch_teardown_msi_irqs default_teardown_msi_irqs > -# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS > -#endif > - > -#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS > +/* > + * We have a default implementation available as a separate non-weak > + * function, as it is used by the Xen x86 PCI code > + */ > void default_teardown_msi_irqs(struct pci_dev *dev) > { > struct msi_desc *entry; > @@ -89,15 +87,13 @@ void default_teardown_msi_irqs(struct pci_dev *dev) > arch_teardown_msi_irq(entry->irq + i); > } > } > -#endif > > -#ifndef arch_restore_msi_irqs > -# define arch_restore_msi_irqs default_restore_msi_irqs > -# define HAVE_DEFAULT_MSI_RESTORE_IRQS > -#endif > +void __weak arch_teardown_msi_irqs(struct pci_dev *dev) > +{ > + return default_teardown_msi_irqs(dev); > +} > > -#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS > -void default_restore_msi_irqs(struct pci_dev *dev, int irq) > +void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq) > { > struct msi_desc *entry; > > @@ -114,7 +110,6 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq) > if (entry) > write_msi_msg(irq, &entry->msg); > } > -#endif > > static void msi_set_enable(struct pci_dev *dev, int enable) > { > diff --git a/include/linux/msi.h b/include/linux/msi.h > index ee66f3a..18870b0 100644 > --- a/include/linux/msi.h > +++ b/include/linux/msi.h > @@ -51,12 +51,17 @@ struct msi_desc { > }; > > /* > - * The arch hook for setup up msi irqs > + * The arch hooks to setup up msi irqs. Those functions are > + * implemented as weak symbols so that they /can/ be overriden by > + * architecture specific code if needed. > */ > int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); > void arch_teardown_msi_irq(unsigned int irq); > int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); > void arch_teardown_msi_irqs(struct pci_dev *dev); > int arch_msi_check_device(struct pci_dev* dev, int nvec, int type); > +void arch_restore_msi_irqs(struct pci_dev *dev, int irq); > + > +void default_teardown_msi_irqs(struct pci_dev *dev); > > #endif /* LINUX_MSI_H */ > -- > 1.8.1.2 > From alexj@rosedu.org Fri Jul 26 16:04:06 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 26 Jul 2013 16:04:12 +0200 (CEST) Received: from mail-qe0-f41.google.com ([209.85.128.41]:41477 "EHLO mail-qe0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6824790Ab3GZOEGUtWN6 (ORCPT ); Fri, 26 Jul 2013 16:04:06 +0200 Received: by mail-qe0-f41.google.com with SMTP id b4so1014592qen.0 for ; Fri, 26 Jul 2013 07:04:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=sVXS2zcJ+wZBOdBsmCsdRtOC88JNaTC04QwmgCCcEFI=; b=jwQLpuy+UjfrZbDnGfqX0FCHWf1qqbGvaDHdUpJFYxHIbMiOtL/iZz0exs3/TP7QkQ txPBXMdBR+xmySbbPKkfLL9KY6fzi6+rFmwNtLQ7/rj7Pb3SwRrPR6DiA2FUt3kq8wUA 1xkwe1TMBkNeZB02DJkC6og9VV8c/0hqCCYB/YjRw7sMN2CGVPBBI2gojfuavL3TcYd7 JRZPzKdEii4sXa8tBwLtnsFRBSMtEQkG9mIyERI9ZQcECFIDzcMCaDyG+9YsCsxjlcDy beK1LkqStDE+srw7Y0C5/2CBPWT9P2CF202pZ8Q+d9ZMFw/9rqsHsvvSTOPY8n02jloM wZsA== X-Received: by 10.224.134.194 with SMTP id k2mr6707321qat.50.1374847439818; Fri, 26 Jul 2013 07:03:59 -0700 (PDT) Received: from ixro-alexj.ixiacom.com ([205.168.23.154]) by mx.google.com with ESMTPSA id g9sm221759qaz.4.2013.07.26.07.03.57 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 26 Jul 2013 07:03:59 -0700 (PDT) From: Alexandru Juncu To: ralf@linux-mips.org, jchandra@broadcom.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandru Juncu Subject: [PATCH] MIPS:Netlogic: Remove redundant value in operation. Date: Fri, 26 Jul 2013 17:03:35 +0300 Message-Id: <1374847415-28449-1-git-send-email-ajuncu@ixiacom.com> X-Mailer: git-send-email 1.8.1.2 X-Gm-Message-State: ALoCoQnwbaYkDzA8t6ZQq8x2D4ZjPGf42tC3XIKkZgzAtgeHVbZenq86I0MuFKGouTHUuUh0uA2d Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37377 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexj@rosedu.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 928 Lines: 27 From: Alexandru Juncu Removed parameters checked twice in logical OR operation. Suggested by coccinelle and manually verified. Signed-off-by: Alexandru Juncu --- arch/mips/netlogic/xlp/usb-init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c index ef3897e..d5378ef 100644 --- a/arch/mips/netlogic/xlp/usb-init.c +++ b/arch/mips/netlogic/xlp/usb-init.c @@ -75,8 +75,7 @@ static void nlm_usb_intr_en(int node, int port) port_addr = nlm_get_usb_regbase(node, port); val = nlm_read_usb_reg(port_addr, USB_INT_EN); val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | - USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN | - USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN; + USB_OHCI_INTERRUPT1_EN | USB_OHCI_INTERRUPT2_EN; nlm_write_usb_reg(port_addr, USB_INT_EN, val); } -- 1.8.1.2 From gregkh@linuxfoundation.org Fri Jul 26 22:48:52 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 26 Jul 2013 22:48:56 +0200 (CEST) Received: from mail.linuxfoundation.org ([140.211.169.12]:52350 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827823Ab3GZUswi8IUy (ORCPT ); Fri, 26 Jul 2013 22:48:52 +0200 Received: from localhost (c-76-28-172-123.hsd1.wa.comcast.net [76.28.172.123]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id 2414EA91; Fri, 26 Jul 2013 20:48:45 +0000 (UTC) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Markos Chandras , "Steven J. Hill" , Ralf Baechle , linux-mips@linux-mips.org Subject: [ 58/79] lib/Kconfig.debug: Restrict FRAME_POINTER for MIPS Date: Fri, 26 Jul 2013 13:47:48 -0700 Message-Id: <20130726204728.725267852@linuxfoundation.org> X-Mailer: git-send-email 1.8.3.rc0.20.gb99dd2e In-Reply-To: <20130726204721.849052763@linuxfoundation.org> References: <20130726204721.849052763@linuxfoundation.org> User-Agent: quilt/0.60-5.1.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37378 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1449 Lines: 41 3.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Markos Chandras commit 25c87eae1725ed77a8b44d782a86abdc279b4ede upstream. FAULT_INJECTION_STACKTRACE_FILTER selects FRAME_POINTER but that symbol is not available for MIPS. Fixes the following problem on a randconfig: warning: (LOCKDEP && FAULT_INJECTION_STACKTRACE_FILTER && LATENCYTOP && KMEMCHECK) selects FRAME_POINTER which has unmet direct dependencies (DEBUG_KERNEL && (CRIS || M68K || FRV || UML || AVR32 || SUPERH || BLACKFIN || MN10300 || METAG) || ARCH_WANT_FRAME_POINTERS) Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5441/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- lib/Kconfig.debug | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -1272,7 +1272,7 @@ config FAULT_INJECTION_STACKTRACE_FILTER depends on FAULT_INJECTION_DEBUG_FS && STACKTRACE_SUPPORT depends on !X86_64 select STACKTRACE - select FRAME_POINTER if !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND + select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND help Provide stacktrace filter for fault-injection capabilities From carlojpisani@gmail.com Sat Jul 27 09:48:02 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 27 Jul 2013 09:48:05 +0200 (CEST) Received: from sam.nabble.com ([216.139.236.26]:41072 "EHLO sam.nabble.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815748Ab3G0HsCdzhxc (ORCPT ); Sat, 27 Jul 2013 09:48:02 +0200 Received: from tom.nabble.com ([192.168.236.105]) by sam.nabble.com with esmtp (Exim 4.72) (envelope-from ) id 1V2zEO-0003hd-Vn for linux-mips@linux-mips.org; Sat, 27 Jul 2013 00:48:01 -0700 Date: Sat, 27 Jul 2013 00:48:00 -0700 (PDT) From: legacy To: linux-mips@linux-mips.org Message-ID: <1374911280954-56301.post@n7.nabble.com> In-Reply-To: <48914C54.3020505@gentoo.org> References: <48914C54.3020505@gentoo.org> Subject: Re: [PATCH/RFC]: SGI Octane (IP30) Patches, Part one, Intro & IOC3 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37379 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: carlojpisani@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 249 Lines: 9 hi any news about this patch ? -- View this message in context: http://linux-mips-org.10913.n7.nabble.com/PATCH-RFC-SGI-Octane-IP30-Patches-Part-one-Intro-IOC3-tp41699p56301.html Sent from the linux-mips main mailing list archive at Nabble.com. From carlojpisani@gmail.com Sat Jul 27 10:03:24 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 27 Jul 2013 10:03:26 +0200 (CEST) Received: from sam.nabble.com ([216.139.236.26]:42214 "EHLO sam.nabble.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6815748Ab3G0IDYmeJPD (ORCPT ); Sat, 27 Jul 2013 10:03:24 +0200 Received: from tom.nabble.com ([192.168.236.105]) by sam.nabble.com with esmtp (Exim 4.72) (envelope-from ) id 1V2zTH-00063j-EJ for linux-mips@linux-mips.org; Sat, 27 Jul 2013 01:03:23 -0700 Date: Sat, 27 Jul 2013 01:03:23 -0700 (PDT) From: legacy To: linux-mips@linux-mips.org Message-ID: <1374912203434-56302.post@n7.nabble.com> Subject: IP30, which is the current working kernel for 2xR12K ? MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37380 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: carlojpisani@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 691 Lines: 20 hi guys i am fighting with an IP30 equipped with - 2xR12K @ 400Mhz - 2Gbyte ram - V6 & ImpactPro, both installed i am new about sgi/mips, i am using 2.6.17.14 and i am a bit confused about the real status of linux kernel on IP30. I saw patches for 2.6.19 (rc4/rc6??) but it is not working as good as 2.6.17.14. And since then ? Any progress ? If so, which kernel should i consider as successor ? Or which kernel should i consider as the best chances to be fixable ? regards =) -- View this message in context: http://linux-mips-org.10913.n7.nabble.com/IP30-which-is-the-current-working-kernel-for-2xR12K-tp56302.html Sent from the linux-mips main mailing list archive at Nabble.com. From Steven.Hill@imgtec.com Sat Jul 27 16:05:51 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 27 Jul 2013 16:05:58 +0200 (CEST) Received: from multi.imgtec.com ([194.200.65.239]:35977 "EHLO multi.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819681Ab3G0OFukAhCe (ORCPT ); Sat, 27 Jul 2013 16:05:50 +0200 From: "Steven J. Hill" To: Greg Kroah-Hartman , "linux-kernel@vger.kernel.org" CC: Greg Kroah-Hartman , "stable@vger.kernel.org" , Markos Chandras , Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [ 58/79] lib/Kconfig.debug: Restrict FRAME_POINTER for MIPS Thread-Topic: [ 58/79] lib/Kconfig.debug: Restrict FRAME_POINTER for MIPS Thread-Index: AQHOikGIZMC+6l0rxUa3DLV/23Swapl4kD1w Date: Sat, 27 Jul 2013 14:05:40 +0000 Message-ID: <0573B2AE5BBFFC408CC8740092293B5A22ABB144@BADAG02.ba.imgtec.org> References: <20130726204721.849052763@linuxfoundation.org>,<20130726204728.725267852@linuxfoundation.org> In-Reply-To: <20130726204728.725267852@linuxfoundation.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: multipart/alternative; boundary="_000_0573B2AE5BBFFC408CC8740092293B5A22ABB144BADAG02baimgtec_" MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01192__2013_07_27_15_05_45 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37381 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Steven.Hill@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 6273 Lines: 172 --_000_0573B2AE5BBFFC408CC8740092293B5A22ABB144BADAG02baimgtec_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Looks good. Thanks Greg. Acked-by: Steven J. Hill Sent from my Verizon Wireless 4G LTE Smartphone ----- Reply message ----- From: "Greg Kroah-Hartman" To: "linux-kernel@vger.kernel.org" Cc: "Greg Kroah-Hartman" , "stable@vger.kernel.= org" , "Markos Chandras" , "Steven J. Hill" , "Ralf Baechle" , "linux-mips@linux-mips.org" Subject: [ 58/79] lib/Kconfig.debug: Restrict FRAME_POINTER for MIPS Date: Fri, Jul 26, 2013 4:48 PM 3.10-stable review patch. If anyone has any objections, please let me know= . ------------------ From: Markos Chandras commit 25c87eae1725ed77a8b44d782a86abdc279b4ede upstream. FAULT_INJECTION_STACKTRACE_FILTER selects FRAME_POINTER but that symbol is not available for MIPS. Fixes the following problem on a randconfig: warning: (LOCKDEP && FAULT_INJECTION_STACKTRACE_FILTER && LATENCYTOP && KMEMCHECK) selects FRAME_POINTER which has unmet direct dependencies (DEBUG_KERNEL && (CRIS || M68K || FRV || UML || AVR32 || SUPERH || BLACKFIN= || MN10300 || METAG) || ARCH_WANT_FRAME_POINTERS) Signed-off-by: Markos Chandras Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5441/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- lib/Kconfig.debug | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -1272,7 +1272,7 @@ config FAULT_INJECTION_STACKTRACE_FILTER depends on FAULT_INJECTION_DEBUG_FS && STACKTRACE_SUPPORT depends on !X86_64 select STACKTRACE - select FRAME_POINTER if !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND + select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !A= RM_UNWIND help Provide stacktrace filter for fault-injection capabilities --_000_0573B2AE5BBFFC408CC8740092293B5A22ABB144BADAG02baimgtec_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Looks good. Thanks Greg.

Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>

Sent from my Verizon Wireless 4G LTE Smartphone


----- Reply message -----
From: "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>
To: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.o= rg>
Cc: "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, &quo= t;stable@vger.kernel.org" <stable@vger.kernel.org>, "Markos= Chandras" <Markos.Chandras@imgtec.com>, "Steven J. Hill&qu= ot; <Steven.Hill@imgtec.com>, "Ralf Baechle" <ralf@linux= -mips.org>, "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>
Subject: [ 58/79] lib/Kconfig.debug: Restrict FRAME_POINTER for MIPS
Date: Fri, Jul 26, 2013 4:48 PM



3.10-stable review patch.  If anyone has any = objections, please let me know.

------------------

From: Markos Chandras <markos.chandras@imgtec.com>

commit 25c87eae1725ed77a8b44d782a86abdc279b4ede upstream.

FAULT_INJECTION_STACKTRACE_FILTER selects FRAME_POINTER but
that symbol is not available for MIPS.

Fixes the following problem on a randconfig:
warning: (LOCKDEP && FAULT_INJECTION_STACKTRACE_FILTER && L= ATENCYTOP &&
 KMEMCHECK) selects FRAME_POINTER which has unmet direct dependencies<= br> (DEBUG_KERNEL && (CRIS || M68K || FRV || UML || AVR32 || SUPERH || = BLACKFIN ||
MN10300 || METAG) || ARCH_WANT_FRAME_POINTERS)

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https:/= /patchwork.linux-mips.org/patch/5441/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

---
 lib/Kconfig.debug |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -1272,7 +1272,7 @@ config FAULT_INJECTION_STACKTRACE_FILTER
         depends on FAULT_INJECTION= _DEBUG_FS && STACKTRACE_SUPPORT
         depends on !X86_64
         select STACKTRACE
-       select FRAME_POINTER if !PPC &&am= p; !S390 && !MICROBLAZE && !ARM_UNWIND
+       select FRAME_POINTER if !MIPS &am= p;& !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND=
         help
           Provide stackt= race filter for fault-injection capabilities
 


 --_000_0573B2AE5BBFFC408CC8740092293B5A22ABB144BADAG02baimgtec_-- From macro@linux-mips.org Sun Jul 28 22:20:25 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 28 Jul 2013 22:20:29 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:47587 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6826888Ab3G1UUZnwx9Z (ORCPT ); Sun, 28 Jul 2013 22:20:25 +0200 Date: Sun, 28 Jul 2013 21:20:25 +0100 (BST) From: "Maciej W. Rozycki" To: linux-mips@linux-mips.org cc: Ralf Baechle Subject: [PATCH] MIPS: uapi/asm/siginfo.h: Fix GCC 4.1.2 compilation Message-ID: User-Agent: Alpine 2.03 (LFD 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37383 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1137 Lines: 34 It wasn't until GCC 4.3 I believe that the __SIZEOF_*__ predefined macros were added. The change below switches to the _MIPS_SZLONG macro so that compilation with e.g. GCC 4.1.2 succeeds. This is a user API header so I think this is even more important, for older userland support. The change adds an unsuccessful default too, to catch any compiler configuration oddities. Signed-off-by: Maciej W. Rozycki --- Ralf, please apply. Maciej linux-mips-sizeof.patch Index: linux/arch/mips/include/uapi/asm/siginfo.h =================================================================== --- linux.orig/arch/mips/include/uapi/asm/siginfo.h +++ linux/arch/mips/include/uapi/asm/siginfo.h @@ -25,11 +25,12 @@ struct siginfo; /* * Careful to keep union _sifields from shifting ... */ -#if __SIZEOF_LONG__ == 4 +#if _MIPS_SZLONG == 32 #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) -#endif -#if __SIZEOF_LONG__ == 8 +#elif _MIPS_SZLONG == 64 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) +#else +#error _MIPS_SZLONG neither 32 nor 64 #endif #include From blogic@openwrt.org Mon Jul 29 12:02:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 12:02:30 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:50992 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6830580Ab3G2KCXrN5YY (ORCPT ); Mon, 29 Jul 2013 12:02:23 +0200 From: John Crispin To: Ralf Baechle Cc: linux-mips@linux-mips.org, John Crispin Subject: [PATCH] MIPS: add proper set_mode() to cevt-r4k Date: Mon, 29 Jul 2013 11:55:43 +0200 Message-Id: <1375091743-20608-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.10.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37384 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1746 Lines: 75 On ralink SoC a secondary cevt exists, that shares irq 7 with the r4k timer. For this to work, we first need to teach cevt-r4k to not hog the irq. Signed-off-by: John Crispin --- arch/mips/kernel/cevt-r4k.c | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 50d3f5a..b726422 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -38,12 +38,6 @@ static int mips_next_event(unsigned long delta, #endif /* CONFIG_MIPS_MT_SMTC */ -void mips_set_clock_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - /* Nothing to do ... */ -} - DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); int cp0_timer_irq_installed; @@ -90,6 +84,32 @@ struct irqaction c0_compare_irqaction = { .name = "timer", }; +void mips_set_clock_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_ONESHOT: + if (cp0_timer_irq_installed) + break; + + cp0_timer_irq_installed = 1; + + setup_irq(evt->irq, &c0_compare_irqaction); + break; + + case CLOCK_EVT_MODE_SHUTDOWN: + if (!cp0_timer_irq_installed) + break; + + cp0_timer_irq_installed = 0; + free_irq(evt->irq, &c0_compare_irqaction); + break; + + default: + pr_err("Unhandeled mips clock_mode\n"); + break; + } +} void mips_event_handler(struct clock_event_device *dev) { @@ -215,13 +235,6 @@ int r4k_clockevent_init(void) #endif clockevents_register_device(cd); - if (cp0_timer_irq_installed) - return 0; - - cp0_timer_irq_installed = 1; - - setup_irq(irq, &c0_compare_irqaction); - return 0; } -- 1.7.10.4 From f.fainelli@gmail.com Mon Jul 29 12:40:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 12:41:00 +0200 (CEST) Received: from mail-pd0-f180.google.com ([209.85.192.180]:49743 "EHLO mail-pd0-f180.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6818027Ab3G2Kk459ctu (ORCPT ); Mon, 29 Jul 2013 12:40:56 +0200 Received: by mail-pd0-f180.google.com with SMTP id 10so5264971pdi.25 for ; Mon, 29 Jul 2013 03:40:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=t5WjskEj1BFLFnCcp8RjTwRY7XTSfCwanVO1enULmuw=; b=a4HFadjgG9eNcs9DxNL47GycCTdu39P/fE4ZASKw8GrefpVeX3fvfKKH4lmvuGsS43 OMvqsid6LUCJ4Fw2lZ6YSwZ7MuMKi64Bu/H3oGOofD2Ie2fD0NhWmlZdkGTlqEFF9GFD RkWI4JR4a47fl+EjpoizcBFCvxWX3pQfE9PCNk+Ws/rn1xRRMrxioaXCOntdMdKgb/eW vz35ROjw0bYbbZav78h5GR0LK2rU2ikv8X6NSG1BAl3uSmngqqo8Z88cck8DWGAFctaY ac7J6KKiNXEgKCDZlKLaN5oNlEXbd1hzTw37r0/PVX7RN57s0SJMqoB1DZjYM4rJRIgY 66zg== X-Received: by 10.66.9.71 with SMTP id x7mr68691477paa.37.1375094450076; Mon, 29 Jul 2013 03:40:50 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.10.101 with HTTP; Mon, 29 Jul 2013 03:40:10 -0700 (PDT) In-Reply-To: <1375091743-20608-1-git-send-email-blogic@openwrt.org> References: <1375091743-20608-1-git-send-email-blogic@openwrt.org> From: Florian Fainelli Date: Mon, 29 Jul 2013 11:40:10 +0100 Message-ID: Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k To: John Crispin Cc: Ralf Baechle , Linux-MIPS Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37385 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: f.fainelli@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 2937 Lines: 95 Hello John, 2013/7/29 John Crispin : > On ralink SoC a secondary cevt exists, that shares irq 7 with the r4k timer. > For this to work, we first need to teach cevt-r4k to not hog the irq. It is not clear to me whether this secondary cevt is also a r4k-cevt device, or if it is something else? If the IRQ is shared, is there any way to differentiate the ralink cevt from the r4k cevt, such that both could request the same irq with the IRQF_SHARED flag? It looks to me like you are moving the irq setup later just to ensure that your ralink clockevent device has been registered before and has set cp0_timer_irq_installed when the set_mode() r4k clockevent device runs, such that it won't register the same IRQ that your platforms uses. If that it the case, cannot you just ensure that you run your cevt device registration before mips_clockevent_init() is called? > > Signed-off-by: John Crispin > --- > arch/mips/kernel/cevt-r4k.c | 39 ++++++++++++++++++++++++++------------- > 1 file changed, 26 insertions(+), 13 deletions(-) > > diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c > index 50d3f5a..b726422 100644 > --- a/arch/mips/kernel/cevt-r4k.c > +++ b/arch/mips/kernel/cevt-r4k.c > @@ -38,12 +38,6 @@ static int mips_next_event(unsigned long delta, > > #endif /* CONFIG_MIPS_MT_SMTC */ > > -void mips_set_clock_mode(enum clock_event_mode mode, > - struct clock_event_device *evt) > -{ > - /* Nothing to do ... */ > -} > - > DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); > int cp0_timer_irq_installed; > > @@ -90,6 +84,32 @@ struct irqaction c0_compare_irqaction = { > .name = "timer", > }; > > +void mips_set_clock_mode(enum clock_event_mode mode, > + struct clock_event_device *evt) > +{ > + switch (mode) { > + case CLOCK_EVT_MODE_ONESHOT: > + if (cp0_timer_irq_installed) > + break; > + > + cp0_timer_irq_installed = 1; > + > + setup_irq(evt->irq, &c0_compare_irqaction); > + break; > + > + case CLOCK_EVT_MODE_SHUTDOWN: > + if (!cp0_timer_irq_installed) > + break; > + > + cp0_timer_irq_installed = 0; > + free_irq(evt->irq, &c0_compare_irqaction); > + break; > + > + default: > + pr_err("Unhandeled mips clock_mode\n"); > + break; > + } > +} > > void mips_event_handler(struct clock_event_device *dev) > { > @@ -215,13 +235,6 @@ int r4k_clockevent_init(void) > #endif > clockevents_register_device(cd); > > - if (cp0_timer_irq_installed) > - return 0; > - > - cp0_timer_irq_installed = 1; > - > - setup_irq(irq, &c0_compare_irqaction); > - > return 0; > } > > -- > 1.7.10.4 -- Florian From john@phrozen.org Mon Jul 29 12:58:46 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 12:58:48 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:52523 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6819764Ab3G2K6qXwFqW (ORCPT ); Mon, 29 Jul 2013 12:58:46 +0200 Message-ID: <51F6495D.9000008@phrozen.org> Date: Mon, 29 Jul 2013 12:52:13 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130116 Icedove/10.0.12 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k References: <1375091743-20608-1-git-send-email-blogic@openwrt.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37386 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1033 Lines: 25 Hi Florian, > It is not clear to me whether this secondary cevt is also a r4k-cevt > device, or if it is something else? If the IRQ is shared, is there any > way to differentiate the ralink cevt from the r4k cevt, such that both > could request the same irq with the IRQF_SHARED flag? > IRQF_SHARED | IRQF_TIMER is not allowed as a combination. > It looks to me like you are moving the irq setup later just to ensure > that your ralink clockevent device has been registered before and has > set cp0_timer_irq_installed when the set_mode() r4k clockevent device > runs, such that it won't register the same IRQ that your platforms > uses. If that it the case, cannot you just ensure that you run your > cevt device registration before mips_clockevent_init() is called? i dont like relying on the order in which the modules get loaded. the actual problem is not the irq sharing but that the cevt-r4k registers the irq when the cevt is registered and not when it is activated. i believe that the patch fixes this problem John From f.fainelli@gmail.com Mon Jul 29 13:15:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 13:15:35 +0200 (CEST) Received: from mail-pd0-f177.google.com ([209.85.192.177]:35093 "EHLO mail-pd0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6818993Ab3G2LPXXj2DA (ORCPT ); Mon, 29 Jul 2013 13:15:23 +0200 Received: by mail-pd0-f177.google.com with SMTP id u11so5331707pdi.22 for ; Mon, 29 Jul 2013 04:15:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=1EbEhixjRc60zwmHRqZInO8iVp3fu0elb7/i9wPElKg=; b=0LsH9/pIgMOTO6nBQaGEzkTa3gJVhSSRCMVgw2vRrCxPflwN3jv26+kqjAZCtEJDXd oV1sj67C1PyuF5IO+BnfKWumHNCMjwEq5q/UwPLgwV2DkIVFN9DOC/MuiX3Ce6l2WU6u rF8xxz/DZHZ+UbQebQAsbSEi8kc0On+zhPpPl97LrC7qPhQQv8jobAEvlHvwNzSzMcmk ZVeNutA2lxJnBodxVMuXRQjYCrusv8j1rspIACaKkfu5w9fkiv2FTYArjvHtZi0wJCUe InkazPIf/YUmK8jLGQ1Jx0PUlZb99+iVFzLw6XXOu1KoZMbh+Sw/dtr/ERogoQOdYCcV WQjA== X-Received: by 10.66.179.78 with SMTP id de14mr22717586pac.18.1375096516671; Mon, 29 Jul 2013 04:15:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.10.101 with HTTP; Mon, 29 Jul 2013 04:14:36 -0700 (PDT) In-Reply-To: <51F6495D.9000008@phrozen.org> References: <1375091743-20608-1-git-send-email-blogic@openwrt.org> <51F6495D.9000008@phrozen.org> From: Florian Fainelli Date: Mon, 29 Jul 2013 12:14:36 +0100 Message-ID: Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k To: John Crispin Cc: Linux-MIPS Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37387 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: f.fainelli@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1514 Lines: 41 2013/7/29 John Crispin : > Hi Florian, > > >> It is not clear to me whether this secondary cevt is also a r4k-cevt >> device, or if it is something else? If the IRQ is shared, is there any >> way to differentiate the ralink cevt from the r4k cevt, such that both >> could request the same irq with the IRQF_SHARED flag? >> > > IRQF_SHARED | IRQF_TIMER is not allowed as a combination. Good point, forgot about that. Then how about a way to let a platform specify its own callback? Pretty much like what is done with the handle_perf(r2) case? > > > >> It looks to me like you are moving the irq setup later just to ensure >> that your ralink clockevent device has been registered before and has >> set cp0_timer_irq_installed when the set_mode() r4k clockevent device >> runs, such that it won't register the same IRQ that your platforms >> uses. If that it the case, cannot you just ensure that you run your >> cevt device registration before mips_clockevent_init() is called? > > > i dont like relying on the order in which the modules get loaded. plat_time_init() runs before mips_clockevent_init() and the ordering is explicit, would not that work for what you are trying to do? > > the actual problem is not the irq sharing but that the cevt-r4k registers > the irq when the cevt is registered and not when it is activated. i believe > that the patch fixes this problem Your patch certainly does what you say it does, but that is kind of an abuse of the set_mode() callback. -- Florian From john@phrozen.org Mon Jul 29 13:21:08 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 13:21:10 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:53105 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6818993Ab3G2LVIMriG9 (ORCPT ); Mon, 29 Jul 2013 13:21:08 +0200 Message-ID: <51F64E9B.8070306@phrozen.org> Date: Mon, 29 Jul 2013 13:14:35 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130116 Icedove/10.0.12 MIME-Version: 1.0 To: Florian Fainelli CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k References: <1375091743-20608-1-git-send-email-blogic@openwrt.org> <51F6495D.9000008@phrozen.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37388 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 399 Lines: 10 >> the actual problem is not the irq sharing but that the cevt-r4k registers >> the irq when the cevt is registered and not when it is activated. i believe >> that the patch fixes this problem > > Your patch certainly does what you say it does, but that is kind of an > abuse of the set_mode() callback. well there are 2 modes "run as oneshot timer and dont run. i dont see how this is an abuse? From macro@linux-mips.org Mon Jul 29 16:53:13 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 16:53:18 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:52794 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825603Ab3G2OxNw5gGq (ORCPT ); Mon, 29 Jul 2013 16:53:13 +0200 Date: Mon, 29 Jul 2013 15:53:13 +0100 (BST) From: "Maciej W. Rozycki" To: Florian Fainelli cc: John Crispin , Ralf Baechle , Linux-MIPS Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k In-Reply-To: Message-ID: References: <1375091743-20608-1-git-send-email-blogic@openwrt.org> User-Agent: Alpine 2.03 (LFD 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37389 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 595 Lines: 13 On Mon, 29 Jul 2013, Florian Fainelli wrote: > It is not clear to me whether this secondary cevt is also a r4k-cevt > device, or if it is something else? If the IRQ is shared, is there any > way to differentiate the ralink cevt from the r4k cevt, such that both > could request the same irq with the IRQF_SHARED flag? As from rev. 2 of the MIPS architecture processors are required to implement a CP0.Cause.TI bit to indicate a CP0.Count/CP0.Compare timer interrupt pending -- so it may all bail down to figuring out what MIPS architecture level this SoC implements. FWIW. HTH. Maciej From ddaney.cavm@gmail.com Mon Jul 29 23:29:26 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 23:29:38 +0200 (CEST) Received: from mail-pa0-f45.google.com ([209.85.220.45]:65028 "EHLO mail-pa0-f45.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831311Ab3G2V30ayvCt (ORCPT ); Mon, 29 Jul 2013 23:29:26 +0200 Received: by mail-pa0-f45.google.com with SMTP id bg4so6311453pad.18 for ; Mon, 29 Jul 2013 14:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=IIGGMWZnYFkI+CRFyCmQcJooQwvKjuZABKNVY7DVIKE=; b=jdzvgS6OfWPSwLhNxGINe5Mo0TmagN1Kzts1cA+/fNPmKb3QbO6YHE1hAnHWEXqAGA g0Na3qDAzHev1i/nbD9yxo2s2FmJOWhMlK8XLAL8u+TWVLqfntwHwHzSyDAHi98K6iNb ohLCJpW+JibXDyGv6pakTQ8HvTct1b6TxmwE3CQKxm6mrLMywsBCFbMyvOMR/vGF32EG iAn/Npycc7ZjRFIdQIENshW2KrVB4fZMlBsvAPN3zZnJy7otmgr6lHnsTt7Rgt6FyTuC BMGwgUSgo3trRRfslyD2YWOcJ0W234MA4AovPvWkfUCFkP4etgE0F5hUkZR1z/Zadf5B aAZw== X-Received: by 10.68.200.104 with SMTP id jr8mr70665401pbc.43.1375133359415; Mon, 29 Jul 2013 14:29:19 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id qh10sm38959317pbb.33.2013.07.29.14.29.17 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 14:29:18 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TLTGKi018867; Mon, 29 Jul 2013 14:29:16 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TLTGAi018866; Mon, 29 Jul 2013 14:29:16 -0700 From: David Daney To: ralf@linux-mips.org, linux-gpio@vger.kernel.org, Linus Walleij Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v2 1/2] MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIB Date: Mon, 29 Jul 2013 14:29:09 -0700 Message-Id: <1375133350-18828-2-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> References: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1788 Lines: 56 From: David Daney ... and create asm/mach-cavium-octeon/gpio.h so that things continue to build. This allows us to use the existing I2C connected GPIO expanders. Signed-off-by: David Daney --- arch/mips/Kconfig | 1 + arch/mips/include/asm/mach-cavium-octeon/gpio.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/mips/include/asm/mach-cavium-octeon/gpio.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c3abed3..9c2293a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -731,6 +731,7 @@ config CAVIUM_OCTEON_SOC select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI select HOLES_IN_ZONE + select ARCH_REQUIRE_GPIOLIB help This option supports all of the Octeon reference boards from Cavium Networks. It builds a kernel that dynamically determines the Octeon diff --git a/arch/mips/include/asm/mach-cavium-octeon/gpio.h b/arch/mips/include/asm/mach-cavium-octeon/gpio.h new file mode 100644 index 0000000..34e9f7a --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/gpio.h @@ -0,0 +1,21 @@ +#ifndef __ASM_MACH_CAVIUM_OCTEON_GPIO_H +#define __ASM_MACH_CAVIUM_OCTEON_GPIO_H + +#ifdef CONFIG_GPIOLIB +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#else +int gpio_request(unsigned gpio, const char *label); +void gpio_free(unsigned gpio); +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); +#endif + +#include + +#define gpio_to_irq __gpio_to_irq + +#endif /* __ASM_MACH_GENERIC_GPIO_H */ -- 1.7.11.7 From ddaney.cavm@gmail.com Mon Jul 29 23:29:55 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 23:30:08 +0200 (CEST) Received: from mail-pd0-f176.google.com ([209.85.192.176]:57020 "EHLO mail-pd0-f176.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831317Ab3G2V30ch1ML (ORCPT ); Mon, 29 Jul 2013 23:29:26 +0200 Received: by mail-pd0-f176.google.com with SMTP id q10so2739593pdj.7 for ; Mon, 29 Jul 2013 14:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=h6rIvBVU3qfh+J/PJpKR87KZm0Quzlto578o85ZR9+I=; b=I5imQztcqtTDfMyJ4CqSC67G+ZiMMesys9couip9WIvZgzOAO2t3vXDixMeJUY8Vgn 3CTIi9djJaGxem7nsN7tO7pQFvGxxbk34ojs4kBpYIcz0m++q4bvaIRKMt+Z9nnL7g96 FJ3oAWA/57PORH6yoYO2IDWkC7Ioa333v387t4TD5zNUqNBU7kbfFraXDrTjjURpunEk OJLZlG3mYPpl6EQ6i4cHQiybPs6YrtzvBvogXnRMIYDsOovbjLd1D2sH0tpKTiZO2zqT JzqK2XBQjGXMQ8Z4d5tIa6BVPNTi1OmGDInSx7355nVBtLNycz5Y4rvczm3GH3WUUrT+ xnXw== X-Received: by 10.68.198.101 with SMTP id jb5mr53084007pbc.127.1375133359581; Mon, 29 Jul 2013 14:29:19 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id r7sm22758610pao.18.2013.07.29.14.29.17 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 14:29:17 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TLTF7o018863; Mon, 29 Jul 2013 14:29:15 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TLTEWb018862; Mon, 29 Jul 2013 14:29:14 -0700 From: David Daney To: ralf@linux-mips.org, linux-gpio@vger.kernel.org, Linus Walleij Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v2 0/2] OCTEON GPIO support. Date: Mon, 29 Jul 2013 14:29:08 -0700 Message-Id: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1022 Lines: 28 From: David Daney The Cavium, OCTEON is a MIPS based SoC. Here we add support for its on-chip GPIO lines. Changes from v1: Cleaned up variable names, messages and added some comments as suggested by Linus Walleij. The second patch depends on the first, but is in code maintained by Ralf. It may be best to mrege both of these together, perhaps from the GPIO tree, with Ralf's Acked-by. David Daney (2): MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIB gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins. arch/mips/Kconfig | 1 + arch/mips/include/asm/mach-cavium-octeon/gpio.h | 21 ++++ drivers/gpio/Kconfig | 8 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-octeon.c | 157 ++++++++++++++++++++++++ 5 files changed, 188 insertions(+) create mode 100644 arch/mips/include/asm/mach-cavium-octeon/gpio.h create mode 100644 drivers/gpio/gpio-octeon.c -- 1.7.11.7 From ddaney.cavm@gmail.com Mon Jul 29 23:30:24 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 23:30:28 +0200 (CEST) Received: from mail-pb0-f44.google.com ([209.85.160.44]:41016 "EHLO mail-pb0-f44.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831319Ab3G2V30nbdW- (ORCPT ); Mon, 29 Jul 2013 23:29:26 +0200 Received: by mail-pb0-f44.google.com with SMTP id wy7so5167527pbc.17 for ; Mon, 29 Jul 2013 14:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=8ZGogrVEn8uNymVdC8gZlun1T1ISViSbjIX1h0p/gss=; b=ZV81zivzSsI3J3B2E9N8R8ijVHv80oq3auTtuYqnKuMU1ystw7m+luuHnhDQ4yVQZJ NCIq3IZDjxrq5P+qGQ2v2MO0CN1euS5zSbIFRWbRPTvU9yc91rWGox7kAHiUilbv+zkL ZglrKQAkGivT9R9tl4DDVOAX5mHXpXnNKMFYCsJ5g/XmVSc0ImjIXmqh/paVyxfOj+7l sF6VYy23Fb8JOhBnfoGjk+AxdNHBHJ1RYxPzUymjsrDxEnqRkA8KJ7vwwwfHaTzcZcG0 IUQX5QEBSDDFf0AsinqizpHHvHCHVC982go4cRzvFNCg6a0eJF6MtdpmAfAX+1rhigVc +QnA== X-Received: by 10.66.135.146 with SMTP id ps18mr70347143pab.172.1375133359746; Mon, 29 Jul 2013 14:29:19 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id a5sm8365228pbw.4.2013.07.29.14.29.17 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 14:29:18 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TLTGDm018871; Mon, 29 Jul 2013 14:29:16 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TLTGeq018870; Mon, 29 Jul 2013 14:29:16 -0700 From: David Daney To: ralf@linux-mips.org, linux-gpio@vger.kernel.org, Linus Walleij Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: [PATCH v2 2/2] gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins. Date: Mon, 29 Jul 2013 14:29:10 -0700 Message-Id: <1375133350-18828-3-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> References: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 5896 Lines: 216 From: David Daney The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip GPIO pins, this driver handles them all. Configuring the pins as interrupt sources is handled elsewhere (OCTEON's irq handling code). Signed-off-by: David Daney --- Device tree binding defintions already exist for this device in Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-octeon.c | 157 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 drivers/gpio/gpio-octeon.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b2450ba..b21b7a2 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -193,6 +193,14 @@ config GPIO_MXS select GPIO_GENERIC select GENERIC_IRQ_CHIP +config GPIO_OCTEON + tristate "Cavium OCTEON GPIO" + depends on GPIOLIB && CAVIUM_OCTEON_SOC + default y + help + Say yes here to support the on-chip GPIO lines on the OCTEON + family of SOCs. + config GPIO_PL061 bool "PrimeCell PL061 GPIO support" depends on ARM && ARM_AMBA diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ef3e983..e7fd980 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o +obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o diff --git a/drivers/gpio/gpio-octeon.c b/drivers/gpio/gpio-octeon.c new file mode 100644 index 0000000..71a4a31 --- /dev/null +++ b/drivers/gpio/gpio-octeon.c @@ -0,0 +1,157 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011, 2012 Cavium Inc. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define RX_DAT 0x80 +#define TX_SET 0x88 +#define TX_CLEAR 0x90 +/* + * The address offset of the GPIO configuration register for a given + * line. + */ +static unsigned int bit_cfg_reg(unsigned int offset) +{ + /* + * The register stride is 8, with a discontinuity after the + * first 16. + */ + if (offset < 16) + return 8 * offset; + else + return 8 * (offset - 16) + 0x100; +} + +struct octeon_gpio { + struct gpio_chip chip; + u64 register_base; +}; + +static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset) +{ + struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip); + + cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0); + return 0; +} + +static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip); + u64 mask = 1ull << offset; + u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR); + cvmx_write_csr(reg, mask); +} + +static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip); + union cvmx_gpio_bit_cfgx cfgx; + + octeon_gpio_set(chip, offset, value); + + cfgx.u64 = 0; + cfgx.s.tx_oe = 1; + + cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64); + return 0; +} + +static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip); + u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT); + + return ((1ull << offset) & read_bits) != 0; +} + +static int octeon_gpio_probe(struct platform_device *pdev) +{ + struct octeon_gpio *gpio; + struct gpio_chip *chip; + struct resource *res_mem; + int err = 0; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + chip = &gpio->chip; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res_mem == NULL) { + dev_err(&pdev->dev, "found no memory resource\n"); + err = -ENXIO; + goto out; + } + if (!devm_request_mem_region(&pdev->dev, res_mem->start, + resource_size(res_mem), + res_mem->name)) { + dev_err(&pdev->dev, "request_mem_region failed\n"); + err = -ENXIO; + goto out; + } + gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start, + resource_size(res_mem)); + + pdev->dev.platform_data = chip; + chip->label = "octeon-gpio"; + chip->dev = &pdev->dev; + chip->owner = THIS_MODULE; + chip->base = 0; + chip->can_sleep = 0; + chip->ngpio = 20; + chip->direction_input = octeon_gpio_dir_in; + chip->get = octeon_gpio_get; + chip->direction_output = octeon_gpio_dir_out; + chip->set = octeon_gpio_set; + err = gpiochip_add(chip); + if (err) + goto out; + + dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n"); +out: + return err; +} + +static int octeon_gpio_remove(struct platform_device *pdev) +{ + struct gpio_chip *chip = pdev->dev.platform_data; + return gpiochip_remove(chip); +} + +static struct of_device_id octeon_gpio_match[] = { + { + .compatible = "cavium,octeon-3860-gpio", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_gpio_match); + +static struct platform_driver octeon_gpio_driver = { + .driver = { + .name = "octeon_gpio", + .owner = THIS_MODULE, + .of_match_table = octeon_gpio_match, + }, + .probe = octeon_gpio_probe, + .remove = octeon_gpio_remove, +}; + +module_platform_driver(octeon_gpio_driver); + +MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver"); +MODULE_AUTHOR("David Daney"); +MODULE_LICENSE("GPL"); -- 1.7.11.7 From David.Daney@caviumnetworks.com Mon Jul 29 23:32:35 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 29 Jul 2013 23:32:38 +0200 (CEST) Received: from mail-by2lp0242.outbound.protection.outlook.com ([207.46.163.242]:27522 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6830610Ab3G2Vcfofgm1 (ORCPT ); Mon, 29 Jul 2013 23:32:35 +0200 Received: from BN1PRD0712HT002.namprd07.prod.outlook.com (10.255.196.35) by SN2PR07MB032.namprd07.prod.outlook.com (10.255.174.42) with Microsoft SMTP Server (TLS) id 15.0.731.12; Mon, 29 Jul 2013 21:32:25 +0000 Received: from dl.caveonetworks.com (64.2.3.195) by pod51018.outlook.com (10.255.196.35) with Microsoft SMTP Server (TLS) id 14.16.341.1; Mon, 29 Jul 2013 21:32:24 +0000 Message-ID: <51F6DF65.9050301@caviumnetworks.com> Date: Mon, 29 Jul 2013 14:32:21 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: , Linus Walleij CC: David Daney , , , , David Daney Subject: Re: [PATCH v2 0/2] OCTEON GPIO support. References: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.195] X-Forefront-PRVS: 09222B39F5 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(377454003)(479174003)(51704005)(24454002)(199002)(189002)(74366001)(79102001)(16406001)(74662001)(23756003)(51856001)(74876001)(65806001)(76796001)(76786001)(65956001)(69226001)(80976001)(80022001)(63696002)(66066001)(64126003)(81542001)(47776003)(81342001)(83072001)(53416003)(31966008)(74706001)(74502001)(47446002)(56776001)(76482001)(33656001)(49866001)(80316001)(50986001)(4396001)(59766001)(47736001)(47976001)(77982001)(50466002)(19580405001)(54356001)(36756003)(53806001)(83322001)(56816003)(19580395003)(46102001)(59896001)(54316002)(77096001)(217873001);DIR:OUT;SFP:;SCL:1;SRVR:SN2PR07MB032;H:BN1PRD0712HT002.namprd07.prod.outlook.com;CLIP:64.2.3.195;RD:InfoNoRecords;A:1;MX:1;LANG:en; X-OriginatorOrg: DuplicateDomain-a3ec847f-e37f-4d9a-9900-9d9d96f75f58.caviumnetworks.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1238 Lines: 34 On 07/29/2013 02:29 PM, David Daney wrote: > From: David Daney > > The Cavium, OCTEON is a MIPS based SoC. Here we add support for its > on-chip GPIO lines. > > Changes from v1: Cleaned up variable names, messages and added some > comments as suggested by Linus Walleij. > > The second patch depends on the first, but is in code maintained by > Ralf. It may be best to mrege both of these together, perhaps from > the GPIO tree, with Ralf's Acked-by. Really I meant to say that the first patch is in the MIPS tree, and should be Acked-by Ralf, if that wasn't clear. David Daney > > David Daney (2): > MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIB > gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins. > > arch/mips/Kconfig | 1 + > arch/mips/include/asm/mach-cavium-octeon/gpio.h | 21 ++++ > drivers/gpio/Kconfig | 8 ++ > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-octeon.c | 157 ++++++++++++++++++++++++ > 5 files changed, 188 insertions(+) > create mode 100644 arch/mips/include/asm/mach-cavium-octeon/gpio.h > create mode 100644 drivers/gpio/gpio-octeon.c > From ddaney.cavm@gmail.com Tue Jul 30 00:07:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 00:07:28 +0200 (CEST) Received: from mail-pd0-f180.google.com ([209.85.192.180]:39191 "EHLO mail-pd0-f180.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831311Ab3G2WHQthjcF (ORCPT ); Tue, 30 Jul 2013 00:07:16 +0200 Received: by mail-pd0-f180.google.com with SMTP id 10so5918547pdi.25 for ; Mon, 29 Jul 2013 15:07:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=ozO4/Zf2XfLznYeMDf8q+a4n5jlDKihVzw2fn5DNFhQ=; b=mb22FlpcLnrwarn33fngazxROouqauwlKjuUIFK75Q8HN55Z/p6Qpmr7eR+0/O8iXS hswJxnqJSdnrjKrA1Y95dW7EEwMXyFHFFpt+vEzPs9jNeSKXkxxe1/gYI6e6AHIXpT+n cpsT3LEIXykEXR54i5SZN6nFotOLgOtHO84lyB38vxFM5LykbFG9j+DLCHN7mwp9vYBw H7YMk1qG5YYS49Klkh0tMEl4GzBVaEBQUJwcM8qqChf9IOsNCUlSCirJ+3mJNXvAXW1j SBPaY2j8mng7NIryuWtWtS/lspptV5oIJEMK9QqVF/SQjiIn4lN6lcxsw8Qxsx3FSLga ZySA== X-Received: by 10.68.189.36 with SMTP id gf4mr70658389pbc.27.1375135630032; Mon, 29 Jul 2013 15:07:10 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id xl3sm79014951pbb.17.2013.07.29.15.07.08 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 15:07:09 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TM76FX030989; Mon, 29 Jul 2013 15:07:07 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TM76o2030988; Mon, 29 Jul 2013 15:07:06 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 0/5] MIPS: Add support for OCTEON III based SoCs. Date: Mon, 29 Jul 2013 15:06:59 -0700 Message-Id: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 792 Lines: 24 From: David Daney These patches add minimal support for SoCs in the OCTEON III family. In many respects, they are similar to OCTEON II, but with larger cache and FPU. FPU support comes later... David Daney (5): MIPS: Add CPU identifiers for more OCTEON family members. MIPS: Probe for new OCTEON CPU/SoC types. MIPS: Use r4k_wait for OCTEON3 CPUs. MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2. MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs. arch/mips/include/asm/cpu.h | 5 ++++- arch/mips/kernel/cpu-probe.c | 7 +++++++ arch/mips/kernel/idle.c | 1 + arch/mips/mm/c-octeon.c | 14 ++++++++++++++ arch/mips/mm/tlbex.c | 2 ++ 5 files changed, 28 insertions(+), 1 deletion(-) -- 1.7.11.7 From ddaney.cavm@gmail.com Tue Jul 30 00:07:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 00:07:58 +0200 (CEST) Received: from mail-pa0-f46.google.com ([209.85.220.46]:50853 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831317Ab3G2WHQw7PlG (ORCPT ); Tue, 30 Jul 2013 00:07:16 +0200 Received: by mail-pa0-f46.google.com with SMTP id fa1so6411193pad.33 for ; Mon, 29 Jul 2013 15:07:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=IZx8rMnvZD3x/CuABzDsC0xWYMKboiAD/gxfQFlXa+U=; b=ulIKOb3ZmgUblJF4eqY9PYPUrlPjD6rAGFt86n4CxSKwqo9PfnRKTUpj6qEMnagShT BTSqqvZprNdw/6ECADeCkG4sf7nNfg0guhWFb1JsCO7+GhwTxRlgM5Wly3UJVD0Eiinj 3qH6OWk3G0t9HYndlIjHcywPGx/vwIDqZend8jPiqwx45e96odISiedalzdsWLcpqrtf NNBadJiGujJOHbf+XGh0N6uSb5YNbnjJz450vjyWA3V1Nq6HE5MvJxJf4OPxfuJfN+5F lG7Eqm91c26Gy7jEnj2ek1GVF/5ICkMeWMJfo1PNk4XkW03WsZ8s7q/FIQPVQRM5K17G 31EA== X-Received: by 10.66.171.77 with SMTP id as13mr30900911pac.170.1375135630432; Mon, 29 Jul 2013 15:07:10 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id wr9sm79053499pbc.7.2013.07.29.15.07.08 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 15:07:09 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TM774S030993; Mon, 29 Jul 2013 15:07:07 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TM77AJ030992; Mon, 29 Jul 2013 15:07:07 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/5] MIPS: Add CPU identifiers for more OCTEON family members. Date: Mon, 29 Jul 2013 15:07:00 -0700 Message-Id: <1375135624-30950-2-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> References: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 985 Lines: 35 From: David Daney Needed to support new SOCs. Signed-off-by: David Daney --- arch/mips/include/asm/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 632bbe5..c198615 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -141,6 +141,9 @@ #define PRID_IMP_CAVIUM_CN68XX 0x9100 #define PRID_IMP_CAVIUM_CN66XX 0x9200 #define PRID_IMP_CAVIUM_CN61XX 0x9300 +#define PRID_IMP_CAVIUM_CNF71XX 0x9400 +#define PRID_IMP_CAVIUM_CN78XX 0x9500 +#define PRID_IMP_CAVIUM_CN70XX 0x9600 /* * These are the PRID's for when 23:16 == PRID_COMP_INGENIC @@ -272,7 +275,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, - CPU_XLR, CPU_XLP, + CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_LAST }; -- 1.7.11.7 From ddaney.cavm@gmail.com Tue Jul 30 00:08:23 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 00:08:35 +0200 (CEST) Received: from mail-pb0-f50.google.com ([209.85.160.50]:56044 "EHLO mail-pb0-f50.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831319Ab3G2WHRfV7rW (ORCPT ); Tue, 30 Jul 2013 00:07:17 +0200 Received: by mail-pb0-f50.google.com with SMTP id uo5so1876019pbc.9 for ; Mon, 29 Jul 2013 15:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=C7htIkuj13wZlJUlzSzc50Zk58Q1i2wCO7mHSMGC958=; b=K5tdAZXpu1E+HGD6Ng85jTjW/5evr/ggZP3tx69r3+xKCsTnqD2OCNQp93Cuietbz9 rZKFybqBMfQScZr7KMjfJb0bCIhuB+jFG7yNejI8kzxpvCvO66kJmyaSFvgqgJQpQdD4 LrPkoVncGiEC1hQIMlc+nsOCU0iqAPLNGtLWoxJNufPvDqE0WqMFXW17SxpbsHhVAcsG FGup91HGXUF7GlUObE3O15kTQuuIZW08rmwTi6a0eGeq5bekhPUcl4Q/V9cuffhAa1Tw RHbGuI4MdvYPuuu4Fop+6yvVem+JlfLitVu4TwoBolkAqpMC1dyQ3+RCF+HWiOWqKUu4 1NiQ== X-Received: by 10.68.252.137 with SMTP id zs9mr70094293pbc.60.1375135630981; Mon, 29 Jul 2013 15:07:10 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id lk9sm22944149pab.2.2013.07.29.15.07.09 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 15:07:10 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TM78fp030997; Mon, 29 Jul 2013 15:07:08 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TM785A030996; Mon, 29 Jul 2013 15:07:08 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/5] MIPS: Probe for new OCTEON CPU/SoC types. Date: Mon, 29 Jul 2013 15:07:01 -0700 Message-Id: <1375135624-30950-3-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> References: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 963 Lines: 34 From: David Daney Add probing for CNF71XX, CN78XX and CN70XX. Signed-off-by: David Daney --- arch/mips/kernel/cpu-probe.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 4c6167a..8e8feb8 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -852,10 +852,17 @@ platform: case PRID_IMP_CAVIUM_CN63XX: case PRID_IMP_CAVIUM_CN66XX: case PRID_IMP_CAVIUM_CN68XX: + case PRID_IMP_CAVIUM_CNF71XX: c->cputype = CPU_CAVIUM_OCTEON2; __cpu_name[cpu] = "Cavium Octeon II"; set_elf_platform(cpu, "octeon2"); break; + case PRID_IMP_CAVIUM_CN70XX: + case PRID_IMP_CAVIUM_CN78XX: + c->cputype = CPU_CAVIUM_OCTEON3; + __cpu_name[cpu] = "Cavium Octeon III"; + set_elf_platform(cpu, "octeon3"); + break; default: printk(KERN_INFO "Unknown Octeon chip!\n"); c->cputype = CPU_UNKNOWN; -- 1.7.11.7 From ddaney.cavm@gmail.com Tue Jul 30 00:08:56 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 00:09:00 +0200 (CEST) Received: from mail-pd0-f169.google.com ([209.85.192.169]:54742 "EHLO mail-pd0-f169.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831320Ab3G2WHRsc-UF (ORCPT ); Tue, 30 Jul 2013 00:07:17 +0200 Received: by mail-pd0-f169.google.com with SMTP id y11so436773pdj.28 for ; Mon, 29 Jul 2013 15:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=sdb1PMZi1hofEQy2mWCMbgHd26PNNXuxxE901iJJZC4=; b=vvrVfZpXIY0kLjFNFQ6eLX5fYLyJNOkSV9gGn0eD6nlvVWqkrtHlHSdw8HmT+m5puO ewDRXBndVHgnicvz+n/skiMGukwQQRzktX5LnUb/V8/dOJEzzco2VyWtcuqnEXL1ooOZ bSXUhL4aj7QcKB9fCoLq40tROv/Wd6/bg11arXUEfLZOdLKqG1jqqWczxLO8pksw6luq znAKuGqdE3Y4KvYmyRSFdhVj8JYT8dasVwIpqnUTFwoiIv6DN4D0EkWLuRkyW4dtqeLV 8eGbkv0VktcJNOqV549KUEzwohv9lQbrMxXEnkDoOVJwg7L9EElleuClH7Uf93pXOaae Soqg== X-Received: by 10.66.21.37 with SMTP id s5mr72425063pae.103.1375135631314; Mon, 29 Jul 2013 15:07:11 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id vi8sm78976815pbc.31.2013.07.29.15.07.09 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 15:07:10 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TM78QW031001; Mon, 29 Jul 2013 15:07:08 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TM78pu031000; Mon, 29 Jul 2013 15:07:08 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 3/5] MIPS: Use r4k_wait for OCTEON3 CPUs. Date: Mon, 29 Jul 2013 15:07:02 -0700 Message-Id: <1375135624-30950-4-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> References: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 548 Lines: 22 From: David Daney Signed-off-by: David Daney --- arch/mips/kernel/idle.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 0c655de..42f8875 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -166,6 +166,7 @@ void __init check_wait(void) case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: case CPU_JZRISC: case CPU_LOONGSON1: case CPU_XLR: -- 1.7.11.7 From ddaney.cavm@gmail.com Tue Jul 30 00:09:16 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 00:09:28 +0200 (CEST) Received: from mail-pb0-f45.google.com ([209.85.160.45]:38066 "EHLO mail-pb0-f45.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831321Ab3G2WHSAeKfF (ORCPT ); Tue, 30 Jul 2013 00:07:18 +0200 Received: by mail-pb0-f45.google.com with SMTP id mc8so5158047pbc.18 for ; Mon, 29 Jul 2013 15:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=aS11ZRjQy9KVcNja7bTOr1SWBMRoG8Ct8LGyp6r5AbA=; b=TnWlR3ZWBg997JsHks1Z4TGTp+KAAmpjMDAS6luy31/fO1rPYdM2GwVFaXGGkc6arR nczfEcL5+lQ8KTf+rut+W7mJl9pvHKSMb1X0c9cMNmCK5/azKvN9bRkn8ShtmdBNKnCy XlJCSsPyKo2OzViwMF0N5/CVlG72NzjHHbiuh7MkrVntLKVQdheTWXK3AI+4YyZq0E/d BJ5zHAmDvFdian4iS7ytTY+LMEGkIbqpJcViB0VPqRWbluAGwHyL+1GOPQvRWUQpjLGo DcZQ2pJNrFneh47+h/F4wsJFnAaTK7zAloBTpOiTC7thls5b7ygGAl6gbLSsilRqTB9V lblQ== X-Received: by 10.66.37.43 with SMTP id v11mr33209869paj.108.1375135631533; Mon, 29 Jul 2013 15:07:11 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id ht5sm78979707pbb.29.2013.07.29.15.07.10 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 15:07:10 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TM79uQ031005; Mon, 29 Jul 2013 15:07:09 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TM78KL031004; Mon, 29 Jul 2013 15:07:08 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 4/5] MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2. Date: Mon, 29 Jul 2013 15:07:03 -0700 Message-Id: <1375135624-30950-5-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> References: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 786 Lines: 33 From: David Daney From the point of view of the TLB Exception handlers, OCTEON3 and OCTEON2 need the same code. Signed-off-by: David Daney --- arch/mips/mm/tlbex.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 556cb48..821b451 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -85,6 +85,7 @@ static int use_bbit_insns(void) case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: return 1; default: return 0; @@ -95,6 +96,7 @@ static int use_lwx_insns(void) { switch (current_cpu_type()) { case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: return 1; default: return 0; -- 1.7.11.7 From ddaney.cavm@gmail.com Tue Jul 30 00:09:45 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 00:10:00 +0200 (CEST) Received: from mail-pb0-f51.google.com ([209.85.160.51]:40339 "EHLO mail-pb0-f51.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6831322Ab3G2WHS2mp7m (ORCPT ); Tue, 30 Jul 2013 00:07:18 +0200 Received: by mail-pb0-f51.google.com with SMTP id um15so5207269pbc.10 for ; Mon, 29 Jul 2013 15:07:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=pjzVLFYX7K47jJCsXEggP+q91bDDmhUrqyA3S8fWSak=; b=ElYjz0zd0fI0vwPWVw0dmDUeseffF40+ViCrGUlQVqNTKU8ssmKTLrJEEJFHRNg8Zg FKCVfjd/lgiQz2mKKWsIoWD2VMHZkIdACwwysa5nCyjun7Ln1k3Nn0m9dQ19vmlx3taF eiRrgl9ohsIRWXPR18rEdDIXTehpgAdQDzfKan1hnAHBIrw7MwASnL9ijJZQCzp58oXo uHM6p94puRPSX7DkIxiCauOosQZbVTJ6+QYwoiESWqYXE/rAH1vuPIfT+8DZeIjq3Gbo FTUIEXkcCKEJibYRqu+NKcY81MwNDcjvoSCMpTdat3+E48IKL6SybhFF3mDiZKNb3h0E wtDQ== X-Received: by 10.68.103.131 with SMTP id fw3mr70110932pbb.65.1375135632032; Mon, 29 Jul 2013 15:07:12 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id dg3sm78994033pbc.24.2013.07.29.15.07.10 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 29 Jul 2013 15:07:11 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id r6TM79rG031009; Mon, 29 Jul 2013 15:07:09 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id r6TM79iU031008; Mon, 29 Jul 2013 15:07:09 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 5/5] MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs. Date: Mon, 29 Jul 2013 15:07:04 -0700 Message-Id: <1375135624-30950-6-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> References: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 921 Lines: 35 From: David Daney Signed-off-by: David Daney --- arch/mips/mm/c-octeon.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index a0bcdbb..729e770 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -224,6 +224,20 @@ static void probe_octeon(void) c->options |= MIPS_CPU_PREFETCH; break; + case CPU_CAVIUM_OCTEON3: + c->icache.linesz = 128; + c->icache.sets = 16; + c->icache.ways = 39; + c->icache.flags |= MIPS_CACHE_VTAG; + icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; + + c->dcache.linesz = 128; + c->dcache.ways = 32; + c->dcache.sets = 8; + dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; + c->options |= MIPS_CPU_PREFETCH; + break; + default: panic("Unsupported Cavium Networks CPU type"); break; -- 1.7.11.7 From f.fainelli@gmail.com Tue Jul 30 12:02:42 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 12:03:01 +0200 (CEST) Received: from mail-pb0-f41.google.com ([209.85.160.41]:42743 "EHLO mail-pb0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6825317Ab3G3KCmBmSct (ORCPT ); Tue, 30 Jul 2013 12:02:42 +0200 Received: by mail-pb0-f41.google.com with SMTP id rp16so5830496pbb.14 for ; Tue, 30 Jul 2013 03:02:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type; bh=nVbAovf8VnpIUxhSGv0BbovmTlxk4YqzzAdpu5nzeJA=; b=bMSaXIQB6iAW3KbjFIiAv5bq2bsz3MbcUZ1oaseuuFhOlu+enNAgqkGQOzfDMXrUZK EHGyUuLHKxJ3poxC0U04cG49Vu+0Sb2Wgp2R6CkB9xbs9C1I2sEpJJdiQBjRtur4rvBX EzYJPGXuNAtnWdgrJ+bFulbtY3eBMMTArcL9pKcsztFanEW11u5xvey7SWPfqMuqpRFe FbicPGvs8/yq2QeHRDyng6mBQYslW2BGPooqvQmm8Pd75MD1QZnSUNAwb/g2+lnER4es JO2VLgylbsCdZ+AG8kwXKDV/g6AXoHdaUJV1wXDGnwN6MIwhWRBfr9gx/Qy0jf2LmLxX l1pQ== X-Received: by 10.66.221.2 with SMTP id qa2mr73514857pac.188.1375178555038; Tue, 30 Jul 2013 03:02:35 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.10.101 with HTTP; Tue, 30 Jul 2013 03:01:53 -0700 (PDT) In-Reply-To: <51F64E9B.8070306@phrozen.org> References: <1375091743-20608-1-git-send-email-blogic@openwrt.org> <51F6495D.9000008@phrozen.org> <51F64E9B.8070306@phrozen.org> From: Florian Fainelli Date: Tue, 30 Jul 2013 11:01:53 +0100 X-Google-Sender-Auth: 4Ovs68OUsPSiWWw8UCVxclwwRC0 Message-ID: Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k To: John Crispin Cc: Linux-MIPS Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 776 Lines: 23 2013/7/29 John Crispin : > >>> the actual problem is not the irq sharing but that the cevt-r4k registers >>> the irq when the cevt is registered and not when it is activated. i >>> believe >>> that the patch fixes this problem >> >> >> Your patch certainly does what you say it does, but that is kind of an >> abuse of the set_mode() callback. > > > well there are 2 modes "run as oneshot timer and dont run. i dont see how > this is an abuse? What you are doing here should be done in some sort of open() call to the device, not in some sort of ioctl() like interface in my opinion, I agree that this is your only choice here though. How about my former proposal to hook your specific use case in plat_time_init(), does not that work for you? -- Florian From ralf@linux-mips.org Tue Jul 30 17:47:10 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 17:47:21 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:59797 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6817535Ab3G3Pqtvprm4 (ORCPT ); Tue, 30 Jul 2013 17:46:49 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r6UFkn9w004822 for ; Tue, 30 Jul 2013 17:46:49 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r6UFkne0004821 for linux-mips@linux-mips.org; Tue, 30 Jul 2013 17:46:49 +0200 Date: Tue, 30 Jul 2013 17:46:49 +0200 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: [ADMIN] linux-mips.org upgrade esp. patchwork Message-ID: <20130730154648.GA4569@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 453 Lines: 11 On the weekend I've upgraded linux-mips.org from it's Linux distribution which is going to reach EOL today to the latest and greatest. Which meant by not one but two releases and as to be expected there's been plenty of fallout, in particular all web services were heavily affected and of those patchwork suffered most. I believe everything is working again as before the upgrade but if any of the services isn't, please let me know. Thanks, Ralf From ralf@linux-mips.org Tue Jul 30 18:01:40 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 18:01:42 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:59831 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6817546Ab3G3QBkiPDg- (ORCPT ); Tue, 30 Jul 2013 18:01:40 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r6UG1alL005560; Tue, 30 Jul 2013 18:01:36 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r6UG1XY9005559; Tue, 30 Jul 2013 18:01:33 +0200 Date: Tue, 30 Jul 2013 18:01:33 +0200 From: Ralf Baechle To: David Daney Cc: linux-gpio@vger.kernel.org, Linus Walleij , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: Re: [PATCH v2 0/2] OCTEON GPIO support. Message-ID: <20130730160133.GA5411@linux-mips.org> References: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1375133350-18828-1-git-send-email-ddaney.cavm@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 554 Lines: 17 On Mon, Jul 29, 2013 at 02:29:08PM -0700, David Daney wrote: > From: David Daney > > The Cavium, OCTEON is a MIPS based SoC. Here we add support for its > on-chip GPIO lines. > > Changes from v1: Cleaned up variable names, messages and added some > comments as suggested by Linus Walleij. > > The second patch depends on the first, but is in code maintained by > Ralf. It may be best to mrege both of these together, perhaps from > the GPIO tree, with Ralf's Acked-by. Acked-by: Ralf Baechle Ralf From ralf@linux-mips.org Tue Jul 30 18:11:13 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 18:11:15 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:59869 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6817549Ab3G3QLNLA6di (ORCPT ); Tue, 30 Jul 2013 18:11:13 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r6UGBBlS006015; Tue, 30 Jul 2013 18:11:11 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r6UGBBLA006014; Tue, 30 Jul 2013 18:11:11 +0200 Date: Tue, 30 Jul 2013 18:11:11 +0200 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, David Daney Subject: Re: [PATCH 0/5] MIPS: Add support for OCTEON III based SoCs. Message-ID: <20130730161111.GA6010@linux-mips.org> References: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1375135624-30950-1-git-send-email-ddaney.cavm@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 333 Lines: 11 On Mon, Jul 29, 2013 at 03:06:59PM -0700, David Daney wrote: > From: David Daney > > These patches add minimal support for SoCs in the OCTEON III family. > In many respects, they are similar to OCTEON II, but with larger cache > and FPU. FPU support comes later... Thanks, entire series applied. Ralf From ralf@linux-mips.org Tue Jul 30 18:16:32 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 30 Jul 2013 18:16:35 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:59885 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6817904Ab3G3QQczZEpn (ORCPT ); Tue, 30 Jul 2013 18:16:32 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r6UGGWsA006284; Tue, 30 Jul 2013 18:16:32 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r6UGGWnF006283; Tue, 30 Jul 2013 18:16:32 +0200 Date: Tue, 30 Jul 2013 18:16:32 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: uapi/asm/siginfo.h: Fix GCC 4.1.2 compilation Message-ID: <20130730161631.GB6010@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 570 Lines: 14 On Sun, Jul 28, 2013 at 09:20:25PM +0100, Maciej W. Rozycki wrote: > It wasn't until GCC 4.3 I believe that the __SIZEOF_*__ predefined macros > were added. The change below switches to the > _MIPS_SZLONG macro so that compilation with e.g. GCC 4.1.2 succeeds. > This is a user API header so I think this is even more important, for > older userland support. The change adds an unsuccessful default too, to > catch any compiler configuration oddities. > > Signed-off-by: Maciej W. Rozycki Thanks, applied. Ralf From ralf@linux-mips.org Wed Jul 31 10:15:28 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 31 Jul 2013 10:15:31 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:34072 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6822674Ab3GaIP2XevLY (ORCPT ); Wed, 31 Jul 2013 10:15:28 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r6V8FMYj019179; Wed, 31 Jul 2013 10:15:22 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r6V8FJse019178; Wed, 31 Jul 2013 10:15:19 +0200 Date: Wed, 31 Jul 2013 10:15:19 +0200 From: Ralf Baechle To: Liam Girdwood , Mark Brown , alsa-devel@alsa-project.org Cc: Manuel Lauss , Mark Brown , linux-mips@linux-mips.org Subject: [PATCH] SOUND: au1x: Fix build Message-ID: <20130731081519.GA18756@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1728 Lines: 30 d8b51c11ff5a70244753ba60abfd47088cf4dcd4 [ASoC: ac97c: Use module_platform_driver()] broke the build: CC sound/soc/au1x/ac97c.o /home/ralf/src/linux/upstream-sfr/sound/soc/au1x/ac97c.c:344:1: error: expected identifier or ‘(’ before ‘&’ token /home/ralf/src/linux/upstream-sfr/sound/soc/au1x/ac97c.c:344:1: error: pasting "__initcall_" and "&" does not give a valid preprocessing token /home/ralf/src/linux/upstream-sfr/sound/soc/au1x/ac97c.c:344:1: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before ‘&’ token /home/ralf/src/linux/upstream-sfr/sound/soc/au1x/ac97c.c:344:1: error: expected identifier or ‘(’ before ‘&’ token /home/ralf/src/linux/upstream-sfr/sound/soc/au1x/ac97c.c:344:1: error: pasting "__exitcall_" and "&" does not give a valid preprocessing token /home/ralf/src/linux/upstream-sfr/sound/soc/au1x/ac97c.c:344:1: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before ‘&’ token /home/ralf/src/linux/upstream-sfr/sound/soc/au1x/ac97c.c:334:31: warning: ‘au1xac97c_driver’ defined but not used [-Wunused-variable] make[5]: *** [sound/soc/au1x/ac97c.o] Error 1 make[4]: *** [sound/soc/au1x] Error 2 make[3]: *** [sound/soc] Error 2 Signed-off-by: Ralf Baechle diff --git a/sound/soc/au1x/ac97c.c b/sound/soc/au1x/ac97c.c index d6f7694..c8a2de1 100644 --- a/sound/soc/au1x/ac97c.c +++ b/sound/soc/au1x/ac97c.c @@ -341,7 +341,7 @@ static struct platform_driver au1xac97c_driver = { .remove = au1xac97c_drvremove, }; -module_platform_driver(&au1xac97c_driver); +module_platform_driver(au1xac97c_driver); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Au1000/1500/1100 AC97C ASoC driver"); From broonie@sirena.org.uk Wed Jul 31 11:07:09 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 31 Jul 2013 11:07:15 +0200 (CEST) Received: from cassiel.sirena.org.uk ([80.68.93.111]:36757 "EHLO cassiel.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6822674Ab3GaJHJooJm6 (ORCPT ); Wed, 31 Jul 2013 11:07:09 +0200 Received: from cpc11-sgyl31-2-0-cust68.sgyl.cable.virginmedia.com ([94.175.92.69] helo=finisterre) by cassiel.sirena.org.uk with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1V4SMy-0007O5-2G; Wed, 31 Jul 2013 10:06:57 +0100 Received: from broonie by finisterre with local (Exim 4.80) (envelope-from ) id 1V4SMx-0007Ka-Iw; Wed, 31 Jul 2013 10:06:55 +0100 Date: Wed, 31 Jul 2013 10:06:55 +0100 From: Mark Brown To: Ralf Baechle Cc: Liam Girdwood , alsa-devel@alsa-project.org, Manuel Lauss , linux-mips@linux-mips.org Message-ID: <20130731090655.GE9858@sirena.org.uk> References: <20130731081519.GA18756@linux-mips.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="FIYk/R+LCB1TX+kR" Content-Disposition: inline In-Reply-To: <20130731081519.GA18756@linux-mips.org> X-Cookie: You will be awarded some great honor. User-Agent: Mutt/1.5.21 (2010-09-15) X-SA-Exim-Connect-IP: 94.175.92.69 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH] SOUND: au1x: Fix build X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:57:07 +0000) X-SA-Exim-Scanned: Yes (on cassiel.sirena.org.uk) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37406 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: broonie@kernel.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1317 Lines: 35 --FIYk/R+LCB1TX+kR Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jul 31, 2013 at 10:15:19AM +0200, Ralf Baechle wrote: > d8b51c11ff5a70244753ba60abfd47088cf4dcd4 [ASoC: ac97c: Use > module_platform_driver()] broke the build: Applied. Please do try to use subject lines appropriate for the subsystem. --FIYk/R+LCB1TX+kR Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.20 (GNU/Linux) iQIcBAEBAgAGBQJR+NOsAAoJELSic+t+oim92FsP/0DWKlYmPmIs+JEDPqSkX4Mm WUk1oPAiIpWjeOH/hIt22UWFmGWTTDojuLCrigpvfcchLiLet1GchnmylYWQg59Z FVgLY/nO7VivXbiPfzoORgxC92fFHnlOn9yYjUtLwTO2ZhjhHDOC5UXQGHmb55lp jOrtFFjq46pWIpyDGIX3fH6Of1H7lNOvUT/CHkXA5oX39oJkGM8JpNQz/H+JH+qc 4m6UTiEfk3s9D5Pp2VjpHV3YVTNLjMIxYrNy9jTUSPeyweQj97CFZdI6F+sd/ZGz R4nV1vUMDf1bb4o7KPSYg/F3fcAo/2Jk+FYa+tiCI9T0KB0PVb/M4S+ADZWB78hE Ap0SvKnEoolERoj2sZSvTROeEl2eRli8FJ4j9cqiCKx5RSpix4rziuuiL0OWl/Aj dZQFYZXwho0zWl1ADJovfsgEappfANGEzLkTZXNbO30NkojnpC6v8/5wq58yqjQx dfE1B7lB/dLW7M37qPhJKHg5NlbHhxJesvHq1iVViMUsw2d1CVs3TEQnlME/VdRf 2RMz3zc2CGYzpQ4sSImQ0W5n9gVv/BAlbaVUf8cIyru+RNYcno6+jrdWyPx39Z+I 2Il83YrtfaBHhODrfbbjKYTfLSFMhfdrBMt6DnbNGoCcEQsd5xcK52Zu12Lv6XGk FWxgqUBmpkj9mFSuMMEr =w5Dy -----END PGP SIGNATURE----- --FIYk/R+LCB1TX+kR-- From ralf@linux-mips.org Wed Jul 31 18:25:27 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 31 Jul 2013 18:25:39 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:35653 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6827293Ab3GaQZ1bEOnb (ORCPT ); Wed, 31 Jul 2013 18:25:27 +0200 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id r6VGPPfi010898; Wed, 31 Jul 2013 18:25:25 +0200 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id r6VGPMLU010897; Wed, 31 Jul 2013 18:25:22 +0200 Date: Wed, 31 Jul 2013 18:25:22 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Stuart Longland , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Michal Marek , linux-kbuild@vger.kernel.org Subject: Re: [RFC MIPS] Update buildtar for MIPS Message-ID: <20130731162521.GA10570@linux-mips.org> References: <1286502337-23882-1-git-send-email-redhatter@gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37407 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 3508 Lines: 73 On Sat, Oct 16, 2010 at 07:17:45AM +0100, Maciej W. Rozycki wrote: > > This updates buildtar to support MIPS targets. MIPS may use 'vmlinux' > > or 'vmlinux.32' depending on the target system. > > Or vmlinux.64 -- why don't you handle that too? Patchwork is patient, nothing gets lost :-) I've updated Stuart's original patch http://patchwork.linux-mips.org/patch/1673/ to also handle compressed kernel images, how about below patch. Michal, when testing this by building "make targz-pkg" for a particular MIPS platform I get tar: lib/*: Cannot stat: No such file or directory and I assume that's because CONFIG_MODULES is not enabled for my test configuration. Ralf kbuild: Add MIPS specific files to generated package. A lot of 64-bit systems supported by Linux/MIPS have boot firmware or bootloaders that only understand 32-bit ELF files, and as such, the vmlinux.32 target exists to support these systems. Therefore, it'd be nice if the tar-pkg target recognised this, and included the right version when packaging up a binary of the kernel. This updates buildtar to support MIPS targets. MIPS may use 'vmlinux' or 'vmlinux.32' depending on the target system. This uses 'vmlinux.32' in preference to 'vmlinux' where present (although I should check which is newer), including either file as /boot/vmlinux-${version}. Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ralf Baechle --- scripts/package/buildtar | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/scripts/package/buildtar b/scripts/package/buildtar index cdd9bb9..aa22f94 100644 --- a/scripts/package/buildtar +++ b/scripts/package/buildtar @@ -87,6 +87,27 @@ case "${ARCH}" in [ -f "${objtree}/vmlinux.SYS" ] && cp -v -- "${objtree}/vmlinux.SYS" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}.SYS" [ -f "${objtree}/vmlinux.dsk" ] && cp -v -- "${objtree}/vmlinux.dsk" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}.dsk" ;; + mips) + if [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.bin" ]; then + cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.bin" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.ecoff" ]; then + cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.ecoff" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.srec" ]; then + cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.srec" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + elif [ -f "${objtree}/vmlinux.32" ]; then + cp -v -- "${objtree}/vmlinux.32" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/vmlinux.64" ]; then + cp -v -- "${objtree}/vmlinux.64" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/vmlinux.bin" ]; then + cp -v -- "${objtree}/arch/mips/boot/vmlinux.bin" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/vmlinux.ecoff" ]; then + cp -v -- "${objtree}/arch/mips/boot/vmlinux.ecoff" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/vmlinux.srec" ]; then + cp -v -- "${objtree}/arch/mips/boot/vmlinux.srec" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/vmlinux" ]; then + cp -v -- "${objtree}/vmlinux" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + fi + ;; *) [ -f "${KBUILD_IMAGE}" ] && cp -v -- "${KBUILD_IMAGE}" "${tmpdir}/boot/vmlinux-kbuild-${KERNELRELEASE}" echo "" >&2 From ddaney.cavm@gmail.com Wed Jul 31 21:22:24 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 31 Jul 2013 21:22:37 +0200 (CEST) Received: from mail-pd0-f169.google.com ([209.85.192.169]:63714 "EHLO mail-pd0-f169.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827280Ab3GaTWYmOsx6 (ORCPT ); Wed, 31 Jul 2013 21:22:24 +0200 Received: by mail-pd0-f169.google.com with SMTP id y11so1117951pdj.14 for ; Wed, 31 Jul 2013 12:22:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=/LsFLiozx6360zatOgzF73MkInT4FcrZfMgBxH8VIhg=; b=Jh1W1cXOYdZuH0c8bOuC/VwAhRd0o8Igs3vbVioA8xskA6Uyp2riqc+J7jTrfvXkCk up8H7XMpR08DqLtDzBxxziXxS3pBGZvFqzqVKhF0DJ0vjOQ8k3azp/hc7oxWn9UM5cah BnG/1A6oW74zxmW6u7vvJ7EJhjSgns8zb4vmQMWKhmcYw+QlZl5Qg0x2pSmOyf0SXpVU cPQGJT9EFXjLjZVofglJoWe27fHAIhQmnpJcVRzR1sAtoNS9x4cs/9M5zLsVhTELFM14 iASCfCl1YAEandeTxY4RKcJyqWJYD+ioRzopOKTf4KAXP9OT7fcEF5d2QTUpel/0Sm0a AAaw== X-Received: by 10.66.2.164 with SMTP id 4mr83617820pav.55.1375298538069; Wed, 31 Jul 2013 12:22:18 -0700 (PDT) Received: from dl.caveonetworks.com (64.2.3.195.ptr.us.xo.net. [64.2.3.195]) by mx.google.com with ESMTPSA id bg3sm3716084pbb.44.2013.07.31.12.22.16 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 31 Jul 2013 12:22:17 -0700 (PDT) Message-ID: <51F963E7.50407@gmail.com> Date: Wed, 31 Jul 2013 12:22:15 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Florian Fainelli CC: John Crispin , Linux-MIPS Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k References: <1375091743-20608-1-git-send-email-blogic@openwrt.org> <51F6495D.9000008@phrozen.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37408 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1312 Lines: 34 On 07/29/2013 04:14 AM, Florian Fainelli wrote: > 2013/7/29 John Crispin : [...] >> >>> It looks to me like you are moving the irq setup later just to ensure >>> that your ralink clockevent device has been registered before and has >>> set cp0_timer_irq_installed when the set_mode() r4k clockevent device >>> runs, such that it won't register the same IRQ that your platforms >>> uses. If that it the case, cannot you just ensure that you run your >>> cevt device registration before mips_clockevent_init() is called? >> >> >> i dont like relying on the order in which the modules get loaded. > > plat_time_init() runs before mips_clockevent_init() and the ordering > is explicit, would not that work for what you are trying to do? > >> >> the actual problem is not the irq sharing but that the cevt-r4k registers >> the irq when the cevt is registered and not when it is activated. i believe >> that the patch fixes this problem > > Your patch certainly does what you say it does, but that is kind of an > abuse of the set_mode() callback. > I might as add my $0.02... There are many other clockevent drivers that do this type of thing aren't there? The clockevent framework uses this to install/remove/switch drivers, so why should cevt-r4k not be made to work like this? David Daney From f.fainelli@gmail.com Wed Jul 31 21:26:11 2013 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 31 Jul 2013 21:26:14 +0200 (CEST) Received: from mail-wg0-f47.google.com ([74.125.82.47]:65177 "EHLO mail-wg0-f47.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6827280Ab3GaT0Ld0nnW convert rfc822-to-8bit (ORCPT ); Wed, 31 Jul 2013 21:26:11 +0200 Received: by mail-wg0-f47.google.com with SMTP id j13so963185wgh.14 for ; Wed, 31 Jul 2013 12:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:user-agent:in-reply-to :references:mime-version:content-transfer-encoding:content-type; bh=E38yIpHMuGTajVVJXrSdFpidfP2iOvaz4LAXL6esRDg=; b=a0tkqISZNIZKxrahocAv4KVxe8bGDsNxhK98q4RGENKcicWIHALgo3IKdrpayX870e rhLXO+hS1rSHGg6Yl60EuaiuOBsOYm2amA1JW6zW2x7rywLQZ1MVMkOISQBzJryuJrlA LDyul9EhZya5joru5yCIQlgB3o+oawVg42qc+LqZTOK8PXArSRC2UafYJn0LHqrknWxT FKlfmp48nS2B7XlzOqrGq6+xgwZGo27lAba+XshvibkpiqHoZoXFRmnnmidxtEi/2RpC H25VqmKxQxuG3KQuixGewFK3NOyq+W5nMbGp/tekd5WLhk2SIm6PmsjFUZRP46IWeCPF ClTQ== X-Received: by 10.180.89.101 with SMTP id bn5mr5254640wib.45.1375298766186; Wed, 31 Jul 2013 12:26:06 -0700 (PDT) Received: from lenovo.localnet (cpc24-aztw25-2-0-cust938.aztw.cable.virginmedia.com. [92.233.35.171]) by mx.google.com with ESMTPSA id l2sm267151wif.8.2013.07.31.12.26.04 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 31 Jul 2013 12:26:04 -0700 (PDT) From: Florian Fainelli To: David Daney Cc: John Crispin , Linux-MIPS Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k Date: Wed, 31 Jul 2013 20:26:02 +0100 Message-ID: <1687511.8JA8mPPmNW@lenovo> User-Agent: KMail/4.10.5 (Linux/3.8.0-27-generic; KDE/4.10.5; x86_64; ; ) In-Reply-To: <51F963E7.50407@gmail.com> References: <1375091743-20608-1-git-send-email-blogic@openwrt.org> <51F963E7.50407@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 37409 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: f.fainelli@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Content-Length: 1550 Lines: 36 Le mercredi 31 juillet 2013 12:22:15 David Daney a crit : > On 07/29/2013 04:14 AM, Florian Fainelli wrote: > > 2013/7/29 John Crispin : > [...] > > >>> It looks to me like you are moving the irq setup later just to ensure > >>> that your ralink clockevent device has been registered before and has > >>> set cp0_timer_irq_installed when the set_mode() r4k clockevent device > >>> runs, such that it won't register the same IRQ that your platforms > >>> uses. If that it the case, cannot you just ensure that you run your > >>> cevt device registration before mips_clockevent_init() is called? > >> > >> i dont like relying on the order in which the modules get loaded. > > > > plat_time_init() runs before mips_clockevent_init() and the ordering > > is explicit, would not that work for what you are trying to do? > > > >> the actual problem is not the irq sharing but that the cevt-r4k registers > >> the irq when the cevt is registered and not when it is activated. i > >> believe > >> that the patch fixes this problem > > > > Your patch certainly does what you say it does, but that is kind of an > > abuse of the set_mode() callback. > > I might as add my $0.02... > > There are many other clockevent drivers that do this type of thing > aren't there? The clockevent framework uses this to > install/remove/switch drivers, so why should cevt-r4k not be made to > work like this? Whatever works for you. I still would like to understand why plat_time_init() is not suitable for John's specific use case. -- Florian